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SourceLevelDebugPkg: Use CPU Local APIC timer to handle timeout.

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Use CPU Local APIC timer to handle timeout when read data from debug port, instead of the TimerLib in Debug Communication lib instances.
It could remove much duplicated code in Debug Communication Lib instances.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>





git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17089 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Jeff Fan
2015-04-01 07:51:15 +00:00
committed by vanjeff
parent 206f412113
commit 08021523f8
17 changed files with 283 additions and 667 deletions
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55
SourceLevelDebugPkg/Library/DebugCommunicationLibUsb3/DebugCommunicationLibUsb3Transfer.c
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@@ -356,58 +356,31 @@ XhcExecTransfer (
)
{
TRANSFER_RING *Ring;
UINT64 Begin;
UINT64 TimeoutTicker;
UINT64 TimerRound;
TRB_TEMPLATE *Trb;
UINTN Loop;
UINTN Index;
Begin = 0;
TimeoutTicker = 0;
TimerRound = 0;
XhcRingDoorBell (Handle, Urb);
if (Timeout != 0) {
Begin = GetPerformanceCounter ();
TimeoutTicker = DivU64x32 (
MultU64x64 (
Handle->TimerFrequency,
Timeout
),
1000000u
);
TimerRound = DivU64x64Remainder (
TimeoutTicker,
DivU64x32 (Handle->TimerCycle, 2),
&TimeoutTicker
);
Loop = Timeout / XHC_DEBUG_PORT_1_MILLISECOND;
if (Timeout == 0) {
Loop = 0xFFFFFFFF;
}
XhcRingDoorBell (Handle, Urb);
//
// Event Ring Not Empty bit can only be set to 1 by XHC after ringing door bell with some delay.
//
while (TRUE) {
if (Timeout != 0) {
if (TimerRound == 0) {
if (IsTimerTimeout (Handle, Begin, TimeoutTicker)) {
//
// If time out occurs.
//
Urb->Result |= EFI_USB_ERR_TIMEOUT;
break;
}
} else {
if (IsTimerTimeout (Handle, Begin, DivU64x32 (Handle->TimerCycle, 2))) {
TimerRound --;
}
}
}
for (Index = 0; Index < Loop; Index++) {
XhcCheckUrbResult (Handle, Urb);
if (Urb->Finished) {
break;
}
MicroSecondDelay (XHC_DEBUG_PORT_1_MILLISECOND);
}
if (Index == Loop) {
//
// If time out occurs.
//
Urb->Result |= EFI_USB_ERR_TIMEOUT;
}
//
// If URB transfer is error, restore transfer ring to original value before URB transfer
// This will make the current transfer TRB is always at the latest unused one in transfer ring.