UefiCpuPkg/CpuExceptionHandlerLib: Support IA32 processors without DE or FXSAVE/FXRESTOR
Use CPUID Leaf 01 to detect support for debug extensions and FXSAVE/FXRESTOR instructions. Do not enable those features in CR4 if they are not supported. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17221 6f19259b-4bc3-4df7-8a09-765794883524
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@@ -1,6 +1,6 @@
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#------------------------------------------------------------------------------
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#*
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#* Copyright (c) 2012 - 2013, Intel Corporation. All rights reserved.<BR>
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#* Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.<BR>
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#* This program and the accompanying materials
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#* are licensed and made available under the terms and conditions of the BSD License
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#* which accompanies this distribution. The full text of the license may be found at
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@@ -447,10 +447,25 @@ ErrorCodeAndVectorOnStack:
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pushl %eax
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#; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
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## insure FXSAVE/FXRSTOR is enabled in CR4...
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## ... while we're at it, make sure DE is also enabled...
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mov $1, %eax
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pushl %ebx # temporarily save value of ebx on stack
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cpuid # use CPUID to determine if FXSAVE/FXRESTOR
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# and DE are supported
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popl %ebx # retore value of ebx that was overwritten
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# by CPUID
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movl %cr4, %eax
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orl $0x208, %eax
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pushl %eax # push cr4 firstly
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testl $BIT24, %edx # Test for FXSAVE/FXRESTOR support
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jz L1
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orl $BIT9, %eax # Set CR4.OSFXSR
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L1:
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testl $BIT2, %edx # Test for Debugging Extensions support
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jz L2
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orl $BIT3, %eax # Set CR4.DE
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L2:
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movl %eax, %cr4
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pushl %eax
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movl %cr3, %eax
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pushl %eax
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movl %cr2, %eax
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@@ -477,7 +492,11 @@ ErrorCodeAndVectorOnStack:
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#; FX_SAVE_STATE_IA32 FxSaveState;
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subl $512, %esp
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movl %esp, %edi
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testl $BIT24, %edx # Test for FXSAVE/FXRESTOR support.
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# edx still contains result from CPUID above
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jz L3
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.byte 0x0f, 0x0ae, 0x07 #fxsave [edi]
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L3:
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#; UEFI calling convention for IA32 requires that Direction flag in EFLAGs is clear
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cld
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@@ -503,7 +522,13 @@ ErrorCodeAndVectorOnStack:
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#; FX_SAVE_STATE_IA32 FxSaveState;
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movl %esp, %esi
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movl $1, %eax
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cpuid # use CPUID to determine if FXSAVE/FXRESTOR
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# are supported
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testl $BIT24, %edx # Test for FXSAVE/FXRESTOR support
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jz L4
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.byte 0x0f, 0x0ae, 0x0e # fxrstor [esi]
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L4:
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addl $512, %esp
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#; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
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