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Move ARM disassembler into a library.

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git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9902 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
andrewfish
2010-02-01 18:25:18 +00:00
parent cb6cb44c1a
commit 097bd461c4
9 changed files with 180 additions and 48 deletions
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448
ArmPkg/Library/ArmDisassemblerLib/ArmDisassembler.c Normal file
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/** @file
Default exception handler
Copyright (c) 2008-2010, Apple Inc. All rights reserved.
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <Base.h>
#include <Library/BaseLib.h>
#include <Library/PrintLib.h>
#include <Library/ArmDisassemblerLib.h>
CHAR8 *gCondition[] = {
"EQ",
"NE",
"CS",
"CC",
"MI",
"PL",
"VS",
"VC",
"HI",
"LS",
"GE",
"LT",
"GT",
"LE",
"",
"2"
};
#define COND(_a) gCondition[(_a) >> 28]
CHAR8 *gReg[] = {
"r0",
"r1",
"r2",
"r3",
"r4",
"r5",
"r6",
"r7",
"r8",
"r9",
"r10",
"r11",
"r12",
"sp",
"lr",
"pc"
};
CHAR8 *gLdmAdr[] = {
"DA",
"IA",
"DB",
"IB"
};
CHAR8 *gLdmStack[] = {
"FA",
"FD",
"EA",
"ED"
};
#define LDM_EXT(_reg, _off) ((_reg == 13) ? gLdmStack[(_off)] : gLdmAdr[(_off)])
#define SIGN(_U) ((_U) ? "" : "-")
#define WRITE(_W) ((_W) ? "!" : "")
#define BYTE(_B) ((_B) ? "B":"")
#define USER(_B) ((_B) ? "^" : "")
CHAR8 mMregListStr[4*15 + 1];
CHAR8 *
MRegList (
UINT32 OpCode
)
{
UINTN Index, Start, End;
CHAR8 *Str;
BOOLEAN First;
Str = mMregListStr;
*Str = '\0';
AsciiStrCat (Str, "{");
for (Index = 0, First = TRUE; Index <= 15; Index++) {
if ((OpCode & (1 << Index)) != 0) {
Start = End = Index;
for (Index++; ((OpCode & (1 << Index)) != 0) && Index <= 15; Index++) {
End = Index;
}
if (!First) {
AsciiStrCat (Str, ",");
} else {
First = FALSE;
}
if (Start == End) {
AsciiStrCat (Str, gReg[Start]);
AsciiStrCat (Str, ", ");
} else {
AsciiStrCat (Str, gReg[Start]);
AsciiStrCat (Str, "-");
AsciiStrCat (Str, gReg[End]);
}
}
}
if (First) {
AsciiStrCat (Str, "ERROR");
}
AsciiStrCat (Str, "}");
// BugBug: Make caller pass in buffer it is cleaner
return mMregListStr;
}
CHAR8 *
FieldMask (
IN UINT32 Mask
)
{
return "";
}
UINT32
RotateRight (
IN UINT32 Op,
IN UINT32 Shift
)
{
return (Op >> Shift) | (Op << (32 - Shift));
}
/**
Place a dissasembly of of **OpCodePtr into buffer, and update OpCodePtr to
point to next instructin.
We cheat and only decode instructions that access
memory. If the instruction is not found we dump the instruction in hex.
@param OpCodePtr Pointer to pointer of ARM instruction to disassemble.
@param Buf Buffer to sprintf disassembly into.
@param Size Size of Buf in bytes.
**/
VOID
DisassembleArmInstruction (
IN UINT32 **OpCodePtr,
OUT CHAR8 *Buf,
OUT UINTN Size
)
{
UINT32 OpCode = **OpCodePtr;
CHAR8 *Type, *Root;
BOOLEAN I, P, U, B, W, L, S, H;
UINT32 Rn, Rd, Rm;
UINT32 imode, offset_8, offset_12;
UINT32 Index;
UINT32 shift_imm, shift;
I = (OpCode & BIT25) == BIT25;
P = (OpCode & BIT24) == BIT24;
U = (OpCode & BIT23) == BIT23;
B = (OpCode & BIT22) == BIT22; // Also called S
W = (OpCode & BIT21) == BIT21;
L = (OpCode & BIT20) == BIT20;
S = (OpCode & BIT6) == BIT6;
H = (OpCode & BIT5) == BIT5;
Rn = (OpCode >> 16) & 0xf;
Rd = (OpCode >> 12) & 0xf;
Rm = (OpCode & 0xf);
// LDREX, STREX
if ((OpCode & 0x0fe000f0) == 0x01800090) {
if (L) {
// A4.1.27 LDREX{<cond>} <Rd>, [<Rn>]
AsciiSPrint (Buf, Size, "LDREX%a %a, [%a]", COND (OpCode), gReg[Rd], gReg[Rn]);
} else {
// A4.1.103 STREX{<cond>} <Rd>, <Rm>, [<Rn>]
AsciiSPrint (Buf, Size, "STREX%a %a, %a, [%a]", COND (OpCode), gReg[Rd], gReg[Rn], gReg[Rn]);
}
return;
}
// LDM/STM
if ((OpCode & 0x0e000000) == 0x08000000) {
if (L) {
// A4.1.20 LDM{<cond>}<addressing_mode> <Rn>{!}, <registers>
// A4.1.21 LDM{<cond>}<addressing_mode> <Rn>, <registers_without_pc>^
// A4.1.22 LDM{<cond>}<addressing_mode> <Rn>{!}, <registers_and_pc>^
AsciiSPrint (Buf, Size, "LDM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn ,(OpCode >> 23) & 3), gReg[Rn], WRITE (W), MRegList (OpCode), USER (B));
} else {
// A4.1.97 STM{<cond>}<addressing_mode> <Rn>{!}, <registers>
// A4.1.98 STM{<cond>}<addressing_mode> <Rn>, <registers>^
AsciiSPrint (Buf, Size, "STM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn ,(OpCode >> 23) & 3), gReg[Rn], WRITE (W), MRegList (OpCode), USER (B));
}
return;
}
// LDR/STR Address Mode 2
if ( ((OpCode & 0x0c000000) == 0x04000000) || ((OpCode & 0xfd70f000 ) == 0xf550f000) ) {
offset_12 = OpCode & 0xfff;
if ((OpCode & 0xfd70f000 ) == 0xf550f000) {
Index = AsciiSPrint (Buf, Size, "PLD");
} else {
Index = AsciiSPrint (Buf, Size, "%a%a%a%a %a, ", L ? "LDR" : "STR", COND (OpCode), BYTE (B), (!P & W) ? "T":"", gReg[Rd]);
}
if (P) {
if (!I) {
// A5.2.2 [<Rn>, #+/-<offset_12>]
// A5.2.5 [<Rn>, #+/-<offset_12>]
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a0x%x]%a", gReg[Rn], SIGN (U), offset_12, WRITE (W));
} else if ((OpCode & 0x03000ff0) == 0x03000000) {
// A5.2.3 [<Rn>, +/-<Rm>]
// A5.2.6 [<Rn>, +/-<Rm>]!
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a]%a", gReg[Rn], SIGN (U), WRITE (W));
} else {
// A5.2.4 [<Rn>, +/-<Rm>, LSL #<shift_imm>]
// A5.2.7 [<Rn>, +/-<Rm>, LSL #<shift_imm>]!
shift_imm = (OpCode >> 7) & 0x1f;
shift = (OpCode >> 5) & 0x3;
if (shift == 0x0) {
Type = "LSL";
} else if (shift == 0x1) {
Type = "LSR";
if (shift_imm == 0) {
shift_imm = 32;
}
} else if (shift == 0x12) {
Type = "ASR";
} else if (shift_imm == 0) {
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a, %a, RRX]%a", gReg[Rn], SIGN (U), gReg[Rm], WRITE (W));
return;
} else {
Type = "ROR";
}
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a, %a, #%d]%a", gReg[Rn], SIGN (U), gReg[Rm], Type, shift_imm, WRITE (W));
}
} else { // !P
if (!I) {
// A5.2.8 [<Rn>], #+/-<offset_12>
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a0x%x", gReg[Rn], SIGN (U), offset_12);
} else if ((OpCode & 0x03000ff0) == 0x03000000) {
// A5.2.9 [<Rn>], +/-<Rm>
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a", gReg[Rn], SIGN (U), gReg[Rm]);
} else {
// A5.2.10 [<Rn>], +/-<Rm>, LSL #<shift_imm>
shift_imm = (OpCode >> 7) & 0x1f;
shift = (OpCode >> 5) & 0x3;
if (shift == 0x0) {
Type = "LSL";
} else if (shift == 0x1) {
Type = "LSR";
if (shift_imm == 0) {
shift_imm = 32;
}
} else if (shift == 0x12) {
Type = "ASR";
} else if (shift_imm == 0) {
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a, %a, RRX", gReg[Rn], SIGN (U), gReg[Rm]);
// FIx me
return;
} else {
Type = "ROR";
}
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a, %a, #%d", gReg[Rn], SIGN (U), gReg[Rm], Type, shift_imm);
}
}
return;
}
if ((OpCode & 0x0e000000) == 0x00000000) {
// LDR/STR address mode 3
// LDR|STR{<cond>}H|SH|SB|D <Rd>, <addressing_mode>
if (L) {
if (!S) {
Root = "LDR%aH %a, ";
} else if (!H) {
Root = "LDR%aSB %a, ";
} else {
Root = "LDR%aSH %a, ";
}
} else {
if (!S) {
Root = "STR%aH %a ";
} else if (!H) {
Root = "LDR%aD %a ";
} else {
Root = "STR%aD %a ";
}
}
Index = AsciiSPrint (Buf, Size, Root, COND (OpCode), gReg[Rd]);
S = (OpCode & BIT6) == BIT6;
H = (OpCode & BIT5) == BIT5;
offset_8 = ((OpCode >> 4) | (OpCode * 0xf)) & 0xff;
if (P & !W) {
// Immediate offset/index
if (B) {
// A5.3.2 [<Rn>, #+/-<offset_8>]
// A5.3.4 [<Rn>, #+/-<offset_8>]!
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%d]%a", gReg[Rn], SIGN (U), offset_8, WRITE (W));
} else {
// A5.3.3 [<Rn>, +/-<Rm>]
// A5.3.5 [<Rn>, +/-<Rm>]!
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%]a", gReg[Rn], SIGN (U), gReg[Rm], WRITE (W));
}
} else {
// Register offset/index
if (B) {
// A5.3.6 [<Rn>], #+/-<offset_8>
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%d", gReg[Rn], SIGN (U), offset_8);
} else {
// A5.3.7 [<Rn>], +/-<Rm>
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a", gReg[Rn], SIGN (U), gReg[Rm]);
}
}
return;
}
if ((OpCode & 0x0fb000f0) == 0x01000050) {
// A4.1.108 SWP SWP{<cond>}B <Rd>, <Rm>, [<Rn>]
// A4.1.109 SWPB SWP{<cond>}B <Rd>, <Rm>, [<Rn>]
AsciiSPrint (Buf, Size, "SWP%a%a %a, %a, [%a]", COND (OpCode), BYTE (B), gReg[Rd], gReg[Rm], gReg[Rn]);
return;
}
if ((OpCode & 0xfe5f0f00) == 0xf84d0500) {
// A4.1.90 SRS SRS<addressing_mode> #<mode>{!}
AsciiSPrint (Buf, Size, "SRS%a #0x%x%a", gLdmStack[(OpCode >> 23) & 3], OpCode & 0x1f, WRITE (W));
return;
}
if ((OpCode & 0xfe500f00) == 0xf8100500) {
// A4.1.59 RFE<addressing_mode> <Rn>{!}
AsciiSPrint (Buf, Size, "RFE%a %a", gLdmStack[(OpCode >> 23) & 3], gReg[Rn], WRITE (W));
return;
}
if ((OpCode & 0xfff000f0) == 0xe1200070) {
// A4.1.7 BKPT <immed_16>
AsciiSPrint (Buf, Size, "BKPT %x", ((OpCode >> 8) | (OpCode & 0xf)) & 0xffff);
return;
}
if ((OpCode & 0xfff10020) == 0xf1000000) {
// A4.1.16 CPS<effect> <iflags> {, #<mode>}
if (((OpCode >> 6) & 0x7) == 0) {
AsciiSPrint (Buf, Size, "CPS #0x%x", (OpCode & 0x2f));
} else {
imode = (OpCode >> 18) & 0x3;
Index = AsciiSPrint (Buf, Size, "CPS%a %a%a%a", (imode == 3) ? "ID":"IE", (OpCode & BIT8) ? "A":"", (OpCode & BIT7) ? "I":"", (OpCode & BIT6) ? "F":"");
if ((OpCode & BIT17) != 0) {
AsciiSPrint (&Buf[Index], Size - Index, ", #0x%x", OpCode & 0x1f);
}
}
return;
}
if ((OpCode & 0x0f000000) == 0x0f000000) {
// A4.1.107 SWI{<cond>} <immed_24>
AsciiSPrint (Buf, Size, "SWI%a %x", COND (OpCode), OpCode & 0x00ffffff);
return;
}
if ((OpCode & 0x0fb00000) == 0x01000000) {
// A4.1.38 MRS{<cond>} <Rd>, CPSR MRS{<cond>} <Rd>, SPSR
AsciiSPrint (Buf, Size, "MRS%a %a, %a", COND (OpCode), gReg[Rd], B ? "SPSR" : "CPSR");
return;
}
if ((OpCode & 0x0db00000) == 0x03200000) {
// A4.1.38 MSR{<cond>} CPSR_<fields>, #<immediate> MSR{<cond>} CPSR_<fields>, <Rm>
if (I) {
// MSR{<cond>} CPSR_<fields>, #<immediate>
AsciiSPrint (Buf, Size, "MRS%a %a_%a, #0x%x", COND (OpCode), B ? "SPSR" : "CPSR", FieldMask ((OpCode >> 16) & 0xf), RotateRight (OpCode & 0xf, ((OpCode >> 8) & 0xf) *2));
} else {
// MSR{<cond>} CPSR_<fields>, <Rm>
AsciiSPrint (Buf, Size, "MRS%a %a_%a, %a", COND (OpCode), B ? "SPSR" : "CPSR", gReg[Rd]);
}
return;
}
if ((OpCode & 0xff000010) == 0xfe000000) {
// A4.1.13 CDP{<cond>} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>, <opcode_2>
AsciiSPrint (Buf, Size, "CDP%a 0x%x, 0x%x, CR%d, CR%d, CR%d, 0x%x", COND (OpCode), (OpCode >> 8) & 0xf, (OpCode >> 20) & 0xf, Rn, Rd, Rm, (OpCode >> 5) &0x7);
return;
}
if ((OpCode & 0x0e000000) == 0x0c000000) {
// A4.1.19 LDC and A4.1.96 SDC
if ((OpCode & 0xf0000000) == 0xf0000000) {
Index = AsciiSPrint (Buf, Size, "%a2 0x%x, CR%d, ", L ? "LDC":"SDC", (OpCode >> 8) & 0xf, Rd);
} else {
Index = AsciiSPrint (Buf, Size, "%a%a 0x%x, CR%d, ", L ? "LDC":"SDC", COND (OpCode), (OpCode >> 8) & 0xf, Rd);
}
if (!P) {
if (!W) {
// A5.5.5.5 [<Rn>], <option>
AsciiSPrint (&Buf[Index], Size - Index, "[%a], {0x%x}", gReg[Rn], OpCode & 0xff);
} else {
// A.5.5.4 [<Rn>], #+/-<offset_8>*4
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a0x%x*4", gReg[Rn], SIGN (U), OpCode & 0xff);
}
} else {
// A5.5.5.2 [<Rn>, #+/-<offset_8>*4 ]!
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a0x%x*4]%a", gReg[Rn], SIGN (U), OpCode & 0xff, WRITE (W));
}
}
if ((OpCode & 0x0f000010) == 0x0e000010) {
// A4.1.32 MRC2, MCR2
AsciiSPrint (Buf, Size, "%a%a 0x%x, 0x%x, %a, CR%d, CR%d, 0x%x", L ? "MRC":"MCR", COND (OpCode), (OpCode >> 8) & 0xf, (OpCode >> 20) & 0xf, gReg[Rd], Rn, Rm, (OpCode >> 5) &0x7);
return;
}
if ((OpCode & 0x0ff00000) == 0x0c400000) {
// A4.1.33 MRRC2, MCRR2
AsciiSPrint (Buf, Size, "%a%a 0x%x, 0x%x, %a, %a, CR%d", L ? "MRRC":"MCRR", COND (OpCode), (OpCode >> 4) & 0xf, (OpCode >> 20) & 0xf, gReg[Rd], gReg[Rn], Rm);
return;
}
AsciiSPrint (Buf, Size, "Faulting OpCode 0x%08x", OpCode);
*OpCodePtr += 1;
return;
}

40
ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf Normal file
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#/** @file
# Semihosting serail port lib
#
# Copyright (c) 2008, Apple Inc.
#
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = SemiHostingSerialPortLib
FILE_GUID = 7ACEC173-F15D-426C-8F2F-BD86B4183EF1
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = ArmDisassemblerLib
[Sources.common]
ArmDisassembler.c
ThumbDisassembler.c
[Packages]
MdePkg/MdePkg.dec
ArmPkg/ArmPkg.dec
[LibraryClasses]
UefiLib
BaseLib
PrintLib
DebugLib
PeCoffGetEntryPointLib

462
ArmPkg/Library/ArmDisassemblerLib/ThumbDisassembler.c Normal file
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/** @file
Default exception handler
Copyright (c) 2008-2010, Apple Inc. All rights reserved.
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <Base.h>
#include <Library/BaseLib.h>
#include <Library/PrintLib.h>
extern CHAR8 *gReg[];
#define LOAD_STORE_FORMAT1 1
#define LOAD_STORE_FORMAT2 2
#define LOAD_STORE_FORMAT3 3
#define LOAD_STORE_FORMAT4 4
#define LOAD_STORE_MULTIPLE_FORMAT1 5
#define LOAD_STORE_MULTIPLE_FORMAT2 6
#define IMMED_8 7
#define CONDITIONAL_BRANCH 8
#define UNCONDITIONAL_BRANCH 9
#define UNCONDITIONAL_BRANCH_SHORT 109
#define BRANCH_EXCHANGE 10
#define DATA_FORMAT1 11
#define DATA_FORMAT2 12
#define DATA_FORMAT3 13
#define DATA_FORMAT4 14
#define DATA_FORMAT5 15
#define DATA_FORMAT6_SP 16
#define DATA_FORMAT6_PC 116
#define DATA_FORMAT7 17
#define DATA_FORMAT8 19
#define CPS_FORMAT 20
#define ENDIAN_FORMAT 21
typedef struct {
CHAR8 *Start;
UINT32 OpCode;
UINT32 Mask;
UINT32 AddressMode;
} THUMB_INSTRUCTIONS;
THUMB_INSTRUCTIONS gOpThumb[] = {
// Thumb 16-bit instrucitons
// Op Mask Format
{ "ADC" , 0x4140, 0xffc0, DATA_FORMAT5 },
{ "ADD" , 0x1c00, 0xfe00, DATA_FORMAT2 },
{ "ADD" , 0x3000, 0xf800, DATA_FORMAT3 },
{ "ADD" , 0x1800, 0xfe00, DATA_FORMAT1 },
{ "ADD" , 0x4400, 0xff00, DATA_FORMAT8 }, // A8.6.9
{ "ADD" , 0xa000, 0xf100, DATA_FORMAT6_PC },
{ "ADD" , 0xa100, 0xf100, DATA_FORMAT6_SP },
{ "ADD" , 0xb000, 0xff10, DATA_FORMAT7 },
{ "AND" , 0x4000, 0xffc0, DATA_FORMAT5 },
{ "ASR" , 0x1000, 0xf800, DATA_FORMAT4 },
{ "ASR" , 0x4100, 0xffc0, DATA_FORMAT5 },
{ "B" , 0xd000, 0xf000, CONDITIONAL_BRANCH },
{ "B" , 0xe000, 0xf100, UNCONDITIONAL_BRANCH_SHORT },
{ "BL" , 0xf100, 0xf100, UNCONDITIONAL_BRANCH },
{ "BLX" , 0xe100, 0xf100, UNCONDITIONAL_BRANCH },
{ "BLX" , 0x4780, 0xff80, BRANCH_EXCHANGE },
{ "BX" , 0x4700, 0xff80, BRANCH_EXCHANGE },
{ "BIC" , 0x4380, 0xffc0, DATA_FORMAT5 },
{ "BKPT", 0xdf00, 0xff00, IMMED_8 },
{ "CMN" , 0x42c0, 0xffc0, DATA_FORMAT5 },
{ "CMP" , 0x2800, 0xf100, DATA_FORMAT3 },
{ "CMP" , 0x4280, 0xffc0, DATA_FORMAT5 },
{ "CMP" , 0x4500, 0xff00, DATA_FORMAT8 },
{ "CPS" , 0xb660, 0xffe8, CPS_FORMAT },
{ "CPY" , 0x4600, 0xff00, DATA_FORMAT8 },
{ "EOR" , 0x4040, 0xffc0, DATA_FORMAT5 },
{ "LDMIA" , 0xc800, 0xf800, LOAD_STORE_MULTIPLE_FORMAT1 },
{ "LDR" , 0x6800, 0xf800, LOAD_STORE_FORMAT1 },
{ "LDR" , 0x5800, 0xfe00, LOAD_STORE_FORMAT2 },
{ "LDR" , 0x4800, 0xf800, LOAD_STORE_FORMAT3 },
{ "LDR" , 0x9800, 0xf800, LOAD_STORE_FORMAT4 },
{ "LDRB" , 0x7800, 0xf800, LOAD_STORE_FORMAT1 },
{ "LDRB" , 0x5c00, 0xfe00, LOAD_STORE_FORMAT2 },
{ "LDRH" , 0x8800, 0xf800, LOAD_STORE_FORMAT1 },
{ "LDRH" , 0x7a00, 0xfe00, LOAD_STORE_FORMAT2 },
{ "LDRSB" , 0x5600, 0xfe00, LOAD_STORE_FORMAT2 },
{ "LDRSH" , 0x5e00, 0xfe00, LOAD_STORE_FORMAT2 },
{ "LSL" , 0x0000, 0xf800, DATA_FORMAT4 },
{ "LSL" , 0x4080, 0xffc0, DATA_FORMAT5 },
{ "LSR" , 0x0001, 0xf800, DATA_FORMAT4 },
{ "LSR" , 0x40c0, 0xffc0, DATA_FORMAT5 },
{ "MOV" , 0x2000, 0xf800, DATA_FORMAT3 },
{ "MOV" , 0x1c00, 0xffc0, DATA_FORMAT3 },
{ "MOV" , 0x4600, 0xff00, DATA_FORMAT8 },
{ "MUL" , 0x4340, 0xffc0, DATA_FORMAT5 },
{ "MVN" , 0x41c0, 0xffc0, DATA_FORMAT5 },
{ "NEG" , 0x4240, 0xffc0, DATA_FORMAT5 },
{ "ORR" , 0x4180, 0xffc0, DATA_FORMAT5 },
{ "POP" , 0xbc00, 0xfe00, LOAD_STORE_MULTIPLE_FORMAT2 },
{ "POP" , 0xe400, 0xfe00, LOAD_STORE_MULTIPLE_FORMAT2 },
{ "REV" , 0xba00, 0xffc0, DATA_FORMAT5 },
{ "REV16" , 0xba40, 0xffc0, DATA_FORMAT5 },
{ "REVSH" , 0xbac0, 0xffc0, DATA_FORMAT5 },
{ "ROR" , 0x41c0, 0xffc0, DATA_FORMAT5 },
{ "SBC" , 0x4180, 0xffc0, DATA_FORMAT5 },
{ "SETEND" , 0xb650, 0xfff0, ENDIAN_FORMAT },
{ "STMIA" , 0xc000, 0xf800, LOAD_STORE_MULTIPLE_FORMAT1 },
{ "STR" , 0x6000, 0xf800, LOAD_STORE_FORMAT1 },
{ "STR" , 0x5000, 0xfe00, LOAD_STORE_FORMAT2 },
{ "STR" , 0x4000, 0xf800, LOAD_STORE_FORMAT3 },
{ "STR" , 0x9000, 0xf800, LOAD_STORE_FORMAT4 },
{ "STRB" , 0x7000, 0xf800, LOAD_STORE_FORMAT1 },
{ "STRB" , 0x5800, 0xfe00, LOAD_STORE_FORMAT2 },
{ "STRH" , 0x8000, 0xf800, LOAD_STORE_FORMAT1 },
{ "STRH" , 0x5200, 0xfe00, LOAD_STORE_FORMAT2 },
{ "SUB" , 0x1e00, 0xfe00, DATA_FORMAT2 },
{ "SUB" , 0x3800, 0xf800, DATA_FORMAT3 },
{ "SUB" , 0x1a00, 0xfe00, DATA_FORMAT1 },
{ "SUB" , 0xb080, 0xff80, DATA_FORMAT7 },
{ "SWI" , 0xdf00, 0xff00, IMMED_8 },
{ "SXTB", 0xb240, 0xffc0, DATA_FORMAT5 },
{ "SXTH", 0xb200, 0xffc0, DATA_FORMAT5 },
{ "TST" , 0x4200, 0xffc0, DATA_FORMAT5 },
{ "UXTB", 0xb2c0, 0xffc0, DATA_FORMAT5 },
{ "UXTH", 0xb280, 0xffc0, DATA_FORMAT5 }
};
#if 0
THUMB_INSTRUCTIONS gOpThumb2[] = {
,
// 32-bit Thumb instructions op1 01
// 1110 100x x0xx xxxx xxxx xxxx xxxx xxxx Load/store multiple
{ "SRSDB", 0xe80dc000, 0xffdffff0, SRS_FORMAT }, // SRSDB<c> SP{!},#<mode>
{ "SRS" , 0xe98dc000, 0xffdffff0, SRS_IA_FORMAT }, // SRS{IA}<c> SP{!},#<mode>
{ "RFEDB", 0xe810c000, 0xffd0ffff, RFE_FORMAT }, // RFEDB<c> <Rn>{!}
{ "RFE" , 0xe990c000, 0xffd0ffff, RFE_IA_FORMAT }, // RFE{IA}<c> <Rn>{!}
{ "STM" , 0xe8800000, 0xffd00000, STM_FORMAT }, // STM<c>.W <Rn>{!},<registers>
{ "LDM" , 0xe8900000, 0xffd00000, STM_FORMAT }, // LDR<c>.W <Rt>,[<Rn>,<Rm>{,LSL #<imm2>}]
{ "POP" , 0xe8bd0000, 0xffff2000, REGLIST_FORMAT }, // POP<c>.W <registers> >1 register
{ "POP" , 0xf85d0b04, 0xffff0fff, RT_FORMAT }, // POP<c>.W <registers> 1 register
{ "STMDB", 0xe9000000, 0xffd00000, STM_FORMAT }, // STMDB
{ "PUSH" , 0xe8bd0000, 0xffffa000, REGLIST_FORMAT }, // PUSH<c>.W <registers> >1 register
{ "PUSH" , 0xf84d0b04, 0xffff0fff, RT_FORMAT }, // PUSH<c>.W <registers> 1 register
{ "LDMDB", 0xe9102000, 0xffd02000, STM_FORMAT }, // LDMDB<c> <Rn>{!},<registers>
// 1110 100x x1xx xxxx xxxx xxxx xxxx xxxx Load/store dual,
{ "STREX" , 0xe0400000, 0xfff000f0, 3REG_IMM8_FORMAT }, // STREX<c> <Rd>,<Rt>,[<Rn>{,#<imm>}]
{ "STREXB", 0xe8c00f40, 0xfff00ff0, 3REG_FORMAT }, // STREXB<c> <Rd>,<Rt>,[<Rn>]
{ "STREXD", 0xe8c00070, 0xfff000f0, 4REG_FORMAT }, // STREXD<c> <Rd>,<Rt>,<Rt2>,[<Rn>]
{ "STREXH", 0xe8c00f70, 0xfff00ff0, 3REG_FORMAT }, // STREXH<c> <Rd>,<Rt>,[<Rn>]
{ "STRH", 0xf8c00000, 0xfff00000, 2REG_IMM8_FORMAT }, // STRH<c>.W <Rt>,[<Rn>{,#<imm12>}]
{ "STRH", 0xf8200000, 0xfff00000, }, // STRH<c>.W <Rt>,[<Rn>,<Rm>{,LSL #<imm2>}]
// 1110 101x xxxx xxxx xxxx xxxx xxxx xxxx Data-processing
// 1110 11xx xxxx xxxx xxxx xxxx xxxx xxxx Coprocessor
// 1111 0x0x xxxx xxxx 0xxx xxxx xxxx xxxx Data-processing modified immediate
// 1111 0x1x xxxx xxxx 0xxx xxxx xxxx xxxx Data-processing plain immediate
// 1111 0xxx xxxx xxxx 1xxx xxxx xxxx xxxx Branches
// 1111 1000 xxx0 xxxx xxxx xxxx xxxx xxxx Store single data item
// 1111 1001 xxx0 xxxx xxxx xxxx xxxx xxxx SIMD or load/store
// 1111 100x x001 xxxx xxxx xxxx xxxx xxxx Load byte, memory hints
// 1111 100x x011 xxxx xxxx xxxx xxxx xxxx Load halfword, memory hints
// 1111 100x x101 xxxx xxxx xxxx xxxx xxxx Load word
// 1111 1 010 xxxx xxxx xxxx xxxx xxxx xxxx Data-processing register
// 1111 1 011 0xxx xxxx xxxx xxxx xxxx xxxx Multiply
// 1111 1 011 1xxx xxxx xxxx xxxx xxxx xxxx Long Multiply
// 1111 1 1xx xxxx xxxx xxxx xxxx xxxx xxxx Coprocessor
};
#endif
CHAR8 mThumbMregListStr[4*15 + 1];
CHAR8 *
ThumbMRegList (
UINT32 OpCode
)
{
UINTN Index, Start, End;
CHAR8 *Str;
BOOLEAN First;
Str = mThumbMregListStr;
*Str = '\0';
AsciiStrCat (Str, "{");
// R0 - R7, PC
for (Index = 0, First = TRUE; Index <= 9; Index++) {
if ((OpCode & (1 << Index)) != 0) {
Start = End = Index;
for (Index++; ((OpCode & (1 << Index)) != 0) && (Index <= 9); Index++) {
End = Index;
}
if (!First) {
AsciiStrCat (Str, ",");
} else {
First = FALSE;
}
if (Start == End) {
AsciiStrCat (Str, gReg[(Start == 9)?15:Start]);
AsciiStrCat (Str, ", ");
} else {
AsciiStrCat (Str, gReg[Start]);
AsciiStrCat (Str, "-");
AsciiStrCat (Str, gReg[(End == 9)?15:End]);
}
}
}
if (First) {
AsciiStrCat (Str, "ERROR");
}
AsciiStrCat (Str, "}");
// BugBug: Make caller pass in buffer it is cleaner
return mThumbMregListStr;
}
UINT32
SignExtend (
IN UINT32 Data
)
{
return 0;
}
/**
Place a dissasembly of of **OpCodePtr into buffer, and update OpCodePtr to
point to next instructin.
We cheat and only decode instructions that access
memory. If the instruction is not found we dump the instruction in hex.
@param OpCodePtrPtr Pointer to pointer of ARM Thumb instruction to disassemble.
@param Buf Buffer to sprintf disassembly into.
@param Size Size of Buf in bytes.
**/
VOID
DisassembleThumbInstruction (
IN UINT16 **OpCodePtrPtr,
OUT CHAR8 *Buf,
OUT UINTN Size
)
{
UINT16 *OpCodePtr;
UINT16 OpCode;
UINT16 OpCode32;
UINT32 Index;
UINT32 Offset;
UINT16 Rd, Rn, Rm;
INT32 target_addr;
BOOLEAN H1, H2, imod;
UINT32 PC;
OpCodePtr = *OpCodePtrPtr;
OpCode = **OpCodePtrPtr;
// Thumb2 is a stream of 16-bit instructions not a 32-bit instruction.
OpCode32 = (OpCode << 16) | *(OpCodePtr + 1);
// These register names match branch form, but not others
Rd = OpCode & 0x7;
Rn = (OpCode >> 3) & 0x7;
Rm = (OpCode >> 6) & 0x7;
H1 = (OpCode & BIT7) != 0;
H2 = (OpCode & BIT6) != 0;
imod = (OpCode & BIT4) != 0;
PC = (UINT32)(UINTN)*OpCodePtr;
// Increment by the minimum instruction size, Thumb2 could be bigger
*OpCodePtrPtr += 1;
for (Index = 0; Index < sizeof (gOpThumb)/sizeof (THUMB_INSTRUCTIONS); Index++) {
if ((OpCode & gOpThumb[Index].Mask) == gOpThumb[Index].OpCode) {
Offset = AsciiSPrint (Buf, Size, "%a", gOpThumb[Index].Start);
switch (gOpThumb[Index].AddressMode) {
case LOAD_STORE_FORMAT1:
// A6.5.1 <Rd>, [<Rn>, #<5_bit_offset>]
AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d #0x%x]", Rd, (OpCode >> 7) & 7, (OpCode >> 6) & 0x1f);
break;
case LOAD_STORE_FORMAT2:
// A6.5.1 <Rd>, [<Rn>, <Rm>]
AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d, r%d]", Rd, (OpCode >> 3) & 7, Rm);
break;
case LOAD_STORE_FORMAT3:
// A6.5.1 <Rd>, [PC, #<8_bit_offset>]
AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [pc, #0x%x]", (OpCode >> 8) & 7, OpCode & 0xff);
break;
case LOAD_STORE_FORMAT4:
// FIX ME!!!!!
AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [sp, #0x%x]", (OpCode >> 8) & 7, OpCode & 0xff);
break;
case LOAD_STORE_MULTIPLE_FORMAT1:
// <Rn>!, <registers>
AsciiSPrint (&Buf[Offset], Size - Offset, " r%d!, %a", (OpCode >> 8) & 7, ThumbMRegList (!BIT8 & OpCode));
break;
case LOAD_STORE_MULTIPLE_FORMAT2:
// <Rn>!, <registers>
// BIT8 is PC
AsciiSPrint (&Buf[Offset], Size - Offset, " r%d!, %a", (OpCode >> 8) & 7, ThumbMRegList (OpCode));
break;
case IMMED_8:
// A6.7 <immed_8>
AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%x", OpCode & 0xff);
break;
case CONDITIONAL_BRANCH:
// A6.3.1 B<cond> <target_address>
AsciiSPrint (&Buf[Offset], Size - Offset, "%a 0x%04x", PC + 4 + SignExtend ((OpCode & 0xff) << 1));
break;
case UNCONDITIONAL_BRANCH_SHORT:
// A6.3.2 B <target_address>
AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", PC + 4 + SignExtend ((OpCode & 0x3ff) << 1));
break;
case UNCONDITIONAL_BRANCH:
// A6.3.2 BL|BLX <target_address> ; Produces two 16-bit instructions
target_addr = *(OpCodePtr - 1);
if ((target_addr & 0xf800) == 0xf000) {
target_addr = ((target_addr & 0x3ff) << 12) | (OpCode & 0x3ff);
} else {
target_addr = OpCode & 0x3ff;
}
// PC + 2 +/- target_addr
AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", PC + 2 + SignExtend (target_addr));
break;
case BRANCH_EXCHANGE:
// A6.3.3 BX|BLX <Rm>
AsciiSPrint (&Buf[Offset], Size - Offset, " r%d", gReg[Rn | (H2 ? 8:0)]);
break;
case DATA_FORMAT1:
// A6.4.3 <Rd>, <Rn>, <Rm>
AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, r%d", Rd, Rn, Rm);
break;
case DATA_FORMAT2:
// A6.4.3 <Rd>, <Rn>, #3_bit_immed
AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, 0x%x", Rd, Rn, Rm);
break;
case DATA_FORMAT3:
// A6.4.3 <Rd>|<Rn>, #8_bit_immed
AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, 0x%x", (OpCode >> 8) & 0x7, OpCode & 0xff);
break;
case DATA_FORMAT4:
// A6.4.3 <Rd>|<Rm>, #immed_5
AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, 0x%x", Rn, Rd, (OpCode >> 6) & 0x1f);
break;
case DATA_FORMAT5:
// A6.4.3 <Rd>|<Rm>, <Rm>|<Rs>
AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d", Rd, Rn);
break;
case DATA_FORMAT6_SP:
// A6.4.3 <Rd>, <reg>, #<8_Bit_immed>
AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, sp, 0x%x", (OpCode >> 8) & 7, OpCode & 0xff);
break;
case DATA_FORMAT6_PC:
// A6.4.3 <Rd>, <reg>, #<8_Bit_immed>
AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, pc, 0x%x", (OpCode >> 8) & 7, OpCode & 0xff);
break;
case DATA_FORMAT7:
// A6.4.3 SP, SP, #<7_Bit_immed>
AsciiSPrint (&Buf[Offset], Size - Offset, " sp, sp 0x%x", (OpCode & 0x7f)*4);
break;
case DATA_FORMAT8:
// A6.4.3 <Rd>|<Rn>, <Rm>
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[Rd | (H1 ? 8:0)], gReg[Rn | (H2 ? 8:0)]);
break;
case CPS_FORMAT:
// A7.1.24
AsciiSPrint (&Buf[Offset], Size - Offset, "%a %a%a%a", imod ? "ID":"IE", ((OpCode & BIT2) == 0) ? "":"a", ((OpCode & BIT1) == 0) ? "":"i", ((OpCode & BIT0) == 0) ? "":"f");
break;
case ENDIAN_FORMAT:
// A7.1.24
AsciiSPrint (&Buf[Offset], Size - Offset, " %a", (OpCode & BIT3) == 0 ? "LE":"BE");
break;
}
}
}
#if 0
// Thumb2 are 32-bit instructions
*OpCodePtrPtr += 1;
for (Index = 0; Index < sizeof (gOpThumb2)/sizeof (THUMB_INSTRUCTIONS); Index++) {
if ((OpCode32 & gOpThumb2[Index].Mask) == gOpThumb2[Index].OpCode) {
}
}
#endif
// Unknown instruction is 16-bits
*OpCodePtrPtr -= 1;
AsciiSPrint (Buf, Size, "0x%04x", OpCode);
}
VOID
DisassembleArmInstruction (
IN UINT32 **OpCodePtr,
OUT CHAR8 *Buf,
OUT UINTN Size
);
/**
Place a dissasembly of of **OpCodePtr into buffer, and update OpCodePtr to
point to next instructin.
We cheat and only decode instructions that access
memory. If the instruction is not found we dump the instruction in hex.
@param OpCodePtrPtr Pointer to pointer of ARM Thumb instruction to disassemble.
@param Thumb TRUE for Thumb(2), FALSE for ARM instruction stream
@param Buf Buffer to sprintf disassembly into.
@param Size Size of Buf in bytes.
**/
VOID
DisassembleInstruction (
IN UINT8 **OpCodePtr,
IN BOOLEAN Thumb,
OUT CHAR8 *Buf,
OUT UINTN Size
)
{
if (Thumb) {
DisassembleThumbInstruction ((UINT16 **)OpCodePtr, Buf, Size);
} else {
DisassembleArmInstruction ((UINT32 **)OpCodePtr, Buf, Size);
}
}