UefiCpuPkg/MpInitLib: Enable 5-level paging for AP when BSP's enabled
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2008 MpInitLib is the library that's responsible to wake up APs to provide MP PPI and Protocol services. The patch synchronizes BSP's CR4.LA57 to each AP's CR4.LA57. Without this change, AP may enter to GP fault when BSP's 5-level page table is set to AP during AP wakes up. Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Eric Dong <eric.dong@intel.com>
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@@ -1,5 +1,5 @@
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;------------------------------------------------------------------------------ ;
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; Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>
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; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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; Module Name:
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@@ -40,3 +40,4 @@ ModeTransitionMemoryLocation equ LockLocation + 94h
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ModeTransitionSegmentLocation equ LockLocation + 98h
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ModeHighMemoryLocation equ LockLocation + 9Ah
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ModeHighSegmentLocation equ LockLocation + 9Eh
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Enable5LevelPagingLocation equ LockLocation + 0A0h
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@@ -1,5 +1,5 @@
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;------------------------------------------------------------------------------ ;
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; Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
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; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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; Module Name:
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@@ -100,6 +100,18 @@ SkipEnableExecuteDisableBit:
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;
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mov eax, cr4
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bts eax, 5
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mov esi, Enable5LevelPagingLocation
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cmp byte [ebx + esi], 0
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jz SkipEnable5LevelPaging
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;
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; Enable 5 Level Paging
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;
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bts eax, 12 ; Set LA57=1.
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SkipEnable5LevelPaging:
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mov cr4, eax
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;
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