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Complement fix for revision #10998 (Remove PI SMM IPL's dependency on CPU AP).

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git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11001 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
rsun3
2010-11-04 05:27:23 +00:00
parent 5469967137
commit 0a6c090521
1 changed files with 12 additions and 8 deletions
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18
MdeModulePkg/Core/PiSmmCore/PiSmmIpl.c
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@@ -567,6 +567,7 @@ SmmIplSmmConfigurationEventNotify (
// //
// Attempt to reset SMRAM cacheability to UC // Attempt to reset SMRAM cacheability to UC
// Assume CPU AP is available at this time
// //
Status = gDS->SetMemorySpaceAttributes( Status = gDS->SetMemorySpaceAttributes(
mSmramCacheBase, mSmramCacheBase,
@@ -1069,6 +1070,7 @@ SmmIplEntry (
// Note that it is expected that cacheability of SMRAM has been set to WB if CPU AP // Note that it is expected that cacheability of SMRAM has been set to WB if CPU AP
// is not available here. // is not available here.
// //
CpuArch = NULL;
Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&CpuArch); Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&CpuArch);
if (!EFI_ERROR (Status)) { if (!EFI_ERROR (Status)) {
Status = gDS->SetMemorySpaceAttributes( Status = gDS->SetMemorySpaceAttributes(
@@ -1121,13 +1123,15 @@ SmmIplEntry (
// //
// Attempt to reset SMRAM cacheability to UC // Attempt to reset SMRAM cacheability to UC
// //
Status = gDS->SetMemorySpaceAttributes( if (CpuArch != NULL) {
mSmramCacheBase, Status = gDS->SetMemorySpaceAttributes(
mSmramCacheSize, mSmramCacheBase,
EFI_MEMORY_UC mSmramCacheSize,
); EFI_MEMORY_UC
if (EFI_ERROR (Status)) { );
DEBUG ((DEBUG_WARN, "SMM IPL failed to reset SMRAM window to EFI_MEMORY_UC\n")); if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_WARN, "SMM IPL failed to reset SMRAM window to EFI_MEMORY_UC\n"));
}
} }
} }
} else { } else {