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IntelFrameworkModulePkg: Clean up source files

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2. No trailing white space in one line
3. All files must end with CRLF

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Liming Gao <liming.gao@intel.com>
This commit is contained in:
Liming Gao
2018-06-27 21:06:35 +08:00
parent e38f26a2f7
commit 0a6f48249a
246 changed files with 4071 additions and 4071 deletions
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40
IntelFrameworkModulePkg/Csm/LegacyBiosDxe/Thunk.c
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@@ -1,7 +1,7 @@
/** @file
Call into 16-bit BIOS code, Use AsmThunk16 function of BaseLib.
Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions
@@ -77,7 +77,7 @@ LegacyBiosInt86 (
Segment = (UINT16)(((UINT32 *)0)[BiosInt] >> 16);
Offset = (UINT16)((UINT32 *)0)[BiosInt];
);
return InternalLegacyBiosFarCall (
This,
Segment,
@@ -131,7 +131,7 @@ LegacyBiosFarCall86 (
}
/**
Provide NULL interrupt handler which is used to check
Provide NULL interrupt handler which is used to check
if there is more than one HW interrupt registers with the CPU AP.
@param InterruptType - The type of interrupt that occured
@@ -218,7 +218,7 @@ InternalLegacyBiosFarCall (
// Disable DXE Timer while executing in real mode
//
Private->Timer->SetTimerPeriod (Private->Timer, 0);
//
// Save and disable interrupt of debug timer
//
@@ -231,14 +231,14 @@ InternalLegacyBiosFarCall (
//
// Check to see if there is more than one HW interrupt registers with the CPU AP.
// If there is, then ASSERT() since that is not compatible with the CSM because
// interupts other than the Timer interrupt that was disabled above can not be
// If there is, then ASSERT() since that is not compatible with the CSM because
// interupts other than the Timer interrupt that was disabled above can not be
// handled properly from real mode.
//
DEBUG_CODE (
UINTN Vector;
UINTN Count;
for (Vector = 0x20, Count = 0; Vector < 0x100; Vector++) {
Status = Private->Cpu->RegisterInterruptHandler (Private->Cpu, Vector, LegacyBiosNullInterruptHandler);
if (Status == EFI_ALREADY_STARTED) {
@@ -255,14 +255,14 @@ InternalLegacyBiosFarCall (
);
//
// If the Timer AP has enabled the 8254 timer IRQ and the current 8254 timer
// period is less than the CSM required rate of 54.9254, then force the 8254
// If the Timer AP has enabled the 8254 timer IRQ and the current 8254 timer
// period is less than the CSM required rate of 54.9254, then force the 8254
// PIT counter to 0, which is the CSM required rate of 54.9254 ms
//
if (Private->TimerUses8254 && TimerPeriod < 549254) {
SetPitCount (0);
}
if (Stack != NULL && StackSize != 0) {
//
// Copy Stack to low memory stack
@@ -310,7 +310,7 @@ InternalLegacyBiosFarCall (
// End critical section
//
gBS->RestoreTPL (OriginalTpl);
//
// OPROM may allocate EBDA range by itself and change EBDA base and EBDA size.
// Get the current EBDA base address, and compared with pre-allocate minimum
@@ -385,27 +385,27 @@ LegacyBiosInitializeThunk (
TimerVector = 0;
Status = Private->Legacy8259->GetVector (Private->Legacy8259, Efi8259Irq0, &TimerVector);
ASSERT_EFI_ERROR (Status);
//
// Check to see if the Timer AP has hooked the IRQ0 from the 8254 PIT
//
//
Status = Private->Cpu->RegisterInterruptHandler (
Private->Cpu,
TimerVector,
Private->Cpu,
TimerVector,
LegacyBiosNullInterruptHandler
);
if (Status == EFI_SUCCESS) {
//
// If the Timer AP has not enabled the 8254 timer IRQ, then force the 8254 PIT
// If the Timer AP has not enabled the 8254 timer IRQ, then force the 8254 PIT
// counter to 0, which is the CSM required rate of 54.9254 ms
//
Private->Cpu->RegisterInterruptHandler (
Private->Cpu,
TimerVector,
Private->Cpu,
TimerVector,
NULL
);
SetPitCount (0);
//
// Save status that the Timer AP is not using the 8254 PIT
//
@@ -421,6 +421,6 @@ LegacyBiosInitializeThunk (
//
ASSERT (FALSE);
}
return EFI_SUCCESS;
}