ArmPlatformPkg: Timer access for non-secure EL1/0
According to Section 2.3.6 of the "UEFI Specification 2.6 Errata A"; the primary CPU must be configured such that 'Timer access must be provided to non-secure EL1 and EL0 by setting bits EL1PCTEN and EL1PCEN in register CNTHCTL_EL2.' This commit adds this missing set-up to the PrePi and PrePeiCore modules. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Sami Mujawar <sami.mujawar@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Leif Lindholm
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@@ -1,5 +1,5 @@
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#========================================================================================
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# Copyright (c) 2011-2013, ARM Limited. All rights reserved.
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# Copyright (c) 2011-2017, ARM Limited. All rights reserved.
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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@@ -36,6 +36,13 @@ ASM_FUNC(SetupExceptionLevel2)
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msr cptr_el2, xzr // Disable copro traps to EL2
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// Enable Timer access for non-secure EL1 and EL0
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// The cnthctl_el2 register bits are architecturally
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// UNKNOWN on reset.
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// Disable event stream as it is not in use at this stage
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mov x0, #(CNTHCTL_EL2_EL1PCTEN | CNTHCTL_EL2_EL1PCEN)
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msr cnthctl_el2, x0
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ret
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ASM_FUNCTION_REMOVE_IF_UNREFERENCED
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