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MdePkg: Add P2P Bridge Secondary Latency Timer register definition

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Add P2P Bridge Secondary Latency Timer register definition to Pci22.h

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Samer El-Haj-Mahmoud <samer.el-haj-mahmoud@hp.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17793 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Samer El-Haj-Mahmoud
2015-07-01 15:21:35 +00:00
committed by lgao4
parent 7b6dad328f
commit 0e8768b65a
1 changed files with 2 additions and 1 deletions
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MdePkg/Include/IndustryStandard/Pci22.h
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@ -9,7 +9,7 @@
Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR> Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2014, Hewlett-Packard Development Company, L.P.<BR> Copyright (c) 2014 - 2105, Hewlett-Packard Development Company, L.P.<BR>
This program and the accompanying materials This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at which accompanies this distribution. The full text of the license may be found at
@ -552,6 +552,7 @@ typedef struct {
#define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET 0x18 #define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET 0x18
#define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET 0x19 #define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET 0x19
#define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET 0x1a #define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET 0x1a
#define PCI_BRIDGE_SECONDARY_LATENCY_TIMER_OFFSET 0x1b
#define PCI_BRIDGE_STATUS_REGISTER_OFFSET 0x1E #define PCI_BRIDGE_STATUS_REGISTER_OFFSET 0x1E
#define PCI_BRIDGE_CONTROL_REGISTER_OFFSET 0x3E #define PCI_BRIDGE_CONTROL_REGISTER_OFFSET 0x3E