sravan/system76-edk2
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

ArmPkg/ArmLib: switch to ASM_FUNC() asm macro

Browse Source 
Annotate functions with ASM_FUNC() so that they are emitted into
separate sections.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
This commit is contained in:
Ard Biesheuvel
2016-08-10 14:35:01 +02:00
parent de656e666c
commit 0efaa42f6e
9 changed files with 203 additions and 422 deletions
Download Patch File Download Diff File Expand all files Collapse all files

47
ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.S
View File

@@ -2,6 +2,7 @@
#
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
# Copyright (c) 2011-2013, ARM Limited. All rights reserved.
# Copyright (c) 2016, Linaro Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@@ -15,27 +16,7 @@
#include <AsmMacroIoLib.h>
.text
.align 2
GCC_ASM_EXPORT(ArmIsMpCore)
GCC_ASM_EXPORT(ArmHasMpExtensions)
GCC_ASM_EXPORT(ArmEnableAsynchronousAbort)
GCC_ASM_EXPORT(ArmDisableAsynchronousAbort)
GCC_ASM_EXPORT(ArmEnableIrq)
GCC_ASM_EXPORT(ArmDisableIrq)
GCC_ASM_EXPORT(ArmEnableFiq)
GCC_ASM_EXPORT(ArmDisableFiq)
GCC_ASM_EXPORT(ArmEnableInterrupts)
GCC_ASM_EXPORT(ArmDisableInterrupts)
GCC_ASM_EXPORT(ReadCCSIDR)
GCC_ASM_EXPORT(ReadCLIDR)
GCC_ASM_EXPORT(ArmReadNsacr)
GCC_ASM_EXPORT(ArmWriteNsacr)
#------------------------------------------------------------------------------
ASM_PFX(ArmIsMpCore):
ASM_FUNC(ArmIsMpCore)
mrc p15,0,R0,c0,c0,5
// Get Multiprocessing extension (bit31) & U bit (bit30)
and R0, R0, #0xC0000000
@@ -45,42 +26,42 @@ ASM_PFX(ArmIsMpCore):
movne R0, #0
bx LR
ASM_PFX(ArmEnableAsynchronousAbort):
ASM_FUNC(ArmEnableAsynchronousAbort)
cpsie a
isb
bx LR
ASM_PFX(ArmDisableAsynchronousAbort):
ASM_FUNC(ArmDisableAsynchronousAbort)
cpsid a
isb
bx LR
ASM_PFX(ArmEnableIrq):
ASM_FUNC(ArmEnableIrq)
cpsie i
isb
bx LR
ASM_PFX(ArmDisableIrq):
ASM_FUNC(ArmDisableIrq)
cpsid i
isb
bx LR
ASM_PFX(ArmEnableFiq):
ASM_FUNC(ArmEnableFiq)
cpsie f
isb
bx LR
ASM_PFX(ArmDisableFiq):
ASM_FUNC(ArmDisableFiq)
cpsid f
isb
bx LR
ASM_PFX(ArmEnableInterrupts):
ASM_FUNC(ArmEnableInterrupts)
cpsie if
isb
bx LR
ASM_PFX(ArmDisableInterrupts):
ASM_FUNC(ArmDisableInterrupts)
cpsid if
isb
bx LR
@@ -89,7 +70,7 @@ ASM_PFX(ArmDisableInterrupts):
// ReadCCSIDR (
// IN UINT32 CSSELR
// )
ASM_PFX(ReadCCSIDR):
ASM_FUNC(ReadCCSIDR)
mcr p15,2,r0,c0,c0,0 @ Write Cache Size Selection Register (CSSELR)
isb
mrc p15,1,r0,c0,c0,0 @ Read current CP15 Cache Size ID Register (CCSIDR)
@@ -99,15 +80,15 @@ ASM_PFX(ReadCCSIDR):
// ReadCLIDR (
// IN UINT32 CSSELR
// )
ASM_PFX(ReadCLIDR):
ASM_FUNC(ReadCLIDR)
mrc p15,1,r0,c0,c0,1 @ Read CP15 Cache Level ID Register
bx lr
ASM_PFX(ArmReadNsacr):
ASM_FUNC(ArmReadNsacr)
mrc p15, 0, r0, c1, c1, 2
bx lr
ASM_PFX(ArmWriteNsacr):
ASM_FUNC(ArmWriteNsacr)
mcr p15, 0, r0, c1, c1, 2
bx lr

65
ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimerSupport.S
View File

@@ -1,6 +1,7 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2011, ARM Limited. All rights reserved.
# Copyright (c) 2016, Linaro Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@@ -12,107 +13,85 @@
#
#------------------------------------------------------------------------------
.text
.align 2
#include <AsmMacroIoLib.h>
GCC_ASM_EXPORT (ArmReadCntFrq)
GCC_ASM_EXPORT (ArmWriteCntFrq)
GCC_ASM_EXPORT (ArmReadCntPct)
GCC_ASM_EXPORT (ArmReadCntkCtl)
GCC_ASM_EXPORT (ArmWriteCntkCtl)
GCC_ASM_EXPORT (ArmReadCntpTval)
GCC_ASM_EXPORT (ArmWriteCntpTval)
GCC_ASM_EXPORT (ArmReadCntpCtl)
GCC_ASM_EXPORT (ArmWriteCntpCtl)
GCC_ASM_EXPORT (ArmReadCntvTval)
GCC_ASM_EXPORT (ArmWriteCntvTval)
GCC_ASM_EXPORT (ArmReadCntvCtl)
GCC_ASM_EXPORT (ArmWriteCntvCtl)
GCC_ASM_EXPORT (ArmReadCntvCt)
GCC_ASM_EXPORT (ArmReadCntpCval)
GCC_ASM_EXPORT (ArmWriteCntpCval)
GCC_ASM_EXPORT (ArmReadCntvCval)
GCC_ASM_EXPORT (ArmWriteCntvCval)
GCC_ASM_EXPORT (ArmReadCntvOff)
GCC_ASM_EXPORT (ArmWriteCntvOff)
ASM_PFX(ArmReadCntFrq):
ASM_FUNC(ArmReadCntFrq)
mrc p15, 0, r0, c14, c0, 0 @ Read CNTFRQ
bx lr
ASM_PFX(ArmWriteCntFrq):
ASM_FUNC(ArmWriteCntFrq)
mcr p15, 0, r0, c14, c0, 0 @ Write to CNTFRQ
bx lr
ASM_PFX(ArmReadCntPct):
ASM_FUNC(ArmReadCntPct)
mrrc p15, 0, r0, r1, c14 @ Read CNTPT (Physical counter register)
bx lr
ASM_PFX(ArmReadCntkCtl):
ASM_FUNC(ArmReadCntkCtl)
mrc p15, 0, r0, c14, c1, 0 @ Read CNTK_CTL (Timer PL1 Control Register)
bx lr
ASM_PFX(ArmWriteCntkCtl):
ASM_FUNC(ArmWriteCntkCtl)
mcr p15, 0, r0, c14, c1, 0 @ Write to CNTK_CTL (Timer PL1 Control Register)
bx lr
ASM_PFX(ArmReadCntpTval):
ASM_FUNC(ArmReadCntpTval)
mrc p15, 0, r0, c14, c2, 0 @ Read CNTP_TVAL (PL1 physical timer value register)
bx lr
ASM_PFX(ArmWriteCntpTval):
ASM_FUNC(ArmWriteCntpTval)
mcr p15, 0, r0, c14, c2, 0 @ Write to CNTP_TVAL (PL1 physical timer value register)
bx lr
ASM_PFX(ArmReadCntpCtl):
ASM_FUNC(ArmReadCntpCtl)
mrc p15, 0, r0, c14, c2, 1 @ Read CNTP_CTL (PL1 Physical Timer Control Register)
bx lr
ASM_PFX(ArmWriteCntpCtl):
ASM_FUNC(ArmWriteCntpCtl)
mcr p15, 0, r0, c14, c2, 1 @ Write to CNTP_CTL (PL1 Physical Timer Control Register)
bx lr
ASM_PFX(ArmReadCntvTval):
ASM_FUNC(ArmReadCntvTval)
mrc p15, 0, r0, c14, c3, 0 @ Read CNTV_TVAL (Virtual Timer Value register)
bx lr
ASM_PFX(ArmWriteCntvTval):
ASM_FUNC(ArmWriteCntvTval)
mcr p15, 0, r0, c14, c3, 0 @ Write to CNTV_TVAL (Virtual Timer Value register)
bx lr
ASM_PFX(ArmReadCntvCtl):
ASM_FUNC(ArmReadCntvCtl)
mrc p15, 0, r0, c14, c3, 1 @ Read CNTV_CTL (Virtual Timer Control Register)
bx lr
ASM_PFX(ArmWriteCntvCtl):
ASM_FUNC(ArmWriteCntvCtl)
mcr p15, 0, r0, c14, c3, 1 @ Write to CNTV_CTL (Virtual Timer Control Register)
bx lr
ASM_PFX(ArmReadCntvCt):
ASM_FUNC(ArmReadCntvCt)
mrrc p15, 1, r0, r1, c14 @ Read CNTVCT (Virtual Count Register)
bx lr
ASM_PFX(ArmReadCntpCval):
ASM_FUNC(ArmReadCntpCval)
mrrc p15, 2, r0, r1, c14 @ Read CNTP_CTVAL (Physical Timer Compare Value Register)
bx lr
ASM_PFX(ArmWriteCntpCval):
ASM_FUNC(ArmWriteCntpCval)
mcrr p15, 2, r0, r1, c14 @ Write to CNTP_CTVAL (Physical Timer Compare Value Register)
bx lr
ASM_PFX(ArmReadCntvCval):
ASM_FUNC(ArmReadCntvCval)
mrrc p15, 3, r0, r1, c14 @ Read CNTV_CTVAL (Virtual Timer Compare Value Register)
bx lr
ASM_PFX(ArmWriteCntvCval):
ASM_FUNC(ArmWriteCntvCval)
mcrr p15, 3, r0, r1, c14 @ write to CNTV_CTVAL (Virtual Timer Compare Value Register)
bx lr
ASM_PFX(ArmReadCntvOff):
ASM_FUNC(ArmReadCntvOff)
mrrc p15, 4, r0, r1, c14 @ Read CNTVOFF (virtual Offset register)
bx lr
ASM_PFX(ArmWriteCntvOff):
ASM_FUNC(ArmWriteCntvOff)
mcrr p15, 4, r0, r1, c14 @ Write to CNTVOFF (Virtual Offset register)
bx lr

113
ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S
View File

@@ -2,6 +2,7 @@
#
# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
# Copyright (c) 2016, Linaro Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@@ -13,45 +14,7 @@
#
#------------------------------------------------------------------------------
.text
.align 2
GCC_ASM_EXPORT (ArmInvalidateInstructionCache)
GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryByMVA)
GCC_ASM_EXPORT (ArmInvalidateInstructionCacheEntryToPoUByMVA)
GCC_ASM_EXPORT (ArmCleanDataCacheEntryByMVA)
GCC_ASM_EXPORT (ArmCleanDataCacheEntryToPoUByMVA)
GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryByMVA)
GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryBySetWay)
GCC_ASM_EXPORT (ArmCleanDataCacheEntryBySetWay)
GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryBySetWay)
GCC_ASM_EXPORT (ArmEnableMmu)
GCC_ASM_EXPORT (ArmDisableMmu)
GCC_ASM_EXPORT (ArmDisableCachesAndMmu)
GCC_ASM_EXPORT (ArmMmuEnabled)
GCC_ASM_EXPORT (ArmEnableDataCache)
GCC_ASM_EXPORT (ArmDisableDataCache)
GCC_ASM_EXPORT (ArmEnableInstructionCache)
GCC_ASM_EXPORT (ArmDisableInstructionCache)
GCC_ASM_EXPORT (ArmEnableSWPInstruction)
GCC_ASM_EXPORT (ArmEnableBranchPrediction)
GCC_ASM_EXPORT (ArmDisableBranchPrediction)
GCC_ASM_EXPORT (ArmSetLowVectors)
GCC_ASM_EXPORT (ArmSetHighVectors)
GCC_ASM_EXPORT (ArmV7AllDataCachesOperation)
GCC_ASM_EXPORT (ArmDataMemoryBarrier)
GCC_ASM_EXPORT (ArmDataSynchronizationBarrier)
GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier)
GCC_ASM_EXPORT (ArmReadVBar)
GCC_ASM_EXPORT (ArmWriteVBar)
GCC_ASM_EXPORT (ArmEnableVFP)
GCC_ASM_EXPORT (ArmCallWFI)
GCC_ASM_EXPORT (ArmReadCbar)
GCC_ASM_EXPORT (ArmReadMpidr)
GCC_ASM_EXPORT (ArmReadTpidrurw)
GCC_ASM_EXPORT (ArmWriteTpidrurw)
GCC_ASM_EXPORT (ArmIsArchTimerImplemented)
GCC_ASM_EXPORT (ArmReadIdPfr1)
#include <AsmMacroIoLib.h>
.set DC_ON, (0x1<<2)
.set IC_ON, (0x1<<12)
@@ -61,50 +24,50 @@ GCC_ASM_EXPORT (ArmReadIdPfr1)
.set CTRL_I_BIT, (1 << 12)
ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
ASM_FUNC(ArmInvalidateDataCacheEntryByMVA)
mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line
bx lr
ASM_PFX(ArmCleanDataCacheEntryByMVA):
ASM_FUNC(ArmCleanDataCacheEntryByMVA)
mcr p15, 0, r0, c7, c10, 1 @clean single data cache line
bx lr
ASM_PFX(ArmCleanDataCacheEntryToPoUByMVA):
ASM_FUNC(ArmCleanDataCacheEntryToPoUByMVA)
mcr p15, 0, r0, c7, c11, 1 @clean single data cache line to PoU
bx lr
ASM_PFX(ArmInvalidateInstructionCacheEntryToPoUByMVA):
ASM_FUNC(ArmInvalidateInstructionCacheEntryToPoUByMVA)
mcr p15, 0, r0, c7, c5, 1 @Invalidate single instruction cache line to PoU
mcr p15, 0, r0, c7, c5, 7 @Invalidate branch predictor
bx lr
ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
ASM_FUNC(ArmCleanInvalidateDataCacheEntryByMVA)
mcr p15, 0, r0, c7, c14, 1 @clean and invalidate single data cache line
bx lr
ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):
ASM_FUNC(ArmInvalidateDataCacheEntryBySetWay)
mcr p15, 0, r0, c7, c6, 2 @ Invalidate this line
bx lr
ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):
ASM_FUNC(ArmCleanInvalidateDataCacheEntryBySetWay)
mcr p15, 0, r0, c7, c14, 2 @ Clean and Invalidate this line
bx lr
ASM_PFX(ArmCleanDataCacheEntryBySetWay):
ASM_FUNC(ArmCleanDataCacheEntryBySetWay)
mcr p15, 0, r0, c7, c10, 2 @ Clean this line
bx lr
ASM_PFX(ArmInvalidateInstructionCache):
ASM_FUNC(ArmInvalidateInstructionCache)
mcr p15,0,R0,c7,c5,0 @Invalidate entire instruction cache
dsb
isb
bx LR
ASM_PFX(ArmEnableMmu):
ASM_FUNC(ArmEnableMmu)
mrc p15,0,R0,c1,c0,0
orr R0,R0,#1
mcr p15,0,R0,c1,c0,0
@@ -113,7 +76,7 @@ ASM_PFX(ArmEnableMmu):
bx LR
ASM_PFX(ArmDisableMmu):
ASM_FUNC(ArmDisableMmu)
mrc p15,0,R0,c1,c0,0
bic R0,R0,#1
mcr p15,0,R0,c1,c0,0 @Disable MMU
@@ -124,7 +87,7 @@ ASM_PFX(ArmDisableMmu):
isb
bx LR
ASM_PFX(ArmDisableCachesAndMmu):
ASM_FUNC(ArmDisableCachesAndMmu)
mrc p15, 0, r0, c1, c0, 0 @ Get control register
bic r0, r0, #CTRL_M_BIT @ Disable MMU
bic r0, r0, #CTRL_C_BIT @ Disable D Cache
@@ -134,12 +97,12 @@ ASM_PFX(ArmDisableCachesAndMmu):
isb
bx LR
ASM_PFX(ArmMmuEnabled):
ASM_FUNC(ArmMmuEnabled)
mrc p15,0,R0,c1,c0,0
and R0,R0,#1
bx LR
ASM_PFX(ArmEnableDataCache):
ASM_FUNC(ArmEnableDataCache)
ldr R1,=DC_ON
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
orr R0,R0,R1 @Set C bit
@@ -148,7 +111,7 @@ ASM_PFX(ArmEnableDataCache):
isb
bx LR
ASM_PFX(ArmDisableDataCache):
ASM_FUNC(ArmDisableDataCache)
ldr R1,=DC_ON
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
bic R0,R0,R1 @Clear C bit
@@ -157,7 +120,7 @@ ASM_PFX(ArmDisableDataCache):
isb
bx LR
ASM_PFX(ArmEnableInstructionCache):
ASM_FUNC(ArmEnableInstructionCache)
ldr R1,=IC_ON
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
orr R0,R0,R1 @Set I bit
@@ -166,7 +129,7 @@ ASM_PFX(ArmEnableInstructionCache):
isb
bx LR
ASM_PFX(ArmDisableInstructionCache):
ASM_FUNC(ArmDisableInstructionCache)
ldr R1,=IC_ON
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
bic R0,R0,R1 @Clear I bit.
@@ -175,14 +138,14 @@ ASM_PFX(ArmDisableInstructionCache):
isb
bx LR
ASM_PFX(ArmEnableSWPInstruction):
ASM_FUNC(ArmEnableSWPInstruction)
mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #0x00000400
mcr p15, 0, r0, c1, c0, 0
isb
bx LR
ASM_PFX(ArmEnableBranchPrediction):
ASM_FUNC(ArmEnableBranchPrediction)
mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #0x00000800
mcr p15, 0, r0, c1, c0, 0
@@ -190,7 +153,7 @@ ASM_PFX(ArmEnableBranchPrediction):
isb
bx LR
ASM_PFX(ArmDisableBranchPrediction):
ASM_FUNC(ArmDisableBranchPrediction)
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x00000800
mcr p15, 0, r0, c1, c0, 0
@@ -198,21 +161,21 @@ ASM_PFX(ArmDisableBranchPrediction):
isb
bx LR
ASM_PFX(ArmSetLowVectors):
ASM_FUNC(ArmSetLowVectors)
mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
bic r0, r0, #0x00002000 @ clear V bit
mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
isb
bx LR
ASM_PFX(ArmSetHighVectors):
ASM_FUNC(ArmSetHighVectors)
mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
orr r0, r0, #0x00002000 @ Set V bit
mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
isb
bx LR
ASM_PFX(ArmV7AllDataCachesOperation):
ASM_FUNC(ArmV7AllDataCachesOperation)
stmfd SP!,{r4-r12, LR}
mov R1, R0 @ Save Function call in R1
mrc p15, 1, R6, c0, c0, 1 @ Read CLIDR
@@ -265,24 +228,24 @@ L_Finished:
ldmfd SP!, {r4-r12, lr}
bx LR
ASM_PFX(ArmDataMemoryBarrier):
ASM_FUNC(ArmDataMemoryBarrier)
dmb
bx LR
ASM_PFX(ArmDataSynchronizationBarrier):
ASM_FUNC(ArmDataSynchronizationBarrier)
dsb
bx LR
ASM_PFX(ArmInstructionSynchronizationBarrier):
ASM_FUNC(ArmInstructionSynchronizationBarrier)
isb
bx LR
ASM_PFX(ArmReadVBar):
ASM_FUNC(ArmReadVBar)
# Set the Address of the Vector Table in the VBAR register
mrc p15, 0, r0, c12, c0, 0
bx lr
ASM_PFX(ArmWriteVBar):
ASM_FUNC(ArmWriteVBar)
# Set the Address of the Vector Table in the VBAR register
mcr p15, 0, r0, c12, c0, 0
# Ensure the SCTLR.V bit is clear
@@ -292,7 +255,7 @@ ASM_PFX(ArmWriteVBar):
isb
bx lr
ASM_PFX(ArmEnableVFP):
ASM_FUNC(ArmEnableVFP)
# Read CPACR (Coprocessor Access Control Register)
mrc p15, 0, r0, c1, c0, 2
# Enable VPF access (Full Access to CP10, CP11) (V* instructions)
@@ -309,33 +272,33 @@ ASM_PFX(ArmEnableVFP):
#endif
bx lr
ASM_PFX(ArmCallWFI):
ASM_FUNC(ArmCallWFI)
wfi
bx lr
#Note: Return 0 in Uniprocessor implementation
ASM_PFX(ArmReadCbar):
ASM_FUNC(ArmReadCbar)
mrc p15, 4, r0, c15, c0, 0 @ Read Configuration Base Address Register
bx lr
ASM_PFX(ArmReadMpidr):
ASM_FUNC(ArmReadMpidr)
mrc p15, 0, r0, c0, c0, 5 @ read MPIDR
bx lr
ASM_PFX(ArmReadTpidrurw):
ASM_FUNC(ArmReadTpidrurw)
mrc p15, 0, r0, c13, c0, 2 @ read TPIDRURW
bx lr
ASM_PFX(ArmWriteTpidrurw):
ASM_FUNC(ArmWriteTpidrurw)
mcr p15, 0, r0, c13, c0, 2 @ write TPIDRURW
bx lr
ASM_PFX(ArmIsArchTimerImplemented):
ASM_FUNC(ArmIsArchTimerImplemented)
mrc p15, 0, r0, c0, c1, 1 @ Read ID_PFR1
and r0, r0, #0x000F0000
bx lr
ASM_PFX(ArmReadIdPfr1):
ASM_FUNC(ArmReadIdPfr1)
mrc p15, 0, r0, c0, c1, 1 @ Read ID_PFR1 Register
bx lr