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ArmPkg/ArmLib: switch to ASM_FUNC() asm macro

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Annotate functions with ASM_FUNC() so that they are emitted into
separate sections.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
This commit is contained in:
Ard Biesheuvel
2016-08-10 14:35:01 +02:00
parent de656e666c
commit 0efaa42f6e
9 changed files with 203 additions and 422 deletions
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78
ArmPkg/Library/ArmLib/Common/AArch64/ArmLibSupport.S
View File

@@ -2,6 +2,7 @@
#
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
# Copyright (c) 2011 - 2016, ARM Limited. All rights reserved.
# Copyright (c) 2016, Linaro Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@@ -15,76 +16,48 @@
#include <AsmMacroIoLibV8.h>
.text
.align 3
GCC_ASM_EXPORT (ArmReadMidr)
GCC_ASM_EXPORT (ArmCacheInfo)
GCC_ASM_EXPORT (ArmGetInterruptState)
GCC_ASM_EXPORT (ArmGetFiqState)
GCC_ASM_EXPORT (ArmGetTTBR0BaseAddress)
GCC_ASM_EXPORT (ArmSetTTBR0)
GCC_ASM_EXPORT (ArmGetTCR)
GCC_ASM_EXPORT (ArmSetTCR)
GCC_ASM_EXPORT (ArmGetMAIR)
GCC_ASM_EXPORT (ArmSetMAIR)
GCC_ASM_EXPORT (ArmWriteCpacr)
GCC_ASM_EXPORT (ArmWriteAuxCr)
GCC_ASM_EXPORT (ArmReadAuxCr)
GCC_ASM_EXPORT (ArmInvalidateTlb)
GCC_ASM_EXPORT (ArmUpdateTranslationTableEntry)
GCC_ASM_EXPORT (ArmWriteCptr)
GCC_ASM_EXPORT (ArmWriteScr)
GCC_ASM_EXPORT (ArmWriteMVBar)
GCC_ASM_EXPORT (ArmCallWFE)
GCC_ASM_EXPORT (ArmCallSEV)
GCC_ASM_EXPORT (ArmReadCpuActlr)
GCC_ASM_EXPORT (ArmWriteCpuActlr)
GCC_ASM_EXPORT (ArmReadSctlr)
#------------------------------------------------------------------------------
.set DAIF_RD_FIQ_BIT, (1 << 6)
.set DAIF_RD_IRQ_BIT, (1 << 7)
ASM_PFX(ArmReadMidr):
ASM_FUNC(ArmReadMidr)
mrs x0, midr_el1 // Read from Main ID Register (MIDR)
ret
ASM_PFX(ArmCacheInfo):
ASM_FUNC(ArmCacheInfo)
mrs x0, ctr_el0 // Read from Cache Type Regiter (CTR)
ret
ASM_PFX(ArmGetInterruptState):
ASM_FUNC(ArmGetInterruptState)
mrs x0, daif
tst w0, #DAIF_RD_IRQ_BIT // Check if IRQ is enabled. Enabled if 0 (Z=1)
cset w0, eq // if Z=1 return 1, else 0
ret
ASM_PFX(ArmGetFiqState):
ASM_FUNC(ArmGetFiqState)
mrs x0, daif
tst w0, #DAIF_RD_FIQ_BIT // Check if FIQ is enabled. Enabled if 0 (Z=1)
cset w0, eq // if Z=1 return 1, else 0
ret
ASM_PFX(ArmWriteCpacr):
ASM_FUNC(ArmWriteCpacr)
msr cpacr_el1, x0 // Coprocessor Access Control Reg (CPACR)
ret
ASM_PFX(ArmWriteAuxCr):
ASM_FUNC(ArmWriteAuxCr)
EL1_OR_EL2(x1)
1:msr actlr_el1, x0 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3
ret
2:msr actlr_el2, x0 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3
ret
ASM_PFX(ArmReadAuxCr):
ASM_FUNC(ArmReadAuxCr)
EL1_OR_EL2(x1)
1:mrs x0, actlr_el1 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3
ret
2:mrs x0, actlr_el2 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3
ret
ASM_PFX(ArmSetTTBR0):
ASM_FUNC(ArmSetTTBR0)
EL1_OR_EL2_OR_EL3(x1)
1:msr ttbr0_el1, x0 // Translation Table Base Reg 0 (TTBR0)
b 4f
@@ -94,17 +67,16 @@ ASM_PFX(ArmSetTTBR0):
4:isb
ret
ASM_PFX(ArmGetTTBR0BaseAddress):
ASM_FUNC(ArmGetTTBR0BaseAddress)
EL1_OR_EL2(x1)
1:mrs x0, ttbr0_el1
b 3f
2:mrs x0, ttbr0_el2
3:LoadConstantToReg(0xFFFFFFFFFFFF, x1) /* Look at bottom 48 bits */
and x0, x0, x1
3:and x0, x0, 0xFFFFFFFFFFFF /* Look at bottom 48 bits */
isb
ret
ASM_PFX(ArmGetTCR):
ASM_FUNC(ArmGetTCR)
EL1_OR_EL2_OR_EL3(x1)
1:mrs x0, tcr_el1
b 4f
@@ -114,7 +86,7 @@ ASM_PFX(ArmGetTCR):
4:isb
ret
ASM_PFX(ArmSetTCR):
ASM_FUNC(ArmSetTCR)
EL1_OR_EL2_OR_EL3(x1)
1:msr tcr_el1, x0
b 4f
@@ -124,7 +96,7 @@ ASM_PFX(ArmSetTCR):
4:isb
ret
ASM_PFX(ArmGetMAIR):
ASM_FUNC(ArmGetMAIR)
EL1_OR_EL2_OR_EL3(x1)
1:mrs x0, mair_el1
b 4f
@@ -134,7 +106,7 @@ ASM_PFX(ArmGetMAIR):
4:isb
ret
ASM_PFX(ArmSetMAIR):
ASM_FUNC(ArmSetMAIR)
EL1_OR_EL2_OR_EL3(x1)
1:msr mair_el1, x0
b 4f
@@ -151,7 +123,7 @@ ASM_PFX(ArmSetMAIR):
// IN VOID *TranslationTableEntry // X0
// IN VOID *MVA // X1
// );
ASM_PFX(ArmUpdateTranslationTableEntry):
ASM_FUNC(ArmUpdateTranslationTableEntry)
dc civac, x0 // Clean and invalidate data line
dsb sy
EL1_OR_EL2_OR_EL3(x0)
@@ -164,7 +136,7 @@ ASM_PFX(ArmUpdateTranslationTableEntry):
isb
ret
ASM_PFX(ArmInvalidateTlb):
ASM_FUNC(ArmInvalidateTlb)
EL1_OR_EL2_OR_EL3(x0)
1: tlbi vmalle1
b 4f
@@ -175,38 +147,38 @@ ASM_PFX(ArmInvalidateTlb):
isb
ret
ASM_PFX(ArmWriteCptr):
ASM_FUNC(ArmWriteCptr)
msr cptr_el3, x0 // EL3 Coprocessor Trap Reg (CPTR)
ret
ASM_PFX(ArmWriteScr):
ASM_FUNC(ArmWriteScr)
msr scr_el3, x0 // Secure configuration register EL3
isb
ret
ASM_PFX(ArmWriteMVBar):
ASM_FUNC(ArmWriteMVBar)
msr vbar_el3, x0 // Exception Vector Base address for Monitor on EL3
ret
ASM_PFX(ArmCallWFE):
ASM_FUNC(ArmCallWFE)
wfe
ret
ASM_PFX(ArmCallSEV):
ASM_FUNC(ArmCallSEV)
sev
ret
ASM_PFX(ArmReadCpuActlr):
ASM_FUNC(ArmReadCpuActlr)
mrs x0, S3_1_c15_c2_0
ret
ASM_PFX(ArmWriteCpuActlr):
ASM_FUNC(ArmWriteCpuActlr)
msr S3_1_c15_c2_0, x0
dsb sy
isb
ret
ASM_PFX(ArmReadSctlr):
ASM_FUNC(ArmReadSctlr)
EL1_OR_EL2_OR_EL3(x1)
1:mrs x0, sctlr_el1
ret

89
ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S
View File

@@ -2,6 +2,7 @@
#
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
# Copyright (c) 2011 - 2016, ARM Limited. All rights reserved.
# Copyright (c) 2016, Linaro Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@@ -15,65 +16,33 @@
#include <AsmMacroIoLib.h>
.text
.align 2
GCC_ASM_EXPORT(ArmReadMidr)
GCC_ASM_EXPORT(ArmCacheInfo)
GCC_ASM_EXPORT(ArmGetInterruptState)
GCC_ASM_EXPORT(ArmGetFiqState)
GCC_ASM_EXPORT(ArmGetTTBR0BaseAddress)
GCC_ASM_EXPORT(ArmSetTTBR0)
GCC_ASM_EXPORT(ArmSetTTBCR)
GCC_ASM_EXPORT(ArmSetDomainAccessControl)
GCC_ASM_EXPORT(CPSRMaskInsert)
GCC_ASM_EXPORT(CPSRRead)
GCC_ASM_EXPORT(ArmReadCpacr)
GCC_ASM_EXPORT(ArmWriteCpacr)
GCC_ASM_EXPORT(ArmWriteAuxCr)
GCC_ASM_EXPORT(ArmReadAuxCr)
GCC_ASM_EXPORT(ArmInvalidateTlb)
GCC_ASM_EXPORT(ArmUpdateTranslationTableEntry)
GCC_ASM_EXPORT(ArmReadScr)
GCC_ASM_EXPORT(ArmWriteScr)
GCC_ASM_EXPORT(ArmReadMVBar)
GCC_ASM_EXPORT(ArmWriteMVBar)
GCC_ASM_EXPORT(ArmReadHVBar)
GCC_ASM_EXPORT(ArmWriteHVBar)
GCC_ASM_EXPORT(ArmCallWFE)
GCC_ASM_EXPORT(ArmCallSEV)
GCC_ASM_EXPORT(ArmReadSctlr)
GCC_ASM_EXPORT(ArmReadCpuActlr)
GCC_ASM_EXPORT(ArmWriteCpuActlr)
#------------------------------------------------------------------------------
ASM_PFX(ArmReadMidr):
ASM_FUNC(ArmReadMidr)
mrc p15,0,R0,c0,c0,0
bx LR
ASM_PFX(ArmCacheInfo):
ASM_FUNC(ArmCacheInfo)
mrc p15,0,R0,c0,c0,1
bx LR
ASM_PFX(ArmGetInterruptState):
ASM_FUNC(ArmGetInterruptState)
mrs R0,CPSR
tst R0,#0x80 @Check if IRQ is enabled.
moveq R0,#1
movne R0,#0
bx LR
ASM_PFX(ArmGetFiqState):
ASM_FUNC(ArmGetFiqState)
mrs R0,CPSR
tst R0,#0x40 @Check if FIQ is enabled.
moveq R0,#1
movne R0,#0
bx LR
ASM_PFX(ArmSetDomainAccessControl):
ASM_FUNC(ArmSetDomainAccessControl)
mcr p15,0,r0,c3,c0,0
bx lr
ASM_PFX(CPSRMaskInsert): @ on entry, r0 is the mask and r1 is the field to insert
ASM_FUNC(CPSRMaskInsert) @ on entry, r0 is the mask and r1 is the field to insert
stmfd sp!, {r4-r12, lr} @ save all the banked registers
mov r3, sp @ copy the stack pointer into a non-banked register
mrs r2, cpsr @ read the cpsr
@@ -86,40 +55,40 @@ ASM_PFX(CPSRMaskInsert): @ on entry, r0 is the mask and r1 is the field to in
ldmfd sp!, {r4-r12, lr} @ restore registers
bx lr @ return (hopefully thumb-safe!)
ASM_PFX(CPSRRead):
ASM_FUNC(CPSRRead)
mrs r0, cpsr
bx lr
ASM_PFX(ArmReadCpacr):
ASM_FUNC(ArmReadCpacr)
mrc p15, 0, r0, c1, c0, 2
bx lr
ASM_PFX(ArmWriteCpacr):
ASM_FUNC(ArmWriteCpacr)
mcr p15, 0, r0, c1, c0, 2
isb
bx lr
ASM_PFX(ArmWriteAuxCr):
ASM_FUNC(ArmWriteAuxCr)
mcr p15, 0, r0, c1, c0, 1
bx lr
ASM_PFX(ArmReadAuxCr):
ASM_FUNC(ArmReadAuxCr)
mrc p15, 0, r0, c1, c0, 1
bx lr
ASM_PFX(ArmSetTTBR0):
ASM_FUNC(ArmSetTTBR0)
mcr p15,0,r0,c2,c0,0
isb
bx lr
ASM_PFX(ArmSetTTBCR):
ASM_FUNC(ArmSetTTBCR)
mcr p15, 0, r0, c2, c0, 2
isb
bx lr
ASM_PFX(ArmGetTTBR0BaseAddress):
ASM_FUNC(ArmGetTTBR0BaseAddress)
mrc p15,0,r0,c2,c0,0
LoadConstantToReg(0xFFFFC000, r1)
MOV32 (r1, 0xFFFFC000)
and r0, r0, r1
isb
bx lr
@@ -130,7 +99,7 @@ ASM_PFX(ArmGetTTBR0BaseAddress):
// IN VOID *TranslationTableEntry // R0
// IN VOID *MVA // R1
// );
ASM_PFX(ArmUpdateTranslationTableEntry):
ASM_FUNC(ArmUpdateTranslationTableEntry)
mcr p15,0,R0,c7,c14,1 @ DCCIMVAC Clean data cache by MVA
dsb
mcr p15,0,R1,c8,c7,1 @ TLBIMVA TLB Invalidate MVA
@@ -139,7 +108,7 @@ ASM_PFX(ArmUpdateTranslationTableEntry):
isb
bx lr
ASM_PFX(ArmInvalidateTlb):
ASM_FUNC(ArmInvalidateTlb)
mov r0,#0
mcr p15,0,r0,c8,c7,0
mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp
@@ -147,48 +116,48 @@ ASM_PFX(ArmInvalidateTlb):
isb
bx lr
ASM_PFX(ArmReadScr):
ASM_FUNC(ArmReadScr)
mrc p15, 0, r0, c1, c1, 0
bx lr
ASM_PFX(ArmWriteScr):
ASM_FUNC(ArmWriteScr)
mcr p15, 0, r0, c1, c1, 0
isb
bx lr
ASM_PFX(ArmReadHVBar):
ASM_FUNC(ArmReadHVBar)
mrc p15, 4, r0, c12, c0, 0
bx lr
ASM_PFX(ArmWriteHVBar):
ASM_FUNC(ArmWriteHVBar)
mcr p15, 4, r0, c12, c0, 0
bx lr
ASM_PFX(ArmReadMVBar):
ASM_FUNC(ArmReadMVBar)
mrc p15, 0, r0, c12, c0, 1
bx lr
ASM_PFX(ArmWriteMVBar):
ASM_FUNC(ArmWriteMVBar)
mcr p15, 0, r0, c12, c0, 1
bx lr
ASM_PFX(ArmCallWFE):
ASM_FUNC(ArmCallWFE)
wfe
bx lr
ASM_PFX(ArmCallSEV):
ASM_FUNC(ArmCallSEV)
sev
bx lr
ASM_PFX(ArmReadSctlr):
ASM_FUNC(ArmReadSctlr)
mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
bx lr
ASM_PFX(ArmReadCpuActlr):
ASM_FUNC(ArmReadCpuActlr)
mrc p15, 0, r0, c1, c0, 1
bx lr
ASM_PFX(ArmWriteCpuActlr):
ASM_FUNC(ArmWriteCpuActlr)
mcr p15, 0, r0, c1, c0, 1
dsb
isb

4
ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm
View File

@@ -13,8 +13,6 @@
//
//------------------------------------------------------------------------------
#include <AsmMacroIoLib.h>
INCLUDE AsmMacroIoLib.inc
@@ -92,7 +90,7 @@
RVCT_ASM_EXPORT ArmGetTTBR0BaseAddress
mrc p15,0,r0,c2,c0,0
LoadConstantToReg(0xFFFFC000, r1)
MOV32 r1, 0xFFFFC000
and r0, r0, r1
isb
bx lr