sravan/system76-edk2
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

UefiCpuPkg/Include: Update MSR header files with SDM (Sep.2016)

Browse Source 
https://bugzilla.tianocore.org/show_bug.cgi?id=176

Update MSR header files of processors (excluding Goldmont and Skylake
processors) according to Intel(R) 64 and IA-32 Architectures Software
Developer's Manual, Volume 3, September 2016, Chapter 35
Model-Specific-Registers (MSR).

Summary of incompatible changes:
General:
1. MSR (address 38EH) IA32_PERF_GLOBAL_STAUS in processor-specific header
files has been removed or renamed to IA32_PERF_GLOBAL_STATUS
Typo 'STAUS' has been fixed in SDM.
If the MSR definition is the same with architectural MSR, we remove it.
Otherwise, we rename the MSR.

2. MSRs (address starting from 400H) MSR_MC{X}_{XXX} (like MSR_MC4_STATUS)
in processor-specific header files have been removed or renamed to
IA32_MC{X}_{XXX} (like IA32_MC4_STATUS)
Register name change from 'MSR_MC{X}_{XXX}' to 'IA32_MC{X}_{XXX}' in SDM.
If the MSR definition is the same with architectural MSR, we remove it.
Otherwise, we rename the MSR.
Please note that for those MSRs still have name like 'MSR_MC{X}_{XXX}' in
SDM are still kept in processor-specific header files.

HaswellMsr.h:
1. MSR (address C80H) IA32_DEBUG_FEATURE has been removed
Register name change from 'IA32_DEBUG_FEATURE' to 'IA32_DEBUG_INTERFACE'
in SDM.
Since the MSR definition is the same with architectural MSR, we remove it.

SandyBridgeMsr.h:
1. MSR (address 391H) MSR_UNC_PERF_GLOBAL_CTRL, name change for bit fields
0:3
Bit description change from 'Core {X} select' to 'Slice {X} select' for
bit 0:3 in SDM.

SilvermontMsr.h:
1. MSR (address 2AH) MSR_EBL_CR_POWERON, structure definition changed
Bit description for this MSR is totally changed in SDM, we modify the
structure definition to align with it.

XeonDMsr.h:
1. MSRs (address 630H to 632H) MSR_PKG_C8_RESIDENCY, MSR_PKG_C9_RESIDENCY
and MSR_PKG_C10_RESIDENCY have been removed
Those 3 MSRs are not defined for this processor in SDM, we remove them.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
This commit is contained in:
Hao Wu
2016-10-25 13:35:54 +08:00
parent 7dede0a219
commit 0f16be6d9e
19 changed files with 1335 additions and 2679 deletions
Download Patch File Download Diff File Expand all files Collapse all files

146
UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h
View File

@@ -17,7 +17,7 @@
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-16.
September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.18.
**/
@@ -927,8 +927,8 @@ typedef union {
///
UINT32 BTS:1;
///
/// [Bit 12] PEBS_UNAVILABLE: Precise Event Based Sampling Unavailable (R)
/// See Table 35-2. When set, the processor does not support precise
/// [Bit 12] PEBS_UNAVILABLE: Processor Event Based Sampling Unavailable
/// (R) See Table 35-2. When set, the processor does not support processor
/// event-based sampling (PEBS); when clear, PEBS is supported.
///
UINT32 PEBS:1;
@@ -1053,7 +1053,7 @@ typedef union {
0, 1, 2, 3, 4, 6. Unique. Last Exception Record From Linear IP (R) Contains
a pointer to the last branch instruction that the processor executed prior
to the last exception that was generated or the last interrupt that was
handled. See Section 17.10.3, "Last Exception Records.". Unique. From Linear
handled. See Section 17.11.3, "Last Exception Records.". Unique. From Linear
IP Linear address of the last branch instruction (If IA32e mode is active).
From Linear IP Linear address of the last branch instruction. Reserved.
@@ -1076,7 +1076,7 @@ typedef union {
0, 1, 2, 3, 4, 6. Unique. Last Exception Record To Linear IP (R) This area
contains a pointer to the target of the last branch instruction that the
processor executed prior to the last exception that was generated or the
last interrupt that was handled. See Section 17.10.3, "Last Exception
last interrupt that was handled. See Section 17.11.3, "Last Exception
Records.". Unique. From Linear IP Linear address of the target of the last
branch instruction (If IA-32e mode is active). From Linear IP Linear address
of the target of the last branch instruction. Reserved.
@@ -1099,7 +1099,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Unique. Debug Control (R/W) Controls how several debug
features are used. Bit definitions are discussed in the referenced section.
See Section 17.10.1, "MSR_DEBUGCTLA MSR.".
See Section 17.11.1, "MSR_DEBUGCTLA MSR.".
@param ECX MSR_PENTIUM_4_DEBUGCTLA (0x000001D9)
@param EAX Lower 32-bits of MSR value.
@@ -1121,7 +1121,7 @@ typedef union {
0, 1, 2, 3, 4, 6. Unique. Last Branch Record Stack TOS (R/W) Contains an
index (0-3 or 0-15) that points to the top of the last branch record stack
(that is, that points the index of the MSR containing the most recent branch
record). See Section 17.10.2, "LBR Stack for Processors Based on Intel
record). See Section 17.11.2, "LBR Stack for Processors Based on Intel
NetBurst(R) Microarchitecture"; and addresses 1DBH-1DEH and 680H-68FH.
@param ECX MSR_PENTIUM_4_LASTBRANCH_TOS (0x000001DA)
@@ -1147,7 +1147,7 @@ typedef union {
exceptions, or interrupts that the processor took. MSR_LASTBRANCH_0 through
MSR_LASTBRANCH_3 at 1DBH-1DEH are available only on family 0FH, models
0H-02H. They have been replaced by the MSRs at 680H68FH and 6C0H-6CFH. See
Section 17.9, "Last Branch, Call Stack, Interrupt, and Exception Recording
Section 17.10, "Last Branch, Call Stack, Interrupt, and Exception Recording
for Processors based on Skylake Microarchitecture.".
@param ECX MSR_PENTIUM_4_LASTBRANCH_n
@@ -1175,7 +1175,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.12.2, "Performance Counters.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.2, "Performance Counters.".
@param ECX MSR_PENTIUM_4_BPU_COUNTERn
@param EAX Lower 32-bits of MSR value.
@@ -1202,7 +1202,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.12.2, "Performance Counters.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.2, "Performance Counters.".
@param ECX MSR_PENTIUM_4_MS_COUNTERn
@param EAX Lower 32-bits of MSR value.
@@ -1229,7 +1229,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.12.2, "Performance Counters.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.2, "Performance Counters.".
@param ECX MSR_PENTIUM_4_FLAME_COUNTERn (0x00000308)
@param EAX Lower 32-bits of MSR value.
@@ -1256,7 +1256,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.12.2, "Performance Counters.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.2, "Performance Counters.".
@param ECX MSR_PENTIUM_4_IQ_COUNTERn
@param EAX Lower 32-bits of MSR value.
@@ -1287,7 +1287,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.12.3, "CCCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.3, "CCCR MSRs.".
@param ECX MSR_PENTIUM_4_BPU_CCCRn
@param EAX Lower 32-bits of MSR value.
@@ -1314,7 +1314,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.12.3, "CCCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.3, "CCCR MSRs.".
@param ECX MSR_PENTIUM_4_MS_CCCRn
@param EAX Lower 32-bits of MSR value.
@@ -1341,7 +1341,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.12.3, "CCCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.3, "CCCR MSRs.".
@param ECX MSR_PENTIUM_4_FLAME_CCCRn
@param EAX Lower 32-bits of MSR value.
@@ -1368,7 +1368,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.12.3, "CCCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.3, "CCCR MSRs.".
@param ECX MSR_PENTIUM_4_IQ_CCCRn
@param EAX Lower 32-bits of MSR value.
@@ -1399,7 +1399,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_BSU_ESCR0 (0x000003A0)
@param EAX Lower 32-bits of MSR value.
@@ -1418,7 +1418,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_BSU_ESCR1 (0x000003A1)
@param EAX Lower 32-bits of MSR value.
@@ -1437,7 +1437,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_FSB_ESCR0 (0x000003A2)
@param EAX Lower 32-bits of MSR value.
@@ -1456,7 +1456,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_FSB_ESCR1 (0x000003A3)
@param EAX Lower 32-bits of MSR value.
@@ -1475,7 +1475,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_FIRM_ESCR0 (0x000003A4)
@param EAX Lower 32-bits of MSR value.
@@ -1494,7 +1494,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_FIRM_ESCR1 (0x000003A5)
@param EAX Lower 32-bits of MSR value.
@@ -1513,7 +1513,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_FLAME_ESCR0 (0x000003A6)
@param EAX Lower 32-bits of MSR value.
@@ -1532,7 +1532,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_FLAME_ESCR1 (0x000003A7)
@param EAX Lower 32-bits of MSR value.
@@ -1551,7 +1551,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_DAC_ESCR0 (0x000003A8)
@param EAX Lower 32-bits of MSR value.
@@ -1570,7 +1570,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_DAC_ESCR1 (0x000003A9)
@param EAX Lower 32-bits of MSR value.
@@ -1589,7 +1589,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_MOB_ESCR0 (0x000003AA)
@param EAX Lower 32-bits of MSR value.
@@ -1608,7 +1608,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_MOB_ESCR1 (0x000003AB)
@param EAX Lower 32-bits of MSR value.
@@ -1627,7 +1627,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_PMH_ESCR0 (0x000003AC)
@param EAX Lower 32-bits of MSR value.
@@ -1646,7 +1646,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_PMH_ESCR1 (0x000003AD)
@param EAX Lower 32-bits of MSR value.
@@ -1665,7 +1665,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_SAAT_ESCR0 (0x000003AE)
@param EAX Lower 32-bits of MSR value.
@@ -1684,7 +1684,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_SAAT_ESCR1 (0x000003AF)
@param EAX Lower 32-bits of MSR value.
@@ -1703,7 +1703,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_U2L_ESCR0 (0x000003B0)
@param EAX Lower 32-bits of MSR value.
@@ -1722,7 +1722,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_U2L_ESCR1 (0x000003B1)
@param EAX Lower 32-bits of MSR value.
@@ -1741,7 +1741,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_BPU_ESCR0 (0x000003B2)
@param EAX Lower 32-bits of MSR value.
@@ -1760,7 +1760,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_BPU_ESCR1 (0x000003B3)
@param EAX Lower 32-bits of MSR value.
@@ -1779,7 +1779,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_IS_ESCR0 (0x000003B4)
@param EAX Lower 32-bits of MSR value.
@@ -1798,7 +1798,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_IS_ESCR1 (0x000003B5)
@param EAX Lower 32-bits of MSR value.
@@ -1817,7 +1817,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_ITLB_ESCR0 (0x000003B6)
@param EAX Lower 32-bits of MSR value.
@@ -1836,7 +1836,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_ITLB_ESCR1 (0x000003B7)
@param EAX Lower 32-bits of MSR value.
@@ -1855,7 +1855,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_CRU_ESCR0 (0x000003B8)
@param EAX Lower 32-bits of MSR value.
@@ -1874,7 +1874,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_CRU_ESCR1 (0x000003B9)
@param EAX Lower 32-bits of MSR value.
@@ -1893,7 +1893,7 @@ typedef union {
/**
0, 1, 2. Shared. See Section 18.12.1, "ESCR MSRs." This MSR is not available
0, 1, 2. Shared. See Section 18.15.1, "ESCR MSRs." This MSR is not available
on later processors. It is only available on processor family 0FH, models
01H-02H.
@@ -1914,7 +1914,7 @@ typedef union {
/**
0, 1, 2. Shared. See Section 18.12.1, "ESCR MSRs." This MSR is not available
0, 1, 2. Shared. See Section 18.15.1, "ESCR MSRs." This MSR is not available
on later processors. It is only available on processor family 0FH, models
01H-02H.
@@ -1935,7 +1935,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_RAT_ESCR0 (0x000003BC)
@param EAX Lower 32-bits of MSR value.
@@ -1954,7 +1954,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_RAT_ESCR1 (0x000003BD)
@param EAX Lower 32-bits of MSR value.
@@ -1973,7 +1973,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_SSU_ESCR0 (0x000003BE)
@param EAX Lower 32-bits of MSR value.
@@ -1992,7 +1992,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_MS_ESCR0 (0x000003C0)
@param EAX Lower 32-bits of MSR value.
@@ -2011,7 +2011,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_MS_ESCR1 (0x000003C1)
@param EAX Lower 32-bits of MSR value.
@@ -2030,7 +2030,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_TBPU_ESCR0 (0x000003C2)
@param EAX Lower 32-bits of MSR value.
@@ -2049,7 +2049,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_TBPU_ESCR1 (0x000003C3)
@param EAX Lower 32-bits of MSR value.
@@ -2068,7 +2068,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_TC_ESCR0 (0x000003C4)
@param EAX Lower 32-bits of MSR value.
@@ -2087,7 +2087,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_TC_ESCR1 (0x000003C5)
@param EAX Lower 32-bits of MSR value.
@@ -2106,7 +2106,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_IX_ESCR0 (0x000003C8)
@param EAX Lower 32-bits of MSR value.
@@ -2125,7 +2125,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_IX_ESCR1 (0x000003C9)
@param EAX Lower 32-bits of MSR value.
@@ -2144,7 +2144,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_ALF_ESCRn
@param EAX Lower 32-bits of MSR value.
@@ -2175,7 +2175,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_TC_PRECISE_EVENT (0x000003F0)
@param EAX Lower 32-bits of MSR value.
@@ -2194,8 +2194,8 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. Precise Event-Based Sampling (PEBS) (R/W)
Controls the enabling of precise event sampling and replay tagging.
0, 1, 2, 3, 4, 6. Shared. Processor Event Based Sampling (PEBS) (R/W)
Controls the enabling of processor event sampling and replay tagging.
@param ECX MSR_PENTIUM_4_PEBS_ENABLE (0x000003F1)
@param EAX Lower 32-bits of MSR value.
@@ -2223,7 +2223,7 @@ typedef union {
///
struct {
///
/// [Bits 12:0] See Table 19-26.
/// [Bits 12:0] See Table 19-33.
///
UINT32 EventNum:13;
UINT32 Reserved1:11;
@@ -2234,7 +2234,7 @@ typedef union {
///
/// [Bit 25] ENABLE_PEBS_MY_THR (R/W) Enables PEBS for the target logical
/// processor when set; disables PEBS when clear (default). See Section
/// 18.13.3, "IA32_PEBS_ENABLE MSR," for an explanation of the target
/// 18.16.3, "IA32_PEBS_ENABLE MSR," for an explanation of the target
/// logical processor. This bit is called ENABLE_PEBS in IA-32 processors
/// that do not support Intel HyperThreading Technology.
///
@@ -2242,7 +2242,7 @@ typedef union {
///
/// [Bit 26] ENABLE_PEBS_OTH_THR (R/W) Enables PEBS for the target logical
/// processor when set; disables PEBS when clear (default). See Section
/// 18.13.3, "IA32_PEBS_ENABLE MSR," for an explanation of the target
/// 18.16.3, "IA32_PEBS_ENABLE MSR," for an explanation of the target
/// logical processor. This bit is reserved for IA-32 processors that do
/// not support Intel Hyper-Threading Technology.
///
@@ -2262,7 +2262,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Table 19-26.
0, 1, 2, 3, 4, 6. Shared. See Table 19-33.
@param ECX MSR_PENTIUM_4_PEBS_MATRIX_VERT (0x000003F2)
@param EAX Lower 32-bits of MSR value.
@@ -2288,7 +2288,7 @@ typedef union {
680H-68FH, 6C0H-6CfH are not available in processor releases before family
0FH, model 03H. These MSRs replace MSRs previously located at
1DBH-1DEH.which performed the same function for early releases. See Section
17.9, "Last Branch, Call Stack, Interrupt, and Exception Recording for
17.10, "Last Branch, Call Stack, Interrupt, and Exception Recording for
Processors based on Skylake Microarchitecture.".
@param ECX MSR_PENTIUM_4_LASTBRANCH_n_FROM_IP
@@ -2344,7 +2344,7 @@ typedef union {
record registers on the last branch record stack (6C0H-6CFH). This part of
the stack contains pointers to the destination instruction for one of the
last 16 branches, exceptions, or interrupts that the processor took. See
Section 17.9, "Last Branch, Call Stack, Interrupt, and Exception Recording
Section 17.10, "Last Branch, Call Stack, Interrupt, and Exception Recording
for Processors based on Skylake Microarchitecture.".
@param ECX MSR_PENTIUM_4_LASTBRANCH_n_TO_IP
@@ -2397,7 +2397,7 @@ typedef union {
/**
3, 4. Shared. IFSB BUSQ Event Control and Counter Register (R/W) See
Section 18.17, "Performance Monitoring on 64-bit Intel Xeon Processor MP
Section 18.21, "Performance Monitoring on 64-bit Intel Xeon Processor MP
with Up to 8-MByte L3 Cache.".
@param ECX MSR_PENTIUM_4_IFSB_BUSQ0 (0x000107CC)
@@ -2437,7 +2437,7 @@ typedef union {
/**
3, 4. Shared. IFSB SNPQ Event Control and Counter Register (R/W) See
Section 18.17, "Performance Monitoring on 64-bit Intel Xeon Processor MP
Section 18.21, "Performance Monitoring on 64-bit Intel Xeon Processor MP
with Up to 8-MByte L3 Cache.".
@param ECX MSR_PENTIUM_4_IFSB_SNPQ0 (0x000107CE)
@@ -2477,7 +2477,7 @@ typedef union {
/**
3, 4. Shared. EFSB DRDY Event Control and Counter Register (R/W) See
Section 18.17, "Performance Monitoring on 64-bit Intel Xeon Processor MP
Section 18.21, "Performance Monitoring on 64-bit Intel Xeon Processor MP
with Up to 8-MByte L3 Cache" for details.
@param ECX MSR_PENTIUM_4_EFSB_DRDY0 (0x000107D0)
@@ -2516,7 +2516,7 @@ typedef union {
/**
3, 4. Shared. IFSB Latency Event Control Register (R/W) See Section 18.17,
3, 4. Shared. IFSB Latency Event Control Register (R/W) See Section 18.21,
"Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte
L3 Cache" for details.
@@ -2537,7 +2537,7 @@ typedef union {
/**
3, 4. Shared. IFSB Latency Event Counter Register (R/W) See Section 18.17,
3, 4. Shared. IFSB Latency Event Counter Register (R/W) See Section 18.21,
"Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte
L3 Cache.".
@@ -2558,7 +2558,7 @@ typedef union {
/**
6. Shared. GBUSQ Event Control and Counter Register (R/W) See Section 18.17,
6. Shared. GBUSQ Event Control and Counter Register (R/W) See Section 18.21,
"Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte
L3 Cache.".
@@ -2599,7 +2599,7 @@ typedef union {
/**
6. Shared. GSNPQ Event Control and Counter Register (R/W) See Section
18.17, "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to
18.21, "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to
8-MByte L3 Cache.".
@param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL2 (0x000107CE)
@@ -2638,7 +2638,7 @@ typedef union {
/**
6. Shared. FSB Event Control and Counter Register (R/W) See Section 18.17,
6. Shared. FSB Event Control and Counter Register (R/W) See Section 18.21,
"Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte
L3 Cache" for details.