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IntelFsp2Pkg: Apply uncrustify changes

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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737

Apply uncrustify changes to .c/.h files in the IntelFsp2Pkg package

Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
This commit is contained in:
Michael Kubacki
2021-12-05 14:53:59 -08:00
committed by mergify[bot]
parent 45ce0a67bb
commit 111f2228dd
33 changed files with 877 additions and 882 deletions
Download Patch File Download Diff File Expand all files Collapse all files

124
IntelFsp2Pkg/Include/FspEas/FspApi.h
View File

@@ -16,21 +16,21 @@
/// FSP Reset Status code
/// These are defined in FSP EAS v2.0 section 11.2.2 - OEM Status Code
/// @{
#define FSP_STATUS_RESET_REQUIRED_COLD 0x40000001
#define FSP_STATUS_RESET_REQUIRED_WARM 0x40000002
#define FSP_STATUS_RESET_REQUIRED_3 0x40000003
#define FSP_STATUS_RESET_REQUIRED_4 0x40000004
#define FSP_STATUS_RESET_REQUIRED_5 0x40000005
#define FSP_STATUS_RESET_REQUIRED_6 0x40000006
#define FSP_STATUS_RESET_REQUIRED_7 0x40000007
#define FSP_STATUS_RESET_REQUIRED_8 0x40000008
#define FSP_STATUS_RESET_REQUIRED_COLD 0x40000001
#define FSP_STATUS_RESET_REQUIRED_WARM 0x40000002
#define FSP_STATUS_RESET_REQUIRED_3 0x40000003
#define FSP_STATUS_RESET_REQUIRED_4 0x40000004
#define FSP_STATUS_RESET_REQUIRED_5 0x40000005
#define FSP_STATUS_RESET_REQUIRED_6 0x40000006
#define FSP_STATUS_RESET_REQUIRED_7 0x40000007
#define FSP_STATUS_RESET_REQUIRED_8 0x40000008
/// @}
///
/// FSP Event related definition.
///
#define FSP_EVENT_CODE 0xF5000000
#define FSP_POST_CODE (FSP_EVENT_CODE | 0x00F80000)
#define FSP_EVENT_CODE 0xF5000000
#define FSP_POST_CODE (FSP_EVENT_CODE | 0x00F80000)
/*
FSP may optionally include the capability of generating events messages to aid in the debugging of firmware issues.
@@ -60,7 +60,7 @@
*/
typedef
EFI_STATUS
(EFIAPI *FSP_EVENT_HANDLER) (
(EFIAPI *FSP_EVENT_HANDLER)(
IN EFI_STATUS_CODE_TYPE Type,
IN EFI_STATUS_CODE_VALUE Value,
IN UINT32 Instance,
@@ -80,8 +80,8 @@ EFI_STATUS
*/
typedef
UINT32
(EFIAPI *FSP_DEBUG_HANDLER) (
IN CHAR8* DebugMessage,
(EFIAPI *FSP_DEBUG_HANDLER)(
IN CHAR8 *DebugMessage,
IN UINT32 MessageLength
);
@@ -97,14 +97,14 @@ typedef struct {
/// "XXXXXX_S" for FSP-S
/// Where XXXXXX is an unique signature
///
UINT64 Signature;
UINT64 Signature;
///
/// Revision of the Data structure.
/// For FSP spec 2.0/2.1 value is 1.
/// For FSP spec 2.2 value is 2.
///
UINT8 Revision;
UINT8 Reserved[23];
UINT8 Revision;
UINT8 Reserved[23];
} FSP_UPD_HEADER;
///
@@ -114,18 +114,18 @@ typedef struct {
///
/// Revision Revision of the structure is 1 for this version of the specification.
///
UINT8 Revision;
UINT8 Reserved[3];
UINT8 Revision;
UINT8 Reserved[3];
///
/// Length Length of the structure in bytes. The current value for this field is 32.
///
UINT32 Length;
UINT32 Length;
///
/// FspDebugHandler Optional debug handler for the bootloader to receive debug messages
/// occurring during FSP execution.
///
FSP_DEBUG_HANDLER FspDebugHandler;
UINT8 Reserved1[20];
FSP_DEBUG_HANDLER FspDebugHandler;
UINT8 Reserved1[20];
} FSPT_ARCH_UPD;
///
@@ -135,55 +135,55 @@ typedef struct {
///
/// Revision of the structure. For FSP v2.0 value is 1.
///
UINT8 Revision;
UINT8 Reserved[3];
UINT8 Revision;
UINT8 Reserved[3];
///
/// Pointer to the non-volatile storage (NVS) data buffer.
/// If it is NULL it indicates the NVS data is not available.
///
VOID *NvsBufferPtr;
VOID *NvsBufferPtr;
///
/// Pointer to the temporary stack base address to be
/// consumed inside FspMemoryInit() API.
///
VOID *StackBase;
VOID *StackBase;
///
/// Temporary stack size to be consumed inside
/// FspMemoryInit() API.
///
UINT32 StackSize;
UINT32 StackSize;
///
/// Size of memory to be reserved by FSP below "top
/// of low usable memory" for bootloader usage.
///
UINT32 BootLoaderTolumSize;
UINT32 BootLoaderTolumSize;
///
/// Current boot mode.
///
UINT32 BootMode;
UINT32 BootMode;
///
/// Optional event handler for the bootloader to be informed of events occurring during FSP execution.
/// This value is only valid if Revision is >= 2.
///
FSP_EVENT_HANDLER *FspEventHandler;
UINT8 Reserved1[4];
FSP_EVENT_HANDLER *FspEventHandler;
UINT8 Reserved1[4];
} FSPM_ARCH_UPD;
typedef struct {
///
/// Revision Revision of the structure is 1 for this version of the specification.
///
UINT8 Revision;
UINT8 Reserved[3];
UINT8 Revision;
UINT8 Reserved[3];
///
/// Length Length of the structure in bytes. The current value for this field is 32.
///
UINT32 Length;
UINT32 Length;
///
/// FspEventHandler Optional event handler for the bootloader to be informed of events
/// occurring during FSP execution.
///
FSP_EVENT_HANDLER FspEventHandler;
FSP_EVENT_HANDLER FspEventHandler;
///
/// A FSP binary may optionally implement multi-phase silicon initialization,
/// This is only supported if the FspMultiPhaseSiInitEntryOffset field in FSP_INFO_HEADER
@@ -191,8 +191,8 @@ typedef struct {
/// To enable multi-phase silicon initialization, the bootloader must set
/// EnableMultiPhaseSiliconInit to a non-zero value.
///
UINT8 EnableMultiPhaseSiliconInit;
UINT8 Reserved1[19];
UINT8 EnableMultiPhaseSiliconInit;
UINT8 Reserved1[19];
} FSPS_ARCH_UPD;
///
@@ -202,7 +202,7 @@ typedef struct {
///
/// FSP_UPD_HEADER Configuration.
///
FSP_UPD_HEADER FspUpdHeader;
FSP_UPD_HEADER FspUpdHeader;
} FSPT_UPD_COMMON;
///
@@ -212,12 +212,12 @@ typedef struct {
///
/// FSP_UPD_HEADER Configuration.
///
FSP_UPD_HEADER FspUpdHeader;
FSP_UPD_HEADER FspUpdHeader;
///
/// FSPT_ARCH_UPD Configuration.
///
FSPT_ARCH_UPD FsptArchUpd;
FSPT_ARCH_UPD FsptArchUpd;
} FSPT_UPD_COMMON_FSP22;
///
@@ -227,11 +227,11 @@ typedef struct {
///
/// FSP_UPD_HEADER Configuration.
///
FSP_UPD_HEADER FspUpdHeader;
FSP_UPD_HEADER FspUpdHeader;
///
/// FSPM_ARCH_UPD Configuration.
///
FSPM_ARCH_UPD FspmArchUpd;
FSPM_ARCH_UPD FspmArchUpd;
} FSPM_UPD_COMMON;
///
@@ -241,7 +241,7 @@ typedef struct {
///
/// FSP_UPD_HEADER Configuration.
///
FSP_UPD_HEADER FspUpdHeader;
FSP_UPD_HEADER FspUpdHeader;
} FSPS_UPD_COMMON;
///
@@ -251,12 +251,12 @@ typedef struct {
///
/// FSP_UPD_HEADER Configuration.
///
FSP_UPD_HEADER FspUpdHeader;
FSP_UPD_HEADER FspUpdHeader;
///
/// FSPS_ARCH_UPD Configuration.
///
FSPS_ARCH_UPD FspsArchUpd;
FSPS_ARCH_UPD FspsArchUpd;
} FSPS_UPD_COMMON_FSP22;
///
@@ -273,13 +273,13 @@ typedef enum {
/// This stage is notified just before the bootloader hand-off
/// to the OS loader.
///
EnumInitPhaseReadyToBoot = 0x40,
EnumInitPhaseReadyToBoot = 0x40,
///
/// This stage is notified just before the firmware/Preboot
/// environment transfers management of all system resources
/// to the OS or next level execution environment.
///
EnumInitPhaseEndOfFirmware = 0xF0
EnumInitPhaseEndOfFirmware = 0xF0
} FSP_INIT_PHASE;
///
@@ -289,15 +289,15 @@ typedef struct {
///
/// Notification phase used for NotifyPhase API
///
FSP_INIT_PHASE Phase;
FSP_INIT_PHASE Phase;
} NOTIFY_PHASE_PARAMS;
///
/// Action definition for FspMultiPhaseSiInit API
///
typedef enum {
EnumMultiPhaseGetNumberOfPhases = 0x0,
EnumMultiPhaseExecutePhase = 0x1
EnumMultiPhaseGetNumberOfPhases = 0x0,
EnumMultiPhaseExecutePhase = 0x1
} FSP_MULTI_PHASE_ACTION;
///
@@ -305,8 +305,8 @@ typedef enum {
/// FspMultiPhaseSiInit API with action 0 (EnumMultiPhaseGetNumberOfPhases)
///
typedef struct {
UINT32 NumberOfPhases;
UINT32 PhasesExecuted;
UINT32 NumberOfPhases;
UINT32 PhasesExecuted;
} FSP_MULTI_PHASE_GET_NUMBER_OF_PHASES_PARAMS;
///
@@ -321,9 +321,9 @@ typedef struct {
/// - MultiPhaseParamPtr shall be NULL.
///
typedef struct {
IN FSP_MULTI_PHASE_ACTION MultiPhaseAction;
IN UINT32 PhaseIndex;
IN OUT VOID *MultiPhaseParamPtr;
IN FSP_MULTI_PHASE_ACTION MultiPhaseAction;
IN UINT32 PhaseIndex;
IN OUT VOID *MultiPhaseParamPtr;
} FSP_MULTI_PHASE_PARAMS;
#pragma pack()
@@ -359,7 +359,7 @@ typedef struct {
**/
typedef
EFI_STATUS
(EFIAPI *FSP_TEMP_RAM_INIT) (
(EFIAPI *FSP_TEMP_RAM_INIT)(
IN VOID *FsptUpdDataPtr
);
@@ -379,7 +379,7 @@ EFI_STATUS
**/
typedef
EFI_STATUS
(EFIAPI *FSP_NOTIFY_PHASE) (
(EFIAPI *FSP_NOTIFY_PHASE)(
IN NOTIFY_PHASE_PARAMS *NotifyPhaseParamPtr
);
@@ -407,12 +407,11 @@ EFI_STATUS
**/
typedef
EFI_STATUS
(EFIAPI *FSP_MEMORY_INIT) (
(EFIAPI *FSP_MEMORY_INIT)(
IN VOID *FspmUpdDataPtr,
OUT VOID **HobListPtr
);
/**
This FSP API is called after FspMemoryInit API. This FSP API tears down the temporary
memory setup by TempRamInit API. This FSP API accepts a pointer to a data structure
@@ -433,11 +432,10 @@ EFI_STATUS
**/
typedef
EFI_STATUS
(EFIAPI *FSP_TEMP_RAM_EXIT) (
(EFIAPI *FSP_TEMP_RAM_EXIT)(
IN VOID *TempRamExitParamPtr
);
/**
This FSP API is called after TempRamExit API.
FspMemoryInit, TempRamExit and FspSiliconInit APIs provide an alternate method to complete the
@@ -454,7 +452,7 @@ EFI_STATUS
**/
typedef
EFI_STATUS
(EFIAPI *FSP_SILICON_INIT) (
(EFIAPI *FSP_SILICON_INIT)(
IN VOID *FspsUpdDataPtr
);
@@ -478,8 +476,8 @@ EFI_STATUS
**/
typedef
EFI_STATUS
(EFIAPI *FSP_MULTI_PHASE_SI_INIT) (
(EFIAPI *FSP_MULTI_PHASE_SI_INIT)(
IN FSP_MULTI_PHASE_PARAMS *MultiPhaseSiInitParamPtr
);
);
#endif

84
IntelFsp2Pkg/Include/FspGlobalData.h
View File

@@ -10,8 +10,8 @@
#include <FspEas.h>
#define FSP_IN_API_MODE 0
#define FSP_IN_DISPATCH_MODE 1
#define FSP_IN_API_MODE 0
#define FSP_IN_DISPATCH_MODE 1
#pragma pack(1)
@@ -27,50 +27,50 @@ typedef enum {
} FSP_API_INDEX;
typedef struct {
VOID *DataPtr;
UINT32 MicrocodeRegionBase;
UINT32 MicrocodeRegionSize;
UINT32 CodeRegionBase;
UINT32 CodeRegionSize;
VOID *DataPtr;
UINT32 MicrocodeRegionBase;
UINT32 MicrocodeRegionSize;
UINT32 CodeRegionBase;
UINT32 CodeRegionSize;
} FSP_PLAT_DATA;
#define FSP_GLOBAL_DATA_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'D')
#define FSP_PERFORMANCE_DATA_SIGNATURE SIGNATURE_32 ('P', 'E', 'R', 'F')
#define FSP_PERFORMANCE_DATA_TIMER_MASK 0xFFFFFFFFFFFFFF
#define FSP_GLOBAL_DATA_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'D')
#define FSP_PERFORMANCE_DATA_SIGNATURE SIGNATURE_32 ('P', 'E', 'R', 'F')
#define FSP_PERFORMANCE_DATA_TIMER_MASK 0xFFFFFFFFFFFFFF
typedef struct {
UINT32 Signature;
UINT8 Version;
UINT8 Reserved1[3];
UINT32 CoreStack;
UINT32 StatusCode;
UINT32 Reserved2[8];
FSP_PLAT_DATA PlatformData;
FSP_INFO_HEADER *FspInfoHeader;
VOID *UpdDataPtr;
VOID *TempRamInitUpdPtr;
VOID *MemoryInitUpdPtr;
VOID *SiliconInitUpdPtr;
UINT8 ApiIdx;
///
/// 0: FSP in API mode; 1: FSP in DISPATCH mode
///
UINT8 FspMode;
UINT8 OnSeparateStack;
UINT8 Reserved3;
UINT32 NumberOfPhases;
UINT32 PhasesExecuted;
///
/// To store function parameters pointer
/// so it can be retrieved after stack switched.
///
VOID *FunctionParameterPtr;
UINT8 Reserved4[16];
UINT32 PerfSig;
UINT16 PerfLen;
UINT16 Reserved5;
UINT32 PerfIdx;
UINT64 PerfData[32];
UINT32 Signature;
UINT8 Version;
UINT8 Reserved1[3];
UINT32 CoreStack;
UINT32 StatusCode;
UINT32 Reserved2[8];
FSP_PLAT_DATA PlatformData;
FSP_INFO_HEADER *FspInfoHeader;
VOID *UpdDataPtr;
VOID *TempRamInitUpdPtr;
VOID *MemoryInitUpdPtr;
VOID *SiliconInitUpdPtr;
UINT8 ApiIdx;
///
/// 0: FSP in API mode; 1: FSP in DISPATCH mode
///
UINT8 FspMode;
UINT8 OnSeparateStack;
UINT8 Reserved3;
UINT32 NumberOfPhases;
UINT32 PhasesExecuted;
///
/// To store function parameters pointer
/// so it can be retrieved after stack switched.
///
VOID *FunctionParameterPtr;
UINT8 Reserved4[16];
UINT32 PerfSig;
UINT16 PerfLen;
UINT16 Reserved5;
UINT32 PerfIdx;
UINT64 PerfData[32];
} FSP_GLOBAL_DATA;
#pragma pack()

48
IntelFsp2Pkg/Include/FspMeasurePointId.h
View File

@@ -11,44 +11,44 @@
//
// 0xD0 - 0xEF are reserved for FSP common measure point
//
#define FSP_PERF_ID_MRC_INIT_ENTRY 0xD0
#define FSP_PERF_ID_MRC_INIT_EXIT (FSP_PERF_ID_MRC_INIT_ENTRY + 1)
#define FSP_PERF_ID_MRC_INIT_ENTRY 0xD0
#define FSP_PERF_ID_MRC_INIT_EXIT (FSP_PERF_ID_MRC_INIT_ENTRY + 1)
#define FSP_PERF_ID_SYSTEM_AGENT_INIT_ENTRY 0xD8
#define FSP_PERF_ID_SYSTEM_AGENT_INIT_EXIT (FSP_PERF_ID_SYSTEM_AGENT_INIT_ENTRY + 1)
#define FSP_PERF_ID_SYSTEM_AGENT_INIT_ENTRY 0xD8
#define FSP_PERF_ID_SYSTEM_AGENT_INIT_EXIT (FSP_PERF_ID_SYSTEM_AGENT_INIT_ENTRY + 1)
#define FSP_PERF_ID_PCH_INIT_ENTRY 0xDA
#define FSP_PERF_ID_PCH_INIT_EXIT (FSP_PERF_ID_PCH_INIT_ENTRY + 1)
#define FSP_PERF_ID_PCH_INIT_ENTRY 0xDA
#define FSP_PERF_ID_PCH_INIT_EXIT (FSP_PERF_ID_PCH_INIT_ENTRY + 1)
#define FSP_PERF_ID_CPU_INIT_ENTRY 0xE0
#define FSP_PERF_ID_CPU_INIT_EXIT (FSP_PERF_ID_CPU_INIT_ENTRY + 1)
#define FSP_PERF_ID_CPU_INIT_ENTRY 0xE0
#define FSP_PERF_ID_CPU_INIT_EXIT (FSP_PERF_ID_CPU_INIT_ENTRY + 1)
#define FSP_PERF_ID_GFX_INIT_ENTRY 0xE8
#define FSP_PERF_ID_GFX_INIT_EXIT (FSP_PERF_ID_GFX_INIT_ENTRY + 1)
#define FSP_PERF_ID_GFX_INIT_ENTRY 0xE8
#define FSP_PERF_ID_GFX_INIT_EXIT (FSP_PERF_ID_GFX_INIT_ENTRY + 1)
#define FSP_PERF_ID_ME_INIT_ENTRY 0xEA
#define FSP_PERF_ID_ME_INIT_EXIT (FSP_PERF_ID_ME_INIT_ENTRY + 1)
#define FSP_PERF_ID_ME_INIT_ENTRY 0xEA
#define FSP_PERF_ID_ME_INIT_EXIT (FSP_PERF_ID_ME_INIT_ENTRY + 1)
//
// 0xF0 - 0xFF are reserved for FSP API
//
#define FSP_PERF_ID_API_TEMP_RAM_INIT_ENTRY 0xF0
#define FSP_PERF_ID_API_TEMP_RAM_INIT_EXIT (FSP_PERF_ID_API_TEMP_RAM_INIT_ENTRY + 1)
#define FSP_PERF_ID_API_TEMP_RAM_INIT_ENTRY 0xF0
#define FSP_PERF_ID_API_TEMP_RAM_INIT_EXIT (FSP_PERF_ID_API_TEMP_RAM_INIT_ENTRY + 1)
#define FSP_PERF_ID_API_FSP_MEMORY_INIT_ENTRY 0xF2
#define FSP_PERF_ID_API_FSP_MEMORY_INIT_EXIT (FSP_PERF_ID_API_FSP_MEMORY_INIT_ENTRY + 1)
#define FSP_PERF_ID_API_FSP_MEMORY_INIT_ENTRY 0xF2
#define FSP_PERF_ID_API_FSP_MEMORY_INIT_EXIT (FSP_PERF_ID_API_FSP_MEMORY_INIT_ENTRY + 1)
#define FSP_PERF_ID_API_TEMP_RAM_EXIT_ENTRY 0xF4
#define FSP_PERF_ID_API_TEMP_RAM_EXIT_EXIT (FSP_PERF_ID_API_TEMP_RAM_EXIT_ENTRY + 1)
#define FSP_PERF_ID_API_TEMP_RAM_EXIT_ENTRY 0xF4
#define FSP_PERF_ID_API_TEMP_RAM_EXIT_EXIT (FSP_PERF_ID_API_TEMP_RAM_EXIT_ENTRY + 1)
#define FSP_PERF_ID_API_FSP_SILICON_INIT_ENTRY 0xF6
#define FSP_PERF_ID_API_FSP_SILICON_INIT_EXIT (FSP_PERF_ID_API_FSP_SILICON_INIT_ENTRY + 1)
#define FSP_PERF_ID_API_FSP_SILICON_INIT_ENTRY 0xF6
#define FSP_PERF_ID_API_FSP_SILICON_INIT_EXIT (FSP_PERF_ID_API_FSP_SILICON_INIT_ENTRY + 1)
#define FSP_PERF_ID_API_NOTIFY_POST_PCI_ENTRY 0xF8
#define FSP_PERF_ID_API_NOTIFY_POST_PCI_EXIT (FSP_PERF_ID_API_NOTIFY_POST_PCI_ENTRY + 1)
#define FSP_PERF_ID_API_NOTIFY_POST_PCI_ENTRY 0xF8
#define FSP_PERF_ID_API_NOTIFY_POST_PCI_EXIT (FSP_PERF_ID_API_NOTIFY_POST_PCI_ENTRY + 1)
#define FSP_PERF_ID_API_NOTIFY_READY_TO_BOOT_ENTRY 0xFA
#define FSP_PERF_ID_API_NOTIFY_READY_TO_BOOT_EXIT (FSP_PERF_ID_API_NOTIFY_READY_TO_BOOT_ENTRY + 1)
#define FSP_PERF_ID_API_NOTIFY_READY_TO_BOOT_ENTRY 0xFA
#define FSP_PERF_ID_API_NOTIFY_READY_TO_BOOT_EXIT (FSP_PERF_ID_API_NOTIFY_READY_TO_BOOT_ENTRY + 1)
#define FSP_PERF_ID_API_NOTIFY_END_OF_FIRMWARE_ENTRY 0xFC
#define FSP_PERF_ID_API_NOTIFY_END_OF_FIRMWARE_EXIT (FSP_PERF_ID_API_NOTIFY_END_OF_FIRMWARE_ENTRY + 1)

34
IntelFsp2Pkg/Include/FspStatusCode.h
View File

@@ -12,29 +12,29 @@
//
// FSP API - 4 BITS
//
#define FSP_STATUS_CODE_TEMP_RAM_INIT 0xF000
#define FSP_STATUS_CODE_MEMORY_INIT 0xD000
#define FSP_STATUS_CODE_TEMP_RAM_EXIT 0xB000
#define FSP_STATUS_CODE_SILICON_INIT 0x9000
#define FSP_STATUS_CODE_POST_PCIE_ENUM_NOTIFICATION 0x6000
#define FSP_STATUS_CODE_READY_TO_BOOT_NOTIFICATION 0x4000
#define FSP_STATUS_CODE_END_OF_FIRMWARE_NOTIFICATION 0x2000
#define FSP_STATUS_CODE_TEMP_RAM_INIT 0xF000
#define FSP_STATUS_CODE_MEMORY_INIT 0xD000
#define FSP_STATUS_CODE_TEMP_RAM_EXIT 0xB000
#define FSP_STATUS_CODE_SILICON_INIT 0x9000
#define FSP_STATUS_CODE_POST_PCIE_ENUM_NOTIFICATION 0x6000
#define FSP_STATUS_CODE_READY_TO_BOOT_NOTIFICATION 0x4000
#define FSP_STATUS_CODE_END_OF_FIRMWARE_NOTIFICATION 0x2000
//
// MODULE - 4 BITS
//
#define FSP_STATUS_CODE_GFX_PEIM 0x0700
#define FSP_STATUS_CODE_COMMON_CODE 0x0800
#define FSP_STATUS_CODE_SILICON_COMMON_CODE 0x0900
#define FSP_STATUS_CODE_SYSTEM_AGENT 0x0A00
#define FSP_STATUS_CODE_PCH 0x0B00
#define FSP_STATUS_CODE_CPU 0x0C00
#define FSP_STATUS_CODE_MRC 0x0D00
#define FSP_STATUS_CODE_ME_BIOS 0x0E00
#define FSP_STATUS_CODE_GFX_PEIM 0x0700
#define FSP_STATUS_CODE_COMMON_CODE 0x0800
#define FSP_STATUS_CODE_SILICON_COMMON_CODE 0x0900
#define FSP_STATUS_CODE_SYSTEM_AGENT 0x0A00
#define FSP_STATUS_CODE_PCH 0x0B00
#define FSP_STATUS_CODE_CPU 0x0C00
#define FSP_STATUS_CODE_MRC 0x0D00
#define FSP_STATUS_CODE_ME_BIOS 0x0E00
//
// Individual Codes - 1 BYTE
//
#define FSP_STATUS_CODE_API_ENTRY 0x0000
#define FSP_STATUS_CODE_API_EXIT 0x007F
#define FSP_STATUS_CODE_API_ENTRY 0x0000
#define FSP_STATUS_CODE_API_EXIT 0x007F
#endif

80
IntelFsp2Pkg/Include/Guid/FspHeaderFile.h
View File

@@ -10,7 +10,7 @@
#ifndef __FSP_HEADER_FILE_H__
#define __FSP_HEADER_FILE_H__
#define FSP_HEADER_REVISION_3 3
#define FSP_HEADER_REVISION_3 3
#define FSPE_HEADER_REVISION_1 1
#define FSPP_HEADER_REVISION_1 1
@@ -18,7 +18,7 @@
///
/// Fixed FSP header offset in the FSP image
///
#define FSP_INFO_HEADER_OFF 0x94
#define FSP_INFO_HEADER_OFF 0x94
#define OFFSET_IN_FSP_INFO_HEADER(x) (UINT32)&((FSP_INFO_HEADER *)(UINTN)0)->x
@@ -33,25 +33,25 @@ typedef struct {
///
/// Byte 0x00: Signature ('FSPH') for the FSP Information Header.
///
UINT32 Signature;
UINT32 Signature;
///
/// Byte 0x04: Length of the FSP Information Header.
///
UINT32 HeaderLength;
UINT32 HeaderLength;
///
/// Byte 0x08: Reserved.
///
UINT8 Reserved1[2];
UINT8 Reserved1[2];
///
/// Byte 0x0A: Indicates compliance with a revision of this specification in the BCD format.
/// For revision v2.3 the value will be 0x23.
///
UINT8 SpecVersion;
UINT8 SpecVersion;
///
/// Byte 0x0B: Revision of the FSP Information Header.
/// The Current value for this field is 0x6.
///
UINT8 HeaderRevision;
UINT8 HeaderRevision;
///
/// Byte 0x0C: Revision of the FSP binary.
/// Major.Minor.Revision.Build
@@ -67,69 +67,69 @@ typedef struct {
/// 23 : 16 - Minor Version
/// 31 : 24 - Major Version
///
UINT32 ImageRevision;
UINT32 ImageRevision;
///
/// Byte 0x10: Signature string that will help match the FSP Binary to a supported HW configuration.
///
CHAR8 ImageId[8];
CHAR8 ImageId[8];
///
/// Byte 0x18: Size of the entire FSP binary.
///
UINT32 ImageSize;
UINT32 ImageSize;
///
/// Byte 0x1C: FSP binary preferred base address.
///
UINT32 ImageBase;
UINT32 ImageBase;
///
/// Byte 0x20: Attribute for the FSP binary.
///
UINT16 ImageAttribute;
UINT16 ImageAttribute;
///
/// Byte 0x22: Attributes of the FSP Component.
///
UINT16 ComponentAttribute;
UINT16 ComponentAttribute;
///
/// Byte 0x24: Offset of the FSP configuration region.
///
UINT32 CfgRegionOffset;
UINT32 CfgRegionOffset;
///
/// Byte 0x28: Size of the FSP configuration region.
///
UINT32 CfgRegionSize;
UINT32 CfgRegionSize;
///
/// Byte 0x2C: Reserved2.
///
UINT32 Reserved2;
UINT32 Reserved2;
///
/// Byte 0x30: The offset for the API to setup a temporary stack till the memory is initialized.
///
UINT32 TempRamInitEntryOffset;
UINT32 TempRamInitEntryOffset;
///
/// Byte 0x34: Reserved3.
///
UINT32 Reserved3;
UINT32 Reserved3;
///
/// Byte 0x38: The offset for the API to inform the FSP about the different stages in the boot process.
///
UINT32 NotifyPhaseEntryOffset;
UINT32 NotifyPhaseEntryOffset;
///
/// Byte 0x3C: The offset for the API to initialize the memory.
///
UINT32 FspMemoryInitEntryOffset;
UINT32 FspMemoryInitEntryOffset;
///
/// Byte 0x40: The offset for the API to tear down temporary RAM.
///
UINT32 TempRamExitEntryOffset;
UINT32 TempRamExitEntryOffset;
///
/// Byte 0x44: The offset for the API to initialize the CPU and chipset.
///
UINT32 FspSiliconInitEntryOffset;
UINT32 FspSiliconInitEntryOffset;
///
/// Byte 0x48: Offset for the API for the optional Multi-Phase processor and chipset initialization.
/// This value is only valid if FSP HeaderRevision is >= 5.
/// If the value is set to 0x00000000, then this API is not available in this component.
///
UINT32 FspMultiPhaseSiInitEntryOffset;
UINT32 FspMultiPhaseSiInitEntryOffset;
///
/// Byte 0x4C: Extended revision of the FSP binary.
/// This value is only valid if FSP HeaderRevision is >= 6.
@@ -142,11 +142,11 @@ typedef struct {
/// Minor Version = ImageRevision[23:16]
/// Major Version = ImageRevision[31:24]
///
UINT16 ExtendedImageRevision;
UINT16 ExtendedImageRevision;
///
/// Byte 0x4E: Reserved4.
///
UINT16 Reserved4;
UINT16 Reserved4;
} FSP_INFO_HEADER;
///
@@ -161,31 +161,31 @@ typedef struct {
///
/// Byte 0x00: Signature ('FSPE') for the FSP Extended Information Header.
///
UINT32 Signature;
UINT32 Signature;
///
/// Byte 0x04: Length of the table in bytes, including all additional FSP producer defined data.
///
UINT32 Length;
UINT32 Length;
///
/// Byte 0x08: FSP producer defined revision of the table.
///
UINT8 Revision;
UINT8 Revision;
///
/// Byte 0x09: Reserved for future use.
///
UINT8 Reserved;
UINT8 Reserved;
///
/// Byte 0x0A: FSP producer identification string
///
CHAR8 FspProducerId[6];
CHAR8 FspProducerId[6];
///
/// Byte 0x10: FSP producer implementation revision number. Larger numbers are assumed to be newer revisions.
///
UINT32 FspProducerRevision;
UINT32 FspProducerRevision;
///
/// Byte 0x14: Size of the FSP producer defined data (n) in bytes.
///
UINT32 FspProducerDataSize;
UINT32 FspProducerDataSize;
///
/// Byte 0x18: FSP producer defined data of size (n) defined by FspProducerDataSize.
///
@@ -195,7 +195,7 @@ typedef struct {
// A generic table search algorithm for additional tables can be implemented with a
// signature search algorithm until a terminator signature 'FSPP' is found.
//
#define FSP_FSPP_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'P')
#define FSP_FSPP_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'P')
#define FSP_PATCH_TABLE_SIGNATURE FSP_FSPP_SIGNATURE
///
@@ -205,31 +205,31 @@ typedef struct {
///
/// Byte 0x00: FSP Patch Table Signature "FSPP".
///
UINT32 Signature;
UINT32 Signature;
///
/// Byte 0x04: Size including the PatchData.
///
UINT16 HeaderLength;
UINT16 HeaderLength;
///
/// Byte 0x06: Revision is set to 0x01.
///
UINT8 HeaderRevision;
UINT8 HeaderRevision;
///
/// Byte 0x07: Reserved for future use.
///
UINT8 Reserved;
UINT8 Reserved;
///
/// Byte 0x08: Number of entries to Patch.
///
UINT32 PatchEntryNum;
UINT32 PatchEntryNum;
///
/// Byte 0x0C: Patch Data.
///
//UINT32 PatchData[];
// UINT32 PatchData[];
} FSP_PATCH_TABLE;
#pragma pack()
extern EFI_GUID gFspHeaderFileGuid;
extern EFI_GUID gFspHeaderFileGuid;
#endif

8
IntelFsp2Pkg/Include/Guid/FspNonVolatileStorageHob2.h
View File

@@ -14,11 +14,11 @@
/// The Non-Volatile Storage (NVS) HOB version 2 provides > 64KB buffer support.
///
typedef struct {
EFI_HOB_GUID_TYPE GuidHob;
EFI_PHYSICAL_ADDRESS NvsDataPtr;
UINT64 NvsDataLength;
EFI_HOB_GUID_TYPE GuidHob;
EFI_PHYSICAL_ADDRESS NvsDataPtr;
UINT64 NvsDataLength;
} FSP_NON_VOLATILE_STORAGE_HOB2;
extern EFI_GUID gFspNonVolatileStorageHob2Guid;
extern EFI_GUID gFspNonVolatileStorageHob2Guid;
#endif

6
IntelFsp2Pkg/Include/Guid/GuidHobFspEas.h
View File

@@ -10,8 +10,8 @@
#ifndef __GUID_HOB_FSP_EAS_GUID__
#define __GUID_HOB_FSP_EAS_GUID__
extern EFI_GUID gFspBootLoaderTolumHobGuid;
extern EFI_GUID gFspReservedMemoryResourceHobGuid;
extern EFI_GUID gFspNonVolatileStorageHobGuid;
extern EFI_GUID gFspBootLoaderTolumHobGuid;
extern EFI_GUID gFspReservedMemoryResourceHobGuid;
extern EFI_GUID gFspNonVolatileStorageHobGuid;
#endif

3
IntelFsp2Pkg/Include/Library/CacheAsRamLib.h
View File

@@ -17,8 +17,7 @@
VOID
EFIAPI
DisableCacheAsRam (
IN BOOLEAN DisableCar
IN BOOLEAN DisableCar
);
#endif

17
IntelFsp2Pkg/Include/Library/CacheLib.h
View File

@@ -13,11 +13,11 @@
//
typedef INT32 EFI_MEMORY_CACHE_TYPE;
#define EFI_CACHE_UNCACHEABLE 0
#define EFI_CACHE_WRITECOMBINING 1
#define EFI_CACHE_WRITETHROUGH 4
#define EFI_CACHE_WRITEPROTECTED 5
#define EFI_CACHE_WRITEBACK 6
#define EFI_CACHE_UNCACHEABLE 0
#define EFI_CACHE_WRITECOMBINING 1
#define EFI_CACHE_WRITETHROUGH 4
#define EFI_CACHE_WRITEPROTECTED 5
#define EFI_CACHE_WRITEBACK 6
/**
Reset all the MTRRs to a known state.
@@ -47,10 +47,9 @@ ResetCacheAttributes (
EFI_STATUS
EFIAPI
SetCacheAttributes (
IN EFI_PHYSICAL_ADDRESS MemoryAddress,
IN UINT64 MemoryLength,
IN EFI_MEMORY_CACHE_TYPE MemoryCacheType
IN EFI_PHYSICAL_ADDRESS MemoryAddress,
IN UINT64 MemoryLength,
IN EFI_MEMORY_CACHE_TYPE MemoryCacheType
);
#endif

22
IntelFsp2Pkg/Include/Library/FspCommonLib.h
View File

@@ -20,7 +20,7 @@
VOID
EFIAPI
SetFspGlobalDataPointer (
IN FSP_GLOBAL_DATA *FspData
IN FSP_GLOBAL_DATA *FspData
);
/**
@@ -60,7 +60,7 @@ GetFspApiParameter2 (
@retval FSP entry stack pointer.
**/
VOID*
VOID *
EFIAPI
GetFspEntryStack (
VOID
@@ -75,7 +75,7 @@ GetFspEntryStack (
VOID
EFIAPI
SetFspApiParameter (
IN UINT32 Value
IN UINT32 Value
);
/**
@@ -99,7 +99,7 @@ SetFspApiReturnStatus (
VOID
EFIAPI
SetFspCoreStackPointer (
IN VOID *NewStackTop
IN VOID *NewStackTop
);
/**
@@ -111,7 +111,7 @@ SetFspCoreStackPointer (
VOID
EFIAPI
SetFspPlatformDataPointer (
IN VOID *PlatformData
IN VOID *PlatformData
);
/**
@@ -134,7 +134,7 @@ GetFspPlatformDataPointer (
VOID
EFIAPI
SetFspUpdDataPointer (
IN VOID *UpdDataPtr
IN VOID *UpdDataPtr
);
/**
@@ -156,7 +156,7 @@ GetFspUpdDataPointer (
VOID
EFIAPI
SetFspMemoryInitUpdDataPointer (
IN VOID *MemoryInitUpdPtr
IN VOID *MemoryInitUpdPtr
);
/**
@@ -178,7 +178,7 @@ GetFspMemoryInitUpdDataPointer (
VOID
EFIAPI
SetFspSiliconInitUpdDataPointer (
IN VOID *SiliconInitUpdPtr
IN VOID *SiliconInitUpdPtr
);
/**
@@ -224,7 +224,7 @@ GetFspInfoHeader (
VOID
EFIAPI
SetFspInfoHeader (
FSP_INFO_HEADER *FspInfoHeader
FSP_INFO_HEADER *FspInfoHeader
);
/**
@@ -282,7 +282,6 @@ GetPhaseStatusCode (
VOID
);
/**
This function sets FSP Phase StatusCode.
@@ -303,6 +302,7 @@ SetPhaseStatusCode (
VOID
EFIAPI
FspApiReturnStatusReset (
IN UINT32 FspResetType
IN UINT32 FspResetType
);
#endif

17
IntelFsp2Pkg/Include/Library/FspPlatformLib.h
View File

@@ -16,7 +16,7 @@
EFI_HOB_RESOURCE_DESCRIPTOR *
EFIAPI
FspGetResourceDescriptorByOwner (
IN EFI_GUID *OwnerGuid
IN EFI_GUID *OwnerGuid
);
/**
@@ -28,11 +28,10 @@ FspGetResourceDescriptorByOwner (
VOID
EFIAPI
FspGetSystemMemorySize (
IN OUT UINT64 *LowMemoryLength,
IN OUT UINT64 *HighMemoryLength
IN OUT UINT64 *LowMemoryLength,
IN OUT UINT64 *HighMemoryLength
);
/**
Set a new stack frame for the continuation function.
@@ -61,7 +60,7 @@ FspSiliconInitDone (
VOID
EFIAPI
FspMemoryInitDone (
IN OUT VOID **HobListPtr
IN OUT VOID **HobListPtr
);
/**
@@ -95,7 +94,7 @@ FspWaitForNotify (
VOID
EFIAPI
FspSiliconInitDone2 (
IN EFI_STATUS Status
IN EFI_STATUS Status
);
/**
@@ -107,8 +106,8 @@ FspSiliconInitDone2 (
VOID
EFIAPI
FspMemoryInitDone2 (
IN EFI_STATUS Status,
IN OUT VOID **HobListPtr
IN EFI_STATUS Status,
IN OUT VOID **HobListPtr
);
/**
@@ -119,7 +118,7 @@ FspMemoryInitDone2 (
VOID
EFIAPI
FspTempRamExitDone2 (
IN EFI_STATUS Status
IN EFI_STATUS Status
);
#endif

12
IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h
View File

@@ -43,7 +43,7 @@ SecPlatformInit (
UINT32
EFIAPI
LoadMicrocode (
IN VOID *FsptUpdDataPtr
IN VOID *FsptUpdDataPtr
);
/**
@@ -62,7 +62,7 @@ LoadMicrocode (
UINT32
EFIAPI
SecCarInit (
IN VOID *FsptUpdDataPtr
IN VOID *FsptUpdDataPtr
);
/**
@@ -75,8 +75,8 @@ SecCarInit (
EFI_STATUS
EFIAPI
FspUpdSignatureCheck (
IN UINT32 ApiIdx,
IN VOID *ApiParam
IN UINT32 ApiIdx,
IN VOID *ApiParam
);
/**
@@ -89,8 +89,8 @@ FspUpdSignatureCheck (
EFI_STATUS
EFIAPI
FspMultiPhaseSiInitApiHandler (
IN UINT32 ApiIdx,
IN VOID *ApiParam
IN UINT32 ApiIdx,
IN VOID *ApiParam
);
#endif

14
IntelFsp2Pkg/Include/Ppi/FspmArchConfigPpi.h
View File

@@ -10,7 +10,7 @@
#ifndef _FSPM_ARCH_CONFIG_PPI_H_
#define _FSPM_ARCH_CONFIG_PPI_H_
#define FSPM_ARCH_CONFIG_PPI_REVISION 0x1
#define FSPM_ARCH_CONFIG_PPI_REVISION 0x1
///
/// Global ID for the FSPM_ARCH_CONFIG_PPI.
@@ -27,21 +27,21 @@ typedef struct {
///
/// Revision of the structure
///
UINT8 Revision;
UINT8 Reserved[3];
UINT8 Revision;
UINT8 Reserved[3];
///
/// Pointer to the non-volatile storage (NVS) data buffer.
/// If it is NULL it indicates the NVS data is not available.
///
VOID *NvsBufferPtr;
VOID *NvsBufferPtr;
///
/// Size of memory to be reserved by FSP below "top
/// of low usable memory" for bootloader usage.
///
UINT32 BootLoaderTolumSize;
UINT8 Reserved1[4];
UINT32 BootLoaderTolumSize;
UINT8 Reserved1[4];
} FSPM_ARCH_CONFIG_PPI;
extern EFI_GUID gFspmArchConfigPpiGuid;
extern EFI_GUID gFspmArchConfigPpiGuid;
#endif // _FSPM_ARCH_CONFIG_PPI_H_

6
IntelFsp2Pkg/Include/Ppi/TempRamExitPpi.h
View File

@@ -36,7 +36,7 @@ typedef struct _FSP_TEMP_RAM_EXIT_PPI FSP_TEMP_RAM_EXIT_PPI;
**/
typedef
EFI_STATUS
(EFIAPI *FSP_TEMP_RAM_EXIT) (
(EFIAPI *FSP_TEMP_RAM_EXIT)(
IN VOID *TempRamExitParamPtr
);
@@ -44,9 +44,9 @@ EFI_STATUS
/// This PPI provides function to disable temporary memory.
///
struct _FSP_TEMP_RAM_EXIT_PPI {
FSP_TEMP_RAM_EXIT TempRamExit;
FSP_TEMP_RAM_EXIT TempRamExit;
};
extern EFI_GUID gFspTempRamExitPpiGuid;
extern EFI_GUID gFspTempRamExitPpiGuid;
#endif // _FSP_TEMP_RAM_EXIT_PPI_H_