Arm Packages: Fixed coding style/Line endings to follow EDK2 coding convention
Arm Packages: Fixed mispelling Arm Packages: Reduced warnings all over the code git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12407 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin
@@ -1,134 +1,132 @@
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#/** @file
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# Arm Versatile Express package.
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#
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||||
# Copyright (c) 2011, ARM Limited. All rights reserved.
|
||||
#
|
||||
# This program and the accompanying materials
|
||||
# are licensed and made available under the terms and conditions of the BSD License
|
||||
# which accompanies this distribution. The full text of the license may be found at
|
||||
# http://opensource.org/licenses/bsd-license.php
|
||||
#
|
||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
#
|
||||
#**/
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||||
|
||||
[Defines]
|
||||
DEC_SPECIFICATION = 0x00010005
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||||
PACKAGE_NAME = ArmPlatformPkg
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||||
PACKAGE_GUID = 3308e0a0-1d94-11e0-915c-0002a5d5c51b
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||||
PACKAGE_VERSION = 0.1
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||||
|
||||
################################################################################
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||||
#
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||||
# Include Section - list of Include Paths that are provided by this package.
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||||
# Comments are used for Keywords and Module Types.
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||||
#
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||||
# Supported Module Types:
|
||||
# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
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||||
#
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||||
################################################################################
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||||
[Includes.common]
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Include # Root include for the package
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[Guids.common]
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gArmPlatformTokenSpaceGuid = { 0x9c0aaed4, 0x74c5, 0x4043, { 0xb4, 0x17, 0xa3, 0x22, 0x38, 0x14, 0xce, 0x76 } }
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#
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||||
# Following Guid must match FILE_GUID in MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
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||||
#
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||||
gVariableRuntimeDxeFileGuid = { 0xcbd2e4d5, 0x7068, 0x4ff5, { 0xb4, 0x62, 0x98, 0x22, 0xb4, 0xad, 0x8d, 0x60 } }
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[PcdsFeatureFlag.common]
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# Set this PCD to TRUE to map NORFlash at 0x0. FALSE means the DRAM is mapped at 0x0.
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gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping|FALSE|BOOLEAN|0x00000012
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gArmPlatformTokenSpaceGuid.PcdStandalone|TRUE|BOOLEAN|0x00000001
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gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|FALSE|BOOLEAN|0x00000002
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gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|FALSE|BOOLEAN|0x00000004
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[PcdsFixedAtBuild.common]
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# These PCDs should be FeaturePcds. But we used these PCDs as an '#if' in an ASM file.
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# Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.
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gArmPlatformTokenSpaceGuid.PcdMPCoreSupport|0|UINT32|0x00000003
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gArmPlatformTokenSpaceGuid.PcdMPCoreMaxCores|1|UINT32|0x0000002D
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# Stack for CPU Cores in Secure Mode
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gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0|UINT32|0x00000005
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gArmPlatformTokenSpaceGuid.PcdCPUCoreSecStackSize|0|UINT32|0x00000006
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# Stack for CPU Cores in Secure Monitor Mode
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gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT32|0x00000007
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gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0|UINT32|0x00000008
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# Stack for CPU Cores in Non Secure Mode
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gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase|0|UINT32|0x00000009
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gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize|0|UINT32|0x0000000A
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# Size of the region used by UEFI in permanent memory (Reserved 128MB by default)
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gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x08000000|UINT32|0x00000015
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# Size to reserve in the primary core stack for PEI Global Variables
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# = sizeof(UINTN) /* PcdPeiServicePtr or HobListPtr */
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gArmPlatformTokenSpaceGuid.PcdPeiGlobalVariableSize|0x4|UINT32|0x00000016
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# PeiServicePtr and HobListPtr shares the same location in the PEI Global Variable list
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# PeiServicePtr is only valid with PEI Core and HobListPtr only when the PEI Core is skipped.
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gArmPlatformTokenSpaceGuid.PcdPeiServicePtrGlobalOffset|0x0|UINT32|0x00000017
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gArmPlatformTokenSpaceGuid.PcdHobListPtrGlobalOffset|0x0|UINT32|0x00000018
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#
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# ARM Primecells
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#
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## SP804 DualTimer
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gArmPlatformTokenSpaceGuid.PcdSP804TimerFrequencyInMHz|1|UINT32|0x0000001D
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gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicInterruptNum|0|UINT32|0x0000001E
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gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicBase|0|UINT32|0x0000002A
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gArmPlatformTokenSpaceGuid.PcdSP804TimerPerformanceBase|0|UINT32|0x0000002B
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gArmPlatformTokenSpaceGuid.PcdSP804TimerMetronomeBase|0|UINT32|0x0000002C
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## SP805 Watchdog
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gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x0|UINT32|0x00000023
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gArmPlatformTokenSpaceGuid.PcdSP805WatchdogClockFrequencyInHz|32000|UINT32|0x00000021
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## PL011 UART
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gArmPlatformTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0x00000000|UINT32|0x0000001F
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gArmPlatformTokenSpaceGuid.PcdUartDefaultTimeout|0x00000000|UINT32|0x00000020
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## PL031 RealTimeClock
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gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0|UINT32|0x00000024
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gArmPlatformTokenSpaceGuid.PcdPL031RtcPpmAccuracy|300000000|UINT32|0x00000022
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## PL061 GPIO
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gArmPlatformTokenSpaceGuid.PcdPL061GpioBase|0x0|UINT32|0x00000025
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## PL111 Lcd
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gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x0|UINT32|0x00000026
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gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase|0x0|UINT32|0x00000027
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## PL180 MCI
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gArmPlatformTokenSpaceGuid.PcdPL180SysMciRegAddress|0x00000000|UINT32|0x00000028
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gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress|0x00000000|UINT32|0x00000029
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#
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# BDS - Boot Manager
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#
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gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Platform"|VOID*|0x00000019
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gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Default Boot Device"|VOID*|0x0000000C
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gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L""|VOID*|0x0000000D
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gArmPlatformTokenSpaceGuid.PcdDefaultBootInitrdPath|L""|VOID*|0x0000000E
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gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|""|VOID*|0x000000F
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# PcdDefaultBootType define the type of the binary pointed by PcdDefaultBootDevicePath:
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# - 0 = an EFI application
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# - 1 = a Linux kernel with ATAG support
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# - 2 = a Linux kernel with FDT support
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gArmPlatformTokenSpaceGuid.PcdDefaultBootType|0|UINT32|0x00000010
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gArmPlatformTokenSpaceGuid.PcdFdtDevicePath|L""|VOID*|0x00000011
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## Timeout value for displaying progressing bar in before boot OS.
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# According to UEFI 2.0 spec, the default TimeOut should be 0xffff.
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gArmPlatformTokenSpaceGuid.PcdPlatformBootTimeOut|0xffff|UINT16|0x0000001A
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gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L""|VOID*|0x0000001B
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gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L""|VOID*|0x0000001C
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#/** @file
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#
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# Copyright (c) 2011, ARM Limited. All rights reserved.
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#
|
||||
# This program and the accompanying materials
|
||||
# are licensed and made available under the terms and conditions of the BSD License
|
||||
# which accompanies this distribution. The full text of the license may be found at
|
||||
# http://opensource.org/licenses/bsd-license.php
|
||||
#
|
||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
#
|
||||
#**/
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||||
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||||
[Defines]
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||||
DEC_SPECIFICATION = 0x00010005
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||||
PACKAGE_NAME = ArmPlatformPkg
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||||
PACKAGE_GUID = 3308e0a0-1d94-11e0-915c-0002a5d5c51b
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PACKAGE_VERSION = 0.1
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||||
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||||
################################################################################
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||||
#
|
||||
# Include Section - list of Include Paths that are provided by this package.
|
||||
# Comments are used for Keywords and Module Types.
|
||||
#
|
||||
# Supported Module Types:
|
||||
# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
|
||||
#
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||||
################################################################################
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||||
[Includes.common]
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||||
Include # Root include for the package
|
||||
|
||||
[Guids.common]
|
||||
gArmPlatformTokenSpaceGuid = { 0x9c0aaed4, 0x74c5, 0x4043, { 0xb4, 0x17, 0xa3, 0x22, 0x38, 0x14, 0xce, 0x76 } }
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||||
#
|
||||
# Following Guid must match FILE_GUID in MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
|
||||
#
|
||||
gVariableRuntimeDxeFileGuid = { 0xcbd2e4d5, 0x7068, 0x4ff5, { 0xb4, 0x62, 0x98, 0x22, 0xb4, 0xad, 0x8d, 0x60 } }
|
||||
|
||||
[PcdsFeatureFlag.common]
|
||||
# Set this PCD to TRUE to map NORFlash at 0x0. FALSE means the DRAM is mapped at 0x0.
|
||||
gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping|FALSE|BOOLEAN|0x00000012
|
||||
|
||||
gArmPlatformTokenSpaceGuid.PcdStandalone|TRUE|BOOLEAN|0x00000001
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||||
gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|FALSE|BOOLEAN|0x00000002
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||||
gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|FALSE|BOOLEAN|0x00000004
|
||||
|
||||
[PcdsFixedAtBuild.common]
|
||||
# These PCDs should be FeaturePcds. But we used these PCDs as an '#if' in an ASM file.
|
||||
# Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.
|
||||
gArmPlatformTokenSpaceGuid.PcdMPCoreSupport|0|UINT32|0x00000003
|
||||
gArmPlatformTokenSpaceGuid.PcdMPCoreMaxCores|1|UINT32|0x0000002D
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||||
|
||||
# Stack for CPU Cores in Secure Mode
|
||||
gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0|UINT32|0x00000005
|
||||
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecStackSize|0|UINT32|0x00000006
|
||||
|
||||
# Stack for CPU Cores in Secure Monitor Mode
|
||||
gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT32|0x00000007
|
||||
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0|UINT32|0x00000008
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||||
|
||||
# Stack for CPU Cores in Non Secure Mode
|
||||
gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase|0|UINT32|0x00000009
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||||
gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize|0|UINT32|0x0000000A
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||||
|
||||
# Size of the region used by UEFI in permanent memory (Reserved 128MB by default)
|
||||
gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x08000000|UINT32|0x00000015
|
||||
|
||||
# Size to reserve in the primary core stack for PEI Global Variables
|
||||
# = sizeof(UINTN) /* PcdPeiServicePtr or HobListPtr */
|
||||
gArmPlatformTokenSpaceGuid.PcdPeiGlobalVariableSize|0x4|UINT32|0x00000016
|
||||
# PeiServicePtr and HobListPtr shares the same location in the PEI Global Variable list
|
||||
# PeiServicePtr is only valid with PEI Core and HobListPtr only when the PEI Core is skipped.
|
||||
gArmPlatformTokenSpaceGuid.PcdPeiServicePtrGlobalOffset|0x0|UINT32|0x00000017
|
||||
gArmPlatformTokenSpaceGuid.PcdHobListPtrGlobalOffset|0x0|UINT32|0x00000018
|
||||
|
||||
#
|
||||
# ARM Primecells
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||||
#
|
||||
|
||||
## SP804 DualTimer
|
||||
gArmPlatformTokenSpaceGuid.PcdSP804TimerFrequencyInMHz|1|UINT32|0x0000001D
|
||||
gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicInterruptNum|0|UINT32|0x0000001E
|
||||
gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicBase|0|UINT32|0x0000002A
|
||||
gArmPlatformTokenSpaceGuid.PcdSP804TimerPerformanceBase|0|UINT32|0x0000002B
|
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gArmPlatformTokenSpaceGuid.PcdSP804TimerMetronomeBase|0|UINT32|0x0000002C
|
||||
|
||||
## SP805 Watchdog
|
||||
gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x0|UINT32|0x00000023
|
||||
gArmPlatformTokenSpaceGuid.PcdSP805WatchdogClockFrequencyInHz|32000|UINT32|0x00000021
|
||||
|
||||
## PL011 UART
|
||||
gArmPlatformTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0x00000000|UINT32|0x0000001F
|
||||
gArmPlatformTokenSpaceGuid.PcdUartDefaultTimeout|0x00000000|UINT32|0x00000020
|
||||
|
||||
## PL031 RealTimeClock
|
||||
gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0|UINT32|0x00000024
|
||||
gArmPlatformTokenSpaceGuid.PcdPL031RtcPpmAccuracy|300000000|UINT32|0x00000022
|
||||
|
||||
## PL061 GPIO
|
||||
gArmPlatformTokenSpaceGuid.PcdPL061GpioBase|0x0|UINT32|0x00000025
|
||||
|
||||
## PL111 Lcd
|
||||
gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x0|UINT32|0x00000026
|
||||
gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase|0x0|UINT32|0x00000027
|
||||
|
||||
## PL180 MCI
|
||||
gArmPlatformTokenSpaceGuid.PcdPL180SysMciRegAddress|0x00000000|UINT32|0x00000028
|
||||
gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress|0x00000000|UINT32|0x00000029
|
||||
|
||||
#
|
||||
# BDS - Boot Manager
|
||||
#
|
||||
gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Platform"|VOID*|0x00000019
|
||||
gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Default Boot Device"|VOID*|0x0000000C
|
||||
gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L""|VOID*|0x0000000D
|
||||
gArmPlatformTokenSpaceGuid.PcdDefaultBootInitrdPath|L""|VOID*|0x0000000E
|
||||
gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|""|VOID*|0x000000F
|
||||
# PcdDefaultBootType define the type of the binary pointed by PcdDefaultBootDevicePath:
|
||||
# - 0 = an EFI application
|
||||
# - 1 = a Linux kernel with ATAG support
|
||||
# - 2 = a Linux kernel with FDT support
|
||||
gArmPlatformTokenSpaceGuid.PcdDefaultBootType|0|UINT32|0x00000010
|
||||
gArmPlatformTokenSpaceGuid.PcdFdtDevicePath|L""|VOID*|0x00000011
|
||||
|
||||
## Timeout value for displaying progressing bar in before boot OS.
|
||||
# According to UEFI 2.0 spec, the default TimeOut should be 0xffff.
|
||||
gArmPlatformTokenSpaceGuid.PcdPlatformBootTimeOut|0xffff|UINT16|0x0000001A
|
||||
|
||||
gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L""|VOID*|0x0000001B
|
||||
gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L""|VOID*|0x0000001C
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,41 +1,41 @@
|
||||
#/* @file
|
||||
# Copyright (c) 2011, ARM Limited. All rights reserved.
|
||||
#
|
||||
# This program and the accompanying materials
|
||||
# are licensed and made available under the terms and conditions of the BSD License
|
||||
# which accompanies this distribution. The full text of the license may be found at
|
||||
# http://opensource.org/licenses/bsd-license.php
|
||||
#
|
||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
#
|
||||
#*/
|
||||
|
||||
[Defines]
|
||||
INF_VERSION = 0x00010005
|
||||
BASE_NAME = ArmRealViewEbLib
|
||||
FILE_GUID = 736343a0-1d96-11e0-aaaa-0002a5d5c51b
|
||||
MODULE_TYPE = BASE
|
||||
VERSION_STRING = 1.0
|
||||
LIBRARY_CLASS = ArmPlatformLib
|
||||
|
||||
[Packages]
|
||||
MdePkg/MdePkg.dec
|
||||
MdeModulePkg/MdeModulePkg.dec
|
||||
EmbeddedPkg/EmbeddedPkg.dec
|
||||
ArmPkg/ArmPkg.dec
|
||||
ArmPlatformPkg/ArmPlatformPkg.dec
|
||||
|
||||
[LibraryClasses]
|
||||
IoLib
|
||||
ArmLib
|
||||
MemoryAllocationLib
|
||||
|
||||
[Sources.common]
|
||||
ArmRealViewEb.c
|
||||
ArmRealViewEbMem.c
|
||||
ArmRealViewEbHelper.asm | RVCT
|
||||
ArmRealViewEbHelper.S | GCC
|
||||
|
||||
[FeaturePcd]
|
||||
gEmbeddedTokenSpaceGuid.PcdCacheEnable
|
||||
#/* @file
|
||||
# Copyright (c) 2011, ARM Limited. All rights reserved.
|
||||
#
|
||||
# This program and the accompanying materials
|
||||
# are licensed and made available under the terms and conditions of the BSD License
|
||||
# which accompanies this distribution. The full text of the license may be found at
|
||||
# http://opensource.org/licenses/bsd-license.php
|
||||
#
|
||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
#
|
||||
#*/
|
||||
|
||||
[Defines]
|
||||
INF_VERSION = 0x00010005
|
||||
BASE_NAME = ArmRealViewEbLib
|
||||
FILE_GUID = 736343a0-1d96-11e0-aaaa-0002a5d5c51b
|
||||
MODULE_TYPE = BASE
|
||||
VERSION_STRING = 1.0
|
||||
LIBRARY_CLASS = ArmPlatformLib
|
||||
|
||||
[Packages]
|
||||
MdePkg/MdePkg.dec
|
||||
MdeModulePkg/MdeModulePkg.dec
|
||||
EmbeddedPkg/EmbeddedPkg.dec
|
||||
ArmPkg/ArmPkg.dec
|
||||
ArmPlatformPkg/ArmPlatformPkg.dec
|
||||
|
||||
[LibraryClasses]
|
||||
IoLib
|
||||
ArmLib
|
||||
MemoryAllocationLib
|
||||
|
||||
[Sources.common]
|
||||
ArmRealViewEb.c
|
||||
ArmRealViewEbMem.c
|
||||
ArmRealViewEbHelper.asm | RVCT
|
||||
ArmRealViewEbHelper.S | GCC
|
||||
|
||||
[FeaturePcd]
|
||||
gEmbeddedTokenSpaceGuid.PcdCacheEnable
|
||||
|
||||
@@ -142,6 +142,8 @@ LcdPlatformGetVram (
|
||||
EFI_STATUS Status;
|
||||
EFI_CPU_ARCH_PROTOCOL *Cpu;
|
||||
|
||||
Status = EFI_SUCCESS;
|
||||
|
||||
// Is it on the motherboard or on the daughterboard?
|
||||
switch(PL111_CLCD_SITE) {
|
||||
|
||||
|
||||
@@ -45,6 +45,7 @@
|
||||
UefiDriverEntryPoint
|
||||
DebugLib
|
||||
PrintLib
|
||||
BaseLib
|
||||
|
||||
[Guids]
|
||||
gEfiFileSystemInfoGuid
|
||||
|
||||
@@ -239,7 +239,7 @@ GenerateDeviceDescriptionName (
|
||||
//TODO: Fixme. we must find the best langague
|
||||
Status = ComponentName2Protocol->GetDriverName (ComponentName2Protocol,"en",&DriverName);
|
||||
if (!EFI_ERROR(Status)) {
|
||||
StrnCpy (Description,DriverName,BOOT_DEVICE_DESCRIPTION_MAX);
|
||||
StrnCpy (Description, DriverName, BOOT_DEVICE_DESCRIPTION_MAX);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -254,7 +254,7 @@ GenerateDeviceDescriptionName (
|
||||
DevicePathNode = GetLastDevicePathNode (DevicePathProtocol);
|
||||
Status = gBS->LocateProtocol (&gEfiDevicePathToTextProtocolGuid, NULL, (VOID **)&DevicePathToTextProtocol);
|
||||
ASSERT_EFI_ERROR(Status);
|
||||
DevicePathTxt = DevicePathToTextProtocol->ConvertDevicePathToText(DevicePathNode,TRUE,TRUE);
|
||||
DevicePathTxt = DevicePathToTextProtocol->ConvertDevicePathToText (DevicePathNode, TRUE, TRUE);
|
||||
StrnCpy (Description, DevicePathTxt, BOOT_DEVICE_DESCRIPTION_MAX);
|
||||
FreePool (DevicePathTxt);
|
||||
}
|
||||
|
||||
@@ -42,6 +42,9 @@
|
||||
|
||||
#define IS_ARM_BDS_BOOTENTRY(ptr) (ReadUnaligned32 ((CONST UINT32*)&((ARM_BDS_LOADER_OPTIONAL_DATA*)((ptr)->OptionalData))->Header.Signature) == ARM_BDS_OPTIONAL_DATA_SIGNATURE)
|
||||
|
||||
#define UPDATE_BOOT_ENTRY L"Update entry: "
|
||||
#define DELETE_BOOT_ENTRY L"Delete entry: "
|
||||
|
||||
typedef enum {
|
||||
BDS_LOADER_EFI_APPLICATION = 0,
|
||||
BDS_LOADER_KERNEL_LINUX_ATAG,
|
||||
|
||||
@@ -315,7 +315,7 @@ BootMenuRemoveBootOption (
|
||||
EFI_STATUS Status;
|
||||
BDS_LOAD_OPTION_ENTRY* BootOptionEntry;
|
||||
|
||||
Status = BootMenuSelectBootOption (BootOptionsList, L"Delete entry: ", FALSE, &BootOptionEntry);
|
||||
Status = BootMenuSelectBootOption (BootOptionsList, DELETE_BOOT_ENTRY, FALSE, &BootOptionEntry);
|
||||
if (EFI_ERROR(Status)) {
|
||||
return Status;
|
||||
}
|
||||
@@ -352,7 +352,7 @@ BootMenuUpdateBootOption (
|
||||
UINTN InitrdSize;
|
||||
UINTN CmdLineSize;
|
||||
|
||||
Status = BootMenuSelectBootOption (BootOptionsList, L"Update entry: ", TRUE, &BootOptionEntry);
|
||||
Status = BootMenuSelectBootOption (BootOptionsList, UPDATE_BOOT_ENTRY, TRUE, &BootOptionEntry);
|
||||
if (EFI_ERROR(Status)) {
|
||||
return Status;
|
||||
}
|
||||
@@ -476,8 +476,7 @@ BootMenuManager (
|
||||
BootManagerEntries[OptionSelected-1].Callback (BootOptionsList);
|
||||
}
|
||||
}
|
||||
|
||||
return EFI_SUCCESS;
|
||||
// Should never go here
|
||||
}
|
||||
|
||||
EFI_STATUS
|
||||
@@ -619,6 +618,5 @@ BootMenuMain (
|
||||
Status = BootOptionStart (BootOption);
|
||||
}
|
||||
}
|
||||
|
||||
return Status;
|
||||
// Should never go here
|
||||
}
|
||||
|
||||
@@ -209,7 +209,7 @@ BootDeviceGetDeviceSupport (
|
||||
|
||||
// Find which supported device is the most appropriate
|
||||
for (Index = 0; Index < BDS_DEVICE_MAX; Index++) {
|
||||
if (BdsLoadOptionSupportList[Index].IsSupported(BootOption)) {
|
||||
if (BdsLoadOptionSupportList[Index].IsSupported (BootOption)) {
|
||||
*DeviceSupport = &BdsLoadOptionSupportList[Index];
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
@@ -29,16 +29,16 @@
|
||||
|
||||
#include <Drivers/SP804Timer.h>
|
||||
|
||||
#define SP804_TIMER_PERIODIC_BASE (UINTN)PcdGet32 (PcdSP804TimerPeriodicBase)
|
||||
#define SP804_TIMER_METRONOME_BASE (UINTN)PcdGet32 (PcdSP804TimerMetronomeBase)
|
||||
#define SP804_TIMER_PERFORMANCE_BASE (UINTN)PcdGet32 (PcdSP804TimerPerformanceBase)
|
||||
#define SP804_TIMER_PERIODIC_BASE ((UINTN)PcdGet32 (PcdSP804TimerPeriodicBase))
|
||||
#define SP804_TIMER_METRONOME_BASE ((UINTN)PcdGet32 (PcdSP804TimerMetronomeBase))
|
||||
#define SP804_TIMER_PERFORMANCE_BASE ((UINTN)PcdGet32 (PcdSP804TimerPerformanceBase))
|
||||
|
||||
// The notification function to call on every timer interrupt.
|
||||
volatile EFI_TIMER_NOTIFY mTimerNotifyFunction = (EFI_TIMER_NOTIFY)NULL;
|
||||
EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL;
|
||||
EFI_TIMER_NOTIFY mTimerNotifyFunction = (EFI_TIMER_NOTIFY)NULL;
|
||||
EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL;
|
||||
|
||||
// The current period of the timer interrupt
|
||||
volatile UINT64 mTimerPeriod = 0;
|
||||
UINT64 mTimerPeriod = 0;
|
||||
|
||||
// Cached copy of the Hardware Interrupt protocol instance
|
||||
EFI_HARDWARE_INTERRUPT_PROTOCOL *gInterrupt = NULL;
|
||||
@@ -78,10 +78,10 @@ TimerInterruptHandler (
|
||||
|
||||
// If the interrupt is shared then we must check if this interrupt source is the one associated to this Timer
|
||||
if (MmioRead32 (SP804_TIMER_PERIODIC_BASE + SP804_TIMER_MSK_INT_STS_REG) != 0) {
|
||||
// clear the periodic interrupt
|
||||
// Clear the periodic interrupt
|
||||
MmioWrite32 (SP804_TIMER_PERIODIC_BASE + SP804_TIMER_INT_CLR_REG, 0);
|
||||
|
||||
// signal end of interrupt early to help avoid losing subsequent ticks from long duration handlers
|
||||
// Signal end of interrupt early to help avoid losing subsequent ticks from long duration handlers
|
||||
gInterrupt->EndOfInterrupt (gInterrupt, Source);
|
||||
|
||||
if (mTimerNotifyFunction) {
|
||||
@@ -213,15 +213,13 @@ TimerDriverSetTimerPeriod (
|
||||
// Disable timer 0/1 interrupt for a TimerPeriod of 0
|
||||
Status = gInterrupt->DisableInterruptSource (gInterrupt, gVector);
|
||||
} else {
|
||||
// Convert TimerPeriod into 1MHz clock counts (us units = 100ns units / 10)
|
||||
// Convert TimerPeriod into 1MHz clock counts (us units = 100ns units * 10)
|
||||
TimerTicks = DivU64x32 (TimerPeriod, 10);
|
||||
TimerTicks = MultU64x32 (TimerTicks, PcdGet32(PcdSP804TimerFrequencyInMHz));
|
||||
|
||||
// if it's larger than 32-bits, pin to highest value
|
||||
if (TimerTicks > 0xffffffff) {
|
||||
|
||||
TimerTicks = 0xffffffff;
|
||||
|
||||
}
|
||||
|
||||
// Program the SP804 timer with the new count value
|
||||
|
||||
@@ -1,69 +1,69 @@
|
||||
//
|
||||
// Copyright (c) 2011, ARM Limited. All rights reserved.
|
||||
//
|
||||
// This program and the accompanying materials
|
||||
// are licensed and made available under the terms and conditions of the BSD License
|
||||
// which accompanies this distribution. The full text of the license may be found at
|
||||
// http://opensource.org/licenses/bsd-license.php
|
||||
//
|
||||
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
//
|
||||
//
|
||||
|
||||
#include <AsmMacroIoLib.h>
|
||||
#include <Base.h>
|
||||
#include <Library/PcdLib.h>
|
||||
#include <AutoGen.h>
|
||||
|
||||
.text
|
||||
.align 3
|
||||
|
||||
#global symbols referenced by this module
|
||||
GCC_ASM_IMPORT(CEntryPoint)
|
||||
|
||||
StartupAddr: .word CEntryPoint
|
||||
|
||||
#make _ModuleEntryPoint as global
|
||||
GCC_ASM_EXPORT(_ModuleEntryPoint)
|
||||
|
||||
|
||||
ASM_PFX(_ModuleEntryPoint):
|
||||
# Identify CPU ID
|
||||
mrc p15, 0, r0, c0, c0, 5
|
||||
and r0, #0xf
|
||||
|
||||
_SetupStack:
|
||||
# Setup Stack for the 4 CPU cores
|
||||
LoadConstantToReg (FixedPcdGet32(PcdCPUCoresNonSecStackBase), r1)
|
||||
LoadConstantToReg (FixedPcdGet32(PcdCPUCoresNonSecStackSize), r2)
|
||||
|
||||
mov r3,r0 @ r3 = core_id
|
||||
mul r3,r3,r2 @ r3 = core_id * stack_size = offset from the stack base
|
||||
add r3,r3,r1 @ r3 = stack_base + offset
|
||||
add r3,r3,r2,LSR #1 @ r3 = stack_offset + (stack_size/2) <-- the top half is for the heap
|
||||
mov sp, r3
|
||||
|
||||
# Only allocate memory in top of the primary core stack
|
||||
cmp r0, #0
|
||||
bne _PrepareArguments
|
||||
|
||||
_AllocateGlobalPeiVariables:
|
||||
# Reserve top of the stack for Global PEI Variables (eg: PeiServicesTablePointer)
|
||||
LoadConstantToReg (FixedPcdGet32(PcdPeiGlobalVariableSize), r1)
|
||||
sub sp, sp, r1
|
||||
|
||||
_PrepareArguments:
|
||||
# The PEI Core Entry Point has been computed by GenFV and stored in the second entry of the Reset Vector
|
||||
LoadConstantToReg (FixedPcdGet32(PcdNormalFvBaseAddress), r2)
|
||||
add r2, r2, #4
|
||||
ldr r1, [r2]
|
||||
|
||||
# move sec startup address into a data register
|
||||
# ensure we're jumping to FV version of the code (not boot remapped alias)
|
||||
ldr r2, StartupAddr
|
||||
|
||||
# jump to PrePeiCore C code
|
||||
# r0 = core_id
|
||||
# r1 = pei_core_address
|
||||
blx r2
|
||||
//
|
||||
// Copyright (c) 2011, ARM Limited. All rights reserved.
|
||||
//
|
||||
// This program and the accompanying materials
|
||||
// are licensed and made available under the terms and conditions of the BSD License
|
||||
// which accompanies this distribution. The full text of the license may be found at
|
||||
// http://opensource.org/licenses/bsd-license.php
|
||||
//
|
||||
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
//
|
||||
//
|
||||
|
||||
#include <AsmMacroIoLib.h>
|
||||
#include <Base.h>
|
||||
#include <Library/PcdLib.h>
|
||||
#include <AutoGen.h>
|
||||
|
||||
.text
|
||||
.align 3
|
||||
|
||||
#global symbols referenced by this module
|
||||
GCC_ASM_IMPORT(CEntryPoint)
|
||||
|
||||
StartupAddr: .word CEntryPoint
|
||||
|
||||
#make _ModuleEntryPoint as global
|
||||
GCC_ASM_EXPORT(_ModuleEntryPoint)
|
||||
|
||||
|
||||
ASM_PFX(_ModuleEntryPoint):
|
||||
# Identify CPU ID
|
||||
mrc p15, 0, r0, c0, c0, 5
|
||||
and r0, #0xf
|
||||
|
||||
_SetupStack:
|
||||
# Setup Stack for the 4 CPU cores
|
||||
LoadConstantToReg (FixedPcdGet32(PcdCPUCoresNonSecStackBase), r1)
|
||||
LoadConstantToReg (FixedPcdGet32(PcdCPUCoresNonSecStackSize), r2)
|
||||
|
||||
mov r3,r0 @ r3 = core_id
|
||||
mul r3,r3,r2 @ r3 = core_id * stack_size = offset from the stack base
|
||||
add r3,r3,r1 @ r3 = stack_base + offset
|
||||
add r3,r3,r2,LSR #1 @ r3 = stack_offset + (stack_size/2) <-- the top half is for the heap
|
||||
mov sp, r3
|
||||
|
||||
# Only allocate memory in top of the primary core stack
|
||||
cmp r0, #0
|
||||
bne _PrepareArguments
|
||||
|
||||
_AllocateGlobalPeiVariables:
|
||||
# Reserve top of the stack for Global PEI Variables (eg: PeiServicesTablePointer)
|
||||
LoadConstantToReg (FixedPcdGet32(PcdPeiGlobalVariableSize), r1)
|
||||
sub sp, sp, r1
|
||||
|
||||
_PrepareArguments:
|
||||
# The PEI Core Entry Point has been computed by GenFV and stored in the second entry of the Reset Vector
|
||||
LoadConstantToReg (FixedPcdGet32(PcdNormalFvBaseAddress), r2)
|
||||
add r2, r2, #4
|
||||
ldr r1, [r2]
|
||||
|
||||
# move sec startup address into a data register
|
||||
# ensure we're jumping to FV version of the code (not boot remapped alias)
|
||||
ldr r2, StartupAddr
|
||||
|
||||
# jump to PrePeiCore C code
|
||||
# r0 = core_id
|
||||
# r1 = pei_core_address
|
||||
blx r2
|
||||
|
||||
@@ -44,6 +44,7 @@
|
||||
DebugAgentLib
|
||||
IoLib
|
||||
PrintLib
|
||||
SerialPortLib
|
||||
|
||||
[Ppis]
|
||||
gEfiTemporaryRamSupportPpiGuid
|
||||
@@ -62,6 +63,3 @@
|
||||
|
||||
gArmTokenSpaceGuid.PcdGicDistributorBase
|
||||
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
|
||||
|
||||
gArmTokenSpaceGuid.PcdNormalFvBaseAddress
|
||||
gArmTokenSpaceGuid.PcdNormalFvSize
|
||||
|
||||
@@ -1,99 +1,99 @@
|
||||
#/** @file
|
||||
#
|
||||
# Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>
|
||||
# This program and the accompanying materials
|
||||
# are licensed and made available under the terms and conditions of the BSD License
|
||||
# which accompanies this distribution. The full text of the license may be found at
|
||||
# http://opensource.org/licenses/bsd-license.php
|
||||
#
|
||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
#
|
||||
#**/
|
||||
|
||||
[Defines]
|
||||
INF_VERSION = 0x00010005
|
||||
BASE_NAME = ArmPlatformPrePiMPCore
|
||||
FILE_GUID = d959e387-7b91-452c-90e0-a1dbac90ddb8
|
||||
MODULE_TYPE = SEC
|
||||
VERSION_STRING = 1.0
|
||||
|
||||
[Sources.ARM]
|
||||
PrePi.c
|
||||
ModuleEntryPoint.S | GCC
|
||||
ModuleEntryPoint.asm | RVCT
|
||||
Exception.S | GCC
|
||||
Exception.asm | RVCT
|
||||
MainMPCore.c
|
||||
|
||||
[Packages]
|
||||
MdePkg/MdePkg.dec
|
||||
MdeModulePkg/MdeModulePkg.dec
|
||||
EmbeddedPkg/EmbeddedPkg.dec
|
||||
ArmPkg/ArmPkg.dec
|
||||
ArmPlatformPkg/ArmPlatformPkg.dec
|
||||
IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec
|
||||
|
||||
[LibraryClasses]
|
||||
BaseLib
|
||||
DebugLib
|
||||
DebugAgentLib
|
||||
ArmLib
|
||||
ArmMPCoreMailBoxLib
|
||||
PL390GicNonSecLib
|
||||
IoLib
|
||||
TimerLib
|
||||
SerialPortLib
|
||||
ExtractGuidedSectionLib
|
||||
LzmaDecompressLib
|
||||
PeCoffGetEntryPointLib
|
||||
DebugAgentLib
|
||||
PrePiLib
|
||||
ArmPlatformLib
|
||||
MemoryAllocationLib
|
||||
HobLib
|
||||
PrePiHobListPointerLib
|
||||
PlatformPeiLib
|
||||
MemoryInitPeiLib
|
||||
|
||||
[FeaturePcd]
|
||||
gEmbeddedTokenSpaceGuid.PcdCacheEnable
|
||||
gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob
|
||||
gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores
|
||||
|
||||
[FixedPcd]
|
||||
gArmTokenSpaceGuid.PcdVFPEnabled
|
||||
|
||||
gArmTokenSpaceGuid.PcdNormalFdBaseAddress
|
||||
gArmTokenSpaceGuid.PcdNormalFdSize
|
||||
|
||||
gArmTokenSpaceGuid.PcdNormalFvBaseAddress
|
||||
gArmTokenSpaceGuid.PcdNormalFvSize
|
||||
|
||||
gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase
|
||||
gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize
|
||||
|
||||
gArmPlatformTokenSpaceGuid.PcdPeiGlobalVariableSize
|
||||
gArmPlatformTokenSpaceGuid.PcdHobListPtrGlobalOffset
|
||||
|
||||
gArmTokenSpaceGuid.PcdGicDistributorBase
|
||||
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
|
||||
|
||||
gArmTokenSpaceGuid.PcdSystemMemoryBase
|
||||
gArmTokenSpaceGuid.PcdSystemMemorySize
|
||||
gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize
|
||||
|
||||
gArmPlatformTokenSpaceGuid.PcdMPCoreMaxCores
|
||||
gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize
|
||||
gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize
|
||||
|
||||
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory
|
||||
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS
|
||||
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType
|
||||
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData
|
||||
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode
|
||||
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode
|
||||
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData
|
||||
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode
|
||||
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData
|
||||
|
||||
#/** @file
|
||||
#
|
||||
# Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>
|
||||
# This program and the accompanying materials
|
||||
# are licensed and made available under the terms and conditions of the BSD License
|
||||
# which accompanies this distribution. The full text of the license may be found at
|
||||
# http://opensource.org/licenses/bsd-license.php
|
||||
#
|
||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
#
|
||||
#**/
|
||||
|
||||
[Defines]
|
||||
INF_VERSION = 0x00010005
|
||||
BASE_NAME = ArmPlatformPrePiMPCore
|
||||
FILE_GUID = d959e387-7b91-452c-90e0-a1dbac90ddb8
|
||||
MODULE_TYPE = SEC
|
||||
VERSION_STRING = 1.0
|
||||
|
||||
[Sources.ARM]
|
||||
PrePi.c
|
||||
ModuleEntryPoint.S | GCC
|
||||
ModuleEntryPoint.asm | RVCT
|
||||
Exception.S | GCC
|
||||
Exception.asm | RVCT
|
||||
MainMPCore.c
|
||||
|
||||
[Packages]
|
||||
MdePkg/MdePkg.dec
|
||||
MdeModulePkg/MdeModulePkg.dec
|
||||
EmbeddedPkg/EmbeddedPkg.dec
|
||||
ArmPkg/ArmPkg.dec
|
||||
ArmPlatformPkg/ArmPlatformPkg.dec
|
||||
IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec
|
||||
|
||||
[LibraryClasses]
|
||||
BaseLib
|
||||
DebugLib
|
||||
DebugAgentLib
|
||||
ArmLib
|
||||
ArmMPCoreMailBoxLib
|
||||
PL390GicNonSecLib
|
||||
IoLib
|
||||
TimerLib
|
||||
SerialPortLib
|
||||
ExtractGuidedSectionLib
|
||||
LzmaDecompressLib
|
||||
PeCoffGetEntryPointLib
|
||||
DebugAgentLib
|
||||
PrePiLib
|
||||
ArmPlatformLib
|
||||
MemoryAllocationLib
|
||||
HobLib
|
||||
PrePiHobListPointerLib
|
||||
PlatformPeiLib
|
||||
MemoryInitPeiLib
|
||||
|
||||
[FeaturePcd]
|
||||
gEmbeddedTokenSpaceGuid.PcdCacheEnable
|
||||
gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob
|
||||
gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores
|
||||
|
||||
[FixedPcd]
|
||||
gArmTokenSpaceGuid.PcdVFPEnabled
|
||||
|
||||
gArmTokenSpaceGuid.PcdNormalFdBaseAddress
|
||||
gArmTokenSpaceGuid.PcdNormalFdSize
|
||||
|
||||
gArmTokenSpaceGuid.PcdNormalFvBaseAddress
|
||||
gArmTokenSpaceGuid.PcdNormalFvSize
|
||||
|
||||
gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase
|
||||
gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize
|
||||
|
||||
gArmPlatformTokenSpaceGuid.PcdPeiGlobalVariableSize
|
||||
gArmPlatformTokenSpaceGuid.PcdHobListPtrGlobalOffset
|
||||
|
||||
gArmTokenSpaceGuid.PcdGicDistributorBase
|
||||
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
|
||||
|
||||
gArmTokenSpaceGuid.PcdSystemMemoryBase
|
||||
gArmTokenSpaceGuid.PcdSystemMemorySize
|
||||
gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize
|
||||
|
||||
gArmPlatformTokenSpaceGuid.PcdMPCoreMaxCores
|
||||
gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize
|
||||
gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize
|
||||
|
||||
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory
|
||||
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS
|
||||
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType
|
||||
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData
|
||||
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode
|
||||
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode
|
||||
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData
|
||||
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode
|
||||
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData
|
||||
|
||||
|
||||
@@ -15,6 +15,7 @@
|
||||
#include <PiPei.h>
|
||||
|
||||
#include <Library/DebugAgentLib.h>
|
||||
#include <Library/BaseMemoryLib.h>
|
||||
#include <Library/PrePiLib.h>
|
||||
#include <Library/IoLib.h>
|
||||
#include <Library/PrintLib.h>
|
||||
|
||||
@@ -1,112 +1,112 @@
|
||||
#------------------------------------------------------------------------------
|
||||
#
|
||||
# ARM VE Entry point. Reset vector in FV header will brach to
|
||||
# _ModuleEntryPoint.
|
||||
#
|
||||
# Copyright (c) 2011, ARM Limited. All rights reserved.
|
||||
#
|
||||
# This program and the accompanying materials
|
||||
# are licensed and made available under the terms and conditions of the BSD License
|
||||
# which accompanies this distribution. The full text of the license may be found at
|
||||
# http://opensource.org/licenses/bsd-license.php
|
||||
#
|
||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
#
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
#include <AsmMacroIoLib.h>
|
||||
#include <Base.h>
|
||||
#include <Library/PcdLib.h>
|
||||
#include <Library/ArmPlatformLib.h>
|
||||
#include <AutoGen.h>
|
||||
|
||||
#Start of Code section
|
||||
.text
|
||||
.align 3
|
||||
|
||||
#make _ModuleEntryPoint as global
|
||||
GCC_ASM_EXPORT(_ModuleEntryPoint)
|
||||
|
||||
#global functions referenced by this module
|
||||
GCC_ASM_IMPORT(CEntryPoint)
|
||||
GCC_ASM_IMPORT(ArmPlatformIsMemoryInitialized)
|
||||
GCC_ASM_IMPORT(ArmPlatformInitializeBootMemory)
|
||||
GCC_ASM_IMPORT(ArmDisableInterrupts)
|
||||
GCC_ASM_IMPORT(ArmDisableCachesAndMmu)
|
||||
GCC_ASM_IMPORT(ArmWriteVBar)
|
||||
GCC_ASM_IMPORT(SecVectorTable)
|
||||
|
||||
#if (FixedPcdGet32(PcdMPCoreSupport))
|
||||
GCC_ASM_IMPORT(ArmIsScuEnable)
|
||||
#endif
|
||||
|
||||
StartupAddr: .word ASM_PFX(CEntryPoint)
|
||||
SecVectorTableAddr: .word ASM_PFX(SecVectorTable)
|
||||
|
||||
ASM_PFX(_ModuleEntryPoint):
|
||||
#Set VBAR to the start of the exception vectors in Secure Mode
|
||||
ldr r0, SecVectorTableAddr
|
||||
bl ASM_PFX(ArmWriteVBar)
|
||||
|
||||
# First ensure all interrupts are disabled
|
||||
bl ASM_PFX(ArmDisableInterrupts)
|
||||
|
||||
# Ensure that the MMU and caches are off
|
||||
bl ASM_PFX(ArmDisableCachesAndMmu)
|
||||
|
||||
_IdentifyCpu:
|
||||
# Identify CPU ID
|
||||
bl ASM_PFX(ArmReadMpidr)
|
||||
and r5, r0, #0xf
|
||||
|
||||
#get ID of this CPU in Multicore system
|
||||
cmp r5, #0
|
||||
# Only the primary core initialize the memory (SMC)
|
||||
beq _InitMem
|
||||
|
||||
#if (FixedPcdGet32(PcdMPCoreSupport))
|
||||
# ... The secondary cores wait for SCU to be enabled
|
||||
_WaitForEnabledScu:
|
||||
bl ASM_PFX(ArmIsScuEnable)
|
||||
tst r1, #1
|
||||
beq _WaitForEnabledScu
|
||||
b _SetupStack
|
||||
#endif
|
||||
|
||||
_InitMem:
|
||||
bl ASM_PFX(ArmPlatformIsMemoryInitialized)
|
||||
bne _SetupStack
|
||||
|
||||
# Initialize Init Memory
|
||||
bl ASM_PFX(ArmPlatformInitializeBootMemory)
|
||||
|
||||
# Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack)
|
||||
mov r5, #0
|
||||
|
||||
_SetupStack:
|
||||
# Setup Stack for the 4 CPU cores
|
||||
#Read Stack Base address from PCD
|
||||
LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)
|
||||
|
||||
#read Stack size from PCD
|
||||
LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecStackSize), r2)
|
||||
|
||||
#calcuate Stack Pointer reg value using Stack size and CPU ID.
|
||||
mov r3,r5 @ r3 = core_id
|
||||
mul r3,r3,r2 @ r3 = core_id * stack_size = offset from the stack base
|
||||
add r3,r3,r1 @ r3 ldr= stack_base + offset
|
||||
mov sp, r3
|
||||
|
||||
# move sec startup address into a data register
|
||||
# ensure we're jumping to FV version of the code (not boot remapped alias)
|
||||
ldr r3, StartupAddr
|
||||
|
||||
# Move the CoreId in r0 to be the first argument of the SEC Entry Point
|
||||
mov r0, r5
|
||||
|
||||
# jump to SEC C code
|
||||
# r0 = core_id
|
||||
blx r3
|
||||
|
||||
|
||||
#------------------------------------------------------------------------------
|
||||
#
|
||||
# ARM VE Entry point. Reset vector in FV header will brach to
|
||||
# _ModuleEntryPoint.
|
||||
#
|
||||
# Copyright (c) 2011, ARM Limited. All rights reserved.
|
||||
#
|
||||
# This program and the accompanying materials
|
||||
# are licensed and made available under the terms and conditions of the BSD License
|
||||
# which accompanies this distribution. The full text of the license may be found at
|
||||
# http://opensource.org/licenses/bsd-license.php
|
||||
#
|
||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
#
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
#include <AsmMacroIoLib.h>
|
||||
#include <Base.h>
|
||||
#include <Library/PcdLib.h>
|
||||
#include <Library/ArmPlatformLib.h>
|
||||
#include <AutoGen.h>
|
||||
|
||||
#Start of Code section
|
||||
.text
|
||||
.align 3
|
||||
|
||||
#make _ModuleEntryPoint as global
|
||||
GCC_ASM_EXPORT(_ModuleEntryPoint)
|
||||
|
||||
#global functions referenced by this module
|
||||
GCC_ASM_IMPORT(CEntryPoint)
|
||||
GCC_ASM_IMPORT(ArmPlatformIsMemoryInitialized)
|
||||
GCC_ASM_IMPORT(ArmPlatformInitializeBootMemory)
|
||||
GCC_ASM_IMPORT(ArmDisableInterrupts)
|
||||
GCC_ASM_IMPORT(ArmDisableCachesAndMmu)
|
||||
GCC_ASM_IMPORT(ArmWriteVBar)
|
||||
GCC_ASM_IMPORT(SecVectorTable)
|
||||
|
||||
#if (FixedPcdGet32(PcdMPCoreSupport))
|
||||
GCC_ASM_IMPORT(ArmIsScuEnable)
|
||||
#endif
|
||||
|
||||
StartupAddr: .word ASM_PFX(CEntryPoint)
|
||||
SecVectorTableAddr: .word ASM_PFX(SecVectorTable)
|
||||
|
||||
ASM_PFX(_ModuleEntryPoint):
|
||||
#Set VBAR to the start of the exception vectors in Secure Mode
|
||||
ldr r0, SecVectorTableAddr
|
||||
bl ASM_PFX(ArmWriteVBar)
|
||||
|
||||
# First ensure all interrupts are disabled
|
||||
bl ASM_PFX(ArmDisableInterrupts)
|
||||
|
||||
# Ensure that the MMU and caches are off
|
||||
bl ASM_PFX(ArmDisableCachesAndMmu)
|
||||
|
||||
_IdentifyCpu:
|
||||
# Identify CPU ID
|
||||
bl ASM_PFX(ArmReadMpidr)
|
||||
and r5, r0, #0xf
|
||||
|
||||
#get ID of this CPU in Multicore system
|
||||
cmp r5, #0
|
||||
# Only the primary core initialize the memory (SMC)
|
||||
beq _InitMem
|
||||
|
||||
#if (FixedPcdGet32(PcdMPCoreSupport))
|
||||
# ... The secondary cores wait for SCU to be enabled
|
||||
_WaitForEnabledScu:
|
||||
bl ASM_PFX(ArmIsScuEnable)
|
||||
tst r1, #1
|
||||
beq _WaitForEnabledScu
|
||||
b _SetupStack
|
||||
#endif
|
||||
|
||||
_InitMem:
|
||||
bl ASM_PFX(ArmPlatformIsMemoryInitialized)
|
||||
bne _SetupStack
|
||||
|
||||
# Initialize Init Memory
|
||||
bl ASM_PFX(ArmPlatformInitializeBootMemory)
|
||||
|
||||
# Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack)
|
||||
mov r5, #0
|
||||
|
||||
_SetupStack:
|
||||
# Setup Stack for the 4 CPU cores
|
||||
#Read Stack Base address from PCD
|
||||
LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)
|
||||
|
||||
#read Stack size from PCD
|
||||
LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecStackSize), r2)
|
||||
|
||||
#calcuate Stack Pointer reg value using Stack size and CPU ID.
|
||||
mov r3,r5 @ r3 = core_id
|
||||
mul r3,r3,r2 @ r3 = core_id * stack_size = offset from the stack base
|
||||
add r3,r3,r1 @ r3 ldr= stack_base + offset
|
||||
mov sp, r3
|
||||
|
||||
# move sec startup address into a data register
|
||||
# ensure we're jumping to FV version of the code (not boot remapped alias)
|
||||
ldr r3, StartupAddr
|
||||
|
||||
# Move the CoreId in r0 to be the first argument of the SEC Entry Point
|
||||
mov r0, r5
|
||||
|
||||
# jump to SEC C code
|
||||
# r0 = core_id
|
||||
blx r3
|
||||
|
||||
|
||||
|
||||
Reference in New Issue
Block a user