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IntelFsp2Pkg: FSP_TEMP_RAM_INIT call must follow X64 Calling Convention

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REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3926
This API accept one parameter using RCX and this is consumed
in mutiple sub functions.

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Ashraf Ali S <ashraf.ali.s@intel.com>
Signed-off-by: cbduggap <chinni.b.duggapu@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
This commit is contained in:
Duggapu, Chinni B
2022-05-17 16:44:00 +08:00
committed by mergify[bot]
parent fa2b212d61
commit 11d8abcba2
2 changed files with 48 additions and 19 deletions
Download Patch File Download Diff File Expand all files Collapse all files

39
IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
View File

@@ -114,7 +114,7 @@ endstruc
global ASM_PFX(LoadMicrocodeDefault)
ASM_PFX(LoadMicrocodeDefault):
; Inputs:
; rsp -> LoadMicrocodeParams pointer
; rcx -> LoadMicrocodeParams pointer
; Register Usage:
; rsp Preserved
; All others destroyed
@@ -130,10 +130,9 @@ ASM_PFX(LoadMicrocodeDefault):
cmp rsp, 0
jz ParamError
mov eax, dword [rsp + 8] ; Parameter pointer
cmp eax, 0
cmp rcx, 0
jz ParamError
mov esp, eax
mov rsp, rcx
; skip loading Microcode if the MicrocodeCodeSize is zero
; and report error if size is less than 2k
@@ -144,14 +143,14 @@ ASM_PFX(LoadMicrocodeDefault):
jne ParamError
; UPD structure is compliant with FSP spec 2.4
mov eax, dword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize]
cmp eax, 0
mov rax, qword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize]
cmp rax, 0
jz Exit2
cmp eax, 0800h
cmp rax, 0800h
jl ParamError
mov esi, dword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeAddr]
cmp esi, 0
mov rsi, qword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeAddr]
cmp rsi, 0
jnz CheckMainHeader
ParamError:
@@ -256,7 +255,8 @@ CheckAddress:
; UPD structure is compliant with FSP spec 2.4
; Is automatic size detection ?
mov rax, qword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize]
cmp rax, 0ffffffffffffffffh
mov rcx, 0ffffffffffffffffh
cmp rax, rcx
jz LoadMicrocodeDefault4
; Address >= microcode region address + microcode region size?
@@ -321,8 +321,7 @@ ASM_PFX(EstablishStackFsp):
;
; Save parameter pointer in rdx
;
mov rdx, qword [rsp + 8]
mov rdx, rcx
;
; Enable FSP STACK
;
@@ -420,7 +419,10 @@ ASM_PFX(TempRamInitApi):
;
ENABLE_SSE
ENABLE_AVX
;
; Save Input Parameter in YMM10
;
SAVE_RCX
;
; Save RBP, RBX, RSI, RDI and RSP in YMM7, YMM8 and YMM6
;
@@ -442,9 +444,8 @@ ASM_PFX(TempRamInitApi):
;
; Check Parameter
;
mov rax, qword [rsp + 8]
cmp rax, 0
mov rax, 08000000000000002h
cmp rcx, 0
mov rcx, 08000000000000002h
jz TempRamInitExit
;
@@ -455,18 +456,18 @@ ASM_PFX(TempRamInitApi):
jnz TempRamInitExit
; Load microcode
LOAD_RSP
LOAD_RCX
CALL_YMM ASM_PFX(LoadMicrocodeDefault)
SAVE_UCODE_STATUS rax ; Save microcode return status in SLOT 0 in YMM9 (upper 128bits).
; @note If return value rax is not 0, microcode did not load, but continue and attempt to boot.
; Call Sec CAR Init
LOAD_RSP
LOAD_RCX
CALL_YMM ASM_PFX(SecCarInit)
cmp rax, 0
jnz TempRamInitExit
LOAD_RSP
LOAD_RCX
CALL_YMM ASM_PFX(EstablishStackFsp)
cmp rax, 0
jnz TempRamInitExit