ArmPlatformPkg/FVP: map motherboard VRAM as uncached memory
The VRAM of the PL111 on the FVP Base/Foundation models is described as device memory rather than uncached memory, which is not an accurate description of the nature of the region (i.e., a framebuffer), and may result in problems when using accelerated string routines to access the region, since this may legally involve unaligned accesses or DC ZVA instructions, which are not allowed on device mappings. So split of the 8 MB VRAM region into a separate region, and map it using memory attributes. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Jeremy Linton <jeremy.linton@arm.com> Tested-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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@@ -21,7 +21,7 @@
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#include <ArmPlatform.h>
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// Number of Virtual Memory Map Descriptors
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#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 8
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#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 9
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// DDR attributes
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#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
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@@ -130,6 +130,18 @@ ArmPlatformGetVirtualMemoryMap (
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VirtualMemoryTable[Index].Length = 2 * ARM_VE_SMB_PERIPH_SZ;
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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// VRAM
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VirtualMemoryTable[++Index].PhysicalBase = PL111_CLCD_VRAM_MOTHERBOARD_BASE;
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VirtualMemoryTable[Index].VirtualBase = PL111_CLCD_VRAM_MOTHERBOARD_BASE;
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VirtualMemoryTable[Index].Length = PL111_CLCD_VRAM_MOTHERBOARD_SIZE;
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//
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// Map the VRAM region as Normal Non-Cacheable memory and not device memory,
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// so that we can use the accelerated string routines that may use unaligned
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// accesses or DC ZVA instructions. The enum identifier is slightly awkward
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// here, but it maps to a memory type that allows buffering and reordering.
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//
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
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// Map sparse memory region if present
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if (HasSparseMemory) {
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VirtualMemoryTable[++Index].PhysicalBase = SparseMemoryBase;
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