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MdeModulePkg: Apply uncrustify changes

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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737

Apply uncrustify changes to .c/.h files in the MdeModulePkg package

Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
This commit is contained in:
Michael Kubacki
2021-12-05 14:54:02 -08:00
committed by mergify[bot]
parent 7c7184e201
commit 1436aea4d5
994 changed files with 107608 additions and 101311 deletions
Download Patch File Download Diff File Expand all files Collapse all files

326
MdeModulePkg/Bus/Ata/AhciPei/AhciPei.h
View File

@@ -33,7 +33,7 @@
//
// Structure forward declarations
//
typedef struct _PEI_AHCI_CONTROLLER_PRIVATE_DATA PEI_AHCI_CONTROLLER_PRIVATE_DATA;
typedef struct _PEI_AHCI_CONTROLLER_PRIVATE_DATA PEI_AHCI_CONTROLLER_PRIVATE_DATA;
#include "AhciPeiPassThru.h"
#include "AhciPeiBlockIo.h"
@@ -46,107 +46,107 @@ typedef struct _PEI_AHCI_CONTROLLER_PRIVATE_DATA PEI_AHCI_CONTROLLER_PRIVATE_DA
// Refer SATA1.0a spec section 5.2, the Phy detection time should be less than 10ms.
// The value is in millisecond units. Add a bit of margin for robustness.
//
#define AHCI_BUS_PHY_DETECT_TIMEOUT 15
#define AHCI_BUS_PHY_DETECT_TIMEOUT 15
//
// Refer SATA1.0a spec, the bus reset time should be less than 1s.
// The value is in 100ns units.
//
#define AHCI_PEI_RESET_TIMEOUT 10000000
#define AHCI_PEI_RESET_TIMEOUT 10000000
//
// Time out Value for ATA pass through protocol, in 100ns units.
//
#define ATA_TIMEOUT 30000000
#define ATA_TIMEOUT 30000000
//
// Maximal number of Physical Region Descriptor Table entries supported.
//
#define AHCI_MAX_PRDT_NUMBER 8
#define AHCI_MAX_PRDT_NUMBER 8
#define AHCI_CAPABILITY_OFFSET 0x0000
#define AHCI_CAP_SAM BIT18
#define AHCI_CAP_SSS BIT27
#define AHCI_CAPABILITY_OFFSET 0x0000
#define AHCI_CAP_SAM BIT18
#define AHCI_CAP_SSS BIT27
#define AHCI_GHC_OFFSET 0x0004
#define AHCI_GHC_RESET BIT0
#define AHCI_GHC_ENABLE BIT31
#define AHCI_GHC_OFFSET 0x0004
#define AHCI_GHC_RESET BIT0
#define AHCI_GHC_ENABLE BIT31
#define AHCI_IS_OFFSET 0x0008
#define AHCI_PI_OFFSET 0x000C
#define AHCI_IS_OFFSET 0x0008
#define AHCI_PI_OFFSET 0x000C
#define AHCI_MAX_PORTS 32
#define AHCI_MAX_PORTS 32
typedef struct {
UINT32 Lower32;
UINT32 Upper32;
UINT32 Lower32;
UINT32 Upper32;
} DATA_32;
typedef union {
DATA_32 Uint32;
UINT64 Uint64;
DATA_32 Uint32;
UINT64 Uint64;
} DATA_64;
#define AHCI_ATAPI_SIG_MASK 0xFFFF0000
#define AHCI_ATA_DEVICE_SIG 0x00000000
#define AHCI_ATAPI_SIG_MASK 0xFFFF0000
#define AHCI_ATA_DEVICE_SIG 0x00000000
//
// Each PRDT entry can point to a memory block up to 4M byte
//
#define AHCI_MAX_DATA_PER_PRDT 0x400000
#define AHCI_MAX_DATA_PER_PRDT 0x400000
#define AHCI_FIS_REGISTER_H2D 0x27 //Register FIS - Host to Device
#define AHCI_FIS_REGISTER_H2D_LENGTH 20
#define AHCI_FIS_REGISTER_D2H 0x34 //Register FIS - Device to Host
#define AHCI_FIS_PIO_SETUP 0x5F //PIO Setup FIS - Device to Host
#define AHCI_FIS_REGISTER_H2D 0x27 // Register FIS - Host to Device
#define AHCI_FIS_REGISTER_H2D_LENGTH 20
#define AHCI_FIS_REGISTER_D2H 0x34 // Register FIS - Device to Host
#define AHCI_FIS_PIO_SETUP 0x5F // PIO Setup FIS - Device to Host
#define AHCI_D2H_FIS_OFFSET 0x40
#define AHCI_PIO_FIS_OFFSET 0x20
#define AHCI_FIS_TYPE_MASK 0xFF
#define AHCI_D2H_FIS_OFFSET 0x40
#define AHCI_PIO_FIS_OFFSET 0x20
#define AHCI_FIS_TYPE_MASK 0xFF
//
// Port register
//
#define AHCI_PORT_START 0x0100
#define AHCI_PORT_REG_WIDTH 0x0080
#define AHCI_PORT_CLB 0x0000
#define AHCI_PORT_CLBU 0x0004
#define AHCI_PORT_FB 0x0008
#define AHCI_PORT_FBU 0x000C
#define AHCI_PORT_IS 0x0010
#define AHCI_PORT_IE 0x0014
#define AHCI_PORT_CMD 0x0018
#define AHCI_PORT_CMD_ST BIT0
#define AHCI_PORT_CMD_SUD BIT1
#define AHCI_PORT_CMD_POD BIT2
#define AHCI_PORT_CMD_CLO BIT3
#define AHCI_PORT_CMD_FRE BIT4
#define AHCI_PORT_CMD_FR BIT14
#define AHCI_PORT_CMD_CR BIT15
#define AHCI_PORT_CMD_CPD BIT20
#define AHCI_PORT_CMD_ATAPI BIT24
#define AHCI_PORT_CMD_DLAE BIT25
#define AHCI_PORT_CMD_ALPE BIT26
#define AHCI_PORT_CMD_ACTIVE (1 << 28)
#define AHCI_PORT_CMD_ICC_MASK (BIT28 | BIT29 | BIT30 | BIT31)
#define AHCI_PORT_START 0x0100
#define AHCI_PORT_REG_WIDTH 0x0080
#define AHCI_PORT_CLB 0x0000
#define AHCI_PORT_CLBU 0x0004
#define AHCI_PORT_FB 0x0008
#define AHCI_PORT_FBU 0x000C
#define AHCI_PORT_IS 0x0010
#define AHCI_PORT_IE 0x0014
#define AHCI_PORT_CMD 0x0018
#define AHCI_PORT_CMD_ST BIT0
#define AHCI_PORT_CMD_SUD BIT1
#define AHCI_PORT_CMD_POD BIT2
#define AHCI_PORT_CMD_CLO BIT3
#define AHCI_PORT_CMD_FRE BIT4
#define AHCI_PORT_CMD_FR BIT14
#define AHCI_PORT_CMD_CR BIT15
#define AHCI_PORT_CMD_CPD BIT20
#define AHCI_PORT_CMD_ATAPI BIT24
#define AHCI_PORT_CMD_DLAE BIT25
#define AHCI_PORT_CMD_ALPE BIT26
#define AHCI_PORT_CMD_ACTIVE (1 << 28)
#define AHCI_PORT_CMD_ICC_MASK (BIT28 | BIT29 | BIT30 | BIT31)
#define AHCI_PORT_TFD 0x0020
#define AHCI_PORT_TFD_ERR BIT0
#define AHCI_PORT_TFD_DRQ BIT3
#define AHCI_PORT_TFD_BSY BIT7
#define AHCI_PORT_TFD_MASK (BIT7 | BIT3 | BIT0)
#define AHCI_PORT_TFD 0x0020
#define AHCI_PORT_TFD_ERR BIT0
#define AHCI_PORT_TFD_DRQ BIT3
#define AHCI_PORT_TFD_BSY BIT7
#define AHCI_PORT_TFD_MASK (BIT7 | BIT3 | BIT0)
#define AHCI_PORT_SIG 0x0024
#define AHCI_PORT_SSTS 0x0028
#define AHCI_PORT_SSTS_DET_MASK 0x000F
#define AHCI_PORT_SSTS_DET 0x0001
#define AHCI_PORT_SSTS_DET_PCE 0x0003
#define AHCI_PORT_SIG 0x0024
#define AHCI_PORT_SSTS 0x0028
#define AHCI_PORT_SSTS_DET_MASK 0x000F
#define AHCI_PORT_SSTS_DET 0x0001
#define AHCI_PORT_SSTS_DET_PCE 0x0003
#define AHCI_PORT_SCTL 0x002C
#define AHCI_PORT_SCTL_IPM_INIT 0x0300
#define AHCI_PORT_SCTL 0x002C
#define AHCI_PORT_SCTL_IPM_INIT 0x0300
#define AHCI_PORT_SERR 0x0030
#define AHCI_PORT_CI 0x0038
#define AHCI_PORT_SERR 0x0030
#define AHCI_PORT_CI 0x0038
#define IS_ALIGNED(addr, size) (((UINTN) (addr) & (size - 1)) == 0)
#define TIMER_PERIOD_SECONDS(Seconds) MultU64x32((UINT64)(Seconds), 10000000)
#define IS_ALIGNED(addr, size) (((UINTN) (addr) & (size - 1)) == 0)
#define TIMER_PERIOD_SECONDS(Seconds) MultU64x32((UINT64)(Seconds), 10000000)
#pragma pack(1)
@@ -170,19 +170,19 @@ typedef struct {
// The entry Data structure is listed at the following.
//
typedef struct {
UINT32 AhciCmdCfl:5; //Command FIS Length
UINT32 AhciCmdA:1; //ATAPI
UINT32 AhciCmdW:1; //Write
UINT32 AhciCmdP:1; //Prefetchable
UINT32 AhciCmdR:1; //Reset
UINT32 AhciCmdB:1; //BIST
UINT32 AhciCmdC:1; //Clear Busy upon R_OK
UINT32 AhciCmdRsvd:1;
UINT32 AhciCmdPmp:4; //Port Multiplier Port
UINT32 AhciCmdPrdtl:16; //Physical Region Descriptor Table Length
UINT32 AhciCmdPrdbc; //Physical Region Descriptor Byte Count
UINT32 AhciCmdCtba; //Command Table Descriptor Base Address
UINT32 AhciCmdCtbau; //Command Table Descriptor Base Address Upper 32-BITs
UINT32 AhciCmdCfl : 5; // Command FIS Length
UINT32 AhciCmdA : 1; // ATAPI
UINT32 AhciCmdW : 1; // Write
UINT32 AhciCmdP : 1; // Prefetchable
UINT32 AhciCmdR : 1; // Reset
UINT32 AhciCmdB : 1; // BIST
UINT32 AhciCmdC : 1; // Clear Busy upon R_OK
UINT32 AhciCmdRsvd : 1;
UINT32 AhciCmdPmp : 4; // Port Multiplier Port
UINT32 AhciCmdPrdtl : 16; // Physical Region Descriptor Table Length
UINT32 AhciCmdPrdbc; // Physical Region Descriptor Byte Count
UINT32 AhciCmdCtba; // Command Table Descriptor Base Address
UINT32 AhciCmdCtbau; // Command Table Descriptor Base Address Upper 32-BITs
UINT32 AhciCmdRsvd1[4];
} EFI_AHCI_COMMAND_LIST;
@@ -192,28 +192,28 @@ typedef struct {
// specified in the Serial ATA Revision 2.6 specification.
//
typedef struct {
UINT8 AhciCFisType;
UINT8 AhciCFisPmNum:4;
UINT8 AhciCFisRsvd:1;
UINT8 AhciCFisRsvd1:1;
UINT8 AhciCFisRsvd2:1;
UINT8 AhciCFisCmdInd:1;
UINT8 AhciCFisCmd;
UINT8 AhciCFisFeature;
UINT8 AhciCFisSecNum;
UINT8 AhciCFisClyLow;
UINT8 AhciCFisClyHigh;
UINT8 AhciCFisDevHead;
UINT8 AhciCFisSecNumExp;
UINT8 AhciCFisClyLowExp;
UINT8 AhciCFisClyHighExp;
UINT8 AhciCFisFeatureExp;
UINT8 AhciCFisSecCount;
UINT8 AhciCFisSecCountExp;
UINT8 AhciCFisRsvd3;
UINT8 AhciCFisControl;
UINT8 AhciCFisRsvd4[4];
UINT8 AhciCFisRsvd5[44];
UINT8 AhciCFisType;
UINT8 AhciCFisPmNum : 4;
UINT8 AhciCFisRsvd : 1;
UINT8 AhciCFisRsvd1 : 1;
UINT8 AhciCFisRsvd2 : 1;
UINT8 AhciCFisCmdInd : 1;
UINT8 AhciCFisCmd;
UINT8 AhciCFisFeature;
UINT8 AhciCFisSecNum;
UINT8 AhciCFisClyLow;
UINT8 AhciCFisClyHigh;
UINT8 AhciCFisDevHead;
UINT8 AhciCFisSecNumExp;
UINT8 AhciCFisClyLowExp;
UINT8 AhciCFisClyHighExp;
UINT8 AhciCFisFeatureExp;
UINT8 AhciCFisSecCount;
UINT8 AhciCFisSecCountExp;
UINT8 AhciCFisRsvd3;
UINT8 AhciCFisControl;
UINT8 AhciCFisRsvd4[4];
UINT8 AhciCFisRsvd5[44];
} EFI_AHCI_COMMAND_FIS;
//
@@ -230,12 +230,12 @@ typedef struct {
// list entry for this command slot.
//
typedef struct {
UINT32 AhciPrdtDba; //Data Base Address
UINT32 AhciPrdtDbau; //Data Base Address Upper 32-BITs
UINT32 AhciPrdtDba; // Data Base Address
UINT32 AhciPrdtDbau; // Data Base Address Upper 32-BITs
UINT32 AhciPrdtRsvd;
UINT32 AhciPrdtDbc:22; //Data Byte Count
UINT32 AhciPrdtRsvd1:9;
UINT32 AhciPrdtIoc:1; //Interrupt on Completion
UINT32 AhciPrdtDbc : 22; // Data Byte Count
UINT32 AhciPrdtRsvd1 : 9;
UINT32 AhciPrdtIoc : 1; // Interrupt on Completion
} EFI_AHCI_COMMAND_PRDT;
//
@@ -268,7 +268,7 @@ typedef struct {
//
// Unique signature for AHCI ATA device information structure.
//
#define AHCI_PEI_ATA_DEVICE_DATA_SIGNATURE SIGNATURE_32 ('A', 'P', 'A', 'D')
#define AHCI_PEI_ATA_DEVICE_DATA_SIGNATURE SIGNATURE_32 ('A', 'P', 'A', 'D')
//
// AHCI mode device information structure.
@@ -301,7 +301,7 @@ typedef struct {
//
// Unique signature for private data structure.
//
#define AHCI_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('A','P','C','P')
#define AHCI_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('A','P','C','P')
//
// ATA AHCI controller private data structure.
@@ -348,7 +348,7 @@ struct _PEI_AHCI_CONTROLLER_PRIVATE_DATA {
//
// Global variables
//
extern UINT32 mMaxTransferBlockNumber[2];
extern UINT32 mMaxTransferBlockNumber[2];
//
// Internal functions
@@ -394,9 +394,9 @@ IoMmuAllocateBuffer (
**/
EFI_STATUS
IoMmuFreeBuffer (
IN UINTN Pages,
IN VOID *HostAddress,
IN VOID *Mapping
IN UINTN Pages,
IN VOID *HostAddress,
IN VOID *Mapping
);
/**
@@ -420,11 +420,11 @@ IoMmuFreeBuffer (
**/
EFI_STATUS
IoMmuMap (
IN EDKII_IOMMU_OPERATION Operation,
IN VOID *HostAddress,
IN OUT UINTN *NumberOfBytes,
OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
OUT VOID **Mapping
IN EDKII_IOMMU_OPERATION Operation,
IN VOID *HostAddress,
IN OUT UINTN *NumberOfBytes,
OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
OUT VOID **Mapping
);
/**
@@ -438,7 +438,7 @@ IoMmuMap (
**/
EFI_STATUS
IoMmuUnmap (
IN VOID *Mapping
IN VOID *Mapping
);
/**
@@ -470,7 +470,7 @@ AhciPeimEndOfPei (
**/
UINT8
AhciGetNumberOfPortsFromMap (
IN UINT32 PortBitMap
IN UINT32 PortBitMap
);
/**
@@ -497,16 +497,16 @@ AhciGetNumberOfPortsFromMap (
**/
EFI_STATUS
AhciPioTransfer (
IN PEI_AHCI_CONTROLLER_PRIVATE_DATA *Private,
IN UINT8 Port,
IN UINT8 PortMultiplier,
IN UINT8 FisIndex,
IN BOOLEAN Read,
IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,
IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock,
IN OUT VOID *MemoryAddr,
IN UINT32 DataCount,
IN UINT64 Timeout
IN PEI_AHCI_CONTROLLER_PRIVATE_DATA *Private,
IN UINT8 Port,
IN UINT8 PortMultiplier,
IN UINT8 FisIndex,
IN BOOLEAN Read,
IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,
IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock,
IN OUT VOID *MemoryAddr,
IN UINT32 DataCount,
IN UINT64 Timeout
);
/**
@@ -529,13 +529,13 @@ AhciPioTransfer (
**/
EFI_STATUS
AhciNonDataTransfer (
IN PEI_AHCI_CONTROLLER_PRIVATE_DATA *Private,
IN UINT8 Port,
IN UINT8 PortMultiplier,
IN UINT8 FisIndex,
IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,
IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock,
IN UINT64 Timeout
IN PEI_AHCI_CONTROLLER_PRIVATE_DATA *Private,
IN UINT8 Port,
IN UINT8 PortMultiplier,
IN UINT8 FisIndex,
IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,
IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock,
IN UINT64 Timeout
);
/**
@@ -554,7 +554,7 @@ AhciNonDataTransfer (
**/
EFI_STATUS
AhciModeInitialization (
IN OUT PEI_AHCI_CONTROLLER_PRIVATE_DATA *Private
IN OUT PEI_AHCI_CONTROLLER_PRIVATE_DATA *Private
);
/**
@@ -576,11 +576,11 @@ AhciModeInitialization (
**/
EFI_STATUS
TransferAtaDevice (
IN PEI_AHCI_ATA_DEVICE_DATA *DeviceData,
IN OUT VOID *Buffer,
IN EFI_LBA StartLba,
IN UINT32 TransferLength,
IN BOOLEAN IsWrite
IN PEI_AHCI_ATA_DEVICE_DATA *DeviceData,
IN OUT VOID *Buffer,
IN EFI_LBA StartLba,
IN UINT32 TransferLength,
IN BOOLEAN IsWrite
);
/**
@@ -621,14 +621,14 @@ TransferAtaDevice (
**/
EFI_STATUS
TrustTransferAtaDevice (
IN PEI_AHCI_ATA_DEVICE_DATA *DeviceData,
IN OUT VOID *Buffer,
IN UINT8 SecurityProtocolId,
IN UINT16 SecurityProtocolSpecificData,
IN UINTN TransferLength,
IN BOOLEAN IsTrustSend,
IN UINT64 Timeout,
OUT UINTN *TransferLengthOut
IN PEI_AHCI_ATA_DEVICE_DATA *DeviceData,
IN OUT VOID *Buffer,
IN UINT8 SecurityProtocolId,
IN UINT16 SecurityProtocolSpecificData,
IN UINTN TransferLength,
IN BOOLEAN IsTrustSend,
IN UINT64 Timeout,
OUT UINTN *TransferLengthOut
);
/**
@@ -662,9 +662,9 @@ NextDevicePathNode (
**/
EFI_STATUS
GetDevicePathInstanceSize (
IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
OUT UINTN *InstanceSize,
OUT BOOLEAN *EntireDevicePathEnd
IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
OUT UINTN *InstanceSize,
OUT BOOLEAN *EntireDevicePathEnd
);
/**
@@ -680,8 +680,8 @@ GetDevicePathInstanceSize (
**/
EFI_STATUS
AhciIsHcDevicePathValid (
IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
IN UINTN DevicePathLength
IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
IN UINTN DevicePathLength
);
/**
@@ -702,11 +702,11 @@ AhciIsHcDevicePathValid (
**/
EFI_STATUS
AhciBuildDevicePath (
IN PEI_AHCI_CONTROLLER_PRIVATE_DATA *Private,
IN UINT16 Port,
IN UINT16 PortMultiplierPort,
OUT UINTN *DevicePathLength,
OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath
IN PEI_AHCI_CONTROLLER_PRIVATE_DATA *Private,
IN UINT16 Port,
IN UINT16 PortMultiplierPort,
OUT UINTN *DevicePathLength,
OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath
);
/**
@@ -723,9 +723,9 @@ AhciBuildDevicePath (
**/
UINT8
AhciS3GetEumeratePorts (
IN EFI_DEVICE_PATH_PROTOCOL *HcDevicePath,
IN UINTN HcDevicePathLength,
OUT UINT32 *PortBitMap
IN EFI_DEVICE_PATH_PROTOCOL *HcDevicePath,
IN UINTN HcDevicePathLength,
OUT UINT32 *PortBitMap
);
#endif