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MdeModulePkg: Apply uncrustify changes

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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737

Apply uncrustify changes to .c/.h files in the MdeModulePkg package

Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
This commit is contained in:
Michael Kubacki
2021-12-05 14:54:02 -08:00
committed by mergify[bot]
parent 7c7184e201
commit 1436aea4d5
994 changed files with 107608 additions and 101311 deletions
Download Patch File Download Diff File Expand all files Collapse all files

34
MdeModulePkg/Bus/Pci/EhciDxe/ComponentName.c
View File

@@ -9,7 +9,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include "Ehci.h"
//
// EFI Component Name Protocol
//
@@ -22,19 +21,17 @@ GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME_PROTOCOL gEhciComponentName =
//
// EFI Component Name 2 Protocol
//
GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gEhciComponentName2 = {
(EFI_COMPONENT_NAME2_GET_DRIVER_NAME) EhciComponentNameGetDriverName,
(EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME) EhciComponentNameGetControllerName,
GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gEhciComponentName2 = {
(EFI_COMPONENT_NAME2_GET_DRIVER_NAME)EhciComponentNameGetDriverName,
(EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME)EhciComponentNameGetControllerName,
"en"
};
GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mEhciDriverNameTable[] = {
GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mEhciDriverNameTable[] = {
{ "eng;en", L"Usb Ehci Driver" },
{ NULL , NULL }
{ NULL, NULL }
};
/**
Retrieves a Unicode string that is the user readable name of the driver.
@@ -162,16 +159,16 @@ EhciComponentNameGetDriverName (
EFI_STATUS
EFIAPI
EhciComponentNameGetControllerName (
IN EFI_COMPONENT_NAME_PROTOCOL *This,
IN EFI_HANDLE ControllerHandle,
IN EFI_HANDLE ChildHandle OPTIONAL,
IN CHAR8 *Language,
OUT CHAR16 **ControllerName
IN EFI_COMPONENT_NAME_PROTOCOL *This,
IN EFI_HANDLE ControllerHandle,
IN EFI_HANDLE ChildHandle OPTIONAL,
IN CHAR8 *Language,
OUT CHAR16 **ControllerName
)
{
EFI_STATUS Status;
USB2_HC_DEV *EhciDev;
EFI_USB2_HC_PROTOCOL *Usb2Hc;
EFI_STATUS Status;
USB2_HC_DEV *EhciDev;
EFI_USB2_HC_PROTOCOL *Usb2Hc;
//
// This is a device driver, so ChildHandle must be NULL.
@@ -179,6 +176,7 @@ EhciComponentNameGetControllerName (
if (ChildHandle != NULL) {
return EFI_UNSUPPORTED;
}
//
// Make sure this driver is currently managing ControllerHandle
//
@@ -190,13 +188,14 @@ EhciComponentNameGetControllerName (
if (EFI_ERROR (Status)) {
return Status;
}
//
// Get the device context
//
Status = gBS->OpenProtocol (
ControllerHandle,
&gEfiUsb2HcProtocolGuid,
(VOID **) &Usb2Hc,
(VOID **)&Usb2Hc,
gEhciDriverBinding.DriverBindingHandle,
ControllerHandle,
EFI_OPEN_PROTOCOL_GET_PROTOCOL
@@ -214,5 +213,4 @@ EhciComponentNameGetControllerName (
ControllerName,
(BOOLEAN)(This == &gEhciComponentName)
);
}

13
MdeModulePkg/Bus/Pci/EhciDxe/ComponentName.h
View File

@@ -10,7 +10,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#ifndef _COMPONENT_NAME_H_
#define _COMPONENT_NAME_H_
/**
Retrieves a Unicode string that is the user readable name of the driver.
@@ -58,7 +57,6 @@ EhciComponentNameGetDriverName (
OUT CHAR16 **DriverName
);
/**
Retrieves a Unicode string that is the user readable name of the controller
that is being managed by a driver.
@@ -130,12 +128,11 @@ EhciComponentNameGetDriverName (
EFI_STATUS
EFIAPI
EhciComponentNameGetControllerName (
IN EFI_COMPONENT_NAME_PROTOCOL *This,
IN EFI_HANDLE ControllerHandle,
IN EFI_HANDLE ChildHandle OPTIONAL,
IN CHAR8 *Language,
OUT CHAR16 **ControllerName
IN EFI_COMPONENT_NAME_PROTOCOL *This,
IN EFI_HANDLE ControllerHandle,
IN EFI_HANDLE ChildHandle OPTIONAL,
IN CHAR8 *Language,
OUT CHAR16 **ControllerName
);
#endif

941
MdeModulePkg/Bus/Pci/EhciDxe/Ehci.c
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File diff suppressed because it is too large Load Diff

114
MdeModulePkg/Bus/Pci/EhciDxe/Ehci.h
View File

@@ -11,7 +11,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#ifndef _EFI_EHCI_H_
#define _EFI_EHCI_H_
#include <Uefi.h>
#include <Protocol/Usb2HostController.h>
@@ -31,7 +30,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <IndustryStandard/Pci.h>
typedef struct _USB2_HC_DEV USB2_HC_DEV;
typedef struct _USB2_HC_DEV USB2_HC_DEV;
#include "UsbHcMem.h"
#include "EhciReg.h"
@@ -44,64 +43,63 @@ typedef struct _USB2_HC_DEV USB2_HC_DEV;
// EHC timeout experience values
//
#define EHC_1_MICROSECOND 1
#define EHC_1_MILLISECOND (1000 * EHC_1_MICROSECOND)
#define EHC_1_SECOND (1000 * EHC_1_MILLISECOND)
#define EHC_1_MICROSECOND 1
#define EHC_1_MILLISECOND (1000 * EHC_1_MICROSECOND)
#define EHC_1_SECOND (1000 * EHC_1_MILLISECOND)
//
// EHCI register operation timeout, set by experience
//
#define EHC_RESET_TIMEOUT (1 * EHC_1_SECOND)
#define EHC_GENERIC_TIMEOUT (10 * EHC_1_MILLISECOND)
#define EHC_RESET_TIMEOUT (1 * EHC_1_SECOND)
#define EHC_GENERIC_TIMEOUT (10 * EHC_1_MILLISECOND)
//
// Wait for roothub port power stable, refers to Spec[EHCI1.0-2.3.9]
//
#define EHC_ROOT_PORT_RECOVERY_STALL (20 * EHC_1_MILLISECOND)
#define EHC_ROOT_PORT_RECOVERY_STALL (20 * EHC_1_MILLISECOND)
//
// Sync and Async transfer polling interval, set by experience,
// and the unit of Async is 100us, means 1ms as interval.
//
#define EHC_SYNC_POLL_INTERVAL (1 * EHC_1_MILLISECOND)
#define EHC_ASYNC_POLL_INTERVAL EFI_TIMER_PERIOD_MILLISECONDS(1)
#define EHC_SYNC_POLL_INTERVAL (1 * EHC_1_MILLISECOND)
#define EHC_ASYNC_POLL_INTERVAL EFI_TIMER_PERIOD_MILLISECONDS(1)
//
// EHCI debug port control status register bit definition
//
#define USB_DEBUG_PORT_IN_USE BIT10
#define USB_DEBUG_PORT_ENABLE BIT28
#define USB_DEBUG_PORT_OWNER BIT30
#define USB_DEBUG_PORT_IN_USE_MASK (USB_DEBUG_PORT_IN_USE | \
#define USB_DEBUG_PORT_IN_USE BIT10
#define USB_DEBUG_PORT_ENABLE BIT28
#define USB_DEBUG_PORT_OWNER BIT30
#define USB_DEBUG_PORT_IN_USE_MASK (USB_DEBUG_PORT_IN_USE | \
USB_DEBUG_PORT_OWNER)
//
// EHC raises TPL to TPL_NOTIFY to serialize all its operations
// to protect shared data structures.
//
#define EHC_TPL TPL_NOTIFY
#define EHC_TPL TPL_NOTIFY
#define EFI_LIST_CONTAINER(Entry, Type, Field) BASE_CR(Entry, Type, Field)
#define EFI_LIST_CONTAINER(Entry, Type, Field) BASE_CR(Entry, Type, Field)
#define EHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0XFFFFFFFF))
#define EHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINTN)(Addr64), 32) & 0XFFFFFFFF))
#define EHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))
#define EHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0XFFFFFFFF))
#define EHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINTN)(Addr64), 32) & 0XFFFFFFFF))
#define EHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))
#define EHC_REG_BIT_IS_SET(Ehc, Offset, Bit) \
(EHC_BIT_IS_SET(EhcReadOpReg ((Ehc), (Offset)), (Bit)))
#define USB2_HC_DEV_SIGNATURE SIGNATURE_32 ('e', 'h', 'c', 'i')
#define EHC_FROM_THIS(a) CR(a, USB2_HC_DEV, Usb2Hc, USB2_HC_DEV_SIGNATURE)
#define EHC_FROM_THIS(a) CR(a, USB2_HC_DEV, Usb2Hc, USB2_HC_DEV_SIGNATURE)
struct _USB2_HC_DEV {
UINTN Signature;
EFI_USB2_HC_PROTOCOL Usb2Hc;
UINTN Signature;
EFI_USB2_HC_PROTOCOL Usb2Hc;
EFI_PCI_IO_PROTOCOL *PciIo;
EFI_DEVICE_PATH_PROTOCOL *DevicePath;
UINT64 OriginalPciAttributes;
USBHC_MEM_POOL *MemPool;
EFI_PCI_IO_PROTOCOL *PciIo;
EFI_DEVICE_PATH_PROTOCOL *DevicePath;
UINT64 OriginalPciAttributes;
USBHC_MEM_POOL *MemPool;
//
// Schedule data shared between asynchronous and periodic
@@ -112,58 +110,57 @@ struct _USB2_HC_DEV {
// For control transfer, even the short read happens, try the
// status stage.
//
EHC_QTD *ShortReadStop;
EFI_EVENT PollTimer;
EHC_QTD *ShortReadStop;
EFI_EVENT PollTimer;
//
// ExitBootServicesEvent is used to stop the EHC DMA operation
// after exit boot service.
//
EFI_EVENT ExitBootServiceEvent;
EFI_EVENT ExitBootServiceEvent;
//
// Asynchronous(bulk and control) transfer schedule data:
// ReclaimHead is used as the head of the asynchronous transfer
// list. It acts as the reclamation header.
//
EHC_QH *ReclaimHead;
EHC_QH *ReclaimHead;
//
// Periodic (interrupt) transfer schedule data:
//
VOID *PeriodFrame; // the buffer pointed by this pointer is used to store pci bus address of the QH descriptor.
VOID *PeriodFrameHost; // the buffer pointed by this pointer is used to store host memory address of the QH descriptor.
VOID *PeriodFrameMap;
VOID *PeriodFrame; // the buffer pointed by this pointer is used to store pci bus address of the QH descriptor.
VOID *PeriodFrameHost; // the buffer pointed by this pointer is used to store host memory address of the QH descriptor.
VOID *PeriodFrameMap;
EHC_QH *PeriodOne;
LIST_ENTRY AsyncIntTransfers;
EHC_QH *PeriodOne;
LIST_ENTRY AsyncIntTransfers;
//
// EHCI configuration data
//
UINT32 HcStructParams; // Cache of HC structure parameter, EHC_HCSPARAMS_OFFSET
UINT32 HcCapParams; // Cache of HC capability parameter, HCCPARAMS
UINT32 CapLen; // Capability length
UINT32 HcStructParams; // Cache of HC structure parameter, EHC_HCSPARAMS_OFFSET
UINT32 HcCapParams; // Cache of HC capability parameter, HCCPARAMS
UINT32 CapLen; // Capability length
//
// Misc
//
EFI_UNICODE_STRING_TABLE *ControllerNameTable;
EFI_UNICODE_STRING_TABLE *ControllerNameTable;
//
// EHCI debug port info
//
UINT16 DebugPortOffset; // The offset of debug port mmio register
UINT8 DebugPortBarNum; // The bar number of debug port mmio register
UINT8 DebugPortNum; // The port number of usb debug port
UINT16 DebugPortOffset; // The offset of debug port mmio register
UINT8 DebugPortBarNum; // The bar number of debug port mmio register
UINT8 DebugPortNum; // The port number of usb debug port
BOOLEAN Support64BitDma; // Whether 64 bit DMA may be used with this device
BOOLEAN Support64BitDma; // Whether 64 bit DMA may be used with this device
};
extern EFI_DRIVER_BINDING_PROTOCOL gEhciDriverBinding;
extern EFI_COMPONENT_NAME_PROTOCOL gEhciComponentName;
extern EFI_COMPONENT_NAME2_PROTOCOL gEhciComponentName2;
extern EFI_DRIVER_BINDING_PROTOCOL gEhciDriverBinding;
extern EFI_COMPONENT_NAME_PROTOCOL gEhciComponentName;
extern EFI_COMPONENT_NAME2_PROTOCOL gEhciComponentName2;
/**
Test to see if this driver supports ControllerHandle. Any
@@ -181,9 +178,9 @@ extern EFI_COMPONENT_NAME2_PROTOCOL gEhciComponentName2;
EFI_STATUS
EFIAPI
EhcDriverBindingSupported (
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
);
/**
@@ -202,9 +199,9 @@ EhcDriverBindingSupported (
EFI_STATUS
EFIAPI
EhcDriverBindingStart (
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
);
/**
@@ -223,11 +220,10 @@ EhcDriverBindingStart (
EFI_STATUS
EFIAPI
EhcDriverBindingStop (
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN UINTN NumberOfChildren,
IN EFI_HANDLE *ChildHandleBuffer
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN UINTN NumberOfChildren,
IN EFI_HANDLE *ChildHandleBuffer
);
#endif

50
MdeModulePkg/Bus/Pci/EhciDxe/EhciDebug.c
View File

@@ -8,7 +8,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include "Ehci.h"
/**
@@ -19,7 +18,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
VOID
EhcDumpStatus (
IN UINT32 State
IN UINT32 State
)
{
if (EHC_BIT_IS_SET (State, QTD_STAT_DO_PING)) {
@@ -57,7 +56,6 @@ EhcDumpStatus (
DEBUG ((DEBUG_VERBOSE, "\n"));
}
/**
Dump the fields of a QTD.
@@ -67,12 +65,12 @@ EhcDumpStatus (
**/
VOID
EhcDumpQtd (
IN EHC_QTD *Qtd,
IN CHAR8 *Msg
IN EHC_QTD *Qtd,
IN CHAR8 *Msg
)
{
QTD_HW *QtdHw;
UINTN Index;
QTD_HW *QtdHw;
UINTN Index;
if (Msg != NULL) {
DEBUG ((DEBUG_VERBOSE, Msg));
@@ -89,13 +87,10 @@ EhcDumpQtd (
if (QtdHw->Pid == QTD_PID_SETUP) {
DEBUG ((DEBUG_VERBOSE, "PID : Setup\n"));
} else if (QtdHw->Pid == QTD_PID_INPUT) {
DEBUG ((DEBUG_VERBOSE, "PID : IN\n"));
} else if (QtdHw->Pid == QTD_PID_OUTPUT) {
DEBUG ((DEBUG_VERBOSE, "PID : OUT\n"));
}
DEBUG ((DEBUG_VERBOSE, "Error Count : %d\n", QtdHw->ErrCnt));
@@ -109,7 +104,6 @@ EhcDumpQtd (
}
}
/**
Dump the queue head.
@@ -120,22 +114,27 @@ EhcDumpQtd (
**/
VOID
EhcDumpQh (
IN EHC_QH *Qh,
IN CHAR8 *Msg,
IN BOOLEAN DumpBuf
IN EHC_QH *Qh,
IN CHAR8 *Msg,
IN BOOLEAN DumpBuf
)
{
EHC_QTD *Qtd;
QH_HW *QhHw;
LIST_ENTRY *Entry;
UINTN Index;
EHC_QTD *Qtd;
QH_HW *QhHw;
LIST_ENTRY *Entry;
UINTN Index;
if (Msg != NULL) {
DEBUG ((DEBUG_VERBOSE, Msg));
}
DEBUG ((DEBUG_VERBOSE, "Queue head @ 0x%p, interval %ld, next qh %p\n",
Qh, (UINT64)Qh->Interval, Qh->NextQh));
DEBUG ((
DEBUG_VERBOSE,
"Queue head @ 0x%p, interval %ld, next qh %p\n",
Qh,
(UINT64)Qh->Interval,
Qh->NextQh
));
QhHw = &Qh->QhHw;
@@ -166,10 +165,8 @@ EhcDumpQh (
if (QhHw->Pid == QTD_PID_SETUP) {
DEBUG ((DEBUG_VERBOSE, "PID : Setup\n"));
} else if (QhHw->Pid == QTD_PID_INPUT) {
DEBUG ((DEBUG_VERBOSE, "PID : IN\n"));
} else if (QhHw->Pid == QTD_PID_OUTPUT) {
DEBUG ((DEBUG_VERBOSE, "PID : OUT\n"));
}
@@ -196,7 +193,6 @@ EhcDumpQh (
}
}
/**
Dump the buffer in the form of hex.
@@ -206,15 +202,15 @@ EhcDumpQh (
**/
VOID
EhcDumpBuf (
IN UINT8 *Buf,
IN UINTN Len
IN UINT8 *Buf,
IN UINTN Len
)
{
UINTN Index;
UINTN Index;
for (Index = 0; Index < Len; Index++) {
if (Index % 16 == 0) {
DEBUG ((DEBUG_VERBOSE,"\n"));
DEBUG ((DEBUG_VERBOSE, "\n"));
}
DEBUG ((DEBUG_VERBOSE, "%02x ", Buf[Index]));

18
MdeModulePkg/Bus/Pci/EhciDxe/EhciDebug.h
View File

@@ -10,7 +10,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#ifndef _EFI_EHCI_DEBUG_H_
#define _EFI_EHCI_DEBUG_H_
/**
Dump the fields of a QTD.
@@ -20,11 +19,10 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
VOID
EhcDumpQtd (
IN EHC_QTD *Qtd,
IN CHAR8 *Msg
IN EHC_QTD *Qtd,
IN CHAR8 *Msg
);
/**
Dump the queue head.
@@ -35,12 +33,11 @@ EhcDumpQtd (
**/
VOID
EhcDumpQh (
IN EHC_QH *Qh,
IN CHAR8 *Msg,
IN BOOLEAN DumpBuf
IN EHC_QH *Qh,
IN CHAR8 *Msg,
IN BOOLEAN DumpBuf
);
/**
Dump the buffer in the form of hex.
@@ -50,9 +47,8 @@ EhcDumpQh (
**/
VOID
EhcDumpBuf (
IN UINT8 *Buf,
IN UINTN Len
IN UINT8 *Buf,
IN UINTN Len
);
#endif

169
MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.c
View File

@@ -7,10 +7,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include "Ehci.h"
/**
Read EHCI capability register.
@@ -23,18 +21,18 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
UINT32
EhcReadCapRegister (
IN USB2_HC_DEV *Ehc,
IN UINT32 Offset
IN USB2_HC_DEV *Ehc,
IN UINT32 Offset
)
{
UINT32 Data;
EFI_STATUS Status;
UINT32 Data;
EFI_STATUS Status;
Status = Ehc->PciIo->Mem.Read (
Ehc->PciIo,
EfiPciIoWidthUint32,
EHC_BAR_INDEX,
(UINT64) Offset,
(UINT64)Offset,
1,
&Data
);
@@ -59,12 +57,12 @@ EhcReadCapRegister (
**/
UINT32
EhcReadDbgRegister (
IN CONST USB2_HC_DEV *Ehc,
IN UINT32 Offset
IN CONST USB2_HC_DEV *Ehc,
IN UINT32 Offset
)
{
UINT32 Data;
EFI_STATUS Status;
UINT32 Data;
EFI_STATUS Status;
Status = Ehc->PciIo->Mem.Read (
Ehc->PciIo,
@@ -83,7 +81,6 @@ EhcReadDbgRegister (
return Data;
}
/**
Check whether the host controller has an in-use debug port.
@@ -105,11 +102,11 @@ EhcReadDbgRegister (
**/
BOOLEAN
EhcIsDebugPortInUse (
IN CONST USB2_HC_DEV *Ehc,
IN CONST UINT8 *PortNumber OPTIONAL
IN CONST USB2_HC_DEV *Ehc,
IN CONST UINT8 *PortNumber OPTIONAL
)
{
UINT32 State;
UINT32 State;
if (Ehc->DebugPortNum == 0) {
//
@@ -121,7 +118,7 @@ EhcIsDebugPortInUse (
//
// The Debug Port Number field in HCSPARAMS is one-based.
//
if (PortNumber != NULL && *PortNumber != Ehc->DebugPortNum - 1) {
if ((PortNumber != NULL) && (*PortNumber != Ehc->DebugPortNum - 1)) {
//
// The caller specified a port, but it's not the debug port of the host
// controller.
@@ -132,11 +129,10 @@ EhcIsDebugPortInUse (
//
// Deduce usage from the Control Register.
//
State = EhcReadDbgRegister(Ehc, 0);
State = EhcReadDbgRegister (Ehc, 0);
return (State & USB_DEBUG_PORT_IN_USE_MASK) == USB_DEBUG_PORT_IN_USE_MASK;
}
/**
Read EHCI Operation register.
@@ -149,12 +145,12 @@ EhcIsDebugPortInUse (
**/
UINT32
EhcReadOpReg (
IN USB2_HC_DEV *Ehc,
IN UINT32 Offset
IN USB2_HC_DEV *Ehc,
IN UINT32 Offset
)
{
UINT32 Data;
EFI_STATUS Status;
UINT32 Data;
EFI_STATUS Status;
ASSERT (Ehc->CapLen != 0);
@@ -175,7 +171,6 @@ EhcReadOpReg (
return Data;
}
/**
Write the data to the EHCI operation register.
@@ -186,12 +181,12 @@ EhcReadOpReg (
**/
VOID
EhcWriteOpReg (
IN USB2_HC_DEV *Ehc,
IN UINT32 Offset,
IN UINT32 Data
IN USB2_HC_DEV *Ehc,
IN UINT32 Offset,
IN UINT32 Data
)
{
EFI_STATUS Status;
EFI_STATUS Status;
ASSERT (Ehc->CapLen != 0);
@@ -209,7 +204,6 @@ EhcWriteOpReg (
}
}
/**
Set one bit of the operational register while keeping other bits.
@@ -220,19 +214,18 @@ EhcWriteOpReg (
**/
VOID
EhcSetOpRegBit (
IN USB2_HC_DEV *Ehc,
IN UINT32 Offset,
IN UINT32 Bit
IN USB2_HC_DEV *Ehc,
IN UINT32 Offset,
IN UINT32 Bit
)
{
UINT32 Data;
UINT32 Data;
Data = EhcReadOpReg (Ehc, Offset);
Data |= Bit;
EhcWriteOpReg (Ehc, Offset, Data);
}
/**
Clear one bit of the operational register while keeping other bits.
@@ -243,19 +236,18 @@ EhcSetOpRegBit (
**/
VOID
EhcClearOpRegBit (
IN USB2_HC_DEV *Ehc,
IN UINT32 Offset,
IN UINT32 Bit
IN USB2_HC_DEV *Ehc,
IN UINT32 Offset,
IN UINT32 Bit
)
{
UINT32 Data;
UINT32 Data;
Data = EhcReadOpReg (Ehc, Offset);
Data &= ~Bit;
EhcWriteOpReg (Ehc, Offset, Data);
}
/**
Wait the operation register's bit as specified by Bit
to become set (or clear).
@@ -272,14 +264,14 @@ EhcClearOpRegBit (
**/
EFI_STATUS
EhcWaitOpRegBit (
IN USB2_HC_DEV *Ehc,
IN UINT32 Offset,
IN UINT32 Bit,
IN BOOLEAN WaitToSet,
IN UINT32 Timeout
IN USB2_HC_DEV *Ehc,
IN UINT32 Offset,
IN UINT32 Bit,
IN BOOLEAN WaitToSet,
IN UINT32 Timeout
)
{
UINT32 Index;
UINT32 Index;
for (Index = 0; Index < Timeout / EHC_SYNC_POLL_INTERVAL + 1; Index++) {
if (EHC_REG_BIT_IS_SET (Ehc, Offset, Bit) == WaitToSet) {
@@ -292,7 +284,6 @@ EhcWaitOpRegBit (
return EFI_TIMEOUT;
}
/**
Add support for UEFI Over Legacy (UoL) feature, stop
the legacy USB SMI support.
@@ -302,13 +293,13 @@ EhcWaitOpRegBit (
**/
VOID
EhcClearLegacySupport (
IN USB2_HC_DEV *Ehc
IN USB2_HC_DEV *Ehc
)
{
UINT32 ExtendCap;
EFI_PCI_IO_PROTOCOL *PciIo;
UINT32 Value;
UINT32 TimeOut;
UINT32 ExtendCap;
EFI_PCI_IO_PROTOCOL *PciIo;
UINT32 Value;
UINT32 TimeOut;
DEBUG ((DEBUG_INFO, "EhcClearLegacySupport: called to clear legacy support\n"));
@@ -337,8 +328,6 @@ EhcClearLegacySupport (
PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, ExtendCap + 0x4, 1, &Value);
}
/**
Set door bell and wait it to be ACKed by host controller.
This function is used to synchronize with the hardware.
@@ -352,12 +341,12 @@ EhcClearLegacySupport (
**/
EFI_STATUS
EhcSetAndWaitDoorBell (
IN USB2_HC_DEV *Ehc,
IN UINT32 Timeout
IN USB2_HC_DEV *Ehc,
IN UINT32 Timeout
)
{
EFI_STATUS Status;
UINT32 Data;
EFI_STATUS Status;
UINT32 Data;
EhcSetOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_IAAD);
@@ -376,7 +365,6 @@ EhcSetAndWaitDoorBell (
return Status;
}
/**
Clear all the interrutp status bits, these bits
are Write-Clean.
@@ -386,13 +374,12 @@ EhcSetAndWaitDoorBell (
**/
VOID
EhcAckAllInterrupt (
IN USB2_HC_DEV *Ehc
IN USB2_HC_DEV *Ehc
)
{
EhcWriteOpReg (Ehc, EHC_USBSTS_OFFSET, USBSTS_INTACK_MASK);
}
/**
Enable the periodic schedule then wait EHC to
actually enable it.
@@ -406,11 +393,11 @@ EhcAckAllInterrupt (
**/
EFI_STATUS
EhcEnablePeriodSchd (
IN USB2_HC_DEV *Ehc,
IN UINT32 Timeout
IN USB2_HC_DEV *Ehc,
IN UINT32 Timeout
)
{
EFI_STATUS Status;
EFI_STATUS Status;
EhcSetOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_ENABLE_PERIOD);
@@ -418,11 +405,6 @@ EhcEnablePeriodSchd (
return Status;
}
/**
Enable asynchrounous schedule.
@@ -435,11 +417,11 @@ EhcEnablePeriodSchd (
**/
EFI_STATUS
EhcEnableAsyncSchd (
IN USB2_HC_DEV *Ehc,
IN UINT32 Timeout
IN USB2_HC_DEV *Ehc,
IN UINT32 Timeout
)
{
EFI_STATUS Status;
EFI_STATUS Status;
EhcSetOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_ENABLE_ASYNC);
@@ -447,12 +429,6 @@ EhcEnableAsyncSchd (
return Status;
}
/**
Whether Ehc is halted.
@@ -464,13 +440,12 @@ EhcEnableAsyncSchd (
**/
BOOLEAN
EhcIsHalt (
IN USB2_HC_DEV *Ehc
IN USB2_HC_DEV *Ehc
)
{
return EHC_REG_BIT_IS_SET (Ehc, EHC_USBSTS_OFFSET, USBSTS_HALT);
}
/**
Whether system error occurred.
@@ -482,13 +457,12 @@ EhcIsHalt (
**/
BOOLEAN
EhcIsSysError (
IN USB2_HC_DEV *Ehc
IN USB2_HC_DEV *Ehc
)
{
return EHC_REG_BIT_IS_SET (Ehc, EHC_USBSTS_OFFSET, USBSTS_SYS_ERROR);
}
/**
Reset the host controller.
@@ -501,11 +475,11 @@ EhcIsSysError (
**/
EFI_STATUS
EhcResetHC (
IN USB2_HC_DEV *Ehc,
IN UINT32 Timeout
IN USB2_HC_DEV *Ehc,
IN UINT32 Timeout
)
{
EFI_STATUS Status;
EFI_STATUS Status;
//
// Host can only be reset when it is halt. If not so, halt it
@@ -523,7 +497,6 @@ EhcResetHC (
return Status;
}
/**
Halt the host controller.
@@ -536,18 +509,17 @@ EhcResetHC (
**/
EFI_STATUS
EhcHaltHC (
IN USB2_HC_DEV *Ehc,
IN UINT32 Timeout
IN USB2_HC_DEV *Ehc,
IN UINT32 Timeout
)
{
EFI_STATUS Status;
EFI_STATUS Status;
EhcClearOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_RUN);
Status = EhcWaitOpRegBit (Ehc, EHC_USBSTS_OFFSET, USBSTS_HALT, TRUE, Timeout);
return Status;
}
/**
Set the EHCI to run.
@@ -560,18 +532,17 @@ EhcHaltHC (
**/
EFI_STATUS
EhcRunHC (
IN USB2_HC_DEV *Ehc,
IN UINT32 Timeout
IN USB2_HC_DEV *Ehc,
IN UINT32 Timeout
)
{
EFI_STATUS Status;
EFI_STATUS Status;
EhcSetOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_RUN);
Status = EhcWaitOpRegBit (Ehc, EHC_USBSTS_OFFSET, USBSTS_HALT, FALSE, Timeout);
return Status;
}
/**
Initialize the HC hardware.
EHCI spec lists the five things to do to initialize the hardware:
@@ -589,12 +560,12 @@ EhcRunHC (
**/
EFI_STATUS
EhcInitHC (
IN USB2_HC_DEV *Ehc
IN USB2_HC_DEV *Ehc
)
{
EFI_STATUS Status;
UINT32 Index;
UINT32 RegVal;
EFI_STATUS Status;
UINT32 Index;
UINT32 RegVal;
// This ASSERT crashes the BeagleBoard. There is some issue in the USB stack.
// This ASSERT needs to be removed so the BeagleBoard will boot. When we fix
@@ -629,15 +600,15 @@ EhcInitHC (
// 3. Power up all ports if EHCI has Port Power Control (PPC) support
//
if (Ehc->HcStructParams & HCSP_PPC) {
for (Index = 0; Index < (UINT8) (Ehc->HcStructParams & HCSP_NPORTS); Index++) {
for (Index = 0; Index < (UINT8)(Ehc->HcStructParams & HCSP_NPORTS); Index++) {
//
// Do not clear port status bits on initialization. Otherwise devices will
// not enumerate properly at startup.
//
RegVal = EhcReadOpReg(Ehc, (UINT32)(EHC_PORT_STAT_OFFSET + (4 * Index)));
RegVal = EhcReadOpReg (Ehc, (UINT32)(EHC_PORT_STAT_OFFSET + (4 * Index)));
RegVal &= ~PORTSC_CHANGE_MASK;
RegVal |= PORTSC_POWER;
EhcWriteOpReg (Ehc, (UINT32) (EHC_PORT_STAT_OFFSET + (4 * Index)), RegVal);
EhcWriteOpReg (Ehc, (UINT32)(EHC_PORT_STAT_OFFSET + (4 * Index)), RegVal);
}
}

153
MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.h
View File

@@ -14,20 +14,19 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
// EHCI register offset
//
//
// Capability register offset
//
#define EHC_CAPLENGTH_OFFSET 0 // Capability register length offset
#define EHC_HCSPARAMS_OFFSET 0x04 // Structural Parameters 04-07h
#define EHC_HCCPARAMS_OFFSET 0x08 // Capability parameters offset
#define EHC_CAPLENGTH_OFFSET 0 // Capability register length offset
#define EHC_HCSPARAMS_OFFSET 0x04 // Structural Parameters 04-07h
#define EHC_HCCPARAMS_OFFSET 0x08 // Capability parameters offset
//
// Capability register bit definition
//
#define HCSP_NPORTS 0x0F // Number of root hub port
#define HCSP_PPC 0x10 // Port Power Control
#define HCCP_64BIT 0x01 // 64-bit addressing capability
#define HCSP_NPORTS 0x0F // Number of root hub port
#define HCSP_PPC 0x10 // Port Power Control
#define HCCP_64BIT 0x01 // 64-bit addressing capability
//
// Operational register offset
@@ -42,66 +41,66 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#define EHC_CONFIG_FLAG_OFFSET 0x40 // Configure flag register offset
#define EHC_PORT_STAT_OFFSET 0x44 // Port status/control offset
#define EHC_FRAME_LEN 1024
#define EHC_FRAME_LEN 1024
//
// Register bit definition
//
#define CONFIGFLAG_ROUTE_EHC 0x01 // Route port to EHC
#define CONFIGFLAG_ROUTE_EHC 0x01 // Route port to EHC
#define USBCMD_RUN 0x01 // Run/stop
#define USBCMD_RESET 0x02 // Start the host controller reset
#define USBCMD_ENABLE_PERIOD 0x10 // Enable periodic schedule
#define USBCMD_ENABLE_ASYNC 0x20 // Enable asynchronous schedule
#define USBCMD_IAAD 0x40 // Interrupt on async advance doorbell
#define USBCMD_RUN 0x01 // Run/stop
#define USBCMD_RESET 0x02 // Start the host controller reset
#define USBCMD_ENABLE_PERIOD 0x10 // Enable periodic schedule
#define USBCMD_ENABLE_ASYNC 0x20 // Enable asynchronous schedule
#define USBCMD_IAAD 0x40 // Interrupt on async advance doorbell
#define USBSTS_IAA 0x20 // Interrupt on async advance
#define USBSTS_PERIOD_ENABLED 0x4000 // Periodic schedule status
#define USBSTS_ASYNC_ENABLED 0x8000 // Asynchronous schedule status
#define USBSTS_HALT 0x1000 // Host controller halted
#define USBSTS_SYS_ERROR 0x10 // Host system error
#define USBSTS_INTACK_MASK 0x003F // Mask for the interrupt ACK, the WC
#define USBSTS_IAA 0x20 // Interrupt on async advance
#define USBSTS_PERIOD_ENABLED 0x4000 // Periodic schedule status
#define USBSTS_ASYNC_ENABLED 0x8000 // Asynchronous schedule status
#define USBSTS_HALT 0x1000 // Host controller halted
#define USBSTS_SYS_ERROR 0x10 // Host system error
#define USBSTS_INTACK_MASK 0x003F // Mask for the interrupt ACK, the WC
// (write clean) bits in USBSTS register
#define PORTSC_CONN 0x01 // Current Connect Status
#define PORTSC_CONN_CHANGE 0x02 // Connect Status Change
#define PORTSC_ENABLED 0x04 // Port Enable / Disable
#define PORTSC_ENABLE_CHANGE 0x08 // Port Enable / Disable Change
#define PORTSC_OVERCUR 0x10 // Over current Active
#define PORTSC_OVERCUR_CHANGE 0x20 // Over current Change
#define PORSTSC_RESUME 0x40 // Force Port Resume
#define PORTSC_SUSPEND 0x80 // Port Suspend State
#define PORTSC_RESET 0x100 // Port Reset
#define PORTSC_LINESTATE_K 0x400 // Line Status K-state
#define PORTSC_LINESTATE_J 0x800 // Line Status J-state
#define PORTSC_POWER 0x1000 // Port Power
#define PORTSC_OWNER 0x2000 // Port Owner
#define PORTSC_CHANGE_MASK 0x2A // Mask of the port change bits,
#define PORTSC_CONN 0x01 // Current Connect Status
#define PORTSC_CONN_CHANGE 0x02 // Connect Status Change
#define PORTSC_ENABLED 0x04 // Port Enable / Disable
#define PORTSC_ENABLE_CHANGE 0x08 // Port Enable / Disable Change
#define PORTSC_OVERCUR 0x10 // Over current Active
#define PORTSC_OVERCUR_CHANGE 0x20 // Over current Change
#define PORSTSC_RESUME 0x40 // Force Port Resume
#define PORTSC_SUSPEND 0x80 // Port Suspend State
#define PORTSC_RESET 0x100 // Port Reset
#define PORTSC_LINESTATE_K 0x400 // Line Status K-state
#define PORTSC_LINESTATE_J 0x800 // Line Status J-state
#define PORTSC_POWER 0x1000 // Port Power
#define PORTSC_OWNER 0x2000 // Port Owner
#define PORTSC_CHANGE_MASK 0x2A // Mask of the port change bits,
// they are WC (write clean)
//
// PCI Configuration Registers
//
#define EHC_BAR_INDEX 0 // how many bytes away from USB_BASE to 0x10
#define EHC_BAR_INDEX 0 // how many bytes away from USB_BASE to 0x10
//
// Debug port capability id
//
#define EHC_DEBUG_PORT_CAP_ID 0x0A
#define EHC_DEBUG_PORT_CAP_ID 0x0A
#define EHC_LINK_TERMINATED(Link) (((Link) & 0x01) != 0)
#define EHC_LINK_TERMINATED(Link) (((Link) & 0x01) != 0)
#define EHC_ADDR(High, QhHw32) \
((VOID *) (UINTN) (LShiftU64 ((High), 32) | ((QhHw32) & 0xFFFFFFF0)))
#define EHCI_IS_DATAIN(EndpointAddr) EHC_BIT_IS_SET((EndpointAddr), 0x80)
#define EHCI_IS_DATAIN(EndpointAddr) EHC_BIT_IS_SET((EndpointAddr), 0x80)
//
// Structure to map the hardware port states to the
// UEFI's port states.
//
typedef struct {
UINT16 HwState;
UINT16 UefiState;
UINT16 HwState;
UINT16 UefiState;
} USB_PORT_STATE_MAP;
//
@@ -109,9 +108,9 @@ typedef struct {
//
#pragma pack(1)
typedef struct {
UINT8 ProgInterface;
UINT8 SubClassCode;
UINT8 BaseCode;
UINT8 ProgInterface;
UINT8 SubClassCode;
UINT8 BaseCode;
} USB_CLASSC;
#pragma pack()
@@ -126,8 +125,8 @@ typedef struct {
**/
UINT32
EhcReadCapRegister (
IN USB2_HC_DEV *Ehc,
IN UINT32 Offset
IN USB2_HC_DEV *Ehc,
IN UINT32 Offset
);
/**
@@ -151,8 +150,8 @@ EhcReadCapRegister (
**/
BOOLEAN
EhcIsDebugPortInUse (
IN CONST USB2_HC_DEV *Ehc,
IN CONST UINT8 *PortNumber OPTIONAL
IN CONST USB2_HC_DEV *Ehc,
IN CONST UINT8 *PortNumber OPTIONAL
);
/**
@@ -166,11 +165,10 @@ EhcIsDebugPortInUse (
**/
UINT32
EhcReadOpReg (
IN USB2_HC_DEV *Ehc,
IN UINT32 Offset
IN USB2_HC_DEV *Ehc,
IN UINT32 Offset
);
/**
Write the data to the EHCI operation register.
@@ -181,9 +179,9 @@ EhcReadOpReg (
**/
VOID
EhcWriteOpReg (
IN USB2_HC_DEV *Ehc,
IN UINT32 Offset,
IN UINT32 Data
IN USB2_HC_DEV *Ehc,
IN UINT32 Offset,
IN UINT32 Data
);
/**
@@ -196,9 +194,9 @@ EhcWriteOpReg (
**/
VOID
EhcSetOpRegBit (
IN USB2_HC_DEV *Ehc,
IN UINT32 Offset,
IN UINT32 Bit
IN USB2_HC_DEV *Ehc,
IN UINT32 Offset,
IN UINT32 Bit
);
/**
@@ -211,9 +209,9 @@ EhcSetOpRegBit (
**/
VOID
EhcClearOpRegBit (
IN USB2_HC_DEV *Ehc,
IN UINT32 Offset,
IN UINT32 Bit
IN USB2_HC_DEV *Ehc,
IN UINT32 Offset,
IN UINT32 Bit
);
/**
@@ -225,11 +223,9 @@ EhcClearOpRegBit (
**/
VOID
EhcClearLegacySupport (
IN USB2_HC_DEV *Ehc
IN USB2_HC_DEV *Ehc
);
/**
Set door bell and wait it to be ACKed by host controller.
This function is used to synchronize with the hardware.
@@ -243,11 +239,10 @@ EhcClearLegacySupport (
**/
EFI_STATUS
EhcSetAndWaitDoorBell (
IN USB2_HC_DEV *Ehc,
IN UINT32 Timeout
IN USB2_HC_DEV *Ehc,
IN UINT32 Timeout
);
/**
Clear all the interrutp status bits, these bits are Write-Clean.
@@ -256,11 +251,9 @@ EhcSetAndWaitDoorBell (
**/
VOID
EhcAckAllInterrupt (
IN USB2_HC_DEV *Ehc
IN USB2_HC_DEV *Ehc
);
/**
Whether Ehc is halted.
@@ -272,10 +265,9 @@ EhcAckAllInterrupt (
**/
BOOLEAN
EhcIsHalt (
IN USB2_HC_DEV *Ehc
IN USB2_HC_DEV *Ehc
);
/**
Whether system error occurred.
@@ -287,10 +279,9 @@ EhcIsHalt (
**/
BOOLEAN
EhcIsSysError (
IN USB2_HC_DEV *Ehc
IN USB2_HC_DEV *Ehc
);
/**
Reset the host controller.
@@ -303,11 +294,10 @@ EhcIsSysError (
**/
EFI_STATUS
EhcResetHC (
IN USB2_HC_DEV *Ehc,
IN UINT32 Timeout
IN USB2_HC_DEV *Ehc,
IN UINT32 Timeout
);
/**
Halt the host controller.
@@ -320,11 +310,10 @@ EhcResetHC (
**/
EFI_STATUS
EhcHaltHC (
IN USB2_HC_DEV *Ehc,
IN UINT32 Timeout
IN USB2_HC_DEV *Ehc,
IN UINT32 Timeout
);
/**
Set the EHCI to run.
@@ -337,12 +326,10 @@ EhcHaltHC (
**/
EFI_STATUS
EhcRunHC (
IN USB2_HC_DEV *Ehc,
IN UINT32 Timeout
IN USB2_HC_DEV *Ehc,
IN UINT32 Timeout
);
/**
Initialize the HC hardware.
EHCI spec lists the five things to do to initialize the hardware:
@@ -360,7 +347,7 @@ EhcRunHC (
**/
EFI_STATUS
EhcInitHC (
IN USB2_HC_DEV *Ehc
IN USB2_HC_DEV *Ehc
);
#endif

377
MdeModulePkg/Bus/Pci/EhciDxe/EhciSched.c
View File

@@ -10,7 +10,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include "Ehci.h"
/**
Create helper QTD/QH for the EHCI device.
@@ -22,14 +21,14 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
EFI_STATUS
EhcCreateHelpQ (
IN USB2_HC_DEV *Ehc
IN USB2_HC_DEV *Ehc
)
{
USB_ENDPOINT Ep;
EHC_QH *Qh;
QH_HW *QhHw;
EHC_QTD *Qtd;
EFI_PHYSICAL_ADDRESS PciAddr;
USB_ENDPOINT Ep;
EHC_QH *Qh;
QH_HW *QhHw;
EHC_QTD *Qtd;
EFI_PHYSICAL_ADDRESS PciAddr;
//
// Create an inactive Qtd to terminate the short packet read.
@@ -40,25 +39,25 @@ EhcCreateHelpQ (
return EFI_OUT_OF_RESOURCES;
}
Qtd->QtdHw.Status = QTD_STAT_HALTED;
Ehc->ShortReadStop = Qtd;
Qtd->QtdHw.Status = QTD_STAT_HALTED;
Ehc->ShortReadStop = Qtd;
//
// Create a QH to act as the EHC reclamation header.
// Set the header to loopback to itself.
//
Ep.DevAddr = 0;
Ep.EpAddr = 1;
Ep.Direction = EfiUsbDataIn;
Ep.DevSpeed = EFI_USB_SPEED_HIGH;
Ep.MaxPacket = 64;
Ep.HubAddr = 0;
Ep.HubPort = 0;
Ep.Toggle = 0;
Ep.Type = EHC_BULK_TRANSFER;
Ep.PollRate = 1;
Ep.DevAddr = 0;
Ep.EpAddr = 1;
Ep.Direction = EfiUsbDataIn;
Ep.DevSpeed = EFI_USB_SPEED_HIGH;
Ep.MaxPacket = 64;
Ep.HubAddr = 0;
Ep.HubPort = 0;
Ep.Toggle = 0;
Ep.Type = EHC_BULK_TRANSFER;
Ep.PollRate = 1;
Qh = EhcCreateQh (Ehc, &Ep);
Qh = EhcCreateQh (Ehc, &Ep);
if (Qh == NULL) {
return EFI_OUT_OF_RESOURCES;
@@ -66,7 +65,7 @@ EhcCreateHelpQ (
PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Qh, sizeof (EHC_QH));
QhHw = &Qh->QhHw;
QhHw->HorizonLink = QH_LINK (PciAddr + OFFSET_OF(EHC_QH, QhHw), EHC_TYPE_QH, FALSE);
QhHw->HorizonLink = QH_LINK (PciAddr + OFFSET_OF (EHC_QH, QhHw), EHC_TYPE_QH, FALSE);
QhHw->Status = QTD_STAT_HALTED;
QhHw->ReclaimHead = 1;
Qh->NextQh = Qh;
@@ -75,10 +74,10 @@ EhcCreateHelpQ (
//
// Create a dummy QH to act as the terminator for periodical schedule
//
Ep.EpAddr = 2;
Ep.Type = EHC_INT_TRANSFER_SYNC;
Ep.EpAddr = 2;
Ep.Type = EHC_INT_TRANSFER_SYNC;
Qh = EhcCreateQh (Ehc, &Ep);
Qh = EhcCreateQh (Ehc, &Ep);
if (Qh == NULL) {
return EFI_OUT_OF_RESOURCES;
@@ -90,7 +89,6 @@ EhcCreateHelpQ (
return EFI_SUCCESS;
}
/**
Initialize the schedule data structure such as frame list.
@@ -102,7 +100,7 @@ EhcCreateHelpQ (
**/
EFI_STATUS
EhcInitSched (
IN USB2_HC_DEV *Ehc
IN USB2_HC_DEV *Ehc
)
{
EFI_PCI_IO_PROTOCOL *PciIo;
@@ -154,8 +152,8 @@ EhcInitSched (
return EFI_OUT_OF_RESOURCES;
}
Ehc->PeriodFrame = Buf;
Ehc->PeriodFrameMap = Map;
Ehc->PeriodFrame = Buf;
Ehc->PeriodFrameMap = Map;
//
// Program the FRAMELISTBASE register with the low 32 bit addr
@@ -191,13 +189,13 @@ EhcInitSched (
//
// Initialize the frame list entries then set the registers
//
Ehc->PeriodFrameHost = AllocateZeroPool (EHC_FRAME_LEN * sizeof (UINTN));
Ehc->PeriodFrameHost = AllocateZeroPool (EHC_FRAME_LEN * sizeof (UINTN));
if (Ehc->PeriodFrameHost == NULL) {
Status = EFI_OUT_OF_RESOURCES;
goto ErrorExit;
}
PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Ehc->PeriodOne, sizeof (EHC_QH));
PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Ehc->PeriodOne, sizeof (EHC_QH));
for (Index = 0; Index < EHC_FRAME_LEN; Index++) {
//
@@ -242,7 +240,6 @@ ErrorExit1:
return Status;
}
/**
Free the schedule data. It may be partially initialized.
@@ -251,10 +248,10 @@ ErrorExit1:
**/
VOID
EhcFreeSched (
IN USB2_HC_DEV *Ehc
IN USB2_HC_DEV *Ehc
)
{
EFI_PCI_IO_PROTOCOL *PciIo;
EFI_PCI_IO_PROTOCOL *PciIo;
EhcWriteOpReg (Ehc, EHC_FRAME_BASE_OFFSET, 0);
EhcWriteOpReg (Ehc, EHC_ASYNC_HEAD_OFFSET, 0);
@@ -300,7 +297,6 @@ EhcFreeSched (
}
}
/**
Link the queue head to the asynchronous schedule list.
UEFI only supports one CTRL/BULK transfer at a time
@@ -314,30 +310,29 @@ EhcFreeSched (
**/
VOID
EhcLinkQhToAsync (
IN USB2_HC_DEV *Ehc,
IN EHC_QH *Qh
IN USB2_HC_DEV *Ehc,
IN EHC_QH *Qh
)
{
EHC_QH *Head;
EFI_PHYSICAL_ADDRESS PciAddr;
EHC_QH *Head;
EFI_PHYSICAL_ADDRESS PciAddr;
//
// Append the queue head after the reclaim header, then
// fix the hardware visiable parts (EHCI R1.0 page 72).
// ReclaimHead is always linked to the EHCI's AsynListAddr.
//
Head = Ehc->ReclaimHead;
Head = Ehc->ReclaimHead;
Qh->NextQh = Head->NextQh;
Head->NextQh = Qh;
Qh->NextQh = Head->NextQh;
Head->NextQh = Qh;
PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Qh->NextQh, sizeof (EHC_QH));
Qh->QhHw.HorizonLink = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);
PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Head->NextQh, sizeof (EHC_QH));
Head->QhHw.HorizonLink = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);
PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Qh->NextQh, sizeof (EHC_QH));
Qh->QhHw.HorizonLink = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);
PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Head->NextQh, sizeof (EHC_QH));
Head->QhHw.HorizonLink = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);
}
/**
Unlink a queue head from the asynchronous schedule list.
Need to synchronize with hardware.
@@ -348,13 +343,13 @@ EhcLinkQhToAsync (
**/
VOID
EhcUnlinkQhFromAsync (
IN USB2_HC_DEV *Ehc,
IN EHC_QH *Qh
IN USB2_HC_DEV *Ehc,
IN EHC_QH *Qh
)
{
EHC_QH *Head;
EFI_STATUS Status;
EFI_PHYSICAL_ADDRESS PciAddr;
EHC_QH *Head;
EFI_STATUS Status;
EFI_PHYSICAL_ADDRESS PciAddr;
ASSERT (Ehc->ReclaimHead->NextQh == Qh);
@@ -363,13 +358,13 @@ EhcUnlinkQhFromAsync (
// visiable part: Only need to loopback the ReclaimHead. The Qh
// is pointing to ReclaimHead (which is staill in the list).
//
Head = Ehc->ReclaimHead;
Head = Ehc->ReclaimHead;
Head->NextQh = Qh->NextQh;
Qh->NextQh = NULL;
Head->NextQh = Qh->NextQh;
Qh->NextQh = NULL;
PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Head->NextQh, sizeof (EHC_QH));
Head->QhHw.HorizonLink = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);
PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Head->NextQh, sizeof (EHC_QH));
Head->QhHw.HorizonLink = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);
//
// Set and wait the door bell to synchronize with the hardware
@@ -381,7 +376,6 @@ EhcUnlinkQhFromAsync (
}
}
/**
Link a queue head for interrupt transfer to the periodic
schedule frame list. This code is very much the same as
@@ -393,23 +387,23 @@ EhcUnlinkQhFromAsync (
**/
VOID
EhcLinkQhToPeriod (
IN USB2_HC_DEV *Ehc,
IN EHC_QH *Qh
IN USB2_HC_DEV *Ehc,
IN EHC_QH *Qh
)
{
UINTN Index;
EHC_QH *Prev;
EHC_QH *Next;
EFI_PHYSICAL_ADDRESS PciAddr;
UINTN Index;
EHC_QH *Prev;
EHC_QH *Next;
EFI_PHYSICAL_ADDRESS PciAddr;
for (Index = 0; Index < EHC_FRAME_LEN; Index += Qh->Interval) {
//
// First QH can't be NULL because we always keep PeriodOne
// heads on the frame list
//
ASSERT (!EHC_LINK_TERMINATED (((UINT32*)Ehc->PeriodFrame)[Index]));
Next = (EHC_QH*)((UINTN*)Ehc->PeriodFrameHost)[Index];
Prev = NULL;
ASSERT (!EHC_LINK_TERMINATED (((UINT32 *)Ehc->PeriodFrame)[Index]));
Next = (EHC_QH *)((UINTN *)Ehc->PeriodFrameHost)[Index];
Prev = NULL;
//
// Now, insert the queue head (Qh) into this frame:
@@ -422,8 +416,8 @@ EhcLinkQhToPeriod (
// Then, insert the Qh between then
//
while (Next->Interval > Qh->Interval) {
Prev = Next;
Next = Next->NextQh;
Prev = Next;
Next = Next->NextQh;
}
ASSERT (Next != NULL);
@@ -449,15 +443,15 @@ EhcLinkQhToPeriod (
//
ASSERT ((Index == 0) && (Qh->NextQh == NULL));
Prev = Next;
Next = Next->NextQh;
Prev = Next;
Next = Next->NextQh;
Qh->NextQh = Next;
Prev->NextQh = Qh;
Qh->NextQh = Next;
Prev->NextQh = Qh;
Qh->QhHw.HorizonLink = Prev->QhHw.HorizonLink;
PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Qh, sizeof (EHC_QH));
Prev->QhHw.HorizonLink = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);
Qh->QhHw.HorizonLink = Prev->QhHw.HorizonLink;
PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Qh, sizeof (EHC_QH));
Prev->QhHw.HorizonLink = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);
break;
}
@@ -467,24 +461,23 @@ EhcLinkQhToPeriod (
// guarranted by 2^n polling interval.
//
if (Qh->NextQh == NULL) {
Qh->NextQh = Next;
PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Next, sizeof (EHC_QH));
Qh->QhHw.HorizonLink = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);
Qh->NextQh = Next;
PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Next, sizeof (EHC_QH));
Qh->QhHw.HorizonLink = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);
}
PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Qh, sizeof (EHC_QH));
if (Prev == NULL) {
((UINT32*)Ehc->PeriodFrame)[Index] = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);
((UINTN*)Ehc->PeriodFrameHost)[Index] = (UINTN)Qh;
((UINT32 *)Ehc->PeriodFrame)[Index] = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);
((UINTN *)Ehc->PeriodFrameHost)[Index] = (UINTN)Qh;
} else {
Prev->NextQh = Qh;
Prev->QhHw.HorizonLink = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);
Prev->NextQh = Qh;
Prev->QhHw.HorizonLink = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);
}
}
}
/**
Unlink an interrupt queue head from the periodic
schedule frame list.
@@ -495,30 +488,30 @@ EhcLinkQhToPeriod (
**/
VOID
EhcUnlinkQhFromPeriod (
IN USB2_HC_DEV *Ehc,
IN EHC_QH *Qh
IN USB2_HC_DEV *Ehc,
IN EHC_QH *Qh
)
{
UINTN Index;
EHC_QH *Prev;
EHC_QH *This;
UINTN Index;
EHC_QH *Prev;
EHC_QH *This;
for (Index = 0; Index < EHC_FRAME_LEN; Index += Qh->Interval) {
//
// Frame link can't be NULL because we always keep PeroidOne
// on the frame list
//
ASSERT (!EHC_LINK_TERMINATED (((UINT32*)Ehc->PeriodFrame)[Index]));
This = (EHC_QH*)((UINTN*)Ehc->PeriodFrameHost)[Index];
Prev = NULL;
ASSERT (!EHC_LINK_TERMINATED (((UINT32 *)Ehc->PeriodFrame)[Index]));
This = (EHC_QH *)((UINTN *)Ehc->PeriodFrameHost)[Index];
Prev = NULL;
//
// Walk through the frame's QH list to find the
// queue head to remove
//
while ((This != NULL) && (This != Qh)) {
Prev = This;
This = This->NextQh;
Prev = This;
This = This->NextQh;
}
//
@@ -533,16 +526,15 @@ EhcUnlinkQhFromPeriod (
//
// Qh is the first entry in the frame
//
((UINT32*)Ehc->PeriodFrame)[Index] = Qh->QhHw.HorizonLink;
((UINTN*)Ehc->PeriodFrameHost)[Index] = (UINTN)Qh->NextQh;
((UINT32 *)Ehc->PeriodFrame)[Index] = Qh->QhHw.HorizonLink;
((UINTN *)Ehc->PeriodFrameHost)[Index] = (UINTN)Qh->NextQh;
} else {
Prev->NextQh = Qh->NextQh;
Prev->QhHw.HorizonLink = Qh->QhHw.HorizonLink;
Prev->NextQh = Qh->NextQh;
Prev->QhHw.HorizonLink = Qh->QhHw.HorizonLink;
}
}
}
/**
Check the URB's execution result and update the URB's
result accordingly.
@@ -555,23 +547,23 @@ EhcUnlinkQhFromPeriod (
**/
BOOLEAN
EhcCheckUrbResult (
IN USB2_HC_DEV *Ehc,
IN URB *Urb
IN USB2_HC_DEV *Ehc,
IN URB *Urb
)
{
LIST_ENTRY *Entry;
EHC_QTD *Qtd;
QTD_HW *QtdHw;
UINT8 State;
BOOLEAN Finished;
EFI_PHYSICAL_ADDRESS PciAddr;
LIST_ENTRY *Entry;
EHC_QTD *Qtd;
QTD_HW *QtdHw;
UINT8 State;
BOOLEAN Finished;
EFI_PHYSICAL_ADDRESS PciAddr;
ASSERT ((Ehc != NULL) && (Urb != NULL) && (Urb->Qh != NULL));
Finished = TRUE;
Urb->Completed = 0;
Finished = TRUE;
Urb->Completed = 0;
Urb->Result = EFI_USB_NOERROR;
Urb->Result = EFI_USB_NOERROR;
if (EhcIsHalt (Ehc) || EhcIsSysError (Ehc)) {
Urb->Result |= EFI_USB_ERR_SYSTEM;
@@ -581,7 +573,7 @@ EhcCheckUrbResult (
BASE_LIST_FOR_EACH (Entry, &Urb->Qh->Qtds) {
Qtd = EFI_LIST_CONTAINER (Entry, EHC_QTD, QtdList);
QtdHw = &Qtd->QtdHw;
State = (UINT8) QtdHw->Status;
State = (UINT8)QtdHw->Status;
if (EHC_BIT_IS_SET (State, QTD_STAT_HALTED)) {
//
@@ -606,7 +598,6 @@ EhcCheckUrbResult (
Finished = TRUE;
goto ON_EXIT;
} else if (EHC_BIT_IS_SET (State, QTD_STAT_ACTIVE)) {
//
// The QTD is still active, no need to check furthur.
@@ -615,7 +606,6 @@ EhcCheckUrbResult (
Finished = FALSE;
goto ON_EXIT;
} else {
//
// This QTD is finished OK or met short packet read. Update the
@@ -657,12 +647,11 @@ ON_EXIT:
// NOTICE: don't move DT update before the loop, otherwise there is
// a race condition that DT is wrong.
//
Urb->DataToggle = (UINT8) Urb->Qh->QhHw.DataToggle;
Urb->DataToggle = (UINT8)Urb->Qh->QhHw.DataToggle;
return Finished;
}
/**
Execute the transfer by polling the URB. This is a synchronous operation.
@@ -677,16 +666,16 @@ ON_EXIT:
**/
EFI_STATUS
EhcExecTransfer (
IN USB2_HC_DEV *Ehc,
IN URB *Urb,
IN UINTN TimeOut
IN USB2_HC_DEV *Ehc,
IN URB *Urb,
IN UINTN TimeOut
)
{
EFI_STATUS Status;
UINTN Index;
UINTN Loop;
BOOLEAN Finished;
BOOLEAN InfiniteLoop;
EFI_STATUS Status;
UINTN Index;
UINTN Loop;
BOOLEAN Finished;
BOOLEAN InfiniteLoop;
Status = EFI_SUCCESS;
Loop = TimeOut * EHC_1_MILLISECOND;
@@ -717,7 +706,6 @@ EhcExecTransfer (
EhcDumpQh (Urb->Qh, NULL, FALSE);
Status = EFI_TIMEOUT;
} else if (Urb->Result != EFI_USB_NOERROR) {
DEBUG ((DEBUG_ERROR, "EhcExecTransfer: transfer failed with %x\n", Urb->Result));
EhcDumpQh (Urb->Qh, NULL, FALSE);
@@ -728,7 +716,6 @@ EhcExecTransfer (
return Status;
}
/**
Delete a single asynchronous interrupt transfer for
the device and endpoint.
@@ -744,10 +731,10 @@ EhcExecTransfer (
**/
EFI_STATUS
EhciDelAsyncIntTransfer (
IN USB2_HC_DEV *Ehc,
IN UINT8 DevAddr,
IN UINT8 EpNum,
OUT UINT8 *DataToggle
IN USB2_HC_DEV *Ehc,
IN UINT8 DevAddr,
IN UINT8 EpNum,
OUT UINT8 *DataToggle
)
{
LIST_ENTRY *Entry;
@@ -762,7 +749,8 @@ EhciDelAsyncIntTransfer (
Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);
if ((Urb->Ep.DevAddr == DevAddr) && (Urb->Ep.EpAddr == EpNum) &&
(Urb->Ep.Direction == Direction)) {
(Urb->Ep.Direction == Direction))
{
//
// Check the URB status to retrieve the next data toggle
// from the associated queue head.
@@ -782,7 +770,6 @@ EhciDelAsyncIntTransfer (
return EFI_NOT_FOUND;
}
/**
Remove all the asynchronous interrutp transfers.
@@ -791,12 +778,12 @@ EhciDelAsyncIntTransfer (
**/
VOID
EhciDelAllAsyncIntTransfers (
IN USB2_HC_DEV *Ehc
IN USB2_HC_DEV *Ehc
)
{
LIST_ENTRY *Entry;
LIST_ENTRY *Next;
URB *Urb;
LIST_ENTRY *Entry;
LIST_ENTRY *Next;
URB *Urb;
BASE_LIST_FOR_EACH_SAFE (Entry, Next, &Ehc->AsyncIntTransfers) {
Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);
@@ -830,21 +817,21 @@ EhciDelAllAsyncIntTransfers (
**/
URB *
EhciInsertAsyncIntTransfer (
IN USB2_HC_DEV *Ehc,
IN UINT8 DevAddr,
IN UINT8 EpAddr,
IN UINT8 DevSpeed,
IN UINT8 Toggle,
IN UINTN MaxPacket,
IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Hub,
IN UINTN DataLen,
IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
IN VOID *Context,
IN UINTN Interval
IN USB2_HC_DEV *Ehc,
IN UINT8 DevAddr,
IN UINT8 EpAddr,
IN UINT8 DevSpeed,
IN UINT8 Toggle,
IN UINTN MaxPacket,
IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Hub,
IN UINTN DataLen,
IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
IN VOID *Context,
IN UINTN Interval
)
{
VOID *Data;
URB *Urb;
VOID *Data;
URB *Urb;
Data = AllocatePool (DataLen);
@@ -899,16 +886,16 @@ EhciInsertAsyncIntTransfer (
**/
EFI_STATUS
EhcFlushAsyncIntMap (
IN USB2_HC_DEV *Ehc,
IN URB *Urb
IN USB2_HC_DEV *Ehc,
IN URB *Urb
)
{
EFI_STATUS Status;
EFI_PHYSICAL_ADDRESS PhyAddr;
EFI_PCI_IO_PROTOCOL_OPERATION MapOp;
EFI_PCI_IO_PROTOCOL *PciIo;
UINTN Len;
VOID *Map;
EFI_STATUS Status;
EFI_PHYSICAL_ADDRESS PhyAddr;
EFI_PCI_IO_PROTOCOL_OPERATION MapOp;
EFI_PCI_IO_PROTOCOL *PciIo;
UINTN Len;
VOID *Map;
PciIo = Ehc->PciIo;
Len = Urb->DataLen;
@@ -931,15 +918,14 @@ EhcFlushAsyncIntMap (
goto ON_ERROR;
}
Urb->DataPhy = (VOID *) ((UINTN) PhyAddr);
Urb->DataMap = Map;
Urb->DataPhy = (VOID *)((UINTN)PhyAddr);
Urb->DataMap = Map;
return EFI_SUCCESS;
ON_ERROR:
return EFI_DEVICE_ERROR;
}
/**
Update the queue head for next round of asynchronous transfer.
@@ -949,17 +935,17 @@ ON_ERROR:
**/
VOID
EhcUpdateAsyncRequest (
IN USB2_HC_DEV *Ehc,
IN URB *Urb
IN USB2_HC_DEV *Ehc,
IN URB *Urb
)
{
LIST_ENTRY *Entry;
EHC_QTD *FirstQtd;
QH_HW *QhHw;
EHC_QTD *Qtd;
QTD_HW *QtdHw;
UINTN Index;
EFI_PHYSICAL_ADDRESS PciAddr;
LIST_ENTRY *Entry;
EHC_QTD *FirstQtd;
QH_HW *QhHw;
EHC_QTD *Qtd;
QTD_HW *QtdHw;
UINTN Index;
EFI_PHYSICAL_ADDRESS PciAddr;
Qtd = NULL;
@@ -985,13 +971,13 @@ EhcUpdateAsyncRequest (
QtdHw->Status = QTD_STAT_ACTIVE;
QtdHw->ErrCnt = QTD_MAX_ERR;
QtdHw->CurPage = 0;
QtdHw->TotalBytes = (UINT32) Qtd->DataLen;
QtdHw->TotalBytes = (UINT32)Qtd->DataLen;
//
// calculate physical address by offset.
//
PciAddr = (UINTN)Urb->DataPhy + ((UINTN)Qtd->Data - (UINTN)Urb->Data);
QtdHw->Page[0] = EHC_LOW_32BIT (PciAddr);
QtdHw->PageHigh[0]= EHC_HIGH_32BIT (PciAddr);
PciAddr = (UINTN)Urb->DataPhy + ((UINTN)Qtd->Data - (UINTN)Urb->Data);
QtdHw->Page[0] = EHC_LOW_32BIT (PciAddr);
QtdHw->PageHigh[0] = EHC_HIGH_32BIT (PciAddr);
}
//
@@ -1000,30 +986,29 @@ EhcUpdateAsyncRequest (
// zero out the overlay area and set NextQtd to the first
// QTD. DateToggle bit is left untouched.
//
QhHw = &Urb->Qh->QhHw;
QhHw->CurQtd = QTD_LINK (0, TRUE);
QhHw->AltQtd = 0;
QhHw = &Urb->Qh->QhHw;
QhHw->CurQtd = QTD_LINK (0, TRUE);
QhHw->AltQtd = 0;
QhHw->Status = 0;
QhHw->Pid = 0;
QhHw->ErrCnt = 0;
QhHw->CurPage = 0;
QhHw->Ioc = 0;
QhHw->TotalBytes = 0;
QhHw->Status = 0;
QhHw->Pid = 0;
QhHw->ErrCnt = 0;
QhHw->CurPage = 0;
QhHw->Ioc = 0;
QhHw->TotalBytes = 0;
for (Index = 0; Index < 5; Index++) {
QhHw->Page[Index] = 0;
QhHw->PageHigh[Index] = 0;
}
PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, FirstQtd, sizeof (EHC_QTD));
PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, FirstQtd, sizeof (EHC_QTD));
QhHw->NextQtd = QTD_LINK (PciAddr, FALSE);
}
return ;
return;
}
/**
Interrupt transfer periodic check handler.
@@ -1034,21 +1019,21 @@ EhcUpdateAsyncRequest (
VOID
EFIAPI
EhcMonitorAsyncRequests (
IN EFI_EVENT Event,
IN VOID *Context
IN EFI_EVENT Event,
IN VOID *Context
)
{
USB2_HC_DEV *Ehc;
EFI_TPL OldTpl;
LIST_ENTRY *Entry;
LIST_ENTRY *Next;
BOOLEAN Finished;
UINT8 *ProcBuf;
URB *Urb;
EFI_STATUS Status;
USB2_HC_DEV *Ehc;
EFI_TPL OldTpl;
LIST_ENTRY *Entry;
LIST_ENTRY *Next;
BOOLEAN Finished;
UINT8 *ProcBuf;
URB *Urb;
EFI_STATUS Status;
OldTpl = gBS->RaiseTPL (EHC_TPL);
Ehc = (USB2_HC_DEV *) Context;
OldTpl = gBS->RaiseTPL (EHC_TPL);
Ehc = (USB2_HC_DEV *)Context;
BASE_LIST_FOR_EACH_SAFE (Entry, Next, &Ehc->AsyncIntTransfers) {
Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);
@@ -1113,7 +1098,7 @@ EhcMonitorAsyncRequests (
// his callback. Some drivers may has a lower TPL restriction.
//
gBS->RestoreTPL (OldTpl);
(Urb->Callback) (ProcBuf, Urb->Completed, Urb->Context, Urb->Result);
(Urb->Callback)(ProcBuf, Urb->Completed, Urb->Context, Urb->Result);
OldTpl = gBS->RaiseTPL (EHC_TPL);
}

72
MdeModulePkg/Bus/Pci/EhciDxe/EhciSched.h
View File

@@ -10,7 +10,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#ifndef _EFI_EHCI_SCHED_H_
#define _EFI_EHCI_SCHED_H_
/**
Initialize the schedule data structure such as frame list.
@@ -22,10 +21,9 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
EFI_STATUS
EhcInitSched (
IN USB2_HC_DEV *Ehc
IN USB2_HC_DEV *Ehc
);
/**
Free the schedule data. It may be partially initialized.
@@ -34,10 +32,9 @@ EhcInitSched (
**/
VOID
EhcFreeSched (
IN USB2_HC_DEV *Ehc
IN USB2_HC_DEV *Ehc
);
/**
Link the queue head to the asynchronous schedule list.
UEFI only supports one CTRL/BULK transfer at a time
@@ -51,11 +48,10 @@ EhcFreeSched (
**/
VOID
EhcLinkQhToAsync (
IN USB2_HC_DEV *Ehc,
IN EHC_QH *Qh
IN USB2_HC_DEV *Ehc,
IN EHC_QH *Qh
);
/**
Unlink a queue head from the asynchronous schedule list.
Need to synchronize with hardware.
@@ -66,11 +62,10 @@ EhcLinkQhToAsync (
**/
VOID
EhcUnlinkQhFromAsync (
IN USB2_HC_DEV *Ehc,
IN EHC_QH *Qh
IN USB2_HC_DEV *Ehc,
IN EHC_QH *Qh
);
/**
Link a queue head for interrupt transfer to the periodic
schedule frame list. This code is very much the same as
@@ -82,11 +77,10 @@ EhcUnlinkQhFromAsync (
**/
VOID
EhcLinkQhToPeriod (
IN USB2_HC_DEV *Ehc,
IN EHC_QH *Qh
IN USB2_HC_DEV *Ehc,
IN EHC_QH *Qh
);
/**
Unlink an interrupt queue head from the periodic
schedule frame list.
@@ -97,12 +91,10 @@ EhcLinkQhToPeriod (
**/
VOID
EhcUnlinkQhFromPeriod (
IN USB2_HC_DEV *Ehc,
IN EHC_QH *Qh
IN USB2_HC_DEV *Ehc,
IN EHC_QH *Qh
);
/**
Execute the transfer by polling the URB. This is a synchronous operation.
@@ -117,12 +109,11 @@ EhcUnlinkQhFromPeriod (
**/
EFI_STATUS
EhcExecTransfer (
IN USB2_HC_DEV *Ehc,
IN URB *Urb,
IN UINTN TimeOut
IN USB2_HC_DEV *Ehc,
IN URB *Urb,
IN UINTN TimeOut
);
/**
Delete a single asynchronous interrupt transfer for
the device and endpoint.
@@ -138,13 +129,12 @@ EhcExecTransfer (
**/
EFI_STATUS
EhciDelAsyncIntTransfer (
IN USB2_HC_DEV *Ehc,
IN UINT8 DevAddr,
IN UINT8 EpNum,
OUT UINT8 *DataToggle
IN USB2_HC_DEV *Ehc,
IN UINT8 DevAddr,
IN UINT8 EpNum,
OUT UINT8 *DataToggle
);
/**
Remove all the asynchronous interrutp transfers.
@@ -153,7 +143,7 @@ EhciDelAsyncIntTransfer (
**/
VOID
EhciDelAllAsyncIntTransfers (
IN USB2_HC_DEV *Ehc
IN USB2_HC_DEV *Ehc
);
/**
@@ -177,17 +167,17 @@ EhciDelAllAsyncIntTransfers (
**/
URB *
EhciInsertAsyncIntTransfer (
IN USB2_HC_DEV *Ehc,
IN UINT8 DevAddr,
IN UINT8 EpAddr,
IN UINT8 DevSpeed,
IN UINT8 Toggle,
IN UINTN MaxPacket,
IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Hub,
IN UINTN DataLen,
IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
IN VOID *Context,
IN UINTN Interval
IN USB2_HC_DEV *Ehc,
IN UINT8 DevAddr,
IN UINT8 EpAddr,
IN UINT8 DevSpeed,
IN UINT8 Toggle,
IN UINTN MaxPacket,
IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Hub,
IN UINTN DataLen,
IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
IN VOID *Context,
IN UINTN Interval
);
/**
@@ -200,8 +190,8 @@ EhciInsertAsyncIntTransfer (
VOID
EFIAPI
EhcMonitorAsyncRequests (
IN EFI_EVENT Event,
IN VOID *Context
IN EFI_EVENT Event,
IN VOID *Context
);
#endif

321
MdeModulePkg/Bus/Pci/EhciDxe/EhciUrb.c
View File

@@ -11,7 +11,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include "Ehci.h"
/**
Create a single QTD to hold the data.
@@ -28,20 +27,20 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
EHC_QTD *
EhcCreateQtd (
IN USB2_HC_DEV *Ehc,
IN UINT8 *Data,
IN UINT8 *DataPhy,
IN UINTN DataLen,
IN UINT8 PktId,
IN UINT8 Toggle,
IN UINTN MaxPacket
IN USB2_HC_DEV *Ehc,
IN UINT8 *Data,
IN UINT8 *DataPhy,
IN UINTN DataLen,
IN UINT8 PktId,
IN UINT8 Toggle,
IN UINTN MaxPacket
)
{
EHC_QTD *Qtd;
QTD_HW *QtdHw;
UINTN Index;
UINTN Len;
UINTN ThisBufLen;
EHC_QTD *Qtd;
QTD_HW *QtdHw;
UINTN Index;
UINTN Len;
UINTN ThisBufLen;
ASSERT (Ehc != NULL);
@@ -51,9 +50,9 @@ EhcCreateQtd (
return NULL;
}
Qtd->Signature = EHC_QTD_SIG;
Qtd->Data = Data;
Qtd->DataLen = 0;
Qtd->Signature = EHC_QTD_SIG;
Qtd->Data = Data;
Qtd->DataLen = 0;
InitializeListHead (&Qtd->QtdList);
@@ -79,18 +78,18 @@ EhcCreateQtd (
// compute the offset and clear Reserved fields. This is already
// done in the data point.
//
QtdHw->Page[Index] = EHC_LOW_32BIT (DataPhy);
QtdHw->PageHigh[Index] = EHC_HIGH_32BIT (DataPhy);
QtdHw->Page[Index] = EHC_LOW_32BIT (DataPhy);
QtdHw->PageHigh[Index] = EHC_HIGH_32BIT (DataPhy);
ThisBufLen = QTD_BUF_LEN - (EHC_LOW_32BIT (DataPhy) & QTD_BUF_MASK);
ThisBufLen = QTD_BUF_LEN - (EHC_LOW_32BIT (DataPhy) & QTD_BUF_MASK);
if (Len + ThisBufLen >= DataLen) {
Len = DataLen;
break;
}
Len += ThisBufLen;
Data += ThisBufLen;
Len += ThisBufLen;
Data += ThisBufLen;
DataPhy += ThisBufLen;
}
@@ -104,15 +103,13 @@ EhcCreateQtd (
Len = Len - Len % MaxPacket;
}
QtdHw->TotalBytes = (UINT32) Len;
QtdHw->TotalBytes = (UINT32)Len;
Qtd->DataLen = Len;
}
return Qtd;
}
/**
Initialize the queue head for interrupt transfer,
that is, initialize the following three fields:
@@ -126,8 +123,8 @@ EhcCreateQtd (
**/
VOID
EhcInitIntQh (
IN USB_ENDPOINT *Ep,
IN QH_HW *QhHw
IN USB_ENDPOINT *Ep,
IN QH_HW *QhHw
)
{
//
@@ -139,7 +136,7 @@ EhcInitIntQh (
//
if (Ep->DevSpeed == EFI_USB_SPEED_HIGH) {
QhHw->SMask = QH_MICROFRAME_0;
return ;
return;
}
//
@@ -157,8 +154,6 @@ EhcInitIntQh (
QhHw->CMask = QH_MICROFRAME_3 | QH_MICROFRAME_4 | QH_MICROFRAME_5;
}
/**
Allocate and initialize a EHCI queue head.
@@ -170,12 +165,12 @@ EhcInitIntQh (
**/
EHC_QH *
EhcCreateQh (
IN USB2_HC_DEV *Ehci,
IN USB_ENDPOINT *Ep
IN USB2_HC_DEV *Ehci,
IN USB_ENDPOINT *Ep
)
{
EHC_QH *Qh;
QH_HW *QhHw;
EHC_QH *Qh;
QH_HW *QhHw;
Qh = UsbHcAllocateMem (Ehci->MemPool, sizeof (EHC_QH));
@@ -183,68 +178,68 @@ EhcCreateQh (
return NULL;
}
Qh->Signature = EHC_QH_SIG;
Qh->NextQh = NULL;
Qh->Interval = Ep->PollRate;
Qh->Signature = EHC_QH_SIG;
Qh->NextQh = NULL;
Qh->Interval = Ep->PollRate;
InitializeListHead (&Qh->Qtds);
QhHw = &Qh->QhHw;
QhHw->HorizonLink = QH_LINK (NULL, 0, TRUE);
QhHw->DeviceAddr = Ep->DevAddr;
QhHw->Inactive = 0;
QhHw->EpNum = Ep->EpAddr;
QhHw->EpSpeed = Ep->DevSpeed;
QhHw->DtCtrl = 0;
QhHw->ReclaimHead = 0;
QhHw->MaxPacketLen = (UINT32) Ep->MaxPacket;
QhHw->CtrlEp = 0;
QhHw->NakReload = QH_NAK_RELOAD;
QhHw->HubAddr = Ep->HubAddr;
QhHw->PortNum = Ep->HubPort;
QhHw->Multiplier = 1;
QhHw->DataToggle = Ep->Toggle;
QhHw = &Qh->QhHw;
QhHw->HorizonLink = QH_LINK (NULL, 0, TRUE);
QhHw->DeviceAddr = Ep->DevAddr;
QhHw->Inactive = 0;
QhHw->EpNum = Ep->EpAddr;
QhHw->EpSpeed = Ep->DevSpeed;
QhHw->DtCtrl = 0;
QhHw->ReclaimHead = 0;
QhHw->MaxPacketLen = (UINT32)Ep->MaxPacket;
QhHw->CtrlEp = 0;
QhHw->NakReload = QH_NAK_RELOAD;
QhHw->HubAddr = Ep->HubAddr;
QhHw->PortNum = Ep->HubPort;
QhHw->Multiplier = 1;
QhHw->DataToggle = Ep->Toggle;
if (Ep->DevSpeed != EFI_USB_SPEED_HIGH) {
QhHw->Status |= QTD_STAT_DO_SS;
}
switch (Ep->Type) {
case EHC_CTRL_TRANSFER:
//
// Special initialization for the control transfer:
// 1. Control transfer initialize data toggle from each QTD
// 2. Set the Control Endpoint Flag (C) for low/full speed endpoint.
//
QhHw->DtCtrl = 1;
case EHC_CTRL_TRANSFER:
//
// Special initialization for the control transfer:
// 1. Control transfer initialize data toggle from each QTD
// 2. Set the Control Endpoint Flag (C) for low/full speed endpoint.
//
QhHw->DtCtrl = 1;
if (Ep->DevSpeed != EFI_USB_SPEED_HIGH) {
QhHw->CtrlEp = 1;
}
break;
if (Ep->DevSpeed != EFI_USB_SPEED_HIGH) {
QhHw->CtrlEp = 1;
}
case EHC_INT_TRANSFER_ASYNC:
case EHC_INT_TRANSFER_SYNC:
//
// Special initialization for the interrupt transfer
// to set the S-Mask and C-Mask
//
QhHw->NakReload = 0;
EhcInitIntQh (Ep, QhHw);
break;
break;
case EHC_BULK_TRANSFER:
if ((Ep->DevSpeed == EFI_USB_SPEED_HIGH) && (Ep->Direction == EfiUsbDataOut)) {
QhHw->Status |= QTD_STAT_DO_PING;
}
case EHC_INT_TRANSFER_ASYNC:
case EHC_INT_TRANSFER_SYNC:
//
// Special initialization for the interrupt transfer
// to set the S-Mask and C-Mask
//
QhHw->NakReload = 0;
EhcInitIntQh (Ep, QhHw);
break;
break;
case EHC_BULK_TRANSFER:
if ((Ep->DevSpeed == EFI_USB_SPEED_HIGH) && (Ep->Direction == EfiUsbDataOut)) {
QhHw->Status |= QTD_STAT_DO_PING;
}
break;
}
return Qh;
}
/**
Convert the poll interval from application to that
be used by EHCI interface data structure. Only need
@@ -260,10 +255,10 @@ EhcCreateQh (
**/
UINTN
EhcConvertPollRate (
IN UINTN Interval
IN UINTN Interval
)
{
UINTN BitCount;
UINTN BitCount;
if (Interval == 0) {
return 1;
@@ -282,7 +277,6 @@ EhcConvertPollRate (
return (UINTN)1 << (BitCount - 1);
}
/**
Free a list of QTDs.
@@ -292,13 +286,13 @@ EhcConvertPollRate (
**/
VOID
EhcFreeQtds (
IN USB2_HC_DEV *Ehc,
IN LIST_ENTRY *Qtds
IN USB2_HC_DEV *Ehc,
IN LIST_ENTRY *Qtds
)
{
LIST_ENTRY *Entry;
LIST_ENTRY *Next;
EHC_QTD *Qtd;
LIST_ENTRY *Entry;
LIST_ENTRY *Next;
EHC_QTD *Qtd;
BASE_LIST_FOR_EACH_SAFE (Entry, Next, Qtds) {
Qtd = EFI_LIST_CONTAINER (Entry, EHC_QTD, QtdList);
@@ -308,7 +302,6 @@ EhcFreeQtds (
}
}
/**
Free an allocated URB. It is possible for it to be partially inited.
@@ -318,11 +311,11 @@ EhcFreeQtds (
**/
VOID
EhcFreeUrb (
IN USB2_HC_DEV *Ehc,
IN URB *Urb
IN USB2_HC_DEV *Ehc,
IN URB *Urb
)
{
EFI_PCI_IO_PROTOCOL *PciIo;
EFI_PCI_IO_PROTOCOL *PciIo;
PciIo = Ehc->PciIo;
@@ -346,7 +339,6 @@ EhcFreeUrb (
gBS->FreePool (Urb);
}
/**
Create a list of QTDs for the URB.
@@ -359,21 +351,21 @@ EhcFreeUrb (
**/
EFI_STATUS
EhcCreateQtds (
IN USB2_HC_DEV *Ehc,
IN URB *Urb
IN USB2_HC_DEV *Ehc,
IN URB *Urb
)
{
USB_ENDPOINT *Ep;
EHC_QH *Qh;
EHC_QTD *Qtd;
EHC_QTD *StatusQtd;
EHC_QTD *NextQtd;
LIST_ENTRY *Entry;
UINT32 AlterNext;
UINT8 Toggle;
UINTN Len;
UINT8 Pid;
EFI_PHYSICAL_ADDRESS PhyAddr;
USB_ENDPOINT *Ep;
EHC_QH *Qh;
EHC_QTD *Qtd;
EHC_QTD *StatusQtd;
EHC_QTD *NextQtd;
LIST_ENTRY *Entry;
UINT32 AlterNext;
UINT8 Toggle;
UINTN Len;
UINT8 Pid;
EFI_PHYSICAL_ADDRESS PhyAddr;
ASSERT ((Urb != NULL) && (Urb->Qh != NULL));
@@ -389,7 +381,7 @@ EhcCreateQtds (
StatusQtd = NULL;
AlterNext = QTD_LINK (NULL, TRUE);
PhyAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Ehc->ShortReadStop, sizeof (EHC_QTD));
PhyAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Ehc->ShortReadStop, sizeof (EHC_QTD));
if (Ep->Direction == EfiUsbDataIn) {
AlterNext = QTD_LINK (PhyAddr, FALSE);
}
@@ -448,8 +440,8 @@ EhcCreateQtds (
while (Len < Urb->DataLen) {
Qtd = EhcCreateQtd (
Ehc,
(UINT8 *) Urb->Data + Len,
(UINT8 *) Urb->DataPhy + Len,
(UINT8 *)Urb->Data + Len,
(UINT8 *)Urb->DataPhy + Len,
Urb->DataLen - Len,
Pid,
Toggle,
@@ -467,7 +459,7 @@ EhcCreateQtds (
// Switch the Toggle bit if odd number of packets are included in the QTD.
//
if (((Qtd->DataLen + Ep->MaxPacket - 1) / Ep->MaxPacket) % 2) {
Toggle = (UINT8) (1 - Toggle);
Toggle = (UINT8)(1 - Toggle);
}
Len += Qtd->DataLen;
@@ -493,17 +485,17 @@ EhcCreateQtds (
break;
}
NextQtd = EFI_LIST_CONTAINER (Entry->ForwardLink, EHC_QTD, QtdList);
PhyAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, NextQtd, sizeof (EHC_QTD));
Qtd->QtdHw.NextQtd = QTD_LINK (PhyAddr, FALSE);
NextQtd = EFI_LIST_CONTAINER (Entry->ForwardLink, EHC_QTD, QtdList);
PhyAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, NextQtd, sizeof (EHC_QTD));
Qtd->QtdHw.NextQtd = QTD_LINK (PhyAddr, FALSE);
}
//
// Link the QTDs to the queue head
//
NextQtd = EFI_LIST_CONTAINER (Qh->Qtds.ForwardLink, EHC_QTD, QtdList);
PhyAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, NextQtd, sizeof (EHC_QTD));
Qh->QhHw.NextQtd = QTD_LINK (PhyAddr, FALSE);
NextQtd = EFI_LIST_CONTAINER (Qh->Qtds.ForwardLink, EHC_QTD, QtdList);
PhyAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, NextQtd, sizeof (EHC_QTD));
Qh->QhHw.NextQtd = QTD_LINK (PhyAddr, FALSE);
return EFI_SUCCESS;
ON_ERROR:
@@ -511,7 +503,6 @@ ON_ERROR:
return EFI_OUT_OF_RESOURCES;
}
/**
Create a new URB and its associated QTD.
@@ -535,30 +526,30 @@ ON_ERROR:
**/
URB *
EhcCreateUrb (
IN USB2_HC_DEV *Ehc,
IN UINT8 DevAddr,
IN UINT8 EpAddr,
IN UINT8 DevSpeed,
IN UINT8 Toggle,
IN UINTN MaxPacket,
IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Hub,
IN UINTN Type,
IN EFI_USB_DEVICE_REQUEST *Request,
IN VOID *Data,
IN UINTN DataLen,
IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
IN VOID *Context,
IN UINTN Interval
IN USB2_HC_DEV *Ehc,
IN UINT8 DevAddr,
IN UINT8 EpAddr,
IN UINT8 DevSpeed,
IN UINT8 Toggle,
IN UINTN MaxPacket,
IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Hub,
IN UINTN Type,
IN EFI_USB_DEVICE_REQUEST *Request,
IN VOID *Data,
IN UINTN DataLen,
IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
IN VOID *Context,
IN UINTN Interval
)
{
USB_ENDPOINT *Ep;
EFI_PHYSICAL_ADDRESS PhyAddr;
EFI_PCI_IO_PROTOCOL_OPERATION MapOp;
EFI_PCI_IO_PROTOCOL *PciIo;
EFI_STATUS Status;
UINTN Len;
URB *Urb;
VOID *Map;
USB_ENDPOINT *Ep;
EFI_PHYSICAL_ADDRESS PhyAddr;
EFI_PCI_IO_PROTOCOL_OPERATION MapOp;
EFI_PCI_IO_PROTOCOL *PciIo;
EFI_STATUS Status;
UINTN Len;
URB *Urb;
VOID *Map;
Urb = AllocateZeroPool (sizeof (URB));
@@ -566,38 +557,38 @@ EhcCreateUrb (
return NULL;
}
Urb->Signature = EHC_URB_SIG;
Urb->Signature = EHC_URB_SIG;
InitializeListHead (&Urb->UrbList);
Ep = &Urb->Ep;
Ep->DevAddr = DevAddr;
Ep->EpAddr = (UINT8) (EpAddr & 0x0F);
Ep->Direction = (((EpAddr & 0x80) != 0) ? EfiUsbDataIn : EfiUsbDataOut);
Ep->DevSpeed = DevSpeed;
Ep->MaxPacket = MaxPacket;
Ep = &Urb->Ep;
Ep->DevAddr = DevAddr;
Ep->EpAddr = (UINT8)(EpAddr & 0x0F);
Ep->Direction = (((EpAddr & 0x80) != 0) ? EfiUsbDataIn : EfiUsbDataOut);
Ep->DevSpeed = DevSpeed;
Ep->MaxPacket = MaxPacket;
Ep->HubAddr = 0;
Ep->HubPort = 0;
Ep->HubAddr = 0;
Ep->HubPort = 0;
if (DevSpeed != EFI_USB_SPEED_HIGH) {
ASSERT (Hub != NULL);
Ep->HubAddr = Hub->TranslatorHubAddress;
Ep->HubPort = Hub->TranslatorPortNumber;
Ep->HubAddr = Hub->TranslatorHubAddress;
Ep->HubPort = Hub->TranslatorPortNumber;
}
Ep->Toggle = Toggle;
Ep->Type = Type;
Ep->PollRate = EhcConvertPollRate (Interval);
Ep->Toggle = Toggle;
Ep->Type = Type;
Ep->PollRate = EhcConvertPollRate (Interval);
Urb->Request = Request;
Urb->Data = Data;
Urb->DataLen = DataLen;
Urb->Callback = Callback;
Urb->Context = Context;
Urb->Request = Request;
Urb->Data = Data;
Urb->DataLen = DataLen;
Urb->Callback = Callback;
Urb->Context = Context;
PciIo = Ehc->PciIo;
Urb->Qh = EhcCreateQh (Ehc, &Urb->Ep);
PciIo = Ehc->PciIo;
Urb->Qh = EhcCreateQh (Ehc, &Urb->Ep);
if (Urb->Qh == NULL) {
goto ON_ERROR;
@@ -607,20 +598,20 @@ EhcCreateUrb (
// Map the request and user data
//
if (Request != NULL) {
Len = sizeof (EFI_USB_DEVICE_REQUEST);
MapOp = EfiPciIoOperationBusMasterRead;
Status = PciIo->Map (PciIo, MapOp, Request, &Len, &PhyAddr, &Map);
Len = sizeof (EFI_USB_DEVICE_REQUEST);
MapOp = EfiPciIoOperationBusMasterRead;
Status = PciIo->Map (PciIo, MapOp, Request, &Len, &PhyAddr, &Map);
if (EFI_ERROR (Status) || (Len != sizeof (EFI_USB_DEVICE_REQUEST))) {
goto ON_ERROR;
}
Urb->RequestPhy = (VOID *) ((UINTN) PhyAddr);
Urb->RequestPhy = (VOID *)((UINTN)PhyAddr);
Urb->RequestMap = Map;
}
if (Data != NULL) {
Len = DataLen;
Len = DataLen;
if (Ep->Direction == EfiUsbDataIn) {
MapOp = EfiPciIoOperationBusMasterWrite;
@@ -628,14 +619,14 @@ EhcCreateUrb (
MapOp = EfiPciIoOperationBusMasterRead;
}
Status = PciIo->Map (PciIo, MapOp, Data, &Len, &PhyAddr, &Map);
Status = PciIo->Map (PciIo, MapOp, Data, &Len, &PhyAddr, &Map);
if (EFI_ERROR (Status) || (Len != DataLen)) {
goto ON_ERROR;
}
Urb->DataPhy = (VOID *) ((UINTN) PhyAddr);
Urb->DataMap = Map;
Urb->DataPhy = (VOID *)((UINTN)PhyAddr);
Urb->DataMap = Map;
}
Status = EhcCreateQtds (Ehc, Urb);

279
MdeModulePkg/Bus/Pci/EhciDxe/EhciUrb.h
View File

@@ -11,7 +11,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#ifndef _EFI_EHCI_URB_H_
#define _EFI_EHCI_URB_H_
typedef struct _EHC_QTD EHC_QTD;
typedef struct _EHC_QH EHC_QH;
typedef struct _URB URB;
@@ -24,51 +23,51 @@ typedef struct _URB URB;
#define EHC_INT_TRANSFER_SYNC 0x04
#define EHC_INT_TRANSFER_ASYNC 0x08
#define EHC_QTD_SIG SIGNATURE_32 ('U', 'S', 'B', 'T')
#define EHC_QH_SIG SIGNATURE_32 ('U', 'S', 'B', 'H')
#define EHC_URB_SIG SIGNATURE_32 ('U', 'S', 'B', 'R')
#define EHC_QTD_SIG SIGNATURE_32 ('U', 'S', 'B', 'T')
#define EHC_QH_SIG SIGNATURE_32 ('U', 'S', 'B', 'H')
#define EHC_URB_SIG SIGNATURE_32 ('U', 'S', 'B', 'R')
//
// Hardware related bit definitions
//
#define EHC_TYPE_ITD 0x00
#define EHC_TYPE_QH 0x02
#define EHC_TYPE_SITD 0x04
#define EHC_TYPE_FSTN 0x06
#define EHC_TYPE_ITD 0x00
#define EHC_TYPE_QH 0x02
#define EHC_TYPE_SITD 0x04
#define EHC_TYPE_FSTN 0x06
#define QH_NAK_RELOAD 3
#define QH_HSHBW_MULTI 1
#define QH_NAK_RELOAD 3
#define QH_HSHBW_MULTI 1
#define QTD_MAX_ERR 3
#define QTD_PID_OUTPUT 0x00
#define QTD_PID_INPUT 0x01
#define QTD_PID_SETUP 0x02
#define QTD_MAX_ERR 3
#define QTD_PID_OUTPUT 0x00
#define QTD_PID_INPUT 0x01
#define QTD_PID_SETUP 0x02
#define QTD_STAT_DO_OUT 0
#define QTD_STAT_DO_SS 0
#define QTD_STAT_DO_PING 0x01
#define QTD_STAT_DO_CS 0x02
#define QTD_STAT_TRANS_ERR 0x08
#define QTD_STAT_BABBLE_ERR 0x10
#define QTD_STAT_BUFF_ERR 0x20
#define QTD_STAT_HALTED 0x40
#define QTD_STAT_ACTIVE 0x80
#define QTD_STAT_ERR_MASK (QTD_STAT_TRANS_ERR | QTD_STAT_BABBLE_ERR | QTD_STAT_BUFF_ERR)
#define QTD_STAT_DO_OUT 0
#define QTD_STAT_DO_SS 0
#define QTD_STAT_DO_PING 0x01
#define QTD_STAT_DO_CS 0x02
#define QTD_STAT_TRANS_ERR 0x08
#define QTD_STAT_BABBLE_ERR 0x10
#define QTD_STAT_BUFF_ERR 0x20
#define QTD_STAT_HALTED 0x40
#define QTD_STAT_ACTIVE 0x80
#define QTD_STAT_ERR_MASK (QTD_STAT_TRANS_ERR | QTD_STAT_BABBLE_ERR | QTD_STAT_BUFF_ERR)
#define QTD_MAX_BUFFER 4
#define QTD_BUF_LEN 4096
#define QTD_BUF_MASK 0x0FFF
#define QTD_MAX_BUFFER 4
#define QTD_BUF_LEN 4096
#define QTD_BUF_MASK 0x0FFF
#define QH_MICROFRAME_0 0x01
#define QH_MICROFRAME_1 0x02
#define QH_MICROFRAME_2 0x04
#define QH_MICROFRAME_3 0x08
#define QH_MICROFRAME_4 0x10
#define QH_MICROFRAME_5 0x20
#define QH_MICROFRAME_6 0x40
#define QH_MICROFRAME_7 0x80
#define QH_MICROFRAME_0 0x01
#define QH_MICROFRAME_1 0x02
#define QH_MICROFRAME_2 0x04
#define QH_MICROFRAME_3 0x08
#define QH_MICROFRAME_4 0x10
#define QH_MICROFRAME_5 0x20
#define QH_MICROFRAME_6 0x40
#define QH_MICROFRAME_7 0x80
#define USB_ERR_SHORT_PACKET 0x200
#define USB_ERR_SHORT_PACKET 0x200
//
// Fill in the hardware link point: pass in a EHC_QH/QH_HW
@@ -77,7 +76,7 @@ typedef struct _URB URB;
#define QH_LINK(Addr, Type, Term) \
((UINT32) ((EHC_LOW_32BIT (Addr) & 0xFFFFFFE0) | (Type) | ((Term) ? 1 : 0)))
#define QTD_LINK(Addr, Term) QH_LINK((Addr), 0, (Term))
#define QTD_LINK(Addr, Term) QH_LINK((Addr), 0, (Term))
//
// The defination of EHCI hardware used data structure for
@@ -87,77 +86,76 @@ typedef struct _URB URB;
//
#pragma pack(1)
typedef struct {
UINT32 NextQtd;
UINT32 AltNext;
UINT32 NextQtd;
UINT32 AltNext;
UINT32 Status : 8;
UINT32 Pid : 2;
UINT32 ErrCnt : 2;
UINT32 CurPage : 3;
UINT32 Ioc : 1;
UINT32 TotalBytes : 15;
UINT32 DataToggle : 1;
UINT32 Status : 8;
UINT32 Pid : 2;
UINT32 ErrCnt : 2;
UINT32 CurPage : 3;
UINT32 Ioc : 1;
UINT32 TotalBytes : 15;
UINT32 DataToggle : 1;
UINT32 Page[5];
UINT32 PageHigh[5];
UINT32 Page[5];
UINT32 PageHigh[5];
} QTD_HW;
typedef struct {
UINT32 HorizonLink;
UINT32 HorizonLink;
//
// Endpoint capabilities/Characteristics DWord 1 and DWord 2
//
UINT32 DeviceAddr : 7;
UINT32 Inactive : 1;
UINT32 EpNum : 4;
UINT32 EpSpeed : 2;
UINT32 DtCtrl : 1;
UINT32 ReclaimHead : 1;
UINT32 MaxPacketLen : 11;
UINT32 CtrlEp : 1;
UINT32 NakReload : 4;
UINT32 DeviceAddr : 7;
UINT32 Inactive : 1;
UINT32 EpNum : 4;
UINT32 EpSpeed : 2;
UINT32 DtCtrl : 1;
UINT32 ReclaimHead : 1;
UINT32 MaxPacketLen : 11;
UINT32 CtrlEp : 1;
UINT32 NakReload : 4;
UINT32 SMask : 8;
UINT32 CMask : 8;
UINT32 HubAddr : 7;
UINT32 PortNum : 7;
UINT32 Multiplier : 2;
UINT32 SMask : 8;
UINT32 CMask : 8;
UINT32 HubAddr : 7;
UINT32 PortNum : 7;
UINT32 Multiplier : 2;
//
// Transaction execution overlay area
//
UINT32 CurQtd;
UINT32 NextQtd;
UINT32 AltQtd;
UINT32 CurQtd;
UINT32 NextQtd;
UINT32 AltQtd;
UINT32 Status : 8;
UINT32 Pid : 2;
UINT32 ErrCnt : 2;
UINT32 CurPage : 3;
UINT32 Ioc : 1;
UINT32 TotalBytes : 15;
UINT32 DataToggle : 1;
UINT32 Status : 8;
UINT32 Pid : 2;
UINT32 ErrCnt : 2;
UINT32 CurPage : 3;
UINT32 Ioc : 1;
UINT32 TotalBytes : 15;
UINT32 DataToggle : 1;
UINT32 Page[5];
UINT32 PageHigh[5];
UINT32 Page[5];
UINT32 PageHigh[5];
} QH_HW;
#pragma pack()
//
// Endpoint address and its capabilities
//
typedef struct _USB_ENDPOINT {
UINT8 DevAddr;
UINT8 EpAddr; // Endpoint address, no direction encoded in
EFI_USB_DATA_DIRECTION Direction;
UINT8 DevSpeed;
UINTN MaxPacket;
UINT8 HubAddr;
UINT8 HubPort;
UINT8 Toggle; // Data toggle, not used for control transfer
UINTN Type;
UINTN PollRate; // Polling interval used by EHCI
UINT8 DevAddr;
UINT8 EpAddr; // Endpoint address, no direction encoded in
EFI_USB_DATA_DIRECTION Direction;
UINT8 DevSpeed;
UINTN MaxPacket;
UINT8 HubAddr;
UINT8 HubPort;
UINT8 Toggle; // Data toggle, not used for control transfer
UINTN Type;
UINTN PollRate; // Polling interval used by EHCI
} USB_ENDPOINT;
//
@@ -165,11 +163,11 @@ typedef struct _USB_ENDPOINT {
// QTD generated from a URB. Don't add fields before QtdHw.
//
struct _EHC_QTD {
QTD_HW QtdHw;
UINT32 Signature;
LIST_ENTRY QtdList; // The list of QTDs to one end point
UINT8 *Data; // Buffer of the original data
UINTN DataLen; // Original amount of data in this QTD
QTD_HW QtdHw;
UINT32 Signature;
LIST_ENTRY QtdList; // The list of QTDs to one end point
UINT8 *Data; // Buffer of the original data
UINTN DataLen; // Original amount of data in this QTD
};
//
@@ -188,11 +186,11 @@ struct _EHC_QTD {
// as the reclamation header. New transfer is inserted after this QH.
//
struct _EHC_QH {
QH_HW QhHw;
UINT32 Signature;
EHC_QH *NextQh; // The queue head pointed to by horizontal link
LIST_ENTRY Qtds; // The list of QTDs to this queue head
UINTN Interval;
QH_HW QhHw;
UINT32 Signature;
EHC_QH *NextQh; // The queue head pointed to by horizontal link
LIST_ENTRY Qtds; // The list of QTDs to this queue head
UINTN Interval;
};
//
@@ -200,38 +198,36 @@ struct _EHC_QH {
// usb requests.
//
struct _URB {
UINT32 Signature;
LIST_ENTRY UrbList;
UINT32 Signature;
LIST_ENTRY UrbList;
//
// Transaction information
//
USB_ENDPOINT Ep;
EFI_USB_DEVICE_REQUEST *Request; // Control transfer only
VOID *RequestPhy; // Address of the mapped request
VOID *RequestMap;
VOID *Data;
UINTN DataLen;
VOID *DataPhy; // Address of the mapped user data
VOID *DataMap;
EFI_ASYNC_USB_TRANSFER_CALLBACK Callback;
VOID *Context;
USB_ENDPOINT Ep;
EFI_USB_DEVICE_REQUEST *Request; // Control transfer only
VOID *RequestPhy; // Address of the mapped request
VOID *RequestMap;
VOID *Data;
UINTN DataLen;
VOID *DataPhy; // Address of the mapped user data
VOID *DataMap;
EFI_ASYNC_USB_TRANSFER_CALLBACK Callback;
VOID *Context;
//
// Schedule data
//
EHC_QH *Qh;
EHC_QH *Qh;
//
// Transaction result
//
UINT32 Result;
UINTN Completed; // completed data length
UINT8 DataToggle;
UINT32 Result;
UINTN Completed; // completed data length
UINT8 DataToggle;
};
/**
Create a single QTD to hold the data.
@@ -248,17 +244,15 @@ struct _URB {
**/
EHC_QTD *
EhcCreateQtd (
IN USB2_HC_DEV *Ehc,
IN UINT8 *Data,
IN UINT8 *DataPhy,
IN UINTN DataLen,
IN UINT8 PktId,
IN UINT8 Toggle,
IN UINTN MaxPacket
IN USB2_HC_DEV *Ehc,
IN UINT8 *Data,
IN UINT8 *DataPhy,
IN UINTN DataLen,
IN UINT8 PktId,
IN UINT8 Toggle,
IN UINTN MaxPacket
);
/**
Allocate and initialize a EHCI queue head.
@@ -270,11 +264,10 @@ EhcCreateQtd (
**/
EHC_QH *
EhcCreateQh (
IN USB2_HC_DEV *Ehci,
IN USB_ENDPOINT *Ep
IN USB2_HC_DEV *Ehci,
IN USB_ENDPOINT *Ep
);
/**
Free an allocated URB. It is possible for it to be partially inited.
@@ -284,11 +277,10 @@ EhcCreateQh (
**/
VOID
EhcFreeUrb (
IN USB2_HC_DEV *Ehc,
IN URB *Urb
IN USB2_HC_DEV *Ehc,
IN URB *Urb
);
/**
Create a new URB and its associated QTD.
@@ -312,19 +304,20 @@ EhcFreeUrb (
**/
URB *
EhcCreateUrb (
IN USB2_HC_DEV *Ehc,
IN UINT8 DevAddr,
IN UINT8 EpAddr,
IN UINT8 DevSpeed,
IN UINT8 Toggle,
IN UINTN MaxPacket,
IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Hub,
IN UINTN Type,
IN EFI_USB_DEVICE_REQUEST *Request,
IN VOID *Data,
IN UINTN DataLen,
IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
IN VOID *Context,
IN UINTN Interval
IN USB2_HC_DEV *Ehc,
IN UINT8 DevAddr,
IN UINT8 EpAddr,
IN UINT8 DevSpeed,
IN UINT8 Toggle,
IN UINTN MaxPacket,
IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Hub,
IN UINTN Type,
IN EFI_USB_DEVICE_REQUEST *Request,
IN VOID *Data,
IN UINTN DataLen,
IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
IN VOID *Context,
IN UINTN Interval
);
#endif

172
MdeModulePkg/Bus/Pci/EhciDxe/UsbHcMem.c
View File

@@ -7,10 +7,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include "Ehci.h"
/**
Allocate a block of memory to be used by the buffer pool.
@@ -22,17 +20,17 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
USBHC_MEM_BLOCK *
UsbHcAllocMemBlock (
IN USBHC_MEM_POOL *Pool,
IN UINTN Pages
IN USBHC_MEM_POOL *Pool,
IN UINTN Pages
)
{
USBHC_MEM_BLOCK *Block;
EFI_PCI_IO_PROTOCOL *PciIo;
VOID *BufHost;
VOID *Mapping;
EFI_PHYSICAL_ADDRESS MappedAddr;
UINTN Bytes;
EFI_STATUS Status;
USBHC_MEM_BLOCK *Block;
EFI_PCI_IO_PROTOCOL *PciIo;
VOID *BufHost;
VOID *Mapping;
EFI_PHYSICAL_ADDRESS MappedAddr;
UINTN Bytes;
EFI_STATUS Status;
PciIo = Pool->PciIo;
@@ -47,9 +45,9 @@ UsbHcAllocMemBlock (
//
ASSERT (USBHC_MEM_UNIT * 8 <= EFI_PAGE_SIZE);
Block->BufLen = EFI_PAGES_TO_SIZE (Pages);
Block->BitsLen = Block->BufLen / (USBHC_MEM_UNIT * 8);
Block->Bits = AllocateZeroPool (Block->BitsLen);
Block->BufLen = EFI_PAGES_TO_SIZE (Pages);
Block->BitsLen = Block->BufLen / (USBHC_MEM_UNIT * 8);
Block->Bits = AllocateZeroPool (Block->BitsLen);
if (Block->Bits == NULL) {
gBS->FreePool (Block);
@@ -73,7 +71,7 @@ UsbHcAllocMemBlock (
goto FREE_BITARRAY;
}
Bytes = EFI_PAGES_TO_SIZE (Pages);
Bytes = EFI_PAGES_TO_SIZE (Pages);
Status = PciIo->Map (
PciIo,
EfiPciIoOperationBusMasterCommonBuffer,
@@ -96,9 +94,9 @@ UsbHcAllocMemBlock (
goto FREE_BUFFER;
}
Block->BufHost = BufHost;
Block->Buf = (UINT8 *) ((UINTN) MappedAddr);
Block->Mapping = Mapping;
Block->BufHost = BufHost;
Block->Buf = (UINT8 *)((UINTN)MappedAddr);
Block->Mapping = Mapping;
return Block;
@@ -111,7 +109,6 @@ FREE_BITARRAY:
return NULL;
}
/**
Free the memory block from the memory pool.
@@ -121,11 +118,11 @@ FREE_BITARRAY:
**/
VOID
UsbHcFreeMemBlock (
IN USBHC_MEM_POOL *Pool,
IN USBHC_MEM_BLOCK *Block
IN USBHC_MEM_POOL *Pool,
IN USBHC_MEM_BLOCK *Block
)
{
EFI_PCI_IO_PROTOCOL *PciIo;
EFI_PCI_IO_PROTOCOL *PciIo;
ASSERT ((Pool != NULL) && (Block != NULL));
@@ -141,7 +138,6 @@ UsbHcFreeMemBlock (
gBS->FreePool (Block);
}
/**
Alloc some memory from the block.
@@ -154,22 +150,22 @@ UsbHcFreeMemBlock (
**/
VOID *
UsbHcAllocMemFromBlock (
IN USBHC_MEM_BLOCK *Block,
IN UINTN Units
IN USBHC_MEM_BLOCK *Block,
IN UINTN Units
)
{
UINTN Byte;
UINT8 Bit;
UINTN StartByte;
UINT8 StartBit;
UINTN Available;
UINTN Count;
UINTN Byte;
UINT8 Bit;
UINTN StartByte;
UINT8 StartBit;
UINTN Available;
UINTN Count;
ASSERT ((Block != 0) && (Units != 0));
StartByte = 0;
StartBit = 0;
Available = 0;
StartByte = 0;
StartBit = 0;
Available = 0;
for (Byte = 0, Bit = 0; Byte < Block->BitsLen;) {
//
@@ -185,13 +181,12 @@ UsbHcAllocMemFromBlock (
}
NEXT_BIT (Byte, Bit);
} else {
NEXT_BIT (Byte, Bit);
Available = 0;
StartByte = Byte;
StartBit = Bit;
Available = 0;
StartByte = Byte;
StartBit = Bit;
}
}
@@ -202,13 +197,13 @@ UsbHcAllocMemFromBlock (
//
// Mark the memory as allocated
//
Byte = StartByte;
Bit = StartBit;
Byte = StartByte;
Bit = StartBit;
for (Count = 0; Count < Units; Count++) {
ASSERT (!USB_HC_BIT_IS_SET (Block->Bits[Byte], Bit));
Block->Bits[Byte] = (UINT8) (Block->Bits[Byte] | USB_HC_BIT (Bit));
Block->Bits[Byte] = (UINT8)(Block->Bits[Byte] | USB_HC_BIT (Bit));
NEXT_BIT (Byte, Bit);
}
@@ -226,16 +221,16 @@ UsbHcAllocMemFromBlock (
**/
EFI_PHYSICAL_ADDRESS
UsbHcGetPciAddressForHostMem (
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
)
{
USBHC_MEM_BLOCK *Head;
USBHC_MEM_BLOCK *Block;
UINTN AllocSize;
EFI_PHYSICAL_ADDRESS PhyAddr;
UINTN Offset;
USBHC_MEM_BLOCK *Head;
USBHC_MEM_BLOCK *Block;
UINTN AllocSize;
EFI_PHYSICAL_ADDRESS PhyAddr;
UINTN Offset;
Head = Pool->Head;
AllocSize = USBHC_MEM_ROUND (Size);
@@ -249,7 +244,7 @@ UsbHcGetPciAddressForHostMem (
// scan the memory block list for the memory block that
// completely contains the allocated memory.
//
if ((Block->BufHost <= (UINT8 *) Mem) && (((UINT8 *) Mem + AllocSize) <= (Block->BufHost + Block->BufLen))) {
if ((Block->BufHost <= (UINT8 *)Mem) && (((UINT8 *)Mem + AllocSize) <= (Block->BufHost + Block->BufLen))) {
break;
}
}
@@ -258,12 +253,11 @@ UsbHcGetPciAddressForHostMem (
//
// calculate the pci memory address for host memory address.
//
Offset = (UINT8 *)Mem - Block->BufHost;
PhyAddr = (EFI_PHYSICAL_ADDRESS)(UINTN) (Block->Buf + Offset);
Offset = (UINT8 *)Mem - Block->BufHost;
PhyAddr = (EFI_PHYSICAL_ADDRESS)(UINTN)(Block->Buf + Offset);
return PhyAddr;
}
/**
Insert the memory block to the pool's list of the blocks.
@@ -273,8 +267,8 @@ UsbHcGetPciAddressForHostMem (
**/
VOID
UsbHcInsertMemBlockToPool (
IN USBHC_MEM_BLOCK *Head,
IN USBHC_MEM_BLOCK *Block
IN USBHC_MEM_BLOCK *Head,
IN USBHC_MEM_BLOCK *Block
)
{
ASSERT ((Head != NULL) && (Block != NULL));
@@ -282,7 +276,6 @@ UsbHcInsertMemBlockToPool (
Head->Next = Block;
}
/**
Is the memory block empty?
@@ -294,10 +287,10 @@ UsbHcInsertMemBlockToPool (
**/
BOOLEAN
UsbHcIsMemBlockEmpty (
IN USBHC_MEM_BLOCK *Block
IN USBHC_MEM_BLOCK *Block
)
{
UINTN Index;
UINTN Index;
for (Index = 0; Index < Block->BitsLen; Index++) {
if (Block->Bits[Index] != 0) {
@@ -308,7 +301,6 @@ UsbHcIsMemBlockEmpty (
return TRUE;
}
/**
Unlink the memory block from the pool's list.
@@ -318,11 +310,11 @@ UsbHcIsMemBlockEmpty (
**/
VOID
UsbHcUnlinkMemBlock (
IN USBHC_MEM_BLOCK *Head,
IN USBHC_MEM_BLOCK *BlockToUnlink
IN USBHC_MEM_BLOCK *Head,
IN USBHC_MEM_BLOCK *BlockToUnlink
)
{
USBHC_MEM_BLOCK *Block;
USBHC_MEM_BLOCK *Block;
ASSERT ((Head != NULL) && (BlockToUnlink != NULL));
@@ -335,7 +327,6 @@ UsbHcUnlinkMemBlock (
}
}
/**
Initialize the memory management pool for the host controller.
@@ -355,7 +346,7 @@ UsbHcInitMemPool (
IN UINT32 Which4G
)
{
USBHC_MEM_POOL *Pool;
USBHC_MEM_POOL *Pool;
Pool = AllocatePool (sizeof (USBHC_MEM_POOL));
@@ -376,7 +367,6 @@ UsbHcInitMemPool (
return Pool;
}
/**
Release the memory management pool.
@@ -388,10 +378,10 @@ UsbHcInitMemPool (
**/
EFI_STATUS
UsbHcFreeMemPool (
IN USBHC_MEM_POOL *Pool
IN USBHC_MEM_POOL *Pool
)
{
USBHC_MEM_BLOCK *Block;
USBHC_MEM_BLOCK *Block;
ASSERT (Pool->Head != NULL);
@@ -410,7 +400,6 @@ UsbHcFreeMemPool (
return EFI_SUCCESS;
}
/**
Allocate some memory from the host controller's memory pool
which can be used to communicate with host controller.
@@ -423,16 +412,16 @@ UsbHcFreeMemPool (
**/
VOID *
UsbHcAllocateMem (
IN USBHC_MEM_POOL *Pool,
IN UINTN Size
IN USBHC_MEM_POOL *Pool,
IN UINTN Size
)
{
USBHC_MEM_BLOCK *Head;
USBHC_MEM_BLOCK *Block;
USBHC_MEM_BLOCK *NewBlock;
VOID *Mem;
UINTN AllocSize;
UINTN Pages;
USBHC_MEM_BLOCK *Head;
USBHC_MEM_BLOCK *Block;
USBHC_MEM_BLOCK *NewBlock;
VOID *Mem;
UINTN AllocSize;
UINTN Pages;
Mem = NULL;
AllocSize = USBHC_MEM_ROUND (Size);
@@ -487,7 +476,6 @@ UsbHcAllocateMem (
return Mem;
}
/**
Free the allocated memory back to the memory pool.
@@ -498,22 +486,22 @@ UsbHcAllocateMem (
**/
VOID
UsbHcFreeMem (
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
)
{
USBHC_MEM_BLOCK *Head;
USBHC_MEM_BLOCK *Block;
UINT8 *ToFree;
UINTN AllocSize;
UINTN Byte;
UINTN Bit;
UINTN Count;
USBHC_MEM_BLOCK *Head;
USBHC_MEM_BLOCK *Block;
UINT8 *ToFree;
UINTN AllocSize;
UINTN Byte;
UINTN Bit;
UINTN Count;
Head = Pool->Head;
AllocSize = USBHC_MEM_ROUND (Size);
ToFree = (UINT8 *) Mem;
ToFree = (UINT8 *)Mem;
for (Block = Head; Block != NULL; Block = Block->Next) {
//
@@ -524,8 +512,8 @@ UsbHcFreeMem (
//
// compute the start byte and bit in the bit array
//
Byte = ((ToFree - Block->BufHost) / USBHC_MEM_UNIT) / 8;
Bit = ((ToFree - Block->BufHost) / USBHC_MEM_UNIT) % 8;
Byte = ((ToFree - Block->BufHost) / USBHC_MEM_UNIT) / 8;
Bit = ((ToFree - Block->BufHost) / USBHC_MEM_UNIT) % 8;
//
// reset associated bits in bit array
@@ -533,7 +521,7 @@ UsbHcFreeMem (
for (Count = 0; Count < (AllocSize / USBHC_MEM_UNIT); Count++) {
ASSERT (USB_HC_BIT_IS_SET (Block->Bits[Byte], Bit));
Block->Bits[Byte] = (UINT8) (Block->Bits[Byte] ^ USB_HC_BIT (Bit));
Block->Bits[Byte] = (UINT8)(Block->Bits[Byte] ^ USB_HC_BIT (Bit));
NEXT_BIT (Byte, Bit);
}
@@ -556,5 +544,5 @@ UsbHcFreeMem (
UsbHcFreeMemBlock (Pool, Block);
}
return ;
return;
}

49
MdeModulePkg/Bus/Pci/EhciDxe/UsbHcMem.h
View File

@@ -10,7 +10,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#ifndef _EFI_EHCI_MEM_H_
#define _EFI_EHCI_MEM_H_
#define USB_HC_BIT(a) ((UINTN)(1 << (a)))
#define USB_HC_BIT(a) ((UINTN)(1 << (a)))
#define USB_HC_BIT_IS_SET(Data, Bit) \
((BOOLEAN)(((Data) & USB_HC_BIT(Bit)) == USB_HC_BIT(Bit)))
@@ -20,13 +20,13 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
typedef struct _USBHC_MEM_BLOCK USBHC_MEM_BLOCK;
struct _USBHC_MEM_BLOCK {
UINT8 *Bits; // Bit array to record which unit is allocated
UINTN BitsLen;
UINT8 *Buf;
UINT8 *BufHost;
UINTN BufLen; // Memory size in bytes
VOID *Mapping;
USBHC_MEM_BLOCK *Next;
UINT8 *Bits; // Bit array to record which unit is allocated
UINTN BitsLen;
UINT8 *Buf;
UINT8 *BufHost;
UINTN BufLen; // Memory size in bytes
VOID *Mapping;
USBHC_MEM_BLOCK *Next;
};
//
@@ -35,16 +35,16 @@ struct _USBHC_MEM_BLOCK {
// data to be on the same 4G memory.
//
typedef struct _USBHC_MEM_POOL {
EFI_PCI_IO_PROTOCOL *PciIo;
BOOLEAN Check4G;
UINT32 Which4G;
USBHC_MEM_BLOCK *Head;
EFI_PCI_IO_PROTOCOL *PciIo;
BOOLEAN Check4G;
UINT32 Which4G;
USBHC_MEM_BLOCK *Head;
} USBHC_MEM_POOL;
//
// Memory allocation unit, must be 2^n, n>4
//
#define USBHC_MEM_UNIT 64
#define USBHC_MEM_UNIT 64
#define USBHC_MEM_UNIT_MASK (USBHC_MEM_UNIT - 1)
#define USBHC_MEM_DEFAULT_PAGES 16
@@ -63,8 +63,6 @@ typedef struct _USBHC_MEM_POOL {
} \
} while (0)
/**
Initialize the memory management pool for the host controller.
@@ -84,7 +82,6 @@ UsbHcInitMemPool (
IN UINT32 Which4G
);
/**
Release the memory management pool.
@@ -96,10 +93,9 @@ UsbHcInitMemPool (
**/
EFI_STATUS
UsbHcFreeMemPool (
IN USBHC_MEM_POOL *Pool
IN USBHC_MEM_POOL *Pool
);
/**
Allocate some memory from the host controller's memory pool
which can be used to communicate with host controller.
@@ -112,11 +108,10 @@ UsbHcFreeMemPool (
**/
VOID *
UsbHcAllocateMem (
IN USBHC_MEM_POOL *Pool,
IN UINTN Size
IN USBHC_MEM_POOL *Pool,
IN UINTN Size
);
/**
Free the allocated memory back to the memory pool.
@@ -127,9 +122,9 @@ UsbHcAllocateMem (
**/
VOID
UsbHcFreeMem (
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
);
/**
@@ -143,9 +138,9 @@ UsbHcFreeMem (
**/
EFI_PHYSICAL_ADDRESS
UsbHcGetPciAddressForHostMem (
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
);
#endif

89
MdeModulePkg/Bus/Pci/EhciPei/DmaMem.c
View File

@@ -39,8 +39,8 @@ IoMmuMap (
OUT VOID **Mapping
)
{
EFI_STATUS Status;
UINT64 Attribute;
EFI_STATUS Status;
UINT64 Attribute;
if (IoMmu != NULL) {
Status = IoMmu->Map (
@@ -54,23 +54,25 @@ IoMmuMap (
if (EFI_ERROR (Status)) {
return EFI_OUT_OF_RESOURCES;
}
switch (Operation) {
case EdkiiIoMmuOperationBusMasterRead:
case EdkiiIoMmuOperationBusMasterRead64:
Attribute = EDKII_IOMMU_ACCESS_READ;
break;
case EdkiiIoMmuOperationBusMasterWrite:
case EdkiiIoMmuOperationBusMasterWrite64:
Attribute = EDKII_IOMMU_ACCESS_WRITE;
break;
case EdkiiIoMmuOperationBusMasterCommonBuffer:
case EdkiiIoMmuOperationBusMasterCommonBuffer64:
Attribute = EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE;
break;
default:
ASSERT(FALSE);
return EFI_INVALID_PARAMETER;
case EdkiiIoMmuOperationBusMasterRead:
case EdkiiIoMmuOperationBusMasterRead64:
Attribute = EDKII_IOMMU_ACCESS_READ;
break;
case EdkiiIoMmuOperationBusMasterWrite:
case EdkiiIoMmuOperationBusMasterWrite64:
Attribute = EDKII_IOMMU_ACCESS_WRITE;
break;
case EdkiiIoMmuOperationBusMasterCommonBuffer:
case EdkiiIoMmuOperationBusMasterCommonBuffer64:
Attribute = EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE;
break;
default:
ASSERT (FALSE);
return EFI_INVALID_PARAMETER;
}
Status = IoMmu->SetAttribute (
IoMmu,
*Mapping,
@@ -82,10 +84,11 @@ IoMmuMap (
return Status;
}
} else {
*DeviceAddress = (EFI_PHYSICAL_ADDRESS) (UINTN) HostAddress;
*Mapping = NULL;
Status = EFI_SUCCESS;
*DeviceAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)HostAddress;
*Mapping = NULL;
Status = EFI_SUCCESS;
}
return Status;
}
@@ -98,8 +101,8 @@ IoMmuMap (
**/
VOID
IoMmuUnmap (
IN EDKII_IOMMU_PPI *IoMmu,
IN VOID *Mapping
IN EDKII_IOMMU_PPI *IoMmu,
IN VOID *Mapping
)
{
if (IoMmu != NULL) {
@@ -140,9 +143,9 @@ IoMmuAllocateBuffer (
UINTN NumberOfBytes;
EFI_PHYSICAL_ADDRESS HostPhyAddress;
*HostAddress = NULL;
*HostAddress = NULL;
*DeviceAddress = 0;
*Mapping = NULL;
*Mapping = NULL;
if (IoMmu != NULL) {
Status = IoMmu->AllocateBuffer (
@@ -157,19 +160,20 @@ IoMmuAllocateBuffer (
}
NumberOfBytes = EFI_PAGES_TO_SIZE (Pages);
Status = IoMmu->Map (
IoMmu,
EdkiiIoMmuOperationBusMasterCommonBuffer,
*HostAddress,
&NumberOfBytes,
DeviceAddress,
Mapping
);
Status = IoMmu->Map (
IoMmu,
EdkiiIoMmuOperationBusMasterCommonBuffer,
*HostAddress,
&NumberOfBytes,
DeviceAddress,
Mapping
);
if (EFI_ERROR (Status)) {
IoMmu->FreeBuffer (IoMmu, Pages, *HostAddress);
*HostAddress = NULL;
return EFI_OUT_OF_RESOURCES;
}
Status = IoMmu->SetAttribute (
IoMmu,
*Mapping,
@@ -178,7 +182,7 @@ IoMmuAllocateBuffer (
if (EFI_ERROR (Status)) {
IoMmu->Unmap (IoMmu, *Mapping);
IoMmu->FreeBuffer (IoMmu, Pages, *HostAddress);
*Mapping = NULL;
*Mapping = NULL;
*HostAddress = NULL;
return Status;
}
@@ -191,10 +195,12 @@ IoMmuAllocateBuffer (
if (EFI_ERROR (Status)) {
return EFI_OUT_OF_RESOURCES;
}
*HostAddress = (VOID *) (UINTN) HostPhyAddress;
*HostAddress = (VOID *)(UINTN)HostPhyAddress;
*DeviceAddress = HostPhyAddress;
*Mapping = NULL;
*Mapping = NULL;
}
return Status;
}
@@ -209,10 +215,10 @@ IoMmuAllocateBuffer (
**/
VOID
IoMmuFreeBuffer (
IN EDKII_IOMMU_PPI *IoMmu,
IN UINTN Pages,
IN VOID *HostAddress,
IN VOID *Mapping
IN EDKII_IOMMU_PPI *IoMmu,
IN UINTN Pages,
IN VOID *HostAddress,
IN VOID *Mapping
)
{
if (IoMmu != NULL) {
@@ -230,14 +236,13 @@ IoMmuFreeBuffer (
**/
VOID
IoMmuInit (
OUT EDKII_IOMMU_PPI **IoMmu
OUT EDKII_IOMMU_PPI **IoMmu
)
{
PeiServicesLocatePpi (
&gEdkiiIoMmuPpiGuid,
0,
NULL,
(VOID **) IoMmu
(VOID **)IoMmu
);
}

592
MdeModulePkg/Bus/Pci/EhciPei/EhcPeim.c
View File

@@ -15,19 +15,19 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
// to the UEFI protocol's port state (change).
//
USB_PORT_STATE_MAP mUsbPortStateMap[] = {
{PORTSC_CONN, USB_PORT_STAT_CONNECTION},
{PORTSC_ENABLED, USB_PORT_STAT_ENABLE},
{PORTSC_SUSPEND, USB_PORT_STAT_SUSPEND},
{PORTSC_OVERCUR, USB_PORT_STAT_OVERCURRENT},
{PORTSC_RESET, USB_PORT_STAT_RESET},
{PORTSC_POWER, USB_PORT_STAT_POWER},
{PORTSC_OWNER, USB_PORT_STAT_OWNER}
{ PORTSC_CONN, USB_PORT_STAT_CONNECTION },
{ PORTSC_ENABLED, USB_PORT_STAT_ENABLE },
{ PORTSC_SUSPEND, USB_PORT_STAT_SUSPEND },
{ PORTSC_OVERCUR, USB_PORT_STAT_OVERCURRENT },
{ PORTSC_RESET, USB_PORT_STAT_RESET },
{ PORTSC_POWER, USB_PORT_STAT_POWER },
{ PORTSC_OWNER, USB_PORT_STAT_OWNER }
};
USB_PORT_STATE_MAP mUsbPortChangeMap[] = {
{PORTSC_CONN_CHANGE, USB_PORT_STAT_C_CONNECTION},
{PORTSC_ENABLE_CHANGE, USB_PORT_STAT_C_ENABLE},
{PORTSC_OVERCUR_CHANGE, USB_PORT_STAT_C_OVERCURRENT}
{ PORTSC_CONN_CHANGE, USB_PORT_STAT_C_CONNECTION },
{ PORTSC_ENABLE_CHANGE, USB_PORT_STAT_C_ENABLE },
{ PORTSC_OVERCUR_CHANGE, USB_PORT_STAT_C_OVERCURRENT }
};
/**
@@ -41,11 +41,11 @@ USB_PORT_STATE_MAP mUsbPortChangeMap[] = {
**/
UINT32
EhcReadOpReg (
IN PEI_USB2_HC_DEV *Ehc,
IN UINT32 Offset
IN PEI_USB2_HC_DEV *Ehc,
IN UINT32 Offset
)
{
UINT32 Data;
UINT32 Data;
ASSERT (Ehc->CapLen != 0);
@@ -64,16 +64,14 @@ EhcReadOpReg (
**/
VOID
EhcWriteOpReg (
IN PEI_USB2_HC_DEV *Ehc,
IN UINT32 Offset,
IN UINT32 Data
IN PEI_USB2_HC_DEV *Ehc,
IN UINT32 Offset,
IN UINT32 Data
)
{
ASSERT (Ehc->CapLen != 0);
MmioWrite32(Ehc->UsbHostControllerBaseAddress + Ehc->CapLen + Offset, Data);
MmioWrite32 (Ehc->UsbHostControllerBaseAddress + Ehc->CapLen + Offset, Data);
}
/**
@@ -86,12 +84,12 @@ EhcWriteOpReg (
**/
VOID
EhcSetOpRegBit (
IN PEI_USB2_HC_DEV *Ehc,
IN UINT32 Offset,
IN UINT32 Bit
IN PEI_USB2_HC_DEV *Ehc,
IN UINT32 Offset,
IN UINT32 Bit
)
{
UINT32 Data;
UINT32 Data;
Data = EhcReadOpReg (Ehc, Offset);
Data |= Bit;
@@ -108,12 +106,12 @@ EhcSetOpRegBit (
**/
VOID
EhcClearOpRegBit (
IN PEI_USB2_HC_DEV *Ehc,
IN UINT32 Offset,
IN UINT32 Bit
IN PEI_USB2_HC_DEV *Ehc,
IN UINT32 Offset,
IN UINT32 Bit
)
{
UINT32 Data;
UINT32 Data;
Data = EhcReadOpReg (Ehc, Offset);
Data &= ~Bit;
@@ -136,14 +134,14 @@ EhcClearOpRegBit (
**/
EFI_STATUS
EhcWaitOpRegBit (
IN PEI_USB2_HC_DEV *Ehc,
IN UINT32 Offset,
IN UINT32 Bit,
IN BOOLEAN WaitToSet,
IN UINT32 Timeout
IN PEI_USB2_HC_DEV *Ehc,
IN UINT32 Offset,
IN UINT32 Bit,
IN BOOLEAN WaitToSet,
IN UINT32 Timeout
)
{
UINT32 Index;
UINT32 Index;
for (Index = 0; Index < Timeout / EHC_SYNC_POLL_INTERVAL + 1; Index++) {
if (EHC_REG_BIT_IS_SET (Ehc, Offset, Bit) == WaitToSet) {
@@ -167,13 +165,13 @@ EhcWaitOpRegBit (
**/
UINT32
EhcReadCapRegister (
IN PEI_USB2_HC_DEV *Ehc,
IN UINT32 Offset
IN PEI_USB2_HC_DEV *Ehc,
IN UINT32 Offset
)
{
UINT32 Data;
UINT32 Data;
Data = MmioRead32(Ehc->UsbHostControllerBaseAddress + Offset);
Data = MmioRead32 (Ehc->UsbHostControllerBaseAddress + Offset);
return Data;
}
@@ -191,12 +189,12 @@ EhcReadCapRegister (
**/
EFI_STATUS
EhcSetAndWaitDoorBell (
IN PEI_USB2_HC_DEV *Ehc,
IN UINT32 Timeout
IN PEI_USB2_HC_DEV *Ehc,
IN UINT32 Timeout
)
{
EFI_STATUS Status;
UINT32 Data;
EFI_STATUS Status;
UINT32 Data;
EhcSetOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_IAAD);
@@ -224,7 +222,7 @@ EhcSetAndWaitDoorBell (
**/
VOID
EhcAckAllInterrupt (
IN PEI_USB2_HC_DEV *Ehc
IN PEI_USB2_HC_DEV *Ehc
)
{
EhcWriteOpReg (Ehc, EHC_USBSTS_OFFSET, USBSTS_INTACK_MASK);
@@ -243,11 +241,11 @@ EhcAckAllInterrupt (
**/
EFI_STATUS
EhcEnablePeriodSchd (
IN PEI_USB2_HC_DEV *Ehc,
IN UINT32 Timeout
IN PEI_USB2_HC_DEV *Ehc,
IN UINT32 Timeout
)
{
EFI_STATUS Status;
EFI_STATUS Status;
EhcSetOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_ENABLE_PERIOD);
@@ -267,11 +265,11 @@ EhcEnablePeriodSchd (
**/
EFI_STATUS
EhcEnableAsyncSchd (
IN PEI_USB2_HC_DEV *Ehc,
IN UINT32 Timeout
IN PEI_USB2_HC_DEV *Ehc,
IN UINT32 Timeout
)
{
EFI_STATUS Status;
EFI_STATUS Status;
EhcSetOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_ENABLE_ASYNC);
@@ -290,7 +288,7 @@ EhcEnableAsyncSchd (
**/
BOOLEAN
EhcIsHalt (
IN PEI_USB2_HC_DEV *Ehc
IN PEI_USB2_HC_DEV *Ehc
)
{
return EHC_REG_BIT_IS_SET (Ehc, EHC_USBSTS_OFFSET, USBSTS_HALT);
@@ -307,7 +305,7 @@ EhcIsHalt (
**/
BOOLEAN
EhcIsSysError (
IN PEI_USB2_HC_DEV *Ehc
IN PEI_USB2_HC_DEV *Ehc
)
{
return EHC_REG_BIT_IS_SET (Ehc, EHC_USBSTS_OFFSET, USBSTS_SYS_ERROR);
@@ -325,11 +323,11 @@ EhcIsSysError (
**/
EFI_STATUS
EhcResetHC (
IN PEI_USB2_HC_DEV *Ehc,
IN UINT32 Timeout
IN PEI_USB2_HC_DEV *Ehc,
IN UINT32 Timeout
)
{
EFI_STATUS Status;
EFI_STATUS Status;
//
// Host can only be reset when it is halt. If not so, halt it
@@ -359,11 +357,11 @@ EhcResetHC (
**/
EFI_STATUS
EhcHaltHC (
IN PEI_USB2_HC_DEV *Ehc,
IN UINT32 Timeout
IN PEI_USB2_HC_DEV *Ehc,
IN UINT32 Timeout
)
{
EFI_STATUS Status;
EFI_STATUS Status;
EhcClearOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_RUN);
Status = EhcWaitOpRegBit (Ehc, EHC_USBSTS_OFFSET, USBSTS_HALT, TRUE, Timeout);
@@ -382,11 +380,11 @@ EhcHaltHC (
**/
EFI_STATUS
EhcRunHC (
IN PEI_USB2_HC_DEV *Ehc,
IN UINT32 Timeout
IN PEI_USB2_HC_DEV *Ehc,
IN UINT32 Timeout
)
{
EFI_STATUS Status;
EFI_STATUS Status;
EhcSetOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_RUN);
Status = EhcWaitOpRegBit (Ehc, EHC_USBSTS_OFFSET, USBSTS_HALT, FALSE, Timeout);
@@ -401,12 +399,12 @@ EhcRunHC (
**/
VOID
EhcPowerOnAllPorts (
IN PEI_USB2_HC_DEV *Ehc
IN PEI_USB2_HC_DEV *Ehc
)
{
UINT8 PortNumber;
UINT8 Index;
UINT32 RegVal;
UINT8 PortNumber;
UINT8 Index;
UINT32 RegVal;
PortNumber = (UINT8)(Ehc->HcStructParams & HCSP_NPORTS);
for (Index = 0; Index < PortNumber; Index++) {
@@ -414,7 +412,7 @@ EhcPowerOnAllPorts (
// Do not clear port status bits on initialization. Otherwise devices will
// not enumerate properly at startup.
//
RegVal = EhcReadOpReg(Ehc, EHC_PORT_STAT_OFFSET + 4 * Index);
RegVal = EhcReadOpReg (Ehc, EHC_PORT_STAT_OFFSET + 4 * Index);
RegVal &= ~PORTSC_CHANGE_MASK;
RegVal |= PORTSC_POWER;
EhcWriteOpReg (Ehc, EHC_PORT_STAT_OFFSET + 4 * Index, RegVal);
@@ -438,12 +436,12 @@ EhcPowerOnAllPorts (
**/
EFI_STATUS
EhcInitHC (
IN PEI_USB2_HC_DEV *Ehc
IN PEI_USB2_HC_DEV *Ehc
)
{
EFI_STATUS Status;
EFI_PHYSICAL_ADDRESS TempPtr;
UINTN PageNumber;
EFI_STATUS Status;
EFI_PHYSICAL_ADDRESS TempPtr;
UINTN PageNumber;
ASSERT (EhcIsHalt (Ehc));
@@ -454,13 +452,14 @@ EhcInitHC (
if (Ehc->PeriodFrame != NULL) {
EhcFreeSched (Ehc);
}
PageNumber = sizeof(PEI_URB)/PAGESIZE +1;
Status = PeiServicesAllocatePages (
EfiBootServicesCode,
PageNumber,
&TempPtr
);
Ehc->Urb = (PEI_URB *) ((UINTN) TempPtr);
PageNumber = sizeof (PEI_URB)/PAGESIZE +1;
Status = PeiServicesAllocatePages (
EfiBootServicesCode,
PageNumber,
&TempPtr
);
Ehc->Urb = (PEI_URB *)((UINTN)TempPtr);
if (Ehc->Urb == NULL) {
return Status;
}
@@ -473,6 +472,7 @@ EhcInitHC (
if (EFI_ERROR (Status)) {
return Status;
}
//
// 1. Program the CTRLDSSEGMENT register with the high 32 bit addr
//
@@ -563,15 +563,16 @@ EhcBulkTransfer (
OUT UINT32 *TransferResult
)
{
PEI_USB2_HC_DEV *Ehc;
PEI_URB *Urb;
EFI_STATUS Status;
PEI_USB2_HC_DEV *Ehc;
PEI_URB *Urb;
EFI_STATUS Status;
//
// Validate the parameters
//
if ((DataLength == NULL) || (*DataLength == 0) ||
(Data == NULL) || (Data[0] == NULL) || (TransferResult == NULL)) {
(Data == NULL) || (Data[0] == NULL) || (TransferResult == NULL))
{
return EFI_INVALID_PARAMETER;
}
@@ -581,11 +582,12 @@ EhcBulkTransfer (
if ((DeviceSpeed == EFI_USB_SPEED_LOW) ||
((DeviceSpeed == EFI_USB_SPEED_FULL) && (MaximumPacketLength > 64)) ||
((EFI_USB_SPEED_HIGH == DeviceSpeed) && (MaximumPacketLength > 512))) {
((EFI_USB_SPEED_HIGH == DeviceSpeed) && (MaximumPacketLength > 512)))
{
return EFI_INVALID_PARAMETER;
}
Ehc =PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS(This);
Ehc = PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS (This);
*TransferResult = EFI_USB_ERR_SYSTEM;
Status = EFI_DEVICE_ERROR;
@@ -656,13 +658,13 @@ ON_EXIT:
EFI_STATUS
EFIAPI
EhcGetRootHubPortNumber (
IN EFI_PEI_SERVICES **PeiServices,
IN PEI_USB2_HOST_CONTROLLER_PPI *This,
OUT UINT8 *PortNumber
IN EFI_PEI_SERVICES **PeiServices,
IN PEI_USB2_HOST_CONTROLLER_PPI *This,
OUT UINT8 *PortNumber
)
{
PEI_USB2_HC_DEV *EhcDev;
PEI_USB2_HC_DEV *EhcDev;
EhcDev = PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS (This);
if (PortNumber == NULL) {
@@ -671,7 +673,6 @@ EhcGetRootHubPortNumber (
*PortNumber = (UINT8)(EhcDev->HcStructParams & HCSP_NPORTS);
return EFI_SUCCESS;
}
/**
@@ -692,20 +693,20 @@ EhcGetRootHubPortNumber (
EFI_STATUS
EFIAPI
EhcClearRootHubPortFeature (
IN EFI_PEI_SERVICES **PeiServices,
IN PEI_USB2_HOST_CONTROLLER_PPI *This,
IN UINT8 PortNumber,
IN EFI_USB_PORT_FEATURE PortFeature
IN EFI_PEI_SERVICES **PeiServices,
IN PEI_USB2_HOST_CONTROLLER_PPI *This,
IN UINT8 PortNumber,
IN EFI_USB_PORT_FEATURE PortFeature
)
{
PEI_USB2_HC_DEV *Ehc;
UINT32 Offset;
UINT32 State;
UINT32 TotalPort;
EFI_STATUS Status;
PEI_USB2_HC_DEV *Ehc;
UINT32 Offset;
UINT32 State;
UINT32 TotalPort;
EFI_STATUS Status;
Ehc = PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS (This);
Status = EFI_SUCCESS;
Ehc = PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS (This);
Status = EFI_SUCCESS;
TotalPort = (Ehc->HcStructParams & HCSP_NPORTS);
@@ -714,82 +715,82 @@ EhcClearRootHubPortFeature (
goto ON_EXIT;
}
Offset = EHC_PORT_STAT_OFFSET + (4 * PortNumber);
State = EhcReadOpReg (Ehc, Offset);
Offset = EHC_PORT_STAT_OFFSET + (4 * PortNumber);
State = EhcReadOpReg (Ehc, Offset);
State &= ~PORTSC_CHANGE_MASK;
switch (PortFeature) {
case EfiUsbPortEnable:
//
// Clear PORT_ENABLE feature means disable port.
//
State &= ~PORTSC_ENABLED;
EhcWriteOpReg (Ehc, Offset, State);
break;
case EfiUsbPortEnable:
//
// Clear PORT_ENABLE feature means disable port.
//
State &= ~PORTSC_ENABLED;
EhcWriteOpReg (Ehc, Offset, State);
break;
case EfiUsbPortSuspend:
//
// A write of zero to this bit is ignored by the host
// controller. The host controller will unconditionally
// set this bit to a zero when:
// 1. software sets the Forct Port Resume bit to a zero from a one.
// 2. software sets the Port Reset bit to a one frome a zero.
//
State &= ~PORSTSC_RESUME;
EhcWriteOpReg (Ehc, Offset, State);
break;
case EfiUsbPortSuspend:
//
// A write of zero to this bit is ignored by the host
// controller. The host controller will unconditionally
// set this bit to a zero when:
// 1. software sets the Forct Port Resume bit to a zero from a one.
// 2. software sets the Port Reset bit to a one frome a zero.
//
State &= ~PORSTSC_RESUME;
EhcWriteOpReg (Ehc, Offset, State);
break;
case EfiUsbPortReset:
//
// Clear PORT_RESET means clear the reset signal.
//
State &= ~PORTSC_RESET;
EhcWriteOpReg (Ehc, Offset, State);
break;
case EfiUsbPortReset:
//
// Clear PORT_RESET means clear the reset signal.
//
State &= ~PORTSC_RESET;
EhcWriteOpReg (Ehc, Offset, State);
break;
case EfiUsbPortOwner:
//
// Clear port owner means this port owned by EHC
//
State &= ~PORTSC_OWNER;
EhcWriteOpReg (Ehc, Offset, State);
break;
case EfiUsbPortOwner:
//
// Clear port owner means this port owned by EHC
//
State &= ~PORTSC_OWNER;
EhcWriteOpReg (Ehc, Offset, State);
break;
case EfiUsbPortConnectChange:
//
// Clear connect status change
//
State |= PORTSC_CONN_CHANGE;
EhcWriteOpReg (Ehc, Offset, State);
break;
case EfiUsbPortConnectChange:
//
// Clear connect status change
//
State |= PORTSC_CONN_CHANGE;
EhcWriteOpReg (Ehc, Offset, State);
break;
case EfiUsbPortEnableChange:
//
// Clear enable status change
//
State |= PORTSC_ENABLE_CHANGE;
EhcWriteOpReg (Ehc, Offset, State);
break;
case EfiUsbPortEnableChange:
//
// Clear enable status change
//
State |= PORTSC_ENABLE_CHANGE;
EhcWriteOpReg (Ehc, Offset, State);
break;
case EfiUsbPortOverCurrentChange:
//
// Clear PortOverCurrent change
//
State |= PORTSC_OVERCUR_CHANGE;
EhcWriteOpReg (Ehc, Offset, State);
break;
case EfiUsbPortOverCurrentChange:
//
// Clear PortOverCurrent change
//
State |= PORTSC_OVERCUR_CHANGE;
EhcWriteOpReg (Ehc, Offset, State);
break;
case EfiUsbPortPower:
case EfiUsbPortSuspendChange:
case EfiUsbPortResetChange:
//
// Not supported or not related operation
//
break;
case EfiUsbPortPower:
case EfiUsbPortSuspendChange:
case EfiUsbPortResetChange:
//
// Not supported or not related operation
//
break;
default:
Status = EFI_INVALID_PARAMETER;
break;
default:
Status = EFI_INVALID_PARAMETER;
break;
}
ON_EXIT:
@@ -812,20 +813,20 @@ ON_EXIT:
EFI_STATUS
EFIAPI
EhcSetRootHubPortFeature (
IN EFI_PEI_SERVICES **PeiServices,
IN PEI_USB2_HOST_CONTROLLER_PPI *This,
IN UINT8 PortNumber,
IN EFI_USB_PORT_FEATURE PortFeature
IN EFI_PEI_SERVICES **PeiServices,
IN PEI_USB2_HOST_CONTROLLER_PPI *This,
IN UINT8 PortNumber,
IN EFI_USB_PORT_FEATURE PortFeature
)
{
PEI_USB2_HC_DEV *Ehc;
UINT32 Offset;
UINT32 State;
UINT32 TotalPort;
EFI_STATUS Status;
PEI_USB2_HC_DEV *Ehc;
UINT32 Offset;
UINT32 State;
UINT32 TotalPort;
EFI_STATUS Status;
Ehc = PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS (This);
Status = EFI_SUCCESS;
Ehc = PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS (This);
Status = EFI_SUCCESS;
TotalPort = (Ehc->HcStructParams & HCSP_NPORTS);
@@ -834,8 +835,8 @@ EhcSetRootHubPortFeature (
goto ON_EXIT;
}
Offset = (UINT32) (EHC_PORT_STAT_OFFSET + (4 * PortNumber));
State = EhcReadOpReg (Ehc, Offset);
Offset = (UINT32)(EHC_PORT_STAT_OFFSET + (4 * PortNumber));
State = EhcReadOpReg (Ehc, Offset);
//
// Mask off the port status change bits, these bits are
@@ -844,54 +845,54 @@ EhcSetRootHubPortFeature (
State &= ~PORTSC_CHANGE_MASK;
switch (PortFeature) {
case EfiUsbPortEnable:
//
// Sofeware can't set this bit, Port can only be enable by
// EHCI as a part of the reset and enable
//
State |= PORTSC_ENABLED;
EhcWriteOpReg (Ehc, Offset, State);
break;
case EfiUsbPortEnable:
//
// Sofeware can't set this bit, Port can only be enable by
// EHCI as a part of the reset and enable
//
State |= PORTSC_ENABLED;
EhcWriteOpReg (Ehc, Offset, State);
break;
case EfiUsbPortSuspend:
State |= PORTSC_SUSPEND;
EhcWriteOpReg (Ehc, Offset, State);
break;
case EfiUsbPortSuspend:
State |= PORTSC_SUSPEND;
EhcWriteOpReg (Ehc, Offset, State);
break;
case EfiUsbPortReset:
//
// Make sure Host Controller not halt before reset it
//
if (EhcIsHalt (Ehc)) {
Status = EhcRunHC (Ehc, EHC_GENERIC_TIMEOUT);
case EfiUsbPortReset:
//
// Make sure Host Controller not halt before reset it
//
if (EhcIsHalt (Ehc)) {
Status = EhcRunHC (Ehc, EHC_GENERIC_TIMEOUT);
if (EFI_ERROR (Status)) {
break;
if (EFI_ERROR (Status)) {
break;
}
}
}
//
// Set one to PortReset bit must also set zero to PortEnable bit
//
State |= PORTSC_RESET;
State &= ~PORTSC_ENABLED;
EhcWriteOpReg (Ehc, Offset, State);
break;
//
// Set one to PortReset bit must also set zero to PortEnable bit
//
State |= PORTSC_RESET;
State &= ~PORTSC_ENABLED;
EhcWriteOpReg (Ehc, Offset, State);
break;
case EfiUsbPortPower:
//
// Not supported, ignore the operation
//
Status = EFI_SUCCESS;
break;
case EfiUsbPortPower:
//
// Not supported, ignore the operation
//
Status = EFI_SUCCESS;
break;
case EfiUsbPortOwner:
State |= PORTSC_OWNER;
EhcWriteOpReg (Ehc, Offset, State);
break;
case EfiUsbPortOwner:
State |= PORTSC_OWNER;
EhcWriteOpReg (Ehc, Offset, State);
break;
default:
Status = EFI_INVALID_PARAMETER;
default:
Status = EFI_INVALID_PARAMETER;
}
ON_EXIT:
@@ -914,26 +915,26 @@ ON_EXIT:
EFI_STATUS
EFIAPI
EhcGetRootHubPortStatus (
IN EFI_PEI_SERVICES **PeiServices,
IN PEI_USB2_HOST_CONTROLLER_PPI *This,
IN UINT8 PortNumber,
OUT EFI_USB_PORT_STATUS *PortStatus
IN EFI_PEI_SERVICES **PeiServices,
IN PEI_USB2_HOST_CONTROLLER_PPI *This,
IN UINT8 PortNumber,
OUT EFI_USB_PORT_STATUS *PortStatus
)
{
PEI_USB2_HC_DEV *Ehc;
UINT32 Offset;
UINT32 State;
UINT32 TotalPort;
UINTN Index;
UINTN MapSize;
EFI_STATUS Status;
PEI_USB2_HC_DEV *Ehc;
UINT32 Offset;
UINT32 State;
UINT32 TotalPort;
UINTN Index;
UINTN MapSize;
EFI_STATUS Status;
if (PortStatus == NULL) {
return EFI_INVALID_PARAMETER;
}
Ehc = PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS(This);
Status = EFI_SUCCESS;
Ehc = PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS (This);
Status = EFI_SUCCESS;
TotalPort = (Ehc->HcStructParams & HCSP_NPORTS);
@@ -942,11 +943,11 @@ EhcGetRootHubPortStatus (
goto ON_EXIT;
}
Offset = (UINT32) (EHC_PORT_STAT_OFFSET + (4 * PortNumber));
PortStatus->PortStatus = 0;
PortStatus->PortChangeStatus = 0;
Offset = (UINT32)(EHC_PORT_STAT_OFFSET + (4 * PortNumber));
PortStatus->PortStatus = 0;
PortStatus->PortChangeStatus = 0;
State = EhcReadOpReg (Ehc, Offset);
State = EhcReadOpReg (Ehc, Offset);
//
// Identify device speed. If in K state, it is low speed.
@@ -956,7 +957,6 @@ EhcGetRootHubPortStatus (
//
if (EHC_BIT_IS_SET (State, PORTSC_LINESTATE_K)) {
PortStatus->PortStatus |= USB_PORT_STAT_LOW_SPEED;
} else if (EHC_BIT_IS_SET (State, PORTSC_ENABLED)) {
PortStatus->PortStatus |= USB_PORT_STAT_HIGH_SPEED;
}
@@ -968,7 +968,7 @@ EhcGetRootHubPortStatus (
for (Index = 0; Index < MapSize; Index++) {
if (EHC_BIT_IS_SET (State, mUsbPortStateMap[Index].HwState)) {
PortStatus->PortStatus = (UINT16) (PortStatus->PortStatus | mUsbPortStateMap[Index].UefiState);
PortStatus->PortStatus = (UINT16)(PortStatus->PortStatus | mUsbPortStateMap[Index].UefiState);
}
}
@@ -976,7 +976,7 @@ EhcGetRootHubPortStatus (
for (Index = 0; Index < MapSize; Index++) {
if (EHC_BIT_IS_SET (State, mUsbPortChangeMap[Index].HwState)) {
PortStatus->PortChangeStatus = (UINT16) (PortStatus->PortChangeStatus | mUsbPortChangeMap[Index].UefiState);
PortStatus->PortChangeStatus = (UINT16)(PortStatus->PortChangeStatus | mUsbPortChangeMap[Index].UefiState);
}
}
@@ -1027,10 +1027,10 @@ EhcControlTransfer (
OUT UINT32 *TransferResult
)
{
PEI_USB2_HC_DEV *Ehc;
PEI_URB *Urb;
UINT8 Endpoint;
EFI_STATUS Status;
PEI_USB2_HC_DEV *Ehc;
PEI_URB *Urb;
UINT8 Endpoint;
EFI_STATUS Status;
//
// Validate parameters
@@ -1041,33 +1041,37 @@ EhcControlTransfer (
if ((TransferDirection != EfiUsbDataIn) &&
(TransferDirection != EfiUsbDataOut) &&
(TransferDirection != EfiUsbNoData)) {
(TransferDirection != EfiUsbNoData))
{
return EFI_INVALID_PARAMETER;
}
if ((TransferDirection == EfiUsbNoData) &&
((Data != NULL) || (*DataLength != 0))) {
((Data != NULL) || (*DataLength != 0)))
{
return EFI_INVALID_PARAMETER;
}
if ((TransferDirection != EfiUsbNoData) &&
((Data == NULL) || (*DataLength == 0))) {
((Data == NULL) || (*DataLength == 0)))
{
return EFI_INVALID_PARAMETER;
}
if ((MaximumPacketLength != 8) && (MaximumPacketLength != 16) &&
(MaximumPacketLength != 32) && (MaximumPacketLength != 64)) {
(MaximumPacketLength != 32) && (MaximumPacketLength != 64))
{
return EFI_INVALID_PARAMETER;
}
if ((DeviceSpeed == EFI_USB_SPEED_LOW) ||
((DeviceSpeed == EFI_USB_SPEED_FULL) && (MaximumPacketLength > 64)) ||
((EFI_USB_SPEED_HIGH == DeviceSpeed) && (MaximumPacketLength > 512))) {
((EFI_USB_SPEED_HIGH == DeviceSpeed) && (MaximumPacketLength > 512)))
{
return EFI_INVALID_PARAMETER;
}
Ehc = PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS (This);
Ehc = PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS (This);
Status = EFI_DEVICE_ERROR;
*TransferResult = EFI_USB_ERR_SYSTEM;
@@ -1088,23 +1092,23 @@ EhcControlTransfer (
// endpoint is bidirectional. EhcCreateUrb expects this
// combination of Ep addr and its direction.
//
Endpoint = (UINT8) (0 | ((TransferDirection == EfiUsbDataIn) ? 0x80 : 0));
Urb = EhcCreateUrb (
Ehc,
DeviceAddress,
Endpoint,
DeviceSpeed,
0,
MaximumPacketLength,
Translator,
EHC_CTRL_TRANSFER,
Request,
Data,
*DataLength,
NULL,
NULL,
1
);
Endpoint = (UINT8)(0 | ((TransferDirection == EfiUsbDataIn) ? 0x80 : 0));
Urb = EhcCreateUrb (
Ehc,
DeviceAddress,
Endpoint,
DeviceSpeed,
0,
MaximumPacketLength,
Translator,
EHC_CTRL_TRANSFER,
Request,
Data,
*DataLength,
NULL,
NULL,
1
);
if (Urb == NULL) {
Status = EFI_OUT_OF_RESOURCES;
@@ -1152,7 +1156,7 @@ EhcEndOfPei (
IN VOID *Ppi
)
{
PEI_USB2_HC_DEV *Ehc;
PEI_USB2_HC_DEV *Ehc;
Ehc = PEI_RECOVERY_USB_EHC_DEV_FROM_THIS_NOTIFY (NotifyDescriptor);
@@ -1177,14 +1181,14 @@ EhcPeimEntry (
IN CONST EFI_PEI_SERVICES **PeiServices
)
{
PEI_USB_CONTROLLER_PPI *ChipSetUsbControllerPpi;
EFI_STATUS Status;
UINT8 Index;
UINTN ControllerType;
UINTN BaseAddress;
UINTN MemPages;
PEI_USB2_HC_DEV *EhcDev;
EFI_PHYSICAL_ADDRESS TempPtr;
PEI_USB_CONTROLLER_PPI *ChipSetUsbControllerPpi;
EFI_STATUS Status;
UINT8 Index;
UINTN ControllerType;
UINTN BaseAddress;
UINTN MemPages;
PEI_USB2_HC_DEV *EhcDev;
EFI_PHYSICAL_ADDRESS TempPtr;
//
// Shadow this PEIM to run from memory
@@ -1197,7 +1201,7 @@ EhcPeimEntry (
&gPeiUsbControllerPpiGuid,
0,
NULL,
(VOID **) &ChipSetUsbControllerPpi
(VOID **)&ChipSetUsbControllerPpi
);
if (EFI_ERROR (Status)) {
return EFI_UNSUPPORTED;
@@ -1206,7 +1210,7 @@ EhcPeimEntry (
Index = 0;
while (TRUE) {
Status = ChipSetUsbControllerPpi->GetUsbController (
(EFI_PEI_SERVICES **) PeiServices,
(EFI_PEI_SERVICES **)PeiServices,
ChipSetUsbControllerPpi,
Index,
&ControllerType,
@@ -1228,24 +1232,23 @@ EhcPeimEntry (
}
MemPages = sizeof (PEI_USB2_HC_DEV) / PAGESIZE + 1;
Status = PeiServicesAllocatePages (
EfiBootServicesCode,
MemPages,
&TempPtr
);
Status = PeiServicesAllocatePages (
EfiBootServicesCode,
MemPages,
&TempPtr
);
if (EFI_ERROR (Status)) {
return EFI_OUT_OF_RESOURCES;
}
ZeroMem((VOID *)(UINTN)TempPtr, MemPages*PAGESIZE);
EhcDev = (PEI_USB2_HC_DEV *) ((UINTN) TempPtr);
ZeroMem ((VOID *)(UINTN)TempPtr, MemPages*PAGESIZE);
EhcDev = (PEI_USB2_HC_DEV *)((UINTN)TempPtr);
EhcDev->Signature = USB2_HC_DEV_SIGNATURE;
IoMmuInit (&EhcDev->IoMmu);
EhcDev->UsbHostControllerBaseAddress = (UINT32) BaseAddress;
EhcDev->UsbHostControllerBaseAddress = (UINT32)BaseAddress;
EhcDev->HcStructParams = EhcReadCapRegister (EhcDev, EHC_HCSPARAMS_OFFSET);
EhcDev->HcCapParams = EhcReadCapRegister (EhcDev, EHC_HCCPARAMS_OFFSET);
@@ -1258,16 +1261,16 @@ EhcPeimEntry (
return Status;
}
EhcDev->Usb2HostControllerPpi.ControlTransfer = EhcControlTransfer;
EhcDev->Usb2HostControllerPpi.BulkTransfer = EhcBulkTransfer;
EhcDev->Usb2HostControllerPpi.GetRootHubPortNumber = EhcGetRootHubPortNumber;
EhcDev->Usb2HostControllerPpi.GetRootHubPortStatus = EhcGetRootHubPortStatus;
EhcDev->Usb2HostControllerPpi.SetRootHubPortFeature = EhcSetRootHubPortFeature;
EhcDev->Usb2HostControllerPpi.ClearRootHubPortFeature = EhcClearRootHubPortFeature;
EhcDev->Usb2HostControllerPpi.ControlTransfer = EhcControlTransfer;
EhcDev->Usb2HostControllerPpi.BulkTransfer = EhcBulkTransfer;
EhcDev->Usb2HostControllerPpi.GetRootHubPortNumber = EhcGetRootHubPortNumber;
EhcDev->Usb2HostControllerPpi.GetRootHubPortStatus = EhcGetRootHubPortStatus;
EhcDev->Usb2HostControllerPpi.SetRootHubPortFeature = EhcSetRootHubPortFeature;
EhcDev->Usb2HostControllerPpi.ClearRootHubPortFeature = EhcClearRootHubPortFeature;
EhcDev->PpiDescriptor.Flags = (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST);
EhcDev->PpiDescriptor.Guid = &gPeiUsb2HostControllerPpiGuid;
EhcDev->PpiDescriptor.Ppi = &EhcDev->Usb2HostControllerPpi;
EhcDev->PpiDescriptor.Guid = &gPeiUsb2HostControllerPpiGuid;
EhcDev->PpiDescriptor.Ppi = &EhcDev->Usb2HostControllerPpi;
Status = PeiServicesInstallPpi (&EhcDev->PpiDescriptor);
if (EFI_ERROR (Status)) {
@@ -1275,8 +1278,8 @@ EhcPeimEntry (
continue;
}
EhcDev->EndOfPeiNotifyList.Flags = (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST);
EhcDev->EndOfPeiNotifyList.Guid = &gEfiEndOfPeiSignalPpiGuid;
EhcDev->EndOfPeiNotifyList.Flags = (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST);
EhcDev->EndOfPeiNotifyList.Guid = &gEfiEndOfPeiSignalPpiGuid;
EhcDev->EndOfPeiNotifyList.Notify = EhcEndOfPei;
PeiServicesNotifyPpi (&EhcDev->EndOfPeiNotifyList);
@@ -1296,12 +1299,11 @@ EhcPeimEntry (
**/
EFI_STATUS
InitializeUsbHC (
IN PEI_USB2_HC_DEV *EhcDev
IN PEI_USB2_HC_DEV *EhcDev
)
{
EFI_STATUS Status;
EhcResetHC (EhcDev, EHC_RESET_TIMEOUT);
Status = EhcInitHC (EhcDev);

116
MdeModulePkg/Bus/Pci/EhciPei/EhcPeim.h
View File

@@ -28,46 +28,44 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
typedef struct _PEI_USB2_HC_DEV PEI_USB2_HC_DEV;
#define EFI_LIST_ENTRY LIST_ENTRY
#define EFI_LIST_ENTRY LIST_ENTRY
#include "UsbHcMem.h"
#include "EhciReg.h"
#include "EhciUrb.h"
#include "EhciSched.h"
#define EFI_USB_SPEED_FULL 0x0000
#define EFI_USB_SPEED_LOW 0x0001
#define EFI_USB_SPEED_HIGH 0x0002
#define EFI_USB_SPEED_FULL 0x0000
#define EFI_USB_SPEED_LOW 0x0001
#define EFI_USB_SPEED_HIGH 0x0002
#define PAGESIZE 4096
#define PAGESIZE 4096
#define EHC_1_MICROSECOND 1
#define EHC_1_MILLISECOND (1000 * EHC_1_MICROSECOND)
#define EHC_1_SECOND (1000 * EHC_1_MILLISECOND)
#define EHC_1_MICROSECOND 1
#define EHC_1_MILLISECOND (1000 * EHC_1_MICROSECOND)
#define EHC_1_SECOND (1000 * EHC_1_MILLISECOND)
//
// EHCI register operation timeout, set by experience
//
#define EHC_RESET_TIMEOUT (1 * EHC_1_SECOND)
#define EHC_GENERIC_TIMEOUT (10 * EHC_1_MILLISECOND)
#define EHC_RESET_TIMEOUT (1 * EHC_1_SECOND)
#define EHC_GENERIC_TIMEOUT (10 * EHC_1_MILLISECOND)
//
// Wait for roothub port power stable, refers to Spec[EHCI1.0-2.3.9]
//
#define EHC_ROOT_PORT_RECOVERY_STALL (20 * EHC_1_MILLISECOND)
#define EHC_ROOT_PORT_RECOVERY_STALL (20 * EHC_1_MILLISECOND)
//
// Sync transfer polling interval, set by experience.
//
#define EHC_SYNC_POLL_INTERVAL (6 * EHC_1_MILLISECOND)
#define EHC_SYNC_POLL_INTERVAL (6 * EHC_1_MILLISECOND)
#define EFI_LIST_CONTAINER(Entry, Type, Field) BASE_CR(Entry, Type, Field)
#define EFI_LIST_CONTAINER(Entry, Type, Field) BASE_CR(Entry, Type, Field)
#define EHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0XFFFFFFFF))
#define EHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINTN)(Addr64), 32) & 0XFFFFFFFF))
#define EHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))
#define EHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0XFFFFFFFF))
#define EHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINTN)(Addr64), 32) & 0XFFFFFFFF))
#define EHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))
#define EHC_REG_BIT_IS_SET(Ehc, Offset, Bit) \
(EHC_BIT_IS_SET(EhcReadOpReg ((Ehc), (Offset)), (Bit)))
@@ -75,18 +73,18 @@ typedef struct _PEI_USB2_HC_DEV PEI_USB2_HC_DEV;
#define USB2_HC_DEV_SIGNATURE SIGNATURE_32 ('e', 'h', 'c', 'i')
struct _PEI_USB2_HC_DEV {
UINTN Signature;
PEI_USB2_HOST_CONTROLLER_PPI Usb2HostControllerPpi;
EDKII_IOMMU_PPI *IoMmu;
EFI_PEI_PPI_DESCRIPTOR PpiDescriptor;
UINTN Signature;
PEI_USB2_HOST_CONTROLLER_PPI Usb2HostControllerPpi;
EDKII_IOMMU_PPI *IoMmu;
EFI_PEI_PPI_DESCRIPTOR PpiDescriptor;
//
// EndOfPei callback is used to stop the EHC DMA operation
// after exit PEI phase.
//
EFI_PEI_NOTIFY_DESCRIPTOR EndOfPeiNotifyList;
UINT32 UsbHostControllerBaseAddress;
PEI_URB *Urb;
USBHC_MEM_POOL *MemPool;
EFI_PEI_NOTIFY_DESCRIPTOR EndOfPeiNotifyList;
UINT32 UsbHostControllerBaseAddress;
PEI_URB *Urb;
USBHC_MEM_POOL *MemPool;
//
// Schedule data shared between asynchronous and periodic
@@ -97,36 +95,36 @@ struct _PEI_USB2_HC_DEV {
// For control transfer, even the short read happens, try the
// status stage.
//
PEI_EHC_QTD *ShortReadStop;
EFI_EVENT PollTimer;
PEI_EHC_QTD *ShortReadStop;
EFI_EVENT PollTimer;
//
// Asynchronous(bulk and control) transfer schedule data:
// ReclaimHead is used as the head of the asynchronous transfer
// list. It acts as the reclamation header.
//
PEI_EHC_QH *ReclaimHead;
PEI_EHC_QH *ReclaimHead;
//
// Periodic (interrupt) transfer schedule data:
//
VOID *PeriodFrame; // Mapped as common buffer
VOID *PeriodFrameMap;
VOID *PeriodFrame; // Mapped as common buffer
VOID *PeriodFrameMap;
PEI_EHC_QH *PeriodOne;
EFI_LIST_ENTRY AsyncIntTransfers;
PEI_EHC_QH *PeriodOne;
EFI_LIST_ENTRY AsyncIntTransfers;
//
// EHCI configuration data
//
UINT32 HcStructParams; // Cache of HC structure parameter, EHC_HCSPARAMS_OFFSET
UINT32 HcCapParams; // Cache of HC capability parameter, HCCPARAMS
UINT32 CapLen; // Capability length
UINT32 High32bitAddr;
UINT32 HcStructParams; // Cache of HC structure parameter, EHC_HCSPARAMS_OFFSET
UINT32 HcCapParams; // Cache of HC capability parameter, HCCPARAMS
UINT32 CapLen; // Capability length
UINT32 High32bitAddr;
};
#define PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS(a) CR (a, PEI_USB2_HC_DEV, Usb2HostControllerPpi, USB2_HC_DEV_SIGNATURE)
#define PEI_RECOVERY_USB_EHC_DEV_FROM_THIS_NOTIFY(a) CR (a, PEI_USB2_HC_DEV, EndOfPeiNotifyList, USB2_HC_DEV_SIGNATURE)
#define PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS(a) CR (a, PEI_USB2_HC_DEV, Usb2HostControllerPpi, USB2_HC_DEV_SIGNATURE)
#define PEI_RECOVERY_USB_EHC_DEV_FROM_THIS_NOTIFY(a) CR (a, PEI_USB2_HC_DEV, EndOfPeiNotifyList, USB2_HC_DEV_SIGNATURE)
/**
@param EhcDev EHCI Device.
@@ -137,7 +135,7 @@ struct _PEI_USB2_HC_DEV {
**/
EFI_STATUS
InitializeUsbHC (
IN PEI_USB2_HC_DEV *EhcDev
IN PEI_USB2_HC_DEV *EhcDev
);
/**
@@ -154,9 +152,9 @@ InitializeUsbHC (
**/
USBHC_MEM_POOL *
UsbHcInitMemPool (
IN PEI_USB2_HC_DEV *Ehc,
IN BOOLEAN Check4G,
IN UINT32 Which4G
IN PEI_USB2_HC_DEV *Ehc,
IN BOOLEAN Check4G,
IN UINT32 Which4G
)
;
@@ -172,8 +170,8 @@ UsbHcInitMemPool (
**/
EFI_STATUS
UsbHcFreeMemPool (
IN PEI_USB2_HC_DEV *Ehc,
IN USBHC_MEM_POOL *Pool
IN PEI_USB2_HC_DEV *Ehc,
IN USBHC_MEM_POOL *Pool
)
;
@@ -190,9 +188,9 @@ UsbHcFreeMemPool (
**/
VOID *
UsbHcAllocateMem (
IN PEI_USB2_HC_DEV *Ehc,
IN USBHC_MEM_POOL *Pool,
IN UINTN Size
IN PEI_USB2_HC_DEV *Ehc,
IN USBHC_MEM_POOL *Pool,
IN UINTN Size
)
;
@@ -207,10 +205,10 @@ UsbHcAllocateMem (
**/
VOID
UsbHcFreeMem (
IN PEI_USB2_HC_DEV *Ehc,
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
IN PEI_USB2_HC_DEV *Ehc,
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
)
;
@@ -253,8 +251,8 @@ IoMmuMap (
**/
VOID
IoMmuUnmap (
IN EDKII_IOMMU_PPI *IoMmu,
IN VOID *Mapping
IN EDKII_IOMMU_PPI *IoMmu,
IN VOID *Mapping
);
/**
@@ -296,10 +294,10 @@ IoMmuAllocateBuffer (
**/
VOID
IoMmuFreeBuffer (
IN EDKII_IOMMU_PPI *IoMmu,
IN UINTN Pages,
IN VOID *HostAddress,
IN VOID *Mapping
IN EDKII_IOMMU_PPI *IoMmu,
IN UINTN Pages,
IN VOID *HostAddress,
IN VOID *Mapping
);
/**
@@ -310,7 +308,7 @@ IoMmuFreeBuffer (
**/
VOID
IoMmuInit (
OUT EDKII_IOMMU_PPI **IoMmu
OUT EDKII_IOMMU_PPI **IoMmu
);
#endif

123
MdeModulePkg/Bus/Pci/EhciPei/EhciReg.h
View File

@@ -10,20 +10,18 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#ifndef _EFI_EHCI_REG_H_
#define _EFI_EHCI_REG_H_
//
// Capability register offset
//
#define EHC_CAPLENGTH_OFFSET 0 // Capability register length offset
#define EHC_HCSPARAMS_OFFSET 0x04 // Structural Parameters 04-07h
#define EHC_HCCPARAMS_OFFSET 0x08 // Capability parameters offset
#define EHC_CAPLENGTH_OFFSET 0 // Capability register length offset
#define EHC_HCSPARAMS_OFFSET 0x04 // Structural Parameters 04-07h
#define EHC_HCCPARAMS_OFFSET 0x08 // Capability parameters offset
//
// Capability register bit definition
//
#define HCSP_NPORTS 0x0F // Number of root hub port
#define HCCP_64BIT 0x01 // 64-bit addressing capability
#define HCSP_NPORTS 0x0F // Number of root hub port
#define HCCP_64BIT 0x01 // 64-bit addressing capability
//
// Operational register offset
@@ -38,61 +36,61 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#define EHC_CONFIG_FLAG_OFFSET 0x40 // Configure flag register offset
#define EHC_PORT_STAT_OFFSET 0x44 // Port status/control offset
#define EHC_FRAME_LEN 1024
#define EHC_FRAME_LEN 1024
//
// Register bit definition
//
#define CONFIGFLAG_ROUTE_EHC 0x01 // Route port to EHC
#define CONFIGFLAG_ROUTE_EHC 0x01 // Route port to EHC
#define USBCMD_RUN 0x01 // Run/stop
#define USBCMD_RESET 0x02 // Start the host controller reset
#define USBCMD_ENABLE_PERIOD 0x10 // Enable periodic schedule
#define USBCMD_ENABLE_ASYNC 0x20 // Enable asynchronous schedule
#define USBCMD_IAAD 0x40 // Interrupt on async advance doorbell
#define USBCMD_RUN 0x01 // Run/stop
#define USBCMD_RESET 0x02 // Start the host controller reset
#define USBCMD_ENABLE_PERIOD 0x10 // Enable periodic schedule
#define USBCMD_ENABLE_ASYNC 0x20 // Enable asynchronous schedule
#define USBCMD_IAAD 0x40 // Interrupt on async advance doorbell
#define USBSTS_IAA 0x20 // Interrupt on async advance
#define USBSTS_PERIOD_ENABLED 0x4000 // Periodic schedule status
#define USBSTS_ASYNC_ENABLED 0x8000 // Asynchronous schedule status
#define USBSTS_HALT 0x1000 // Host controller halted
#define USBSTS_SYS_ERROR 0x10 // Host system error
#define USBSTS_INTACK_MASK 0x003F // Mask for the interrupt ACK, the WC
#define USBSTS_IAA 0x20 // Interrupt on async advance
#define USBSTS_PERIOD_ENABLED 0x4000 // Periodic schedule status
#define USBSTS_ASYNC_ENABLED 0x8000 // Asynchronous schedule status
#define USBSTS_HALT 0x1000 // Host controller halted
#define USBSTS_SYS_ERROR 0x10 // Host system error
#define USBSTS_INTACK_MASK 0x003F // Mask for the interrupt ACK, the WC
// (write clean) bits in USBSTS register
#define PORTSC_CONN 0x01 // Current Connect Status
#define PORTSC_CONN_CHANGE 0x02 // Connect Status Change
#define PORTSC_ENABLED 0x04 // Port Enable / Disable
#define PORTSC_ENABLE_CHANGE 0x08 // Port Enable / Disable Change
#define PORTSC_OVERCUR 0x10 // Over current Active
#define PORTSC_OVERCUR_CHANGE 0x20 // Over current Change
#define PORSTSC_RESUME 0x40 // Force Port Resume
#define PORTSC_SUSPEND 0x80 // Port Suspend State
#define PORTSC_RESET 0x100 // Port Reset
#define PORTSC_LINESTATE_K 0x400 // Line Status K-state
#define PORTSC_LINESTATE_J 0x800 // Line Status J-state
#define PORTSC_POWER 0x1000 // Port Power
#define PORTSC_OWNER 0x2000 // Port Owner
#define PORTSC_CHANGE_MASK 0x2A // Mask of the port change bits,
#define PORTSC_CONN 0x01 // Current Connect Status
#define PORTSC_CONN_CHANGE 0x02 // Connect Status Change
#define PORTSC_ENABLED 0x04 // Port Enable / Disable
#define PORTSC_ENABLE_CHANGE 0x08 // Port Enable / Disable Change
#define PORTSC_OVERCUR 0x10 // Over current Active
#define PORTSC_OVERCUR_CHANGE 0x20 // Over current Change
#define PORSTSC_RESUME 0x40 // Force Port Resume
#define PORTSC_SUSPEND 0x80 // Port Suspend State
#define PORTSC_RESET 0x100 // Port Reset
#define PORTSC_LINESTATE_K 0x400 // Line Status K-state
#define PORTSC_LINESTATE_J 0x800 // Line Status J-state
#define PORTSC_POWER 0x1000 // Port Power
#define PORTSC_OWNER 0x2000 // Port Owner
#define PORTSC_CHANGE_MASK 0x2A // Mask of the port change bits,
// they are WC (write clean)
//
// PCI Configuration Registers
//
#define EHC_BAR_INDEX 0 // how many bytes away from USB_BASE to 0x10
#define EHC_BAR_INDEX 0 // how many bytes away from USB_BASE to 0x10
#define EHC_LINK_TERMINATED(Link) (((Link) & 0x01) != 0)
#define EHC_LINK_TERMINATED(Link) (((Link) & 0x01) != 0)
#define EHC_ADDR(High, QhHw32) \
((VOID *) (UINTN) (LShiftU64 ((High), 32) | ((QhHw32) & 0xFFFFFFF0)))
#define EHCI_IS_DATAIN(EndpointAddr) EHC_BIT_IS_SET((EndpointAddr), 0x80)
#define EHCI_IS_DATAIN(EndpointAddr) EHC_BIT_IS_SET((EndpointAddr), 0x80)
//
// Structure to map the hardware port states to the
// UEFI's port states.
//
typedef struct {
UINT16 HwState;
UINT16 UefiState;
UINT16 HwState;
UINT16 UefiState;
} USB_PORT_STATE_MAP;
//
@@ -100,13 +98,12 @@ typedef struct {
//
#pragma pack(1)
typedef struct {
UINT8 Pi;
UINT8 SubClassCode;
UINT8 BaseCode;
UINT8 Pi;
UINT8 SubClassCode;
UINT8 BaseCode;
} USB_CLASSC;
#pragma pack()
/**
Read EHCI capability register.
@@ -118,8 +115,8 @@ typedef struct {
**/
UINT32
EhcReadCapRegister (
IN PEI_USB2_HC_DEV *Ehc,
IN UINT32 Offset
IN PEI_USB2_HC_DEV *Ehc,
IN UINT32 Offset
)
;
@@ -134,8 +131,8 @@ EhcReadCapRegister (
**/
UINT32
EhcReadOpReg (
IN PEI_USB2_HC_DEV *Ehc,
IN UINT32 Offset
IN PEI_USB2_HC_DEV *Ehc,
IN UINT32 Offset
)
;
@@ -149,9 +146,9 @@ EhcReadOpReg (
**/
VOID
EhcWriteOpReg (
IN PEI_USB2_HC_DEV *Ehc,
IN UINT32 Offset,
IN UINT32 Data
IN PEI_USB2_HC_DEV *Ehc,
IN UINT32 Offset,
IN UINT32 Data
)
;
@@ -163,7 +160,7 @@ EhcWriteOpReg (
**/
VOID
EhcClearLegacySupport (
IN PEI_USB2_HC_DEV *Ehc
IN PEI_USB2_HC_DEV *Ehc
)
;
@@ -180,8 +177,8 @@ EhcClearLegacySupport (
**/
EFI_STATUS
EhcSetAndWaitDoorBell (
IN PEI_USB2_HC_DEV *Ehc,
IN UINT32 Timeout
IN PEI_USB2_HC_DEV *Ehc,
IN UINT32 Timeout
)
;
@@ -194,7 +191,7 @@ EhcSetAndWaitDoorBell (
**/
VOID
EhcAckAllInterrupt (
IN PEI_USB2_HC_DEV *Ehc
IN PEI_USB2_HC_DEV *Ehc
)
;
@@ -209,7 +206,7 @@ EhcAckAllInterrupt (
**/
BOOLEAN
EhcIsHalt (
IN PEI_USB2_HC_DEV *Ehc
IN PEI_USB2_HC_DEV *Ehc
)
;
@@ -224,7 +221,7 @@ EhcIsHalt (
**/
BOOLEAN
EhcIsSysError (
IN PEI_USB2_HC_DEV *Ehc
IN PEI_USB2_HC_DEV *Ehc
)
;
@@ -240,8 +237,8 @@ EhcIsSysError (
**/
EFI_STATUS
EhcResetHC (
IN PEI_USB2_HC_DEV *Ehc,
IN UINT32 Timeout
IN PEI_USB2_HC_DEV *Ehc,
IN UINT32 Timeout
)
;
@@ -257,8 +254,8 @@ EhcResetHC (
**/
EFI_STATUS
EhcHaltHC (
IN PEI_USB2_HC_DEV *Ehc,
IN UINT32 Timeout
IN PEI_USB2_HC_DEV *Ehc,
IN UINT32 Timeout
)
;
@@ -274,8 +271,8 @@ EhcHaltHC (
**/
EFI_STATUS
EhcRunHC (
IN PEI_USB2_HC_DEV *Ehc,
IN UINT32 Timeout
IN PEI_USB2_HC_DEV *Ehc,
IN UINT32 Timeout
)
;
@@ -296,7 +293,7 @@ EhcRunHC (
**/
EFI_STATUS
EhcInitHC (
IN PEI_USB2_HC_DEV *Ehc
IN PEI_USB2_HC_DEV *Ehc
)
;

138
MdeModulePkg/Bus/Pci/EhciPei/EhciSched.c
View File

@@ -22,13 +22,13 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
EFI_STATUS
EhcCreateHelpQ (
IN PEI_USB2_HC_DEV *Ehc
IN PEI_USB2_HC_DEV *Ehc
)
{
USB_ENDPOINT Ep;
PEI_EHC_QH *Qh;
QH_HW *QhHw;
PEI_EHC_QTD *Qtd;
USB_ENDPOINT Ep;
PEI_EHC_QH *Qh;
QH_HW *QhHw;
PEI_EHC_QTD *Qtd;
//
// Create an inactive Qtd to terminate the short packet read.
@@ -39,25 +39,25 @@ EhcCreateHelpQ (
return EFI_OUT_OF_RESOURCES;
}
Qtd->QtdHw.Status = QTD_STAT_HALTED;
Ehc->ShortReadStop = Qtd;
Qtd->QtdHw.Status = QTD_STAT_HALTED;
Ehc->ShortReadStop = Qtd;
//
// Create a QH to act as the EHC reclamation header.
// Set the header to loopback to itself.
//
Ep.DevAddr = 0;
Ep.EpAddr = 1;
Ep.Direction = EfiUsbDataIn;
Ep.DevSpeed = EFI_USB_SPEED_HIGH;
Ep.MaxPacket = 64;
Ep.HubAddr = 0;
Ep.HubPort = 0;
Ep.Toggle = 0;
Ep.Type = EHC_BULK_TRANSFER;
Ep.PollRate = 1;
Ep.DevAddr = 0;
Ep.EpAddr = 1;
Ep.Direction = EfiUsbDataIn;
Ep.DevSpeed = EFI_USB_SPEED_HIGH;
Ep.MaxPacket = 64;
Ep.HubAddr = 0;
Ep.HubPort = 0;
Ep.Toggle = 0;
Ep.Type = EHC_BULK_TRANSFER;
Ep.PollRate = 1;
Qh = EhcCreateQh (Ehc, &Ep);
Qh = EhcCreateQh (Ehc, &Ep);
if (Qh == NULL) {
return EFI_OUT_OF_RESOURCES;
@@ -72,10 +72,10 @@ EhcCreateHelpQ (
//
// Create a dummy QH to act as the terminator for periodical schedule
//
Ep.EpAddr = 2;
Ep.Type = EHC_INT_TRANSFER_SYNC;
Ep.EpAddr = 2;
Ep.Type = EHC_INT_TRANSFER_SYNC;
Qh = EhcCreateQh (Ehc, &Ep);
Qh = EhcCreateQh (Ehc, &Ep);
if (Qh == NULL) {
return EFI_OUT_OF_RESOURCES;
@@ -98,7 +98,7 @@ EhcCreateHelpQ (
**/
EFI_STATUS
EhcInitSched (
IN PEI_USB2_HC_DEV *Ehc
IN PEI_USB2_HC_DEV *Ehc
)
{
VOID *Buf;
@@ -132,9 +132,9 @@ EhcInitSched (
return EFI_OUT_OF_RESOURCES;
}
Ehc->PeriodFrame = Buf;
Ehc->PeriodFrameMap = Map;
Ehc->High32bitAddr = EHC_HIGH_32BIT (PhyAddr);
Ehc->PeriodFrame = Buf;
Ehc->PeriodFrameMap = Map;
Ehc->High32bitAddr = EHC_HIGH_32BIT (PhyAddr);
//
// Init memory pool management then create the helper
@@ -160,8 +160,8 @@ EhcInitSched (
//
// Initialize the frame list entries then set the registers
//
Desc = (UINT32 *) Ehc->PeriodFrame;
PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Ehc->PeriodOne, sizeof (PEI_EHC_QH));
Desc = (UINT32 *)Ehc->PeriodFrame;
PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Ehc->PeriodOne, sizeof (PEI_EHC_QH));
for (Index = 0; Index < EHC_FRAME_LEN; Index++) {
Desc[Index] = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);
}
@@ -173,7 +173,7 @@ EhcInitSched (
// Only need to set the AsynListAddr register to
// the reclamation header
//
PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Ehc->ReclaimHead, sizeof (PEI_EHC_QH));
PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Ehc->ReclaimHead, sizeof (PEI_EHC_QH));
EhcWriteOpReg (Ehc, EHC_ASYNC_HEAD_OFFSET, EHC_LOW_32BIT (PciAddr));
return EFI_SUCCESS;
}
@@ -186,7 +186,7 @@ EhcInitSched (
**/
VOID
EhcFreeSched (
IN PEI_USB2_HC_DEV *Ehc
IN PEI_USB2_HC_DEV *Ehc
)
{
EhcWriteOpReg (Ehc, EHC_FRAME_BASE_OFFSET, 0);
@@ -231,24 +231,24 @@ EhcFreeSched (
**/
VOID
EhcLinkQhToAsync (
IN PEI_USB2_HC_DEV *Ehc,
IN PEI_EHC_QH *Qh
IN PEI_USB2_HC_DEV *Ehc,
IN PEI_EHC_QH *Qh
)
{
PEI_EHC_QH *Head;
PEI_EHC_QH *Head;
//
// Append the queue head after the reclaim header, then
// fix the hardware visiable parts (EHCI R1.0 page 72).
// ReclaimHead is always linked to the EHCI's AsynListAddr.
//
Head = Ehc->ReclaimHead;
Head = Ehc->ReclaimHead;
Qh->NextQh = Head->NextQh;
Head->NextQh = Qh;
Qh->NextQh = Head->NextQh;
Head->NextQh = Qh;
Qh->QhHw.HorizonLink = QH_LINK (Head, EHC_TYPE_QH, FALSE);;
Head->QhHw.HorizonLink = QH_LINK (Qh, EHC_TYPE_QH, FALSE);
Qh->QhHw.HorizonLink = QH_LINK (Head, EHC_TYPE_QH, FALSE);
Head->QhHw.HorizonLink = QH_LINK (Qh, EHC_TYPE_QH, FALSE);
}
/**
@@ -261,11 +261,11 @@ EhcLinkQhToAsync (
**/
VOID
EhcUnlinkQhFromAsync (
IN PEI_USB2_HC_DEV *Ehc,
IN PEI_EHC_QH *Qh
IN PEI_USB2_HC_DEV *Ehc,
IN PEI_EHC_QH *Qh
)
{
PEI_EHC_QH *Head;
PEI_EHC_QH *Head;
ASSERT (Ehc->ReclaimHead->NextQh == Qh);
@@ -274,12 +274,12 @@ EhcUnlinkQhFromAsync (
// visiable part: Only need to loopback the ReclaimHead. The Qh
// is pointing to ReclaimHead (which is staill in the list).
//
Head = Ehc->ReclaimHead;
Head = Ehc->ReclaimHead;
Head->NextQh = Qh->NextQh;
Qh->NextQh = NULL;
Head->NextQh = Qh->NextQh;
Qh->NextQh = NULL;
Head->QhHw.HorizonLink = QH_LINK (Head, EHC_TYPE_QH, FALSE);
Head->QhHw.HorizonLink = QH_LINK (Head, EHC_TYPE_QH, FALSE);
//
// Set and wait the door bell to synchronize with the hardware
@@ -302,22 +302,22 @@ EhcUnlinkQhFromAsync (
**/
BOOLEAN
EhcCheckUrbResult (
IN PEI_USB2_HC_DEV *Ehc,
IN PEI_URB *Urb
IN PEI_USB2_HC_DEV *Ehc,
IN PEI_URB *Urb
)
{
EFI_LIST_ENTRY *Entry;
PEI_EHC_QTD *Qtd;
QTD_HW *QtdHw;
UINT8 State;
BOOLEAN Finished;
EFI_LIST_ENTRY *Entry;
PEI_EHC_QTD *Qtd;
QTD_HW *QtdHw;
UINT8 State;
BOOLEAN Finished;
ASSERT ((Ehc != NULL) && (Urb != NULL) && (Urb->Qh != NULL));
Finished = TRUE;
Urb->Completed = 0;
Finished = TRUE;
Urb->Completed = 0;
Urb->Result = EFI_USB_NOERROR;
Urb->Result = EFI_USB_NOERROR;
if (EhcIsHalt (Ehc) || EhcIsSysError (Ehc)) {
Urb->Result |= EFI_USB_ERR_SYSTEM;
@@ -327,7 +327,7 @@ EhcCheckUrbResult (
BASE_LIST_FOR_EACH (Entry, &Urb->Qh->Qtds) {
Qtd = EFI_LIST_CONTAINER (Entry, PEI_EHC_QTD, QtdList);
QtdHw = &Qtd->QtdHw;
State = (UINT8) QtdHw->Status;
State = (UINT8)QtdHw->Status;
if (EHC_BIT_IS_SET (State, QTD_STAT_HALTED)) {
//
@@ -352,7 +352,6 @@ EhcCheckUrbResult (
Finished = TRUE;
goto ON_EXIT;
} else if (EHC_BIT_IS_SET (State, QTD_STAT_ACTIVE)) {
//
// The QTD is still active, no need to check furthur.
@@ -361,7 +360,6 @@ EhcCheckUrbResult (
Finished = FALSE;
goto ON_EXIT;
} else {
//
// This QTD is finished OK or met short packet read. Update the
@@ -372,7 +370,7 @@ EhcCheckUrbResult (
}
if ((QtdHw->TotalBytes != 0) && (QtdHw->Pid == QTD_PID_INPUT)) {
//EHC_DUMP_QH ((Urb->Qh, "Short packet read", FALSE));
// EHC_DUMP_QH ((Urb->Qh, "Short packet read", FALSE));
//
// Short packet read condition. If it isn't a setup transfer,
@@ -381,7 +379,6 @@ EhcCheckUrbResult (
// Status Stage of the setup transfer to get the finial result
//
if (QtdHw->AltNext == QTD_LINK (Ehc->ShortReadStop, FALSE)) {
Finished = TRUE;
goto ON_EXIT;
}
@@ -399,7 +396,7 @@ ON_EXIT:
// NOTICE: don't move DT update before the loop, otherwise there is
// a race condition that DT is wrong.
//
Urb->DataToggle = (UINT8) Urb->Qh->QhHw.DataToggle;
Urb->DataToggle = (UINT8)Urb->Qh->QhHw.DataToggle;
return Finished;
}
@@ -418,19 +415,19 @@ ON_EXIT:
**/
EFI_STATUS
EhcExecTransfer (
IN PEI_USB2_HC_DEV *Ehc,
IN PEI_URB *Urb,
IN UINTN TimeOut
IN PEI_USB2_HC_DEV *Ehc,
IN PEI_URB *Urb,
IN UINTN TimeOut
)
{
EFI_STATUS Status;
UINTN Index;
UINTN Loop;
BOOLEAN Finished;
BOOLEAN InfiniteLoop;
EFI_STATUS Status;
UINTN Index;
UINTN Loop;
BOOLEAN Finished;
BOOLEAN InfiniteLoop;
Status = EFI_SUCCESS;
Loop = TimeOut * EHC_1_MILLISECOND;
Status = EFI_SUCCESS;
Loop = TimeOut * EHC_1_MILLISECOND;
Finished = FALSE;
InfiniteLoop = FALSE;
@@ -460,4 +457,3 @@ EhcExecTransfer (
return Status;
}

18
MdeModulePkg/Bus/Pci/EhciPei/EhciSched.h
View File

@@ -21,7 +21,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
EFI_STATUS
EhcInitSched (
IN PEI_USB2_HC_DEV *Ehc
IN PEI_USB2_HC_DEV *Ehc
)
;
@@ -33,7 +33,7 @@ EhcInitSched (
**/
VOID
EhcFreeSched (
IN PEI_USB2_HC_DEV *Ehc
IN PEI_USB2_HC_DEV *Ehc
)
;
@@ -50,8 +50,8 @@ EhcFreeSched (
**/
VOID
EhcLinkQhToAsync (
IN PEI_USB2_HC_DEV *Ehc,
IN PEI_EHC_QH *Qh
IN PEI_USB2_HC_DEV *Ehc,
IN PEI_EHC_QH *Qh
)
;
@@ -65,8 +65,8 @@ EhcLinkQhToAsync (
**/
VOID
EhcUnlinkQhFromAsync (
IN PEI_USB2_HC_DEV *Ehc,
IN PEI_EHC_QH *Qh
IN PEI_USB2_HC_DEV *Ehc,
IN PEI_EHC_QH *Qh
)
;
@@ -84,9 +84,9 @@ EhcUnlinkQhFromAsync (
**/
EFI_STATUS
EhcExecTransfer (
IN PEI_USB2_HC_DEV *Ehc,
IN PEI_URB *Urb,
IN UINTN TimeOut
IN PEI_USB2_HC_DEV *Ehc,
IN PEI_URB *Urb,
IN UINTN TimeOut
)
;

297
MdeModulePkg/Bus/Pci/EhciPei/EhciUrb.c
View File

@@ -27,19 +27,19 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
PEI_EHC_QTD *
EhcCreateQtd (
IN PEI_USB2_HC_DEV *Ehc,
IN UINT8 *Data,
IN UINTN DataLen,
IN UINT8 PktId,
IN UINT8 Toggle,
IN UINTN MaxPacket
IN PEI_USB2_HC_DEV *Ehc,
IN UINT8 *Data,
IN UINTN DataLen,
IN UINT8 PktId,
IN UINT8 Toggle,
IN UINTN MaxPacket
)
{
PEI_EHC_QTD *Qtd;
QTD_HW *QtdHw;
UINTN Index;
UINTN Len;
UINTN ThisBufLen;
PEI_EHC_QTD *Qtd;
QTD_HW *QtdHw;
UINTN Index;
UINTN Len;
UINTN ThisBufLen;
ASSERT (Ehc != NULL);
@@ -49,9 +49,9 @@ EhcCreateQtd (
return NULL;
}
Qtd->Signature = EHC_QTD_SIG;
Qtd->Data = Data;
Qtd->DataLen = 0;
Qtd->Signature = EHC_QTD_SIG;
Qtd->Data = Data;
Qtd->DataLen = 0;
InitializeListHead (&Qtd->QtdList);
@@ -77,17 +77,17 @@ EhcCreateQtd (
// compute the offset and clear Reserved fields. This is already
// done in the data point.
//
QtdHw->Page[Index] = EHC_LOW_32BIT (Data);
QtdHw->PageHigh[Index] = EHC_HIGH_32BIT (Data);
QtdHw->Page[Index] = EHC_LOW_32BIT (Data);
QtdHw->PageHigh[Index] = EHC_HIGH_32BIT (Data);
ThisBufLen = QTD_BUF_LEN - (EHC_LOW_32BIT (Data) & QTD_BUF_MASK);
ThisBufLen = QTD_BUF_LEN - (EHC_LOW_32BIT (Data) & QTD_BUF_MASK);
if (Len + ThisBufLen >= DataLen) {
Len = DataLen;
break;
}
Len += ThisBufLen;
Len += ThisBufLen;
Data += ThisBufLen;
}
@@ -101,7 +101,7 @@ EhcCreateQtd (
Len = Len - Len % MaxPacket;
}
QtdHw->TotalBytes = (UINT32) Len;
QtdHw->TotalBytes = (UINT32)Len;
Qtd->DataLen = Len;
}
@@ -121,8 +121,8 @@ EhcCreateQtd (
**/
VOID
EhcInitIntQh (
IN USB_ENDPOINT *Ep,
IN QH_HW *QhHw
IN USB_ENDPOINT *Ep,
IN QH_HW *QhHw
)
{
//
@@ -134,7 +134,7 @@ EhcInitIntQh (
//
if (Ep->DevSpeed == EFI_USB_SPEED_HIGH) {
QhHw->SMask = QH_MICROFRAME_0;
return ;
return;
}
//
@@ -163,12 +163,12 @@ EhcInitIntQh (
**/
PEI_EHC_QH *
EhcCreateQh (
IN PEI_USB2_HC_DEV *Ehci,
IN USB_ENDPOINT *Ep
IN PEI_USB2_HC_DEV *Ehci,
IN USB_ENDPOINT *Ep
)
{
PEI_EHC_QH *Qh;
QH_HW *QhHw;
PEI_EHC_QH *Qh;
QH_HW *QhHw;
Qh = UsbHcAllocateMem (Ehci, Ehci->MemPool, sizeof (PEI_EHC_QH));
@@ -176,62 +176,63 @@ EhcCreateQh (
return NULL;
}
Qh->Signature = EHC_QH_SIG;
Qh->NextQh = NULL;
Qh->Interval = Ep->PollRate;
Qh->Signature = EHC_QH_SIG;
Qh->NextQh = NULL;
Qh->Interval = Ep->PollRate;
InitializeListHead (&Qh->Qtds);
QhHw = &Qh->QhHw;
QhHw->HorizonLink = QH_LINK (NULL, 0, TRUE);
QhHw->DeviceAddr = Ep->DevAddr;
QhHw->Inactive = 0;
QhHw->EpNum = Ep->EpAddr;
QhHw->EpSpeed = Ep->DevSpeed;
QhHw->DtCtrl = 0;
QhHw->ReclaimHead = 0;
QhHw->MaxPacketLen = (UINT32) Ep->MaxPacket;
QhHw->CtrlEp = 0;
QhHw->NakReload = QH_NAK_RELOAD;
QhHw->HubAddr = Ep->HubAddr;
QhHw->PortNum = Ep->HubPort;
QhHw->Multiplier = 1;
QhHw->DataToggle = Ep->Toggle;
QhHw = &Qh->QhHw;
QhHw->HorizonLink = QH_LINK (NULL, 0, TRUE);
QhHw->DeviceAddr = Ep->DevAddr;
QhHw->Inactive = 0;
QhHw->EpNum = Ep->EpAddr;
QhHw->EpSpeed = Ep->DevSpeed;
QhHw->DtCtrl = 0;
QhHw->ReclaimHead = 0;
QhHw->MaxPacketLen = (UINT32)Ep->MaxPacket;
QhHw->CtrlEp = 0;
QhHw->NakReload = QH_NAK_RELOAD;
QhHw->HubAddr = Ep->HubAddr;
QhHw->PortNum = Ep->HubPort;
QhHw->Multiplier = 1;
QhHw->DataToggle = Ep->Toggle;
if (Ep->DevSpeed != EFI_USB_SPEED_HIGH) {
QhHw->Status |= QTD_STAT_DO_SS;
}
switch (Ep->Type) {
case EHC_CTRL_TRANSFER:
//
// Special initialization for the control transfer:
// 1. Control transfer initialize data toggle from each QTD
// 2. Set the Control Endpoint Flag (C) for low/full speed endpoint.
//
QhHw->DtCtrl = 1;
case EHC_CTRL_TRANSFER:
//
// Special initialization for the control transfer:
// 1. Control transfer initialize data toggle from each QTD
// 2. Set the Control Endpoint Flag (C) for low/full speed endpoint.
//
QhHw->DtCtrl = 1;
if (Ep->DevSpeed != EFI_USB_SPEED_HIGH) {
QhHw->CtrlEp = 1;
}
break;
if (Ep->DevSpeed != EFI_USB_SPEED_HIGH) {
QhHw->CtrlEp = 1;
}
case EHC_INT_TRANSFER_ASYNC:
case EHC_INT_TRANSFER_SYNC:
//
// Special initialization for the interrupt transfer
// to set the S-Mask and C-Mask
//
QhHw->NakReload = 0;
EhcInitIntQh (Ep, QhHw);
break;
break;
case EHC_BULK_TRANSFER:
if ((Ep->DevSpeed == EFI_USB_SPEED_HIGH) && (Ep->Direction == EfiUsbDataOut)) {
QhHw->Status |= QTD_STAT_DO_PING;
}
case EHC_INT_TRANSFER_ASYNC:
case EHC_INT_TRANSFER_SYNC:
//
// Special initialization for the interrupt transfer
// to set the S-Mask and C-Mask
//
QhHw->NakReload = 0;
EhcInitIntQh (Ep, QhHw);
break;
break;
case EHC_BULK_TRANSFER:
if ((Ep->DevSpeed == EFI_USB_SPEED_HIGH) && (Ep->Direction == EfiUsbDataOut)) {
QhHw->Status |= QTD_STAT_DO_PING;
}
break;
}
return Qh;
@@ -252,10 +253,10 @@ EhcCreateQh (
**/
UINTN
EhcConvertPollRate (
IN UINTN Interval
IN UINTN Interval
)
{
UINTN BitCount;
UINTN BitCount;
if (Interval == 0) {
return 1;
@@ -283,13 +284,13 @@ EhcConvertPollRate (
**/
VOID
EhcFreeQtds (
IN PEI_USB2_HC_DEV *Ehc,
IN EFI_LIST_ENTRY *Qtds
IN PEI_USB2_HC_DEV *Ehc,
IN EFI_LIST_ENTRY *Qtds
)
{
EFI_LIST_ENTRY *Entry;
EFI_LIST_ENTRY *Next;
PEI_EHC_QTD *Qtd;
EFI_LIST_ENTRY *Entry;
EFI_LIST_ENTRY *Next;
PEI_EHC_QTD *Qtd;
BASE_LIST_FOR_EACH_SAFE (Entry, Next, Qtds) {
Qtd = EFI_LIST_CONTAINER (Entry, PEI_EHC_QTD, QtdList);
@@ -308,8 +309,8 @@ EhcFreeQtds (
**/
VOID
EhcFreeUrb (
IN PEI_USB2_HC_DEV *Ehc,
IN PEI_URB *Urb
IN PEI_USB2_HC_DEV *Ehc,
IN PEI_URB *Urb
)
{
if (Urb->RequestPhy != NULL) {
@@ -342,20 +343,20 @@ EhcFreeUrb (
**/
EFI_STATUS
EhcCreateQtds (
IN PEI_USB2_HC_DEV *Ehc,
IN PEI_URB *Urb
IN PEI_USB2_HC_DEV *Ehc,
IN PEI_URB *Urb
)
{
USB_ENDPOINT *Ep;
PEI_EHC_QH *Qh;
PEI_EHC_QTD *Qtd;
PEI_EHC_QTD *StatusQtd;
PEI_EHC_QTD *NextQtd;
EFI_LIST_ENTRY *Entry;
UINT32 AlterNext;
UINT8 Toggle;
UINTN Len;
UINT8 Pid;
USB_ENDPOINT *Ep;
PEI_EHC_QH *Qh;
PEI_EHC_QTD *Qtd;
PEI_EHC_QTD *StatusQtd;
PEI_EHC_QTD *NextQtd;
EFI_LIST_ENTRY *Entry;
UINT32 AlterNext;
UINT8 Toggle;
UINTN Len;
UINT8 Pid;
ASSERT ((Urb != NULL) && (Urb->Qh != NULL));
@@ -428,7 +429,7 @@ EhcCreateQtds (
while (Len < Urb->DataLen) {
Qtd = EhcCreateQtd (
Ehc,
(UINT8 *) Urb->DataPhy + Len,
(UINT8 *)Urb->DataPhy + Len,
Urb->DataLen - Len,
Pid,
Toggle,
@@ -446,7 +447,7 @@ EhcCreateQtds (
// Switch the Toggle bit if odd number of packets are included in the QTD.
//
if (((Qtd->DataLen + Ep->MaxPacket - 1) / Ep->MaxPacket) % 2) {
Toggle = (UINT8) (1 - Toggle);
Toggle = (UINT8)(1 - Toggle);
}
Len += Qtd->DataLen;
@@ -472,15 +473,15 @@ EhcCreateQtds (
break;
}
NextQtd = EFI_LIST_CONTAINER (Entry->ForwardLink, PEI_EHC_QTD, QtdList);
Qtd->QtdHw.NextQtd = QTD_LINK (NextQtd, FALSE);
NextQtd = EFI_LIST_CONTAINER (Entry->ForwardLink, PEI_EHC_QTD, QtdList);
Qtd->QtdHw.NextQtd = QTD_LINK (NextQtd, FALSE);
}
//
// Link the QTDs to the queue head
//
NextQtd = EFI_LIST_CONTAINER (Qh->Qtds.ForwardLink, PEI_EHC_QTD, QtdList);
Qh->QhHw.NextQtd = QTD_LINK (NextQtd, FALSE);
NextQtd = EFI_LIST_CONTAINER (Qh->Qtds.ForwardLink, PEI_EHC_QTD, QtdList);
Qh->QhHw.NextQtd = QTD_LINK (NextQtd, FALSE);
return EFI_SUCCESS;
ON_ERROR:
@@ -511,63 +512,63 @@ ON_ERROR:
**/
PEI_URB *
EhcCreateUrb (
IN PEI_USB2_HC_DEV *Ehc,
IN UINT8 DevAddr,
IN UINT8 EpAddr,
IN UINT8 DevSpeed,
IN UINT8 Toggle,
IN UINTN MaxPacket,
IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Hub,
IN UINTN Type,
IN EFI_USB_DEVICE_REQUEST *Request,
IN VOID *Data,
IN UINTN DataLen,
IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
IN VOID *Context,
IN UINTN Interval
IN PEI_USB2_HC_DEV *Ehc,
IN UINT8 DevAddr,
IN UINT8 EpAddr,
IN UINT8 DevSpeed,
IN UINT8 Toggle,
IN UINTN MaxPacket,
IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Hub,
IN UINTN Type,
IN EFI_USB_DEVICE_REQUEST *Request,
IN VOID *Data,
IN UINTN DataLen,
IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
IN VOID *Context,
IN UINTN Interval
)
{
USB_ENDPOINT *Ep;
EFI_PHYSICAL_ADDRESS PhyAddr;
EDKII_IOMMU_OPERATION MapOp;
EFI_STATUS Status;
UINTN Len;
PEI_URB *Urb;
VOID *Map;
USB_ENDPOINT *Ep;
EFI_PHYSICAL_ADDRESS PhyAddr;
EDKII_IOMMU_OPERATION MapOp;
EFI_STATUS Status;
UINTN Len;
PEI_URB *Urb;
VOID *Map;
Map = NULL;
Urb = Ehc->Urb;
Urb->Signature = EHC_URB_SIG;
Urb = Ehc->Urb;
Urb->Signature = EHC_URB_SIG;
InitializeListHead (&Urb->UrbList);
Ep = &Urb->Ep;
Ep->DevAddr = DevAddr;
Ep->EpAddr = (UINT8) (EpAddr & 0x0F);
Ep->Direction = (((EpAddr & 0x80) != 0) ? EfiUsbDataIn : EfiUsbDataOut);
Ep->DevSpeed = DevSpeed;
Ep->MaxPacket = MaxPacket;
Ep = &Urb->Ep;
Ep->DevAddr = DevAddr;
Ep->EpAddr = (UINT8)(EpAddr & 0x0F);
Ep->Direction = (((EpAddr & 0x80) != 0) ? EfiUsbDataIn : EfiUsbDataOut);
Ep->DevSpeed = DevSpeed;
Ep->MaxPacket = MaxPacket;
Ep->HubAddr = 0;
Ep->HubPort = 0;
Ep->HubAddr = 0;
Ep->HubPort = 0;
if (DevSpeed != EFI_USB_SPEED_HIGH) {
ASSERT (Hub != NULL);
Ep->HubAddr = Hub->TranslatorHubAddress;
Ep->HubPort = Hub->TranslatorPortNumber;
Ep->HubAddr = Hub->TranslatorHubAddress;
Ep->HubPort = Hub->TranslatorPortNumber;
}
Ep->Toggle = Toggle;
Ep->Type = Type;
Ep->PollRate = EhcConvertPollRate (Interval);
Ep->Toggle = Toggle;
Ep->Type = Type;
Ep->PollRate = EhcConvertPollRate (Interval);
Urb->Request = Request;
Urb->Data = Data;
Urb->DataLen = DataLen;
Urb->Callback = Callback;
Urb->Context = Context;
Urb->Qh = EhcCreateQh (Ehc, &Urb->Ep);
Urb->Request = Request;
Urb->Data = Data;
Urb->DataLen = DataLen;
Urb->Callback = Callback;
Urb->Context = Context;
Urb->Qh = EhcCreateQh (Ehc, &Urb->Ep);
if (Urb->Qh == NULL) {
goto ON_ERROR;
@@ -575,27 +576,27 @@ EhcCreateUrb (
Urb->RequestPhy = NULL;
Urb->RequestMap = NULL;
Urb->DataPhy = NULL;
Urb->DataMap = NULL;
Urb->DataPhy = NULL;
Urb->DataMap = NULL;
//
// Map the request and user data
//
if (Request != NULL) {
Len = sizeof (EFI_USB_DEVICE_REQUEST);
MapOp = EdkiiIoMmuOperationBusMasterRead;
Status = IoMmuMap (Ehc->IoMmu, MapOp, Request, &Len, &PhyAddr, &Map);
Len = sizeof (EFI_USB_DEVICE_REQUEST);
MapOp = EdkiiIoMmuOperationBusMasterRead;
Status = IoMmuMap (Ehc->IoMmu, MapOp, Request, &Len, &PhyAddr, &Map);
if (EFI_ERROR (Status) || (Len != sizeof (EFI_USB_DEVICE_REQUEST))) {
goto ON_ERROR;
}
Urb->RequestPhy = (VOID *) ((UINTN) PhyAddr);
Urb->RequestPhy = (VOID *)((UINTN)PhyAddr);
Urb->RequestMap = Map;
}
if (Data != NULL) {
Len = DataLen;
Len = DataLen;
if (Ep->Direction == EfiUsbDataIn) {
MapOp = EdkiiIoMmuOperationBusMasterWrite;
@@ -603,14 +604,14 @@ EhcCreateUrb (
MapOp = EdkiiIoMmuOperationBusMasterRead;
}
Status = IoMmuMap (Ehc->IoMmu, MapOp, Data, &Len, &PhyAddr, &Map);
Status = IoMmuMap (Ehc->IoMmu, MapOp, Data, &Len, &PhyAddr, &Map);
if (EFI_ERROR (Status) || (Len != DataLen)) {
goto ON_ERROR;
}
Urb->DataPhy = (VOID *) ((UINTN) PhyAddr);
Urb->DataMap = Map;
Urb->DataPhy = (VOID *)((UINTN)PhyAddr);
Urb->DataMap = Map;
}
Status = EhcCreateQtds (Ehc, Urb);

278
MdeModulePkg/Bus/Pci/EhciPei/EhciUrb.h
View File

@@ -10,60 +10,60 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#ifndef _EFI_EHCI_URB_H_
#define _EFI_EHCI_URB_H_
typedef struct _PEI_EHC_QTD PEI_EHC_QTD;
typedef struct _PEI_EHC_QH PEI_EHC_QH;
typedef struct _PEI_URB PEI_URB;
typedef struct _PEI_EHC_QTD PEI_EHC_QTD;
typedef struct _PEI_EHC_QH PEI_EHC_QH;
typedef struct _PEI_URB PEI_URB;
#define EHC_CTRL_TRANSFER 0x01
#define EHC_BULK_TRANSFER 0x02
#define EHC_INT_TRANSFER_SYNC 0x04
#define EHC_INT_TRANSFER_ASYNC 0x08
#define EHC_QTD_SIG SIGNATURE_32 ('U', 'S', 'B', 'T')
#define EHC_QH_SIG SIGNATURE_32 ('U', 'S', 'B', 'H')
#define EHC_URB_SIG SIGNATURE_32 ('U', 'S', 'B', 'R')
#define EHC_QTD_SIG SIGNATURE_32 ('U', 'S', 'B', 'T')
#define EHC_QH_SIG SIGNATURE_32 ('U', 'S', 'B', 'H')
#define EHC_URB_SIG SIGNATURE_32 ('U', 'S', 'B', 'R')
//
// Hardware related bit definitions
//
#define EHC_TYPE_ITD 0x00
#define EHC_TYPE_QH 0x02
#define EHC_TYPE_SITD 0x04
#define EHC_TYPE_FSTN 0x06
#define EHC_TYPE_ITD 0x00
#define EHC_TYPE_QH 0x02
#define EHC_TYPE_SITD 0x04
#define EHC_TYPE_FSTN 0x06
#define QH_NAK_RELOAD 3
#define QH_HSHBW_MULTI 1
#define QH_NAK_RELOAD 3
#define QH_HSHBW_MULTI 1
#define QTD_MAX_ERR 3
#define QTD_PID_OUTPUT 0x00
#define QTD_PID_INPUT 0x01
#define QTD_PID_SETUP 0x02
#define QTD_MAX_ERR 3
#define QTD_PID_OUTPUT 0x00
#define QTD_PID_INPUT 0x01
#define QTD_PID_SETUP 0x02
#define QTD_STAT_DO_OUT 0
#define QTD_STAT_DO_SS 0
#define QTD_STAT_DO_PING 0x01
#define QTD_STAT_DO_CS 0x02
#define QTD_STAT_TRANS_ERR 0x08
#define QTD_STAT_BABBLE_ERR 0x10
#define QTD_STAT_BUFF_ERR 0x20
#define QTD_STAT_HALTED 0x40
#define QTD_STAT_ACTIVE 0x80
#define QTD_STAT_ERR_MASK (QTD_STAT_TRANS_ERR | QTD_STAT_BABBLE_ERR | QTD_STAT_BUFF_ERR)
#define QTD_STAT_DO_OUT 0
#define QTD_STAT_DO_SS 0
#define QTD_STAT_DO_PING 0x01
#define QTD_STAT_DO_CS 0x02
#define QTD_STAT_TRANS_ERR 0x08
#define QTD_STAT_BABBLE_ERR 0x10
#define QTD_STAT_BUFF_ERR 0x20
#define QTD_STAT_HALTED 0x40
#define QTD_STAT_ACTIVE 0x80
#define QTD_STAT_ERR_MASK (QTD_STAT_TRANS_ERR | QTD_STAT_BABBLE_ERR | QTD_STAT_BUFF_ERR)
#define QTD_MAX_BUFFER 4
#define QTD_BUF_LEN 4096
#define QTD_BUF_MASK 0x0FFF
#define QTD_MAX_BUFFER 4
#define QTD_BUF_LEN 4096
#define QTD_BUF_MASK 0x0FFF
#define QH_MICROFRAME_0 0x01
#define QH_MICROFRAME_1 0x02
#define QH_MICROFRAME_2 0x04
#define QH_MICROFRAME_3 0x08
#define QH_MICROFRAME_4 0x10
#define QH_MICROFRAME_5 0x20
#define QH_MICROFRAME_6 0x40
#define QH_MICROFRAME_7 0x80
#define QH_MICROFRAME_0 0x01
#define QH_MICROFRAME_1 0x02
#define QH_MICROFRAME_2 0x04
#define QH_MICROFRAME_3 0x08
#define QH_MICROFRAME_4 0x10
#define QH_MICROFRAME_5 0x20
#define QH_MICROFRAME_6 0x40
#define QH_MICROFRAME_7 0x80
#define USB_ERR_SHORT_PACKET 0x200
#define USB_ERR_SHORT_PACKET 0x200
//
// Fill in the hardware link point: pass in a EHC_QH/QH_HW
@@ -72,7 +72,7 @@ typedef struct _PEI_URB PEI_URB;
#define QH_LINK(Addr, Type, Term) \
((UINT32) ((EHC_LOW_32BIT (Addr) & 0xFFFFFFE0) | (Type) | ((Term) ? 1 : 0)))
#define QTD_LINK(Addr, Term) QH_LINK((Addr), 0, (Term))
#define QTD_LINK(Addr, Term) QH_LINK((Addr), 0, (Term))
//
// The defination of EHCI hardware used data structure for
@@ -82,77 +82,76 @@ typedef struct _PEI_URB PEI_URB;
//
#pragma pack(1)
typedef struct {
UINT32 NextQtd;
UINT32 AltNext;
UINT32 NextQtd;
UINT32 AltNext;
UINT32 Status : 8;
UINT32 Pid : 2;
UINT32 ErrCnt : 2;
UINT32 CurPage : 3;
UINT32 Ioc : 1;
UINT32 TotalBytes : 15;
UINT32 DataToggle : 1;
UINT32 Status : 8;
UINT32 Pid : 2;
UINT32 ErrCnt : 2;
UINT32 CurPage : 3;
UINT32 Ioc : 1;
UINT32 TotalBytes : 15;
UINT32 DataToggle : 1;
UINT32 Page[5];
UINT32 PageHigh[5];
UINT32 Page[5];
UINT32 PageHigh[5];
} QTD_HW;
typedef struct {
UINT32 HorizonLink;
UINT32 HorizonLink;
//
// Endpoint capabilities/Characteristics DWord 1 and DWord 2
//
UINT32 DeviceAddr : 7;
UINT32 Inactive : 1;
UINT32 EpNum : 4;
UINT32 EpSpeed : 2;
UINT32 DtCtrl : 1;
UINT32 ReclaimHead : 1;
UINT32 MaxPacketLen : 11;
UINT32 CtrlEp : 1;
UINT32 NakReload : 4;
UINT32 DeviceAddr : 7;
UINT32 Inactive : 1;
UINT32 EpNum : 4;
UINT32 EpSpeed : 2;
UINT32 DtCtrl : 1;
UINT32 ReclaimHead : 1;
UINT32 MaxPacketLen : 11;
UINT32 CtrlEp : 1;
UINT32 NakReload : 4;
UINT32 SMask : 8;
UINT32 CMask : 8;
UINT32 HubAddr : 7;
UINT32 PortNum : 7;
UINT32 Multiplier : 2;
UINT32 SMask : 8;
UINT32 CMask : 8;
UINT32 HubAddr : 7;
UINT32 PortNum : 7;
UINT32 Multiplier : 2;
//
// Transaction execution overlay area
//
UINT32 CurQtd;
UINT32 NextQtd;
UINT32 AltQtd;
UINT32 CurQtd;
UINT32 NextQtd;
UINT32 AltQtd;
UINT32 Status : 8;
UINT32 Pid : 2;
UINT32 ErrCnt : 2;
UINT32 CurPage : 3;
UINT32 Ioc : 1;
UINT32 TotalBytes : 15;
UINT32 DataToggle : 1;
UINT32 Status : 8;
UINT32 Pid : 2;
UINT32 ErrCnt : 2;
UINT32 CurPage : 3;
UINT32 Ioc : 1;
UINT32 TotalBytes : 15;
UINT32 DataToggle : 1;
UINT32 Page[5];
UINT32 PageHigh[5];
UINT32 Page[5];
UINT32 PageHigh[5];
} QH_HW;
#pragma pack()
//
// Endpoint address and its capabilities
//
typedef struct _USB_ENDPOINT {
UINT8 DevAddr;
UINT8 EpAddr; // Endpoint address, no direction encoded in
EFI_USB_DATA_DIRECTION Direction;
UINT8 DevSpeed;
UINTN MaxPacket;
UINT8 HubAddr;
UINT8 HubPort;
UINT8 Toggle; // Data toggle, not used for control transfer
UINTN Type;
UINTN PollRate; // Polling interval used by EHCI
UINT8 DevAddr;
UINT8 EpAddr; // Endpoint address, no direction encoded in
EFI_USB_DATA_DIRECTION Direction;
UINT8 DevSpeed;
UINTN MaxPacket;
UINT8 HubAddr;
UINT8 HubPort;
UINT8 Toggle; // Data toggle, not used for control transfer
UINTN Type;
UINTN PollRate; // Polling interval used by EHCI
} USB_ENDPOINT;
//
@@ -160,15 +159,13 @@ typedef struct _USB_ENDPOINT {
// QTD generated from a URB. Don't add fields before QtdHw.
//
struct _PEI_EHC_QTD {
QTD_HW QtdHw;
UINT32 Signature;
EFI_LIST_ENTRY QtdList; // The list of QTDs to one end point
UINT8 *Data; // Buffer of the original data
UINTN DataLen; // Original amount of data in this QTD
QTD_HW QtdHw;
UINT32 Signature;
EFI_LIST_ENTRY QtdList; // The list of QTDs to one end point
UINT8 *Data; // Buffer of the original data
UINTN DataLen; // Original amount of data in this QTD
};
//
// Software QH structure. All three different transaction types
// supported by UEFI USB, that is the control/bulk/interrupt
@@ -185,11 +182,11 @@ struct _PEI_EHC_QTD {
// as the reclamation header. New transfer is inserted after this QH.
//
struct _PEI_EHC_QH {
QH_HW QhHw;
UINT32 Signature;
PEI_EHC_QH *NextQh; // The queue head pointed to by horizontal link
EFI_LIST_ENTRY Qtds; // The list of QTDs to this queue head
UINTN Interval;
QH_HW QhHw;
UINT32 Signature;
PEI_EHC_QH *NextQh; // The queue head pointed to by horizontal link
EFI_LIST_ENTRY Qtds; // The list of QTDs to this queue head
UINTN Interval;
};
//
@@ -197,34 +194,34 @@ struct _PEI_EHC_QH {
// usb requests.
//
struct _PEI_URB {
UINT32 Signature;
EFI_LIST_ENTRY UrbList;
UINT32 Signature;
EFI_LIST_ENTRY UrbList;
//
// Transaction information
//
USB_ENDPOINT Ep;
EFI_USB_DEVICE_REQUEST *Request; // Control transfer only
VOID *RequestPhy; // Address of the mapped request
VOID *RequestMap;
VOID *Data;
UINTN DataLen;
VOID *DataPhy; // Address of the mapped user data
VOID *DataMap;
EFI_ASYNC_USB_TRANSFER_CALLBACK Callback;
VOID *Context;
USB_ENDPOINT Ep;
EFI_USB_DEVICE_REQUEST *Request; // Control transfer only
VOID *RequestPhy; // Address of the mapped request
VOID *RequestMap;
VOID *Data;
UINTN DataLen;
VOID *DataPhy; // Address of the mapped user data
VOID *DataMap;
EFI_ASYNC_USB_TRANSFER_CALLBACK Callback;
VOID *Context;
//
// Schedule data
//
PEI_EHC_QH *Qh;
PEI_EHC_QH *Qh;
//
// Transaction result
//
UINT32 Result;
UINTN Completed; // completed data length
UINT8 DataToggle;
UINT32 Result;
UINTN Completed; // completed data length
UINT8 DataToggle;
};
/**
@@ -243,12 +240,12 @@ struct _PEI_URB {
**/
PEI_EHC_QTD *
EhcCreateQtd (
IN PEI_USB2_HC_DEV *Ehc,
IN UINT8 *Data,
IN UINTN DataLen,
IN UINT8 PktId,
IN UINT8 Toggle,
IN UINTN MaxPacket
IN PEI_USB2_HC_DEV *Ehc,
IN UINT8 *Data,
IN UINTN DataLen,
IN UINT8 PktId,
IN UINT8 Toggle,
IN UINTN MaxPacket
)
;
@@ -263,8 +260,8 @@ EhcCreateQtd (
**/
PEI_EHC_QH *
EhcCreateQh (
IN PEI_USB2_HC_DEV *Ehci,
IN USB_ENDPOINT *Ep
IN PEI_USB2_HC_DEV *Ehci,
IN USB_ENDPOINT *Ep
)
;
@@ -277,8 +274,8 @@ EhcCreateQh (
**/
VOID
EhcFreeUrb (
IN PEI_USB2_HC_DEV *Ehc,
IN PEI_URB *Urb
IN PEI_USB2_HC_DEV *Ehc,
IN PEI_URB *Urb
)
;
@@ -305,20 +302,21 @@ EhcFreeUrb (
**/
PEI_URB *
EhcCreateUrb (
IN PEI_USB2_HC_DEV *Ehc,
IN UINT8 DevAddr,
IN UINT8 EpAddr,
IN UINT8 DevSpeed,
IN UINT8 Toggle,
IN UINTN MaxPacket,
IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Hub,
IN UINTN Type,
IN EFI_USB_DEVICE_REQUEST *Request,
IN VOID *Data,
IN UINTN DataLen,
IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
IN VOID *Context,
IN UINTN Interval
IN PEI_USB2_HC_DEV *Ehc,
IN UINT8 DevAddr,
IN UINT8 EpAddr,
IN UINT8 DevSpeed,
IN UINT8 Toggle,
IN UINTN MaxPacket,
IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Hub,
IN UINTN Type,
IN EFI_USB_DEVICE_REQUEST *Request,
IN VOID *Data,
IN UINTN DataLen,
IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
IN VOID *Context,
IN UINTN Interval
)
;
#endif

243
MdeModulePkg/Bus/Pci/EhciPei/UsbHcMem.c
View File

@@ -22,30 +22,31 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
USBHC_MEM_BLOCK *
UsbHcAllocMemBlock (
IN PEI_USB2_HC_DEV *Ehc,
IN USBHC_MEM_POOL *Pool,
IN UINTN Pages
IN PEI_USB2_HC_DEV *Ehc,
IN USBHC_MEM_POOL *Pool,
IN UINTN Pages
)
{
USBHC_MEM_BLOCK *Block;
VOID *BufHost;
VOID *Mapping;
EFI_PHYSICAL_ADDRESS MappedAddr;
EFI_STATUS Status;
UINTN PageNumber;
EFI_PHYSICAL_ADDRESS TempPtr;
USBHC_MEM_BLOCK *Block;
VOID *BufHost;
VOID *Mapping;
EFI_PHYSICAL_ADDRESS MappedAddr;
EFI_STATUS Status;
UINTN PageNumber;
EFI_PHYSICAL_ADDRESS TempPtr;
Mapping = NULL;
PageNumber = sizeof(USBHC_MEM_BLOCK)/PAGESIZE +1;
Status = PeiServicesAllocatePages (
EfiBootServicesCode,
PageNumber,
&TempPtr
);
Mapping = NULL;
PageNumber = sizeof (USBHC_MEM_BLOCK)/PAGESIZE +1;
Status = PeiServicesAllocatePages (
EfiBootServicesCode,
PageNumber,
&TempPtr
);
if (EFI_ERROR (Status)) {
return NULL;
return NULL;
}
ZeroMem ((VOID *)(UINTN)TempPtr, PageNumber*EFI_PAGE_SIZE);
//
@@ -54,34 +55,36 @@ UsbHcAllocMemBlock (
//
ASSERT (USBHC_MEM_UNIT * 8 <= EFI_PAGE_SIZE);
Block = (USBHC_MEM_BLOCK*)(UINTN)TempPtr;
Block->BufLen = EFI_PAGES_TO_SIZE (Pages);
Block->BitsLen = Block->BufLen / (USBHC_MEM_UNIT * 8);
Block = (USBHC_MEM_BLOCK *)(UINTN)TempPtr;
Block->BufLen = EFI_PAGES_TO_SIZE (Pages);
Block->BitsLen = Block->BufLen / (USBHC_MEM_UNIT * 8);
PageNumber = (Block->BitsLen)/PAGESIZE +1;
Status = PeiServicesAllocatePages (
EfiBootServicesCode,
PageNumber,
&TempPtr
);
Status = PeiServicesAllocatePages (
EfiBootServicesCode,
PageNumber,
&TempPtr
);
if (EFI_ERROR (Status)) {
return NULL;
}
if (EFI_ERROR (Status)) {
return NULL;
}
ZeroMem ((VOID *)(UINTN)TempPtr, PageNumber*EFI_PAGE_SIZE);
Block->Bits = (UINT8 *)(UINTN)TempPtr;
Block->Bits = (UINT8 *)(UINTN)TempPtr;
Status = IoMmuAllocateBuffer (
Ehc->IoMmu,
Pages,
(VOID **) &BufHost,
(VOID **)&BufHost,
&MappedAddr,
&Mapping
);
if (EFI_ERROR (Status)) {
return NULL;
}
ZeroMem (BufHost, Pages*EFI_PAGE_SIZE);
//
@@ -89,16 +92,15 @@ UsbHcAllocMemBlock (
// should be restricted into the same 4G
//
if (Pool->Check4G && (Pool->Which4G != USB_HC_HIGH_32BIT (MappedAddr))) {
return NULL;
return NULL;
}
Block->BufHost = BufHost;
Block->Buf = (UINT8 *) ((UINTN) MappedAddr);
Block->Mapping = Mapping;
Block->Next = NULL;
Block->BufHost = BufHost;
Block->Buf = (UINT8 *)((UINTN)MappedAddr);
Block->Mapping = Mapping;
Block->Next = NULL;
return Block;
}
/**
@@ -111,9 +113,9 @@ UsbHcAllocMemBlock (
**/
VOID
UsbHcFreeMemBlock (
IN PEI_USB2_HC_DEV *Ehc,
IN USBHC_MEM_POOL *Pool,
IN USBHC_MEM_BLOCK *Block
IN PEI_USB2_HC_DEV *Ehc,
IN USBHC_MEM_POOL *Pool,
IN USBHC_MEM_BLOCK *Block
)
{
ASSERT ((Pool != NULL) && (Block != NULL));
@@ -133,22 +135,22 @@ UsbHcFreeMemBlock (
**/
VOID *
UsbHcAllocMemFromBlock (
IN USBHC_MEM_BLOCK *Block,
IN UINTN Units
IN USBHC_MEM_BLOCK *Block,
IN UINTN Units
)
{
UINTN Byte;
UINT8 Bit;
UINTN StartByte;
UINT8 StartBit;
UINTN Available;
UINTN Count;
UINTN Byte;
UINT8 Bit;
UINTN StartByte;
UINT8 StartBit;
UINTN Available;
UINTN Count;
ASSERT ((Block != 0) && (Units != 0));
StartByte = 0;
StartBit = 0;
Available = 0;
StartByte = 0;
StartBit = 0;
Available = 0;
for (Byte = 0, Bit = 0; Byte < Block->BitsLen;) {
//
@@ -164,13 +166,12 @@ UsbHcAllocMemFromBlock (
}
NEXT_BIT (Byte, Bit);
} else {
NEXT_BIT (Byte, Bit);
Available = 0;
StartByte = Byte;
StartBit = Bit;
Available = 0;
StartByte = Byte;
StartBit = Bit;
}
}
@@ -181,13 +182,13 @@ UsbHcAllocMemFromBlock (
//
// Mark the memory as allocated
//
Byte = StartByte;
Bit = StartBit;
Byte = StartByte;
Bit = StartBit;
for (Count = 0; Count < Units; Count++) {
ASSERT (!USB_HC_BIT_IS_SET (Block->Bits[Byte], Bit));
Block->Bits[Byte] = (UINT8) (Block->Bits[Byte] | (UINT8) USB_HC_BIT (Bit));
Block->Bits[Byte] = (UINT8)(Block->Bits[Byte] | (UINT8)USB_HC_BIT (Bit));
NEXT_BIT (Byte, Bit);
}
@@ -205,16 +206,16 @@ UsbHcAllocMemFromBlock (
**/
EFI_PHYSICAL_ADDRESS
UsbHcGetPciAddressForHostMem (
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
)
{
USBHC_MEM_BLOCK *Head;
USBHC_MEM_BLOCK *Block;
UINTN AllocSize;
EFI_PHYSICAL_ADDRESS PhyAddr;
UINTN Offset;
USBHC_MEM_BLOCK *Head;
USBHC_MEM_BLOCK *Block;
UINTN AllocSize;
EFI_PHYSICAL_ADDRESS PhyAddr;
UINTN Offset;
Head = Pool->Head;
AllocSize = USBHC_MEM_ROUND (Size);
@@ -228,7 +229,7 @@ UsbHcGetPciAddressForHostMem (
// scan the memory block list for the memory block that
// completely contains the allocated memory.
//
if ((Block->BufHost <= (UINT8 *) Mem) && (((UINT8 *) Mem + AllocSize) <= (Block->BufHost + Block->BufLen))) {
if ((Block->BufHost <= (UINT8 *)Mem) && (((UINT8 *)Mem + AllocSize) <= (Block->BufHost + Block->BufLen))) {
break;
}
}
@@ -237,8 +238,8 @@ UsbHcGetPciAddressForHostMem (
//
// calculate the pci memory address for host memory address.
//
Offset = (UINT8 *)Mem - Block->BufHost;
PhyAddr = (EFI_PHYSICAL_ADDRESS)(UINTN) (Block->Buf + Offset);
Offset = (UINT8 *)Mem - Block->BufHost;
PhyAddr = (EFI_PHYSICAL_ADDRESS)(UINTN)(Block->Buf + Offset);
return PhyAddr;
}
@@ -251,8 +252,8 @@ UsbHcGetPciAddressForHostMem (
**/
VOID
UsbHcInsertMemBlockToPool (
IN USBHC_MEM_BLOCK *Head,
IN USBHC_MEM_BLOCK *Block
IN USBHC_MEM_BLOCK *Head,
IN USBHC_MEM_BLOCK *Block
)
{
ASSERT ((Head != NULL) && (Block != NULL));
@@ -271,11 +272,10 @@ UsbHcInsertMemBlockToPool (
**/
BOOLEAN
UsbHcIsMemBlockEmpty (
IN USBHC_MEM_BLOCK *Block
IN USBHC_MEM_BLOCK *Block
)
{
UINTN Index;
UINTN Index;
for (Index = 0; Index < Block->BitsLen; Index++) {
if (Block->Bits[Index] != 0) {
@@ -286,7 +286,6 @@ UsbHcIsMemBlockEmpty (
return TRUE;
}
/**
Initialize the memory management pool for the host controller.
@@ -301,29 +300,30 @@ UsbHcIsMemBlockEmpty (
**/
USBHC_MEM_POOL *
UsbHcInitMemPool (
IN PEI_USB2_HC_DEV *Ehc,
IN BOOLEAN Check4G,
IN UINT32 Which4G
IN PEI_USB2_HC_DEV *Ehc,
IN BOOLEAN Check4G,
IN UINT32 Which4G
)
{
USBHC_MEM_POOL *Pool;
UINTN PageNumber;
EFI_STATUS Status;
EFI_PHYSICAL_ADDRESS TempPtr;
USBHC_MEM_POOL *Pool;
UINTN PageNumber;
EFI_STATUS Status;
EFI_PHYSICAL_ADDRESS TempPtr;
PageNumber = sizeof(USBHC_MEM_POOL)/PAGESIZE +1;
Status = PeiServicesAllocatePages (
EfiBootServicesCode,
PageNumber,
&TempPtr
);
PageNumber = sizeof (USBHC_MEM_POOL)/PAGESIZE +1;
Status = PeiServicesAllocatePages (
EfiBootServicesCode,
PageNumber,
&TempPtr
);
if (EFI_ERROR (Status)) {
return NULL;
}
if (EFI_ERROR (Status)) {
return NULL;
}
ZeroMem ((VOID *)(UINTN)TempPtr, PageNumber*EFI_PAGE_SIZE);
Pool = (USBHC_MEM_POOL *) ((UINTN) TempPtr);
Pool = (USBHC_MEM_POOL *)((UINTN)TempPtr);
Pool->Check4G = Check4G;
Pool->Which4G = Which4G;
@@ -348,11 +348,11 @@ UsbHcInitMemPool (
**/
EFI_STATUS
UsbHcFreeMemPool (
IN PEI_USB2_HC_DEV *Ehc,
IN USBHC_MEM_POOL *Pool
IN PEI_USB2_HC_DEV *Ehc,
IN USBHC_MEM_POOL *Pool
)
{
USBHC_MEM_BLOCK *Block;
USBHC_MEM_BLOCK *Block;
ASSERT (Pool->Head != NULL);
@@ -381,17 +381,17 @@ UsbHcFreeMemPool (
**/
VOID *
UsbHcAllocateMem (
IN PEI_USB2_HC_DEV *Ehc,
IN USBHC_MEM_POOL *Pool,
IN UINTN Size
IN PEI_USB2_HC_DEV *Ehc,
IN USBHC_MEM_POOL *Pool,
IN UINTN Size
)
{
USBHC_MEM_BLOCK *Head;
USBHC_MEM_BLOCK *Block;
USBHC_MEM_BLOCK *NewBlock;
VOID *Mem;
UINTN AllocSize;
UINTN Pages;
USBHC_MEM_BLOCK *Head;
USBHC_MEM_BLOCK *Block;
USBHC_MEM_BLOCK *NewBlock;
VOID *Mem;
UINTN AllocSize;
UINTN Pages;
Mem = NULL;
AllocSize = USBHC_MEM_ROUND (Size);
@@ -425,7 +425,8 @@ UsbHcAllocateMem (
} else {
Pages = USBHC_MEM_DEFAULT_PAGES;
}
NewBlock = UsbHcAllocMemBlock (Ehc,Pool, Pages);
NewBlock = UsbHcAllocMemBlock (Ehc, Pool, Pages);
if (NewBlock == NULL) {
return NULL;
@@ -455,23 +456,23 @@ UsbHcAllocateMem (
**/
VOID
UsbHcFreeMem (
IN PEI_USB2_HC_DEV *Ehc,
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
IN PEI_USB2_HC_DEV *Ehc,
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
)
{
USBHC_MEM_BLOCK *Head;
USBHC_MEM_BLOCK *Block;
UINT8 *ToFree;
UINTN AllocSize;
UINTN Byte;
UINTN Bit;
UINTN Count;
USBHC_MEM_BLOCK *Head;
USBHC_MEM_BLOCK *Block;
UINT8 *ToFree;
UINTN AllocSize;
UINTN Byte;
UINTN Bit;
UINTN Count;
Head = Pool->Head;
AllocSize = USBHC_MEM_ROUND (Size);
ToFree = (UINT8 *) Mem;
ToFree = (UINT8 *)Mem;
for (Block = Head; Block != NULL; Block = Block->Next) {
//
@@ -482,8 +483,8 @@ UsbHcFreeMem (
//
// compute the start byte and bit in the bit array
//
Byte = ((ToFree - Block->Buf) / USBHC_MEM_UNIT) / 8;
Bit = ((ToFree - Block->Buf) / USBHC_MEM_UNIT) % 8;
Byte = ((ToFree - Block->Buf) / USBHC_MEM_UNIT) / 8;
Bit = ((ToFree - Block->Buf) / USBHC_MEM_UNIT) % 8;
//
// reset associated bits in bit array
@@ -491,7 +492,7 @@ UsbHcFreeMem (
for (Count = 0; Count < (AllocSize / USBHC_MEM_UNIT); Count++) {
ASSERT (USB_HC_BIT_IS_SET (Block->Bits[Byte], Bit));
Block->Bits[Byte] = (UINT8) (Block->Bits[Byte] ^ USB_HC_BIT (Bit));
Block->Bits[Byte] = (UINT8)(Block->Bits[Byte] ^ USB_HC_BIT (Bit));
NEXT_BIT (Byte, Bit);
}
@@ -513,5 +514,5 @@ UsbHcFreeMem (
UsbHcFreeMemBlock (Ehc, Pool, Block);
}
return ;
return;
}

31
MdeModulePkg/Bus/Pci/EhciPei/UsbHcMem.h
View File

@@ -13,7 +13,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Uefi.h>
#include <IndustryStandard/Pci22.h>
#define USB_HC_BIT(a) ((UINTN)(1 << (a)))
#define USB_HC_BIT(a) ((UINTN)(1 << (a)))
#define USB_HC_BIT_IS_SET(Data, Bit) \
((BOOLEAN)(((Data) & USB_HC_BIT(Bit)) == USB_HC_BIT(Bit)))
@@ -24,13 +24,13 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
typedef struct _USBHC_MEM_BLOCK USBHC_MEM_BLOCK;
struct _USBHC_MEM_BLOCK {
UINT8 *Bits; // Bit array to record which unit is allocated
UINTN BitsLen;
UINT8 *Buf;
UINT8 *BufHost;
UINTN BufLen; // Memory size in bytes
VOID *Mapping;
USBHC_MEM_BLOCK *Next;
UINT8 *Bits; // Bit array to record which unit is allocated
UINTN BitsLen;
UINT8 *Buf;
UINT8 *BufHost;
UINTN BufLen; // Memory size in bytes
VOID *Mapping;
USBHC_MEM_BLOCK *Next;
};
//
@@ -39,15 +39,15 @@ struct _USBHC_MEM_BLOCK {
// data to be on the same 4G memory.
//
typedef struct _USBHC_MEM_POOL {
BOOLEAN Check4G;
UINT32 Which4G;
USBHC_MEM_BLOCK *Head;
BOOLEAN Check4G;
UINT32 Which4G;
USBHC_MEM_BLOCK *Head;
} USBHC_MEM_POOL;
//
// Memory allocation unit, must be 2^n, n>4
//
#define USBHC_MEM_UNIT 64
#define USBHC_MEM_UNIT 64
#define USBHC_MEM_UNIT_MASK (USBHC_MEM_UNIT - 1)
#define USBHC_MEM_DEFAULT_PAGES 16
@@ -66,7 +66,6 @@ typedef struct _USBHC_MEM_POOL {
} \
} while (0)
/**
Calculate the corresponding pci bus address according to the Mem parameter.
@@ -78,9 +77,9 @@ typedef struct _USBHC_MEM_POOL {
**/
EFI_PHYSICAL_ADDRESS
UsbHcGetPciAddressForHostMem (
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
);
#endif

908
MdeModulePkg/Bus/Pci/IdeBusPei/AtapiPeim.c
View File

File diff suppressed because it is too large Load Diff

208
MdeModulePkg/Bus/Pci/IdeBusPei/AtapiPeim.h
View File

@@ -26,12 +26,11 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/MemoryAllocationLib.h>
#include <Library/PcdLib.h>
#include <IndustryStandard/Atapi.h>
#define MAX_SENSE_KEY_COUNT 6
#define MAX_IDE_CHANNELS 4 // Ide and Sata Primary, Secondary Channel.
#define MAX_IDE_DEVICES 8 // Ide, Sata Primary, Secondary and Master, Slave device.
#define MAX_SENSE_KEY_COUNT 6
#define MAX_IDE_CHANNELS 4 // Ide and Sata Primary, Secondary Channel.
#define MAX_IDE_DEVICES 8 // Ide, Sata Primary, Secondary and Master, Slave device.
typedef enum {
IdePrimary = 0,
@@ -40,72 +39,69 @@ typedef enum {
} EFI_IDE_CHANNEL;
typedef enum {
IdeMaster = 0,
IdeSlave = 1,
IdeMaxDevice = 2
IdeMaster = 0,
IdeSlave = 1,
IdeMaxDevice = 2
} EFI_IDE_DEVICE;
//
// IDE Registers
//
typedef union {
UINT16 Command; /* when write */
UINT16 Status; /* when read */
UINT16 Command; /* when write */
UINT16 Status; /* when read */
} IDE_CMD_OR_STATUS;
typedef union {
UINT16 Error; /* when read */
UINT16 Feature; /* when write */
UINT16 Error; /* when read */
UINT16 Feature; /* when write */
} IDE_ERROR_OR_FEATURE;
typedef union {
UINT16 AltStatus; /* when read */
UINT16 DeviceControl; /* when write */
UINT16 AltStatus; /* when read */
UINT16 DeviceControl; /* when write */
} IDE_ALTSTATUS_OR_DEVICECONTROL;
//
// IDE registers set
//
typedef struct {
UINT16 Data;
IDE_ERROR_OR_FEATURE Reg1;
UINT16 SectorCount;
UINT16 SectorNumber;
UINT16 CylinderLsb;
UINT16 CylinderMsb;
UINT16 Head;
IDE_CMD_OR_STATUS Reg;
UINT16 Data;
IDE_ERROR_OR_FEATURE Reg1;
UINT16 SectorCount;
UINT16 SectorNumber;
UINT16 CylinderLsb;
UINT16 CylinderMsb;
UINT16 Head;
IDE_CMD_OR_STATUS Reg;
IDE_ALTSTATUS_OR_DEVICECONTROL Alt;
UINT16 DriveAddress;
IDE_ALTSTATUS_OR_DEVICECONTROL Alt;
UINT16 DriveAddress;
} IDE_BASE_REGISTERS;
typedef struct {
UINTN DevicePosition;
EFI_PEI_BLOCK_IO_MEDIA MediaInfo;
EFI_PEI_BLOCK_IO2_MEDIA MediaInfo2;
UINTN DevicePosition;
EFI_PEI_BLOCK_IO_MEDIA MediaInfo;
EFI_PEI_BLOCK_IO2_MEDIA MediaInfo2;
} PEI_ATAPI_DEVICE_INFO;
#define ATAPI_BLK_IO_DEV_SIGNATURE SIGNATURE_32 ('a', 'b', 'i', 'o')
typedef struct {
UINTN Signature;
UINTN Signature;
EFI_PEI_RECOVERY_BLOCK_IO_PPI AtapiBlkIo;
EFI_PEI_RECOVERY_BLOCK_IO2_PPI AtapiBlkIo2;
EFI_PEI_PPI_DESCRIPTOR PpiDescriptor;
EFI_PEI_PPI_DESCRIPTOR PpiDescriptor2;
PEI_ATA_CONTROLLER_PPI *AtaControllerPpi;
EFI_PEI_RECOVERY_BLOCK_IO_PPI AtapiBlkIo;
EFI_PEI_RECOVERY_BLOCK_IO2_PPI AtapiBlkIo2;
EFI_PEI_PPI_DESCRIPTOR PpiDescriptor;
EFI_PEI_PPI_DESCRIPTOR PpiDescriptor2;
PEI_ATA_CONTROLLER_PPI *AtaControllerPpi;
UINTN DeviceCount;
PEI_ATAPI_DEVICE_INFO DeviceInfo[MAX_IDE_DEVICES]; //for max 8 device
IDE_BASE_REGISTERS IdeIoPortReg[MAX_IDE_CHANNELS]; //for max 4 channel.
UINTN DeviceCount;
PEI_ATAPI_DEVICE_INFO DeviceInfo[MAX_IDE_DEVICES]; // for max 8 device
IDE_BASE_REGISTERS IdeIoPortReg[MAX_IDE_CHANNELS]; // for max 4 channel.
} ATAPI_BLK_IO_DEV;
#define PEI_RECOVERY_ATAPI_FROM_BLKIO_THIS(a) CR (a, ATAPI_BLK_IO_DEV, AtapiBlkIo, ATAPI_BLK_IO_DEV_SIGNATURE)
#define PEI_RECOVERY_ATAPI_FROM_BLKIO2_THIS(a) CR (a, ATAPI_BLK_IO_DEV, AtapiBlkIo2, ATAPI_BLK_IO_DEV_SIGNATURE)
#define PEI_RECOVERY_ATAPI_FROM_BLKIO_THIS(a) CR (a, ATAPI_BLK_IO_DEV, AtapiBlkIo, ATAPI_BLK_IO_DEV_SIGNATURE)
#define PEI_RECOVERY_ATAPI_FROM_BLKIO2_THIS(a) CR (a, ATAPI_BLK_IO_DEV, AtapiBlkIo2, ATAPI_BLK_IO_DEV_SIGNATURE)
#define STALL_1_MILLI_SECOND 1000 // stall 1 ms
#define STALL_1_SECONDS 1000 * STALL_1_MILLI_SECOND
@@ -152,9 +148,9 @@ typedef struct {
EFI_STATUS
EFIAPI
AtapiGetNumberOfBlockDevices (
IN EFI_PEI_SERVICES **PeiServices,
IN EFI_PEI_RECOVERY_BLOCK_IO_PPI *This,
OUT UINTN *NumberBlockDevices
IN EFI_PEI_SERVICES **PeiServices,
IN EFI_PEI_RECOVERY_BLOCK_IO_PPI *This,
OUT UINTN *NumberBlockDevices
);
/**
@@ -188,10 +184,10 @@ AtapiGetNumberOfBlockDevices (
EFI_STATUS
EFIAPI
AtapiGetBlockDeviceMediaInfo (
IN EFI_PEI_SERVICES **PeiServices,
IN EFI_PEI_RECOVERY_BLOCK_IO_PPI *This,
IN UINTN DeviceIndex,
OUT EFI_PEI_BLOCK_IO_MEDIA *MediaInfo
IN EFI_PEI_SERVICES **PeiServices,
IN EFI_PEI_RECOVERY_BLOCK_IO_PPI *This,
IN UINTN DeviceIndex,
OUT EFI_PEI_BLOCK_IO_MEDIA *MediaInfo
);
/**
@@ -231,12 +227,12 @@ AtapiGetBlockDeviceMediaInfo (
EFI_STATUS
EFIAPI
AtapiReadBlocks (
IN EFI_PEI_SERVICES **PeiServices,
IN EFI_PEI_RECOVERY_BLOCK_IO_PPI *This,
IN UINTN DeviceIndex,
IN EFI_PEI_LBA StartLBA,
IN UINTN BufferSize,
OUT VOID *Buffer
IN EFI_PEI_SERVICES **PeiServices,
IN EFI_PEI_RECOVERY_BLOCK_IO_PPI *This,
IN UINTN DeviceIndex,
IN EFI_PEI_LBA StartLBA,
IN UINTN BufferSize,
OUT VOID *Buffer
);
/**
@@ -261,9 +257,9 @@ AtapiReadBlocks (
EFI_STATUS
EFIAPI
AtapiGetNumberOfBlockDevices2 (
IN EFI_PEI_SERVICES **PeiServices,
IN EFI_PEI_RECOVERY_BLOCK_IO2_PPI *This,
OUT UINTN *NumberBlockDevices
IN EFI_PEI_SERVICES **PeiServices,
IN EFI_PEI_RECOVERY_BLOCK_IO2_PPI *This,
OUT UINTN *NumberBlockDevices
);
/**
@@ -297,10 +293,10 @@ AtapiGetNumberOfBlockDevices2 (
EFI_STATUS
EFIAPI
AtapiGetBlockDeviceMediaInfo2 (
IN EFI_PEI_SERVICES **PeiServices,
IN EFI_PEI_RECOVERY_BLOCK_IO2_PPI *This,
IN UINTN DeviceIndex,
OUT EFI_PEI_BLOCK_IO2_MEDIA *MediaInfo
IN EFI_PEI_SERVICES **PeiServices,
IN EFI_PEI_RECOVERY_BLOCK_IO2_PPI *This,
IN UINTN DeviceIndex,
OUT EFI_PEI_BLOCK_IO2_MEDIA *MediaInfo
);
/**
@@ -340,12 +336,12 @@ AtapiGetBlockDeviceMediaInfo2 (
EFI_STATUS
EFIAPI
AtapiReadBlocks2 (
IN EFI_PEI_SERVICES **PeiServices,
IN EFI_PEI_RECOVERY_BLOCK_IO2_PPI *This,
IN UINTN DeviceIndex,
IN EFI_PEI_LBA StartLBA,
IN UINTN BufferSize,
OUT VOID *Buffer
IN EFI_PEI_SERVICES **PeiServices,
IN EFI_PEI_RECOVERY_BLOCK_IO2_PPI *This,
IN UINTN DeviceIndex,
IN EFI_PEI_LBA StartLBA,
IN UINTN BufferSize,
OUT VOID *Buffer
);
//
@@ -379,10 +375,10 @@ AtapiEnumerateDevices (
**/
BOOLEAN
DiscoverAtapiDevice (
IN ATAPI_BLK_IO_DEV *AtapiBlkIoDev,
IN UINTN DevicePosition,
OUT EFI_PEI_BLOCK_IO_MEDIA *MediaInfo,
OUT EFI_PEI_BLOCK_IO2_MEDIA *MediaInfo2
IN ATAPI_BLK_IO_DEV *AtapiBlkIoDev,
IN UINTN DevicePosition,
OUT EFI_PEI_BLOCK_IO_MEDIA *MediaInfo,
OUT EFI_PEI_BLOCK_IO2_MEDIA *MediaInfo2
);
/**
@@ -397,8 +393,8 @@ DiscoverAtapiDevice (
**/
BOOLEAN
DetectIDEController (
IN ATAPI_BLK_IO_DEV *AtapiBlkIoDev,
IN UINTN DevicePosition
IN ATAPI_BLK_IO_DEV *AtapiBlkIoDev,
IN UINTN DevicePosition
);
/**
@@ -523,8 +519,8 @@ DRQReady2 (
**/
EFI_STATUS
CheckErrorStatus (
IN ATAPI_BLK_IO_DEV *AtapiBlkIoDev,
IN UINT16 StatusReg
IN ATAPI_BLK_IO_DEV *AtapiBlkIoDev,
IN UINT16 StatusReg
);
/**
@@ -539,8 +535,8 @@ CheckErrorStatus (
**/
EFI_STATUS
ATAPIIdentify (
IN ATAPI_BLK_IO_DEV *AtapiBlkIoDev,
IN UINTN DevicePosition
IN ATAPI_BLK_IO_DEV *AtapiBlkIoDev,
IN UINTN DevicePosition
);
/**
@@ -556,9 +552,9 @@ ATAPIIdentify (
**/
EFI_STATUS
TestUnitReady (
IN ATAPI_BLK_IO_DEV *AtapiBlkIoDev,
IN UINTN DevicePosition
) ;
IN ATAPI_BLK_IO_DEV *AtapiBlkIoDev,
IN UINTN DevicePosition
);
/**
Send out ATAPI commands conforms to the Packet Command with PIO Data In Protocol.
@@ -600,10 +596,10 @@ AtapiPacketCommandIn (
**/
EFI_STATUS
Inquiry (
IN ATAPI_BLK_IO_DEV *AtapiBlkIoDev,
IN UINTN DevicePosition,
OUT EFI_PEI_BLOCK_IO_MEDIA *MediaInfo,
OUT EFI_PEI_BLOCK_IO2_MEDIA *MediaInfo2
IN ATAPI_BLK_IO_DEV *AtapiBlkIoDev,
IN UINTN DevicePosition,
OUT EFI_PEI_BLOCK_IO_MEDIA *MediaInfo,
OUT EFI_PEI_BLOCK_IO2_MEDIA *MediaInfo2
);
/**
@@ -623,10 +619,10 @@ Inquiry (
**/
EFI_STATUS
DetectMedia (
IN ATAPI_BLK_IO_DEV *AtapiBlkIoDev,
IN UINTN DevicePosition,
IN OUT EFI_PEI_BLOCK_IO_MEDIA *MediaInfo,
IN OUT EFI_PEI_BLOCK_IO2_MEDIA *MediaInfo2
IN ATAPI_BLK_IO_DEV *AtapiBlkIoDev,
IN UINTN DevicePosition,
IN OUT EFI_PEI_BLOCK_IO_MEDIA *MediaInfo,
IN OUT EFI_PEI_BLOCK_IO2_MEDIA *MediaInfo2
);
/**
@@ -683,10 +679,10 @@ RequestSense (
**/
EFI_STATUS
ReadCapacity (
IN ATAPI_BLK_IO_DEV *AtapiBlkIoDev,
IN UINTN DevicePosition,
IN OUT EFI_PEI_BLOCK_IO_MEDIA *MediaInfo,
IN OUT EFI_PEI_BLOCK_IO2_MEDIA *MediaInfo2
IN ATAPI_BLK_IO_DEV *AtapiBlkIoDev,
IN UINTN DevicePosition,
IN OUT EFI_PEI_BLOCK_IO_MEDIA *MediaInfo,
IN OUT EFI_PEI_BLOCK_IO2_MEDIA *MediaInfo2
);
/**
@@ -705,12 +701,12 @@ ReadCapacity (
**/
EFI_STATUS
ReadSectors (
IN ATAPI_BLK_IO_DEV *AtapiBlkIoDev,
IN UINTN DevicePosition,
IN VOID *Buffer,
IN EFI_PEI_LBA StartLba,
IN UINTN NumberOfBlocks,
IN UINTN BlockSize
IN ATAPI_BLK_IO_DEV *AtapiBlkIoDev,
IN UINTN DevicePosition,
IN VOID *Buffer,
IN EFI_PEI_LBA StartLba,
IN UINTN NumberOfBlocks,
IN UINTN BlockSize
);
/**
@@ -725,8 +721,8 @@ ReadSectors (
**/
BOOLEAN
IsNoMedia (
IN ATAPI_REQUEST_SENSE_DATA *SenseData,
IN UINTN SenseCounts
IN ATAPI_REQUEST_SENSE_DATA *SenseData,
IN UINTN SenseCounts
);
/**
@@ -741,8 +737,8 @@ IsNoMedia (
**/
BOOLEAN
IsDeviceStateUnclear (
IN ATAPI_REQUEST_SENSE_DATA *SenseData,
IN UINTN SenseCounts
IN ATAPI_REQUEST_SENSE_DATA *SenseData,
IN UINTN SenseCounts
);
/**
@@ -757,8 +753,8 @@ IsDeviceStateUnclear (
**/
BOOLEAN
IsMediaError (
IN ATAPI_REQUEST_SENSE_DATA *SenseData,
IN UINTN SenseCounts
IN ATAPI_REQUEST_SENSE_DATA *SenseData,
IN UINTN SenseCounts
);
/**
@@ -774,9 +770,9 @@ IsMediaError (
**/
BOOLEAN
IsDriveReady (
IN ATAPI_REQUEST_SENSE_DATA *SenseData,
IN UINTN SenseCounts,
OUT BOOLEAN *NeedRetry
IN ATAPI_REQUEST_SENSE_DATA *SenseData,
IN UINTN SenseCounts,
OUT BOOLEAN *NeedRetry
);
#endif

250
MdeModulePkg/Bus/Pci/IncompatiblePciDeviceSupportDxe/IncompatiblePciDeviceSupport.c
View File

@@ -21,32 +21,32 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <IndustryStandard/Acpi.h>
typedef struct {
UINT64 VendorId;
UINT64 DeviceId;
UINT64 RevisionId;
UINT64 SubsystemVendorId;
UINT64 SubsystemDeviceId;
UINT64 VendorId;
UINT64 DeviceId;
UINT64 RevisionId;
UINT64 SubsystemVendorId;
UINT64 SubsystemDeviceId;
} EFI_PCI_DEVICE_HEADER_INFO;
typedef struct {
UINT64 ResType;
UINT64 GenFlag;
UINT64 SpecificFlag;
UINT64 AddrSpaceGranularity;
UINT64 AddrRangeMin;
UINT64 AddrRangeMax;
UINT64 AddrTranslationOffset;
UINT64 AddrLen;
UINT64 ResType;
UINT64 GenFlag;
UINT64 SpecificFlag;
UINT64 AddrSpaceGranularity;
UINT64 AddrRangeMin;
UINT64 AddrRangeMax;
UINT64 AddrTranslationOffset;
UINT64 AddrLen;
} EFI_PCI_RESOUCE_DESCRIPTOR;
#define PCI_DEVICE_ID(VendorId, DeviceId, Revision, SubVendorId, SubDeviceId) \
VendorId, DeviceId, Revision, SubVendorId, SubDeviceId
#define DEVICE_INF_TAG 0xFFF2
#define DEVICE_RES_TAG 0xFFF1
#define LIST_END_TAG 0x0000
#define DEVICE_INF_TAG 0xFFF2
#define DEVICE_RES_TAG 0xFFF1
#define LIST_END_TAG 0x0000
#define EVEN_ALIGN 0xFFFFFFFFFFFFFFFEULL
#define EVEN_ALIGN 0xFFFFFFFFFFFFFFFEULL
/**
Returns a list of ACPI resource descriptors that detail the special
@@ -82,7 +82,7 @@ PCheckDevice (
//
// Handle onto which the Incompatible PCI Device List is installed
//
EFI_HANDLE mIncompatiblePciDeviceSupportHandle = NULL;
EFI_HANDLE mIncompatiblePciDeviceSupportHandle = NULL;
//
// The Incompatible PCI Device Support Protocol instance produced by this driver
@@ -94,7 +94,7 @@ EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL mIncompatiblePciDeviceSupport = {
//
// The incompatible PCI devices list template
//
GLOBAL_REMOVE_IF_UNREFERENCED UINT64 mIncompatiblePciDeviceList[] = {
GLOBAL_REMOVE_IF_UNREFERENCED UINT64 mIncompatiblePciDeviceList[] = {
//
// DEVICE_INF_TAG,
// PCI_DEVICE_ID (VendorID, DeviceID, Revision, SubVendorId, SubDeviceId),
@@ -106,7 +106,7 @@ GLOBAL_REMOVE_IF_UNREFERENCED UINT64 mIncompatiblePciDeviceList[] = {
// Device Adaptec 9004
//
DEVICE_INF_TAG,
PCI_DEVICE_ID(0x9004, MAX_UINT64, MAX_UINT64, MAX_UINT64, MAX_UINT64),
PCI_DEVICE_ID (0x9004, MAX_UINT64, MAX_UINT64, MAX_UINT64, MAX_UINT64),
DEVICE_RES_TAG,
ACPI_ADDRESS_SPACE_TYPE_IO,
0,
@@ -120,7 +120,7 @@ GLOBAL_REMOVE_IF_UNREFERENCED UINT64 mIncompatiblePciDeviceList[] = {
// Device Adaptec 9005
//
DEVICE_INF_TAG,
PCI_DEVICE_ID(0x9005, MAX_UINT64, MAX_UINT64, MAX_UINT64, MAX_UINT64),
PCI_DEVICE_ID (0x9005, MAX_UINT64, MAX_UINT64, MAX_UINT64, MAX_UINT64),
DEVICE_RES_TAG,
ACPI_ADDRESS_SPACE_TYPE_IO,
0,
@@ -134,7 +134,7 @@ GLOBAL_REMOVE_IF_UNREFERENCED UINT64 mIncompatiblePciDeviceList[] = {
// Device QLogic 1007
//
DEVICE_INF_TAG,
PCI_DEVICE_ID(0x1077, MAX_UINT64, MAX_UINT64, MAX_UINT64, MAX_UINT64),
PCI_DEVICE_ID (0x1077, MAX_UINT64, MAX_UINT64, MAX_UINT64, MAX_UINT64),
DEVICE_RES_TAG,
ACPI_ADDRESS_SPACE_TYPE_IO,
0,
@@ -148,7 +148,7 @@ GLOBAL_REMOVE_IF_UNREFERENCED UINT64 mIncompatiblePciDeviceList[] = {
// Device Agilent 103C
//
DEVICE_INF_TAG,
PCI_DEVICE_ID(0x103C, MAX_UINT64, MAX_UINT64, MAX_UINT64, MAX_UINT64),
PCI_DEVICE_ID (0x103C, MAX_UINT64, MAX_UINT64, MAX_UINT64, MAX_UINT64),
DEVICE_RES_TAG,
ACPI_ADDRESS_SPACE_TYPE_IO,
0,
@@ -162,7 +162,7 @@ GLOBAL_REMOVE_IF_UNREFERENCED UINT64 mIncompatiblePciDeviceList[] = {
// Device Agilent 15BC
//
DEVICE_INF_TAG,
PCI_DEVICE_ID(0x15BC, MAX_UINT64, MAX_UINT64, MAX_UINT64, MAX_UINT64),
PCI_DEVICE_ID (0x15BC, MAX_UINT64, MAX_UINT64, MAX_UINT64, MAX_UINT64),
DEVICE_RES_TAG,
ACPI_ADDRESS_SPACE_TYPE_IO,
0,
@@ -178,7 +178,6 @@ GLOBAL_REMOVE_IF_UNREFERENCED UINT64 mIncompatiblePciDeviceList[] = {
LIST_END_TAG
};
/**
Entry point of the incompatible pci device support code. Setup an incompatible device list template
and install EFI Incompatible PCI Device Support protocol.
@@ -193,11 +192,11 @@ GLOBAL_REMOVE_IF_UNREFERENCED UINT64 mIncompatiblePciDeviceList[] = {
EFI_STATUS
EFIAPI
IncompatiblePciDeviceSupportEntryPoint (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
EFI_STATUS Status;
//
// Install EFI Incompatible PCI Device Support Protocol on a new handle
@@ -244,15 +243,15 @@ PCheckDevice (
OUT VOID **Configuration
)
{
UINT64 Tag;
UINT64 *ListPtr;
UINT64 *TempListPtr;
EFI_PCI_DEVICE_HEADER_INFO *Header;
EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *AcpiPtr;
EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *OldAcpiPtr;
EFI_PCI_RESOUCE_DESCRIPTOR *Dsc;
EFI_ACPI_END_TAG_DESCRIPTOR *PtrEnd;
UINTN Index;
UINT64 Tag;
UINT64 *ListPtr;
UINT64 *TempListPtr;
EFI_PCI_DEVICE_HEADER_INFO *Header;
EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *AcpiPtr;
EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *OldAcpiPtr;
EFI_PCI_RESOUCE_DESCRIPTOR *Dsc;
EFI_ACPI_END_TAG_DESCRIPTOR *PtrEnd;
UINTN Index;
//
// Validate the parameters
@@ -260,120 +259,121 @@ PCheckDevice (
if (Configuration == NULL) {
return EFI_INVALID_PARAMETER;
}
//
// Initialize the return value to NULL
//
* (VOID **) Configuration = NULL;
*(VOID **)Configuration = NULL;
ListPtr = mIncompatiblePciDeviceList;
ListPtr = mIncompatiblePciDeviceList;
while (*ListPtr != LIST_END_TAG) {
Tag = *ListPtr;
switch (Tag) {
case DEVICE_INF_TAG:
Header = (EFI_PCI_DEVICE_HEADER_INFO *) (ListPtr + 1);
ListPtr = ListPtr + 1 + sizeof (EFI_PCI_DEVICE_HEADER_INFO) / sizeof (UINT64);
//
// See if the Header matches the parameters passed in
//
if ((Header->VendorId != MAX_UINT64) && (VendorId != MAX_UINTN)) {
if (Header->VendorId != VendorId) {
continue;
case DEVICE_INF_TAG:
Header = (EFI_PCI_DEVICE_HEADER_INFO *)(ListPtr + 1);
ListPtr = ListPtr + 1 + sizeof (EFI_PCI_DEVICE_HEADER_INFO) / sizeof (UINT64);
//
// See if the Header matches the parameters passed in
//
if ((Header->VendorId != MAX_UINT64) && (VendorId != MAX_UINTN)) {
if (Header->VendorId != VendorId) {
continue;
}
}
}
if ((Header->DeviceId != MAX_UINT64) && (DeviceId != MAX_UINTN)) {
if (DeviceId != Header->DeviceId) {
continue;
if ((Header->DeviceId != MAX_UINT64) && (DeviceId != MAX_UINTN)) {
if (DeviceId != Header->DeviceId) {
continue;
}
}
}
if ((Header->RevisionId != MAX_UINT64) && (RevisionId != MAX_UINTN)) {
if (RevisionId != Header->RevisionId) {
continue;
if ((Header->RevisionId != MAX_UINT64) && (RevisionId != MAX_UINTN)) {
if (RevisionId != Header->RevisionId) {
continue;
}
}
}
if ((Header->SubsystemVendorId != MAX_UINT64) && (SubsystemVendorId != MAX_UINTN)) {
if (SubsystemVendorId != Header->SubsystemVendorId) {
continue;
if ((Header->SubsystemVendorId != MAX_UINT64) && (SubsystemVendorId != MAX_UINTN)) {
if (SubsystemVendorId != Header->SubsystemVendorId) {
continue;
}
}
}
if ((Header->SubsystemDeviceId != MAX_UINT64) && (SubsystemDeviceId != MAX_UINTN)) {
if (SubsystemDeviceId != Header->SubsystemDeviceId) {
continue;
if ((Header->SubsystemDeviceId != MAX_UINT64) && (SubsystemDeviceId != MAX_UINTN)) {
if (SubsystemDeviceId != Header->SubsystemDeviceId) {
continue;
}
}
}
//
// Matched an item, so construct the ACPI descriptor for the resource.
//
//
// Count the resource items so that to allocate space
//
for (Index = 0, TempListPtr = ListPtr; *TempListPtr == DEVICE_RES_TAG; Index++) {
TempListPtr = TempListPtr + 1 + ((sizeof (EFI_PCI_RESOUCE_DESCRIPTOR)) / sizeof (UINT64));
}
//
// If there is at least one type of resource request,
// allocate an acpi resource node
//
if (Index == 0) {
return EFI_UNSUPPORTED;
}
AcpiPtr = AllocateZeroPool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * Index + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));
if (AcpiPtr == NULL) {
return EFI_OUT_OF_RESOURCES;
}
//
// Matched an item, so construct the ACPI descriptor for the resource.
//
//
// Count the resource items so that to allocate space
//
for (Index = 0, TempListPtr = ListPtr; *TempListPtr == DEVICE_RES_TAG; Index++) {
TempListPtr = TempListPtr + 1 + ((sizeof (EFI_PCI_RESOUCE_DESCRIPTOR)) / sizeof (UINT64));
}
OldAcpiPtr = AcpiPtr;
//
// Fill the EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR structure
// according to the EFI_PCI_RESOUCE_DESCRIPTOR structure
//
for (; *ListPtr == DEVICE_RES_TAG;) {
//
// If there is at least one type of resource request,
// allocate an acpi resource node
//
if (Index == 0) {
return EFI_UNSUPPORTED;
}
Dsc = (EFI_PCI_RESOUCE_DESCRIPTOR *) (ListPtr + 1);
AcpiPtr = AllocateZeroPool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * Index + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));
if (AcpiPtr == NULL) {
return EFI_OUT_OF_RESOURCES;
}
AcpiPtr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
AcpiPtr->Len = (UINT16) sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;
AcpiPtr->ResType = (UINT8) Dsc->ResType;
AcpiPtr->GenFlag = (UINT8) Dsc->GenFlag;
AcpiPtr->SpecificFlag = (UINT8) Dsc->SpecificFlag;
AcpiPtr->AddrSpaceGranularity = Dsc->AddrSpaceGranularity;;
AcpiPtr->AddrRangeMin = Dsc->AddrRangeMin;
AcpiPtr->AddrRangeMax = Dsc->AddrRangeMax;
AcpiPtr->AddrTranslationOffset = Dsc->AddrTranslationOffset;
AcpiPtr->AddrLen = Dsc->AddrLen;
OldAcpiPtr = AcpiPtr;
//
// Fill the EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR structure
// according to the EFI_PCI_RESOUCE_DESCRIPTOR structure
//
for ( ; *ListPtr == DEVICE_RES_TAG;) {
Dsc = (EFI_PCI_RESOUCE_DESCRIPTOR *)(ListPtr + 1);
AcpiPtr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
AcpiPtr->Len = (UINT16)sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;
AcpiPtr->ResType = (UINT8)Dsc->ResType;
AcpiPtr->GenFlag = (UINT8)Dsc->GenFlag;
AcpiPtr->SpecificFlag = (UINT8)Dsc->SpecificFlag;
AcpiPtr->AddrSpaceGranularity = Dsc->AddrSpaceGranularity;
AcpiPtr->AddrRangeMin = Dsc->AddrRangeMin;
AcpiPtr->AddrRangeMax = Dsc->AddrRangeMax;
AcpiPtr->AddrTranslationOffset = Dsc->AddrTranslationOffset;
AcpiPtr->AddrLen = Dsc->AddrLen;
ListPtr = ListPtr + 1 + ((sizeof (EFI_PCI_RESOUCE_DESCRIPTOR)) / sizeof (UINT64));
AcpiPtr++;
}
//
// Put the checksum
//
PtrEnd = (EFI_ACPI_END_TAG_DESCRIPTOR *)(AcpiPtr);
PtrEnd->Desc = ACPI_END_TAG_DESCRIPTOR;
PtrEnd->Checksum = 0;
*(VOID **)Configuration = OldAcpiPtr;
return EFI_SUCCESS;
case DEVICE_RES_TAG:
//
// Adjust the pointer to the next PCI resource descriptor item
//
ListPtr = ListPtr + 1 + ((sizeof (EFI_PCI_RESOUCE_DESCRIPTOR)) / sizeof (UINT64));
AcpiPtr++;
}
//
// Put the checksum
//
PtrEnd = (EFI_ACPI_END_TAG_DESCRIPTOR *) (AcpiPtr);
PtrEnd->Desc = ACPI_END_TAG_DESCRIPTOR;
PtrEnd->Checksum = 0;
break;
*(VOID **) Configuration = OldAcpiPtr;
return EFI_SUCCESS;
case DEVICE_RES_TAG:
//
// Adjust the pointer to the next PCI resource descriptor item
//
ListPtr = ListPtr + 1 + ((sizeof (EFI_PCI_RESOUCE_DESCRIPTOR)) / sizeof (UINT64));
break;
default:
return EFI_UNSUPPORTED;
default:
return EFI_UNSUPPORTED;
}
}
return EFI_UNSUPPORTED;
}

30
MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/ComponentName.c
View File

@@ -17,12 +17,12 @@
//
STATIC
EFI_UNICODE_STRING_TABLE mDriverNameTable[] = {
EFI_UNICODE_STRING_TABLE mDriverNameTable[] = {
{ "eng;en", L"PCI I/O protocol emulation driver for non-discoverable devices" },
{ NULL, NULL }
{ NULL, NULL }
};
EFI_COMPONENT_NAME_PROTOCOL gComponentName;
EFI_COMPONENT_NAME_PROTOCOL gComponentName;
/**
Retrieves a Unicode string that is the user readable name of the UEFI Driver.
@@ -49,9 +49,9 @@ STATIC
EFI_STATUS
EFIAPI
NonDiscoverablePciGetDriverName (
IN EFI_COMPONENT_NAME_PROTOCOL *This,
IN CHAR8 *Language,
OUT CHAR16 **DriverName
IN EFI_COMPONENT_NAME_PROTOCOL *This,
IN CHAR8 *Language,
OUT CHAR16 **DriverName
)
{
return LookupUnicodeString2 (
@@ -93,24 +93,24 @@ STATIC
EFI_STATUS
EFIAPI
NonDiscoverablePciGetDeviceName (
IN EFI_COMPONENT_NAME_PROTOCOL *This,
IN EFI_HANDLE DeviceHandle,
IN EFI_HANDLE ChildHandle,
IN CHAR8 *Language,
OUT CHAR16 **ControllerName
IN EFI_COMPONENT_NAME_PROTOCOL *This,
IN EFI_HANDLE DeviceHandle,
IN EFI_HANDLE ChildHandle,
IN CHAR8 *Language,
OUT CHAR16 **ControllerName
)
{
return EFI_UNSUPPORTED;
}
EFI_COMPONENT_NAME_PROTOCOL gComponentName = {
EFI_COMPONENT_NAME_PROTOCOL gComponentName = {
&NonDiscoverablePciGetDriverName,
&NonDiscoverablePciGetDeviceName,
"eng" // SupportedLanguages, ISO 639-2 language codes
};
EFI_COMPONENT_NAME2_PROTOCOL gComponentName2 = {
(EFI_COMPONENT_NAME2_GET_DRIVER_NAME) &NonDiscoverablePciGetDriverName,
(EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME) &NonDiscoverablePciGetDeviceName,
EFI_COMPONENT_NAME2_PROTOCOL gComponentName2 = {
(EFI_COMPONENT_NAME2_GET_DRIVER_NAME)&NonDiscoverablePciGetDriverName,
(EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME)&NonDiscoverablePciGetDeviceName,
"en" // SupportedLanguages, RFC 4646 language codes
};

139
MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.c
View File

@@ -10,16 +10,16 @@
#include <Protocol/DriverBinding.h>
#define MAX_NON_DISCOVERABLE_PCI_DEVICE_ID (32 * 256)
#define MAX_NON_DISCOVERABLE_PCI_DEVICE_ID (32 * 256)
STATIC UINTN mUniqueIdCounter = 0;
EFI_CPU_ARCH_PROTOCOL *mCpu;
STATIC UINTN mUniqueIdCounter = 0;
EFI_CPU_ARCH_PROTOCOL *mCpu;
//
// We only support the following device types
//
STATIC
CONST EFI_GUID * CONST
CONST EFI_GUID *CONST
SupportedNonDiscoverableDevices[] = {
&gEdkiiNonDiscoverableAhciDeviceGuid,
&gEdkiiNonDiscoverableEhciDeviceGuid,
@@ -63,27 +63,31 @@ STATIC
EFI_STATUS
EFIAPI
NonDiscoverablePciDeviceSupported (
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE DeviceHandle,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE DeviceHandle,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
)
{
NON_DISCOVERABLE_DEVICE *Device;
EFI_STATUS Status;
EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Desc;
INTN Idx;
NON_DISCOVERABLE_DEVICE *Device;
EFI_STATUS Status;
EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Desc;
INTN Idx;
Status = gBS->OpenProtocol (DeviceHandle,
&gEdkiiNonDiscoverableDeviceProtocolGuid, (VOID **)&Device,
This->DriverBindingHandle, DeviceHandle,
EFI_OPEN_PROTOCOL_BY_DRIVER);
Status = gBS->OpenProtocol (
DeviceHandle,
&gEdkiiNonDiscoverableDeviceProtocolGuid,
(VOID **)&Device,
This->DriverBindingHandle,
DeviceHandle,
EFI_OPEN_PROTOCOL_BY_DRIVER
);
if (EFI_ERROR (Status)) {
return Status;
}
Status = EFI_UNSUPPORTED;
for (Idx = 0; Idx < ARRAY_SIZE (SupportedNonDiscoverableDevices); Idx++) {
if (CompareGuid (Device->Type, SupportedNonDiscoverableDevices [Idx])) {
if (CompareGuid (Device->Type, SupportedNonDiscoverableDevices[Idx])) {
Status = EFI_SUCCESS;
break;
}
@@ -98,17 +102,23 @@ NonDiscoverablePciDeviceSupported (
// that they only describe things that we can handle
//
for (Desc = Device->Resources; Desc->Desc != ACPI_END_TAG_DESCRIPTOR;
Desc = (VOID *)((UINT8 *)Desc + Desc->Len + 3)) {
if (Desc->Desc != ACPI_ADDRESS_SPACE_DESCRIPTOR ||
Desc->ResType != ACPI_ADDRESS_SPACE_TYPE_MEM) {
Desc = (VOID *)((UINT8 *)Desc + Desc->Len + 3))
{
if ((Desc->Desc != ACPI_ADDRESS_SPACE_DESCRIPTOR) ||
(Desc->ResType != ACPI_ADDRESS_SPACE_TYPE_MEM))
{
Status = EFI_UNSUPPORTED;
break;
}
}
CloseProtocol:
gBS->CloseProtocol (DeviceHandle, &gEdkiiNonDiscoverableDeviceProtocolGuid,
This->DriverBindingHandle, DeviceHandle);
gBS->CloseProtocol (
DeviceHandle,
&gEdkiiNonDiscoverableDeviceProtocolGuid,
This->DriverBindingHandle,
DeviceHandle
);
return Status;
}
@@ -130,13 +140,13 @@ STATIC
EFI_STATUS
EFIAPI
NonDiscoverablePciDeviceStart (
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE DeviceHandle,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE DeviceHandle,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
)
{
NON_DISCOVERABLE_PCI_DEVICE *Dev;
EFI_STATUS Status;
NON_DISCOVERABLE_PCI_DEVICE *Dev;
EFI_STATUS Status;
ASSERT (mUniqueIdCounter < MAX_NON_DISCOVERABLE_PCI_DEVICE_ID);
if (mUniqueIdCounter >= MAX_NON_DISCOVERABLE_PCI_DEVICE_ID) {
@@ -148,10 +158,14 @@ NonDiscoverablePciDeviceStart (
return EFI_OUT_OF_RESOURCES;
}
Status = gBS->OpenProtocol (DeviceHandle,
Status = gBS->OpenProtocol (
DeviceHandle,
&gEdkiiNonDiscoverableDeviceProtocolGuid,
(VOID **)&Dev->Device, This->DriverBindingHandle,
DeviceHandle, EFI_OPEN_PROTOCOL_BY_DRIVER);
(VOID **)&Dev->Device,
This->DriverBindingHandle,
DeviceHandle,
EFI_OPEN_PROTOCOL_BY_DRIVER
);
if (EFI_ERROR (Status)) {
goto FreeDev;
}
@@ -163,8 +177,12 @@ NonDiscoverablePciDeviceStart (
// EFI_PCI_IO_PROTOCOL interface.
//
Dev->Signature = NON_DISCOVERABLE_PCI_DEVICE_SIG;
Status = gBS->InstallProtocolInterface (&DeviceHandle, &gEfiPciIoProtocolGuid,
EFI_NATIVE_INTERFACE, &Dev->PciIo);
Status = gBS->InstallProtocolInterface (
&DeviceHandle,
&gEfiPciIoProtocolGuid,
EFI_NATIVE_INTERFACE,
&Dev->PciIo
);
if (EFI_ERROR (Status)) {
goto CloseProtocol;
}
@@ -174,8 +192,12 @@ NonDiscoverablePciDeviceStart (
return EFI_SUCCESS;
CloseProtocol:
gBS->CloseProtocol (DeviceHandle, &gEdkiiNonDiscoverableDeviceProtocolGuid,
This->DriverBindingHandle, DeviceHandle);
gBS->CloseProtocol (
DeviceHandle,
&gEdkiiNonDiscoverableDeviceProtocolGuid,
This->DriverBindingHandle,
DeviceHandle
);
FreeDev:
FreePool (Dev);
@@ -199,19 +221,24 @@ STATIC
EFI_STATUS
EFIAPI
NonDiscoverablePciDeviceStop (
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE DeviceHandle,
IN UINTN NumberOfChildren,
IN EFI_HANDLE *ChildHandleBuffer
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE DeviceHandle,
IN UINTN NumberOfChildren,
IN EFI_HANDLE *ChildHandleBuffer
)
{
EFI_STATUS Status;
EFI_PCI_IO_PROTOCOL *PciIo;
NON_DISCOVERABLE_PCI_DEVICE *Dev;
EFI_STATUS Status;
EFI_PCI_IO_PROTOCOL *PciIo;
NON_DISCOVERABLE_PCI_DEVICE *Dev;
Status = gBS->OpenProtocol (DeviceHandle, &gEfiPciIoProtocolGuid,
(VOID **)&PciIo, This->DriverBindingHandle, DeviceHandle,
EFI_OPEN_PROTOCOL_GET_PROTOCOL);
Status = gBS->OpenProtocol (
DeviceHandle,
&gEfiPciIoProtocolGuid,
(VOID **)&PciIo,
This->DriverBindingHandle,
DeviceHandle,
EFI_OPEN_PROTOCOL_GET_PROTOCOL
);
if (EFI_ERROR (Status)) {
return Status;
}
@@ -221,27 +248,33 @@ NonDiscoverablePciDeviceStop (
//
// Handle Stop() requests for in-use driver instances gracefully.
//
Status = gBS->UninstallProtocolInterface (DeviceHandle,
&gEfiPciIoProtocolGuid, &Dev->PciIo);
Status = gBS->UninstallProtocolInterface (
DeviceHandle,
&gEfiPciIoProtocolGuid,
&Dev->PciIo
);
if (EFI_ERROR (Status)) {
return Status;
}
gBS->CloseProtocol (DeviceHandle, &gEdkiiNonDiscoverableDeviceProtocolGuid,
This->DriverBindingHandle, DeviceHandle);
gBS->CloseProtocol (
DeviceHandle,
&gEdkiiNonDiscoverableDeviceProtocolGuid,
This->DriverBindingHandle,
DeviceHandle
);
FreePool (Dev);
return EFI_SUCCESS;
}
//
// The static object that groups the Supported() (ie. probe), Start() and
// Stop() functions of the driver together. Refer to UEFI Spec 2.3.1 + Errata
// C, 10.1 EFI Driver Binding Protocol.
//
STATIC EFI_DRIVER_BINDING_PROTOCOL gDriverBinding = {
STATIC EFI_DRIVER_BINDING_PROTOCOL gDriverBinding = {
&NonDiscoverablePciDeviceSupported,
&NonDiscoverablePciDeviceStart,
&NonDiscoverablePciDeviceStop,
@@ -263,14 +296,14 @@ STATIC EFI_DRIVER_BINDING_PROTOCOL gDriverBinding = {
EFI_STATUS
EFIAPI
NonDiscoverablePciDeviceDxeEntryPoint (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
EFI_STATUS Status;
Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&mCpu);
ASSERT_EFI_ERROR(Status);
ASSERT_EFI_ERROR (Status);
return EfiLibInstallDriverBindingComponentName2 (
ImageHandle,

923
MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceIo.c
View File

File diff suppressed because it is too large Load Diff

42
MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceIo.h
View File

@@ -24,7 +24,7 @@
#include <Protocol/Cpu.h>
#include <Protocol/PciIo.h>
#define NON_DISCOVERABLE_PCI_DEVICE_SIG SIGNATURE_32 ('P', 'P', 'I', 'D')
#define NON_DISCOVERABLE_PCI_DEVICE_SIG SIGNATURE_32 ('P', 'P', 'I', 'D')
#define NON_DISCOVERABLE_PCI_DEVICE_FROM_PCI_IO(PciIoPointer) \
CR (PciIoPointer, NON_DISCOVERABLE_PCI_DEVICE, PciIo, \
@@ -33,74 +33,74 @@
#define DEV_SUPPORTED_ATTRIBUTES \
(EFI_PCI_DEVICE_ENABLE | EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE)
#define PCI_ID_VENDOR_UNKNOWN 0xffff
#define PCI_ID_DEVICE_DONTCARE 0x0000
#define PCI_ID_VENDOR_UNKNOWN 0xffff
#define PCI_ID_DEVICE_DONTCARE 0x0000
extern EFI_CPU_ARCH_PROTOCOL *mCpu;
extern EFI_CPU_ARCH_PROTOCOL *mCpu;
typedef struct {
//
// The linked-list next pointer
//
LIST_ENTRY List;
LIST_ENTRY List;
//
// The address of the uncached allocation
//
VOID *HostAddress;
VOID *HostAddress;
//
// The number of pages in the allocation
//
UINTN NumPages;
UINTN NumPages;
//
// The attributes of the allocation
//
UINT64 Attributes;
UINT64 Attributes;
} NON_DISCOVERABLE_DEVICE_UNCACHED_ALLOCATION;
typedef struct {
UINT32 Signature;
UINT32 Signature;
//
// The bound non-discoverable device protocol instance
//
NON_DISCOVERABLE_DEVICE *Device;
NON_DISCOVERABLE_DEVICE *Device;
//
// The exposed PCI I/O protocol instance.
//
EFI_PCI_IO_PROTOCOL PciIo;
EFI_PCI_IO_PROTOCOL PciIo;
//
// The emulated PCI config space of the device. Only the minimally required
// items are assigned.
//
PCI_TYPE00 ConfigSpace;
PCI_TYPE00 ConfigSpace;
//
// The first virtual BAR to assign based on the resources described
// by the non-discoverable device.
//
UINT32 BarOffset;
UINT32 BarOffset;
//
// The number of virtual BARs we expose based on the number of
// resources
//
UINT32 BarCount;
UINT32 BarCount;
//
// The PCI I/O attributes for this device
//
UINT64 Attributes;
UINT64 Attributes;
//
// Whether this device has been enabled
//
BOOLEAN Enabled;
BOOLEAN Enabled;
//
// Linked list to keep track of uncached allocations performed
// on behalf of this device
//
LIST_ENTRY UncachedAllocationList;
LIST_ENTRY UncachedAllocationList;
//
// Unique ID for this device instance: needed so that we can report unique
// segment/bus/device number for each device instance. Note that this number
// may change when disconnecting/reconnecting the driver.
//
UINTN UniqueId;
UINTN UniqueId;
} NON_DISCOVERABLE_PCI_DEVICE;
/**
@@ -111,10 +111,10 @@ typedef struct {
**/
VOID
InitializePciIoProtocol (
NON_DISCOVERABLE_PCI_DEVICE *Device
NON_DISCOVERABLE_PCI_DEVICE *Device
);
extern EFI_COMPONENT_NAME_PROTOCOL gComponentName;
extern EFI_COMPONENT_NAME2_PROTOCOL gComponentName2;
extern EFI_COMPONENT_NAME_PROTOCOL gComponentName;
extern EFI_COMPONENT_NAME2_PROTOCOL gComponentName2;
#endif

47
MdeModulePkg/Bus/Pci/NvmExpressDxe/ComponentName.c
View File

@@ -12,7 +12,7 @@
//
// EFI Component Name Protocol
//
GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME_PROTOCOL gNvmExpressComponentName = {
GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME_PROTOCOL gNvmExpressComponentName = {
NvmExpressComponentNameGetDriverName,
NvmExpressComponentNameGetControllerName,
"eng"
@@ -21,20 +21,20 @@ GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME_PROTOCOL gNvmExpressComponentNa
//
// EFI Component Name 2 Protocol
//
GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gNvmExpressComponentName2 = {
(EFI_COMPONENT_NAME2_GET_DRIVER_NAME) NvmExpressComponentNameGetDriverName,
(EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME) NvmExpressComponentNameGetControllerName,
GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gNvmExpressComponentName2 = {
(EFI_COMPONENT_NAME2_GET_DRIVER_NAME)NvmExpressComponentNameGetDriverName,
(EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME)NvmExpressComponentNameGetControllerName,
"en"
};
GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mNvmExpressDriverNameTable[] = {
GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mNvmExpressDriverNameTable[] = {
{ "eng;en", L"NVM Express Driver" },
{ NULL, NULL }
{ NULL, NULL }
};
GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mNvmExpressControllerNameTable[] = {
GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mNvmExpressControllerNameTable[] = {
{ "eng;en", L"NVM Express Controller" },
{ NULL, NULL }
{ NULL, NULL }
};
/**
@@ -79,9 +79,9 @@ GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mNvmExpressControllerName
EFI_STATUS
EFIAPI
NvmExpressComponentNameGetDriverName (
IN EFI_COMPONENT_NAME_PROTOCOL *This,
IN CHAR8 *Language,
OUT CHAR16 **DriverName
IN EFI_COMPONENT_NAME_PROTOCOL *This,
IN CHAR8 *Language,
OUT CHAR16 **DriverName
)
{
return LookupUnicodeString2 (
@@ -164,17 +164,17 @@ NvmExpressComponentNameGetDriverName (
EFI_STATUS
EFIAPI
NvmExpressComponentNameGetControllerName (
IN EFI_COMPONENT_NAME_PROTOCOL *This,
IN EFI_HANDLE ControllerHandle,
IN EFI_HANDLE ChildHandle OPTIONAL,
IN CHAR8 *Language,
OUT CHAR16 **ControllerName
IN EFI_COMPONENT_NAME_PROTOCOL *This,
IN EFI_HANDLE ControllerHandle,
IN EFI_HANDLE ChildHandle OPTIONAL,
IN CHAR8 *Language,
OUT CHAR16 **ControllerName
)
{
EFI_STATUS Status;
EFI_BLOCK_IO_PROTOCOL *BlockIo;
NVME_DEVICE_PRIVATE_DATA *Device;
EFI_UNICODE_STRING_TABLE *ControllerNameTable;
EFI_STATUS Status;
EFI_BLOCK_IO_PROTOCOL *BlockIo;
NVME_DEVICE_PRIVATE_DATA *Device;
EFI_UNICODE_STRING_TABLE *ControllerNameTable;
//
// Make sure this driver is currently managing ControllHandle
@@ -198,13 +198,14 @@ NvmExpressComponentNameGetControllerName (
if (EFI_ERROR (Status)) {
return Status;
}
//
// Get the child context
//
Status = gBS->OpenProtocol (
ChildHandle,
&gEfiBlockIoProtocolGuid,
(VOID **) &BlockIo,
(VOID **)&BlockIo,
gNvmExpressDriverBinding.DriverBindingHandle,
ChildHandle,
EFI_OPEN_PROTOCOL_GET_PROTOCOL
@@ -212,7 +213,8 @@ NvmExpressComponentNameGetControllerName (
if (EFI_ERROR (Status)) {
return EFI_UNSUPPORTED;
}
Device = NVME_DEVICE_PRIVATE_DATA_FROM_BLOCK_IO (BlockIo);
Device = NVME_DEVICE_PRIVATE_DATA_FROM_BLOCK_IO (BlockIo);
ControllerNameTable = Device->ControllerNameTable;
}
@@ -223,5 +225,4 @@ NvmExpressComponentNameGetControllerName (
ControllerName,
(BOOLEAN)(This == &gNvmExpressComponentName)
);
}

343
MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.c
View File

@@ -12,7 +12,7 @@
//
// NVM Express Driver Binding Protocol Instance
//
EFI_DRIVER_BINDING_PROTOCOL gNvmExpressDriverBinding = {
EFI_DRIVER_BINDING_PROTOCOL gNvmExpressDriverBinding = {
NvmExpressDriverBindingSupported,
NvmExpressDriverBindingStart,
NvmExpressDriverBindingStop,
@@ -24,7 +24,7 @@ EFI_DRIVER_BINDING_PROTOCOL gNvmExpressDriverBinding = {
//
// NVM Express EFI Driver Supported EFI Version Protocol Instance
//
EFI_DRIVER_SUPPORTED_EFI_VERSION_PROTOCOL gNvmExpressDriverSupportedEfiVersion = {
EFI_DRIVER_SUPPORTED_EFI_VERSION_PROTOCOL gNvmExpressDriverSupportedEfiVersion = {
sizeof (EFI_DRIVER_SUPPORTED_EFI_VERSION_PROTOCOL), // Size of Protocol structure.
0 // Version number to be filled at start up.
};
@@ -32,7 +32,7 @@ EFI_DRIVER_SUPPORTED_EFI_VERSION_PROTOCOL gNvmExpressDriverSupportedEfiVersion =
//
// Template for NVM Express Pass Thru Mode data structure.
//
GLOBAL_REMOVE_IF_UNREFERENCED EFI_NVM_EXPRESS_PASS_THRU_MODE gEfiNvmExpressPassThruMode = {
GLOBAL_REMOVE_IF_UNREFERENCED EFI_NVM_EXPRESS_PASS_THRU_MODE gEfiNvmExpressPassThruMode = {
EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_PHYSICAL |
EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_LOGICAL |
EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_NONBLOCKIO |
@@ -56,24 +56,24 @@ GLOBAL_REMOVE_IF_UNREFERENCED EFI_NVM_EXPRESS_PASS_THRU_MODE gEfiNvmExpressPassT
**/
EFI_STATUS
EnumerateNvmeDevNamespace (
IN NVME_CONTROLLER_PRIVATE_DATA *Private,
UINT32 NamespaceId
IN NVME_CONTROLLER_PRIVATE_DATA *Private,
UINT32 NamespaceId
)
{
NVME_ADMIN_NAMESPACE_DATA *NamespaceData;
EFI_DEVICE_PATH_PROTOCOL *NewDevicePathNode;
EFI_DEVICE_PATH_PROTOCOL *DevicePath;
EFI_HANDLE DeviceHandle;
EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath;
EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath;
NVME_DEVICE_PRIVATE_DATA *Device;
EFI_STATUS Status;
UINT32 Lbads;
UINT32 Flbas;
UINT32 LbaFmtIdx;
UINT8 Sn[21];
UINT8 Mn[41];
VOID *DummyInterface;
NVME_ADMIN_NAMESPACE_DATA *NamespaceData;
EFI_DEVICE_PATH_PROTOCOL *NewDevicePathNode;
EFI_DEVICE_PATH_PROTOCOL *DevicePath;
EFI_HANDLE DeviceHandle;
EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath;
EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath;
NVME_DEVICE_PRIVATE_DATA *Device;
EFI_STATUS Status;
UINT32 Lbads;
UINT32 Flbas;
UINT32 LbaFmtIdx;
UINT8 Sn[21];
UINT8 Mn[41];
VOID *DummyInterface;
NewDevicePathNode = NULL;
DevicePath = NULL;
@@ -82,8 +82,8 @@ EnumerateNvmeDevNamespace (
//
// Allocate a buffer for Identify Namespace data
//
NamespaceData = AllocateZeroPool(sizeof (NVME_ADMIN_NAMESPACE_DATA));
if(NamespaceData == NULL) {
NamespaceData = AllocateZeroPool (sizeof (NVME_ADMIN_NAMESPACE_DATA));
if (NamespaceData == NULL) {
return EFI_OUT_OF_RESOURCES;
}
@@ -96,9 +96,10 @@ EnumerateNvmeDevNamespace (
NamespaceId,
(VOID *)NamespaceData
);
if (EFI_ERROR(Status)) {
if (EFI_ERROR (Status)) {
goto Exit;
}
//
// Validate Namespace
//
@@ -108,7 +109,7 @@ EnumerateNvmeDevNamespace (
//
// allocate device private data for each discovered namespace
//
Device = AllocateZeroPool(sizeof(NVME_DEVICE_PRIVATE_DATA));
Device = AllocateZeroPool (sizeof (NVME_DEVICE_PRIVATE_DATA));
if (Device == NULL) {
Status = EFI_OUT_OF_RESOURCES;
goto Exit;
@@ -117,9 +118,9 @@ EnumerateNvmeDevNamespace (
//
// Initialize SSD namespace instance data
//
Device->Signature = NVME_DEVICE_PRIVATE_DATA_SIGNATURE;
Device->NamespaceId = NamespaceId;
Device->NamespaceUuid = NamespaceData->Eui64;
Device->Signature = NVME_DEVICE_PRIVATE_DATA_SIGNATURE;
Device->NamespaceId = NamespaceId;
Device->NamespaceUuid = NamespaceData->Eui64;
Device->ControllerHandle = Private->ControllerHandle;
Device->DriverBindingHandle = Private->DriverBindingHandle;
@@ -128,17 +129,17 @@ EnumerateNvmeDevNamespace (
//
// Build BlockIo media structure
//
Device->Media.MediaId = 0;
Device->Media.RemovableMedia = FALSE;
Device->Media.MediaPresent = TRUE;
Device->Media.MediaId = 0;
Device->Media.RemovableMedia = FALSE;
Device->Media.MediaPresent = TRUE;
Device->Media.LogicalPartition = FALSE;
Device->Media.ReadOnly = FALSE;
Device->Media.WriteCaching = FALSE;
Device->Media.IoAlign = Private->PassThruMode.IoAlign;
Device->Media.ReadOnly = FALSE;
Device->Media.WriteCaching = FALSE;
Device->Media.IoAlign = Private->PassThruMode.IoAlign;
Flbas = NamespaceData->Flbas;
LbaFmtIdx = Flbas & 0xF;
Lbads = NamespaceData->LbaFormat[LbaFmtIdx].Lbads;
Flbas = NamespaceData->Flbas;
LbaFmtIdx = Flbas & 0xF;
Lbads = NamespaceData->LbaFormat[LbaFmtIdx].Lbads;
Device->Media.BlockSize = (UINT32)1 << Lbads;
Device->Media.LastBlock = NamespaceData->Nsze - 1;
@@ -148,21 +149,21 @@ EnumerateNvmeDevNamespace (
//
// Create BlockIo Protocol instance
//
Device->BlockIo.Revision = EFI_BLOCK_IO_PROTOCOL_REVISION2;
Device->BlockIo.Media = &Device->Media;
Device->BlockIo.Reset = NvmeBlockIoReset;
Device->BlockIo.ReadBlocks = NvmeBlockIoReadBlocks;
Device->BlockIo.WriteBlocks = NvmeBlockIoWriteBlocks;
Device->BlockIo.FlushBlocks = NvmeBlockIoFlushBlocks;
Device->BlockIo.Revision = EFI_BLOCK_IO_PROTOCOL_REVISION2;
Device->BlockIo.Media = &Device->Media;
Device->BlockIo.Reset = NvmeBlockIoReset;
Device->BlockIo.ReadBlocks = NvmeBlockIoReadBlocks;
Device->BlockIo.WriteBlocks = NvmeBlockIoWriteBlocks;
Device->BlockIo.FlushBlocks = NvmeBlockIoFlushBlocks;
//
// Create BlockIo2 Protocol instance
//
Device->BlockIo2.Media = &Device->Media;
Device->BlockIo2.Reset = NvmeBlockIoResetEx;
Device->BlockIo2.ReadBlocksEx = NvmeBlockIoReadBlocksEx;
Device->BlockIo2.WriteBlocksEx = NvmeBlockIoWriteBlocksEx;
Device->BlockIo2.FlushBlocksEx = NvmeBlockIoFlushBlocksEx;
Device->BlockIo2.Media = &Device->Media;
Device->BlockIo2.Reset = NvmeBlockIoResetEx;
Device->BlockIo2.ReadBlocksEx = NvmeBlockIoReadBlocksEx;
Device->BlockIo2.WriteBlocksEx = NvmeBlockIoWriteBlocksEx;
Device->BlockIo2.FlushBlocksEx = NvmeBlockIoFlushBlocksEx;
InitializeListHead (&Device->AsyncQueue);
//
@@ -186,7 +187,7 @@ EnumerateNvmeDevNamespace (
&NewDevicePathNode
);
if (EFI_ERROR(Status)) {
if (EFI_ERROR (Status)) {
goto Exit;
}
@@ -199,10 +200,10 @@ EnumerateNvmeDevNamespace (
goto Exit;
}
DeviceHandle = NULL;
DeviceHandle = NULL;
RemainingDevicePath = DevicePath;
Status = gBS->LocateDevicePath (&gEfiDevicePathProtocolGuid, &RemainingDevicePath, &DeviceHandle);
if (!EFI_ERROR (Status) && (DeviceHandle != NULL) && IsDevicePathEnd(RemainingDevicePath)) {
Status = gBS->LocateDevicePath (&gEfiDevicePathProtocolGuid, &RemainingDevicePath, &DeviceHandle);
if (!EFI_ERROR (Status) && (DeviceHandle != NULL) && IsDevicePathEnd (RemainingDevicePath)) {
Status = EFI_ALREADY_STARTED;
FreePool (DevicePath);
goto Exit;
@@ -228,7 +229,7 @@ EnumerateNvmeDevNamespace (
NULL
);
if(EFI_ERROR(Status)) {
if (EFI_ERROR (Status)) {
goto Exit;
}
@@ -242,7 +243,7 @@ EnumerateNvmeDevNamespace (
EFI_NATIVE_INTERFACE,
&Device->StorageSecurity
);
if(EFI_ERROR(Status)) {
if (EFI_ERROR (Status)) {
gBS->UninstallMultipleProtocolInterfaces (
Device->DeviceHandle,
&gEfiDevicePathProtocolGuid,
@@ -262,7 +263,7 @@ EnumerateNvmeDevNamespace (
gBS->OpenProtocol (
Private->ControllerHandle,
&gEfiNvmExpressPassThruProtocolGuid,
(VOID **) &DummyInterface,
(VOID **)&DummyInterface,
Private->DriverBindingHandle,
Device->DeviceHandle,
EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER
@@ -304,7 +305,7 @@ EnumerateNvmeDevNamespace (
}
Exit:
if(NamespaceData != NULL) {
if (NamespaceData != NULL) {
FreePool (NamespaceData);
}
@@ -312,12 +313,14 @@ Exit:
FreePool (NewDevicePathNode);
}
if(EFI_ERROR(Status) && (Device != NULL) && (Device->DevicePath != NULL)) {
if (EFI_ERROR (Status) && (Device != NULL) && (Device->DevicePath != NULL)) {
FreePool (Device->DevicePath);
}
if(EFI_ERROR(Status) && (Device != NULL)) {
if (EFI_ERROR (Status) && (Device != NULL)) {
FreePool (Device);
}
return Status;
}
@@ -333,15 +336,15 @@ Exit:
**/
EFI_STATUS
DiscoverAllNamespaces (
IN NVME_CONTROLLER_PRIVATE_DATA *Private
IN NVME_CONTROLLER_PRIVATE_DATA *Private
)
{
EFI_STATUS Status;
UINT32 NamespaceId;
EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *Passthru;
EFI_STATUS Status;
UINT32 NamespaceId;
EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *Passthru;
NamespaceId = 0xFFFFFFFF;
Passthru = &Private->Passthru;
NamespaceId = 0xFFFFFFFF;
Passthru = &Private->Passthru;
while (TRUE) {
Status = Passthru->GetNextNamespace (
@@ -358,7 +361,7 @@ DiscoverAllNamespaces (
NamespaceId
);
if (EFI_ERROR(Status)) {
if (EFI_ERROR (Status)) {
continue;
}
}
@@ -382,25 +385,25 @@ DiscoverAllNamespaces (
**/
EFI_STATUS
UnregisterNvmeNamespace (
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN EFI_HANDLE Handle
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN EFI_HANDLE Handle
)
{
EFI_STATUS Status;
EFI_BLOCK_IO_PROTOCOL *BlockIo;
NVME_DEVICE_PRIVATE_DATA *Device;
EFI_STORAGE_SECURITY_COMMAND_PROTOCOL *StorageSecurity;
BOOLEAN IsEmpty;
EFI_TPL OldTpl;
VOID *DummyInterface;
EFI_STATUS Status;
EFI_BLOCK_IO_PROTOCOL *BlockIo;
NVME_DEVICE_PRIVATE_DATA *Device;
EFI_STORAGE_SECURITY_COMMAND_PROTOCOL *StorageSecurity;
BOOLEAN IsEmpty;
EFI_TPL OldTpl;
VOID *DummyInterface;
BlockIo = NULL;
Status = gBS->OpenProtocol (
Handle,
&gEfiBlockIoProtocolGuid,
(VOID **) &BlockIo,
(VOID **)&BlockIo,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_GET_PROTOCOL
@@ -409,7 +412,7 @@ UnregisterNvmeNamespace (
return Status;
}
Device = NVME_DEVICE_PRIVATE_DATA_FROM_BLOCK_IO (BlockIo);
Device = NVME_DEVICE_PRIVATE_DATA_FROM_BLOCK_IO (BlockIo);
//
// Wait for the device's asynchronous I/O queue to become empty.
@@ -457,7 +460,7 @@ UnregisterNvmeNamespace (
gBS->OpenProtocol (
Controller,
&gEfiNvmExpressPassThruProtocolGuid,
(VOID **) &DummyInterface,
(VOID **)&DummyInterface,
This->DriverBindingHandle,
Handle,
EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER
@@ -471,7 +474,7 @@ UnregisterNvmeNamespace (
Status = gBS->OpenProtocol (
Handle,
&gEfiStorageSecurityCommandProtocolGuid,
(VOID **) &StorageSecurity,
(VOID **)&StorageSecurity,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_GET_PROTOCOL
@@ -485,18 +488,18 @@ UnregisterNvmeNamespace (
);
if (EFI_ERROR (Status)) {
gBS->OpenProtocol (
Controller,
&gEfiNvmExpressPassThruProtocolGuid,
(VOID **) &DummyInterface,
This->DriverBindingHandle,
Handle,
EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER
);
Controller,
&gEfiNvmExpressPassThruProtocolGuid,
(VOID **)&DummyInterface,
This->DriverBindingHandle,
Handle,
EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER
);
return Status;
}
}
if(Device->DevicePath != NULL) {
if (Device->DevicePath != NULL) {
FreePool (Device->DevicePath);
}
@@ -520,25 +523,25 @@ UnregisterNvmeNamespace (
VOID
EFIAPI
ProcessAsyncTaskList (
IN EFI_EVENT Event,
IN VOID* Context
IN EFI_EVENT Event,
IN VOID *Context
)
{
NVME_CONTROLLER_PRIVATE_DATA *Private;
EFI_PCI_IO_PROTOCOL *PciIo;
NVME_CQ *Cq;
UINT16 QueueId;
UINT32 Data;
LIST_ENTRY *Link;
LIST_ENTRY *NextLink;
NVME_PASS_THRU_ASYNC_REQ *AsyncRequest;
NVME_BLKIO2_SUBTASK *Subtask;
NVME_BLKIO2_REQUEST *BlkIo2Request;
EFI_BLOCK_IO2_TOKEN *Token;
BOOLEAN HasNewItem;
EFI_STATUS Status;
NVME_CONTROLLER_PRIVATE_DATA *Private;
EFI_PCI_IO_PROTOCOL *PciIo;
NVME_CQ *Cq;
UINT16 QueueId;
UINT32 Data;
LIST_ENTRY *Link;
LIST_ENTRY *NextLink;
NVME_PASS_THRU_ASYNC_REQ *AsyncRequest;
NVME_BLKIO2_SUBTASK *Subtask;
NVME_BLKIO2_REQUEST *BlkIo2Request;
EFI_BLOCK_IO2_TOKEN *Token;
BOOLEAN HasNewItem;
EFI_STATUS Status;
Private = (NVME_CONTROLLER_PRIVATE_DATA*)Context;
Private = (NVME_CONTROLLER_PRIVATE_DATA *)Context;
QueueId = 2;
Cq = Private->CqBuffer[QueueId] + Private->CqHdbl[QueueId].Cqh;
HasNewItem = FALSE;
@@ -549,7 +552,8 @@ ProcessAsyncTaskList (
//
for (Link = GetFirstNode (&Private->UnsubmittedSubtasks);
!IsNull (&Private->UnsubmittedSubtasks, Link);
Link = NextLink) {
Link = NextLink)
{
NextLink = GetNextNode (&Private->UnsubmittedSubtasks, Link);
Subtask = NVME_BLKIO2_SUBTASK_FROM_LINK (Link);
BlkIo2Request = Subtask->BlockIo2Request;
@@ -563,7 +567,8 @@ ProcessAsyncTaskList (
if (Token->TransactionStatus != EFI_SUCCESS) {
if (IsListEmpty (&BlkIo2Request->SubtasksQueue) &&
BlkIo2Request->LastSubtaskSubmitted &&
(BlkIo2Request->UnsubmittedSubtaskNum == 0)) {
(BlkIo2Request->UnsubmittedSubtaskNum == 0))
{
//
// Remove the BlockIo2 request from the device asynchronous queue.
//
@@ -594,7 +599,8 @@ ProcessAsyncTaskList (
Token->TransactionStatus = EFI_DEVICE_ERROR;
if (IsListEmpty (&BlkIo2Request->SubtasksQueue) &&
Subtask->IsLast) {
Subtask->IsLast)
{
//
// Remove the BlockIo2 request from the device asynchronous queue.
//
@@ -625,8 +631,9 @@ ProcessAsyncTaskList (
//
for (Link = GetFirstNode (&Private->AsyncPassThruQueue);
!IsNull (&Private->AsyncPassThruQueue, Link);
Link = NextLink) {
NextLink = GetNextNode (&Private->AsyncPassThruQueue, Link);
Link = NextLink)
{
NextLink = GetNextNode (&Private->AsyncPassThruQueue, Link);
AsyncRequest = NVME_PASS_THRU_ASYNC_REQ_FROM_THIS (Link);
if (AsyncRequest->CommandId == Cq->Cid) {
//
@@ -636,7 +643,7 @@ ProcessAsyncTaskList (
CopyMem (
AsyncRequest->Packet->NvmeCompletion,
Cq,
sizeof(EFI_NVM_EXPRESS_COMPLETION)
sizeof (EFI_NVM_EXPRESS_COMPLETION)
);
//
@@ -645,12 +652,15 @@ ProcessAsyncTaskList (
if (AsyncRequest->MapData != NULL) {
PciIo->Unmap (PciIo, AsyncRequest->MapData);
}
if (AsyncRequest->MapMeta != NULL) {
PciIo->Unmap (PciIo, AsyncRequest->MapMeta);
}
if (AsyncRequest->MapPrpList != NULL) {
PciIo->Unmap (PciIo, AsyncRequest->MapPrpList);
}
if (AsyncRequest->PrpListHost != NULL) {
PciIo->FreeBuffer (
PciIo,
@@ -674,19 +684,19 @@ ProcessAsyncTaskList (
Private->CqHdbl[QueueId].Cqh++;
if (Private->CqHdbl[QueueId].Cqh > MIN (NVME_ASYNC_CCQ_SIZE, Private->Cap.Mqes)) {
Private->CqHdbl[QueueId].Cqh = 0;
Private->Pt[QueueId] ^= 1;
Private->Pt[QueueId] ^= 1;
}
Cq = Private->CqBuffer[QueueId] + Private->CqHdbl[QueueId].Cqh;
}
if (HasNewItem) {
Data = ReadUnaligned32 ((UINT32*)&Private->CqHdbl[QueueId]);
Data = ReadUnaligned32 ((UINT32 *)&Private->CqHdbl[QueueId]);
PciIo->Mem.Write (
PciIo,
EfiPciIoWidthUint32,
NVME_BAR,
NVME_CQHDBL_OFFSET(QueueId, Private->Cap.Dstrd),
NVME_CQHDBL_OFFSET (QueueId, Private->Cap.Dstrd),
1,
&Data
);
@@ -766,8 +776,9 @@ NvmExpressDriverBindingSupported (
if ((DevicePathNode.DevPath->Type != MESSAGING_DEVICE_PATH) ||
(DevicePathNode.DevPath->SubType != MSG_NVME_NAMESPACE_DP) ||
(DevicePathNodeLength(DevicePathNode.DevPath) != sizeof(NVME_NAMESPACE_DEVICE_PATH))) {
return EFI_UNSUPPORTED;
(DevicePathNodeLength (DevicePathNode.DevPath) != sizeof (NVME_NAMESPACE_DEVICE_PATH)))
{
return EFI_UNSUPPORTED;
}
}
}
@@ -778,7 +789,7 @@ NvmExpressDriverBindingSupported (
Status = gBS->OpenProtocol (
Controller,
&gEfiDevicePathProtocolGuid,
(VOID **) &ParentDevicePath,
(VOID **)&ParentDevicePath,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_BY_DRIVER
@@ -807,7 +818,7 @@ NvmExpressDriverBindingSupported (
Status = gBS->OpenProtocol (
Controller,
&gEfiPciIoProtocolGuid,
(VOID **) &PciIo,
(VOID **)&PciIo,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_BY_DRIVER
@@ -853,7 +864,6 @@ Done:
return Status;
}
/**
Starts a device controller or a bus controller.
@@ -915,7 +925,7 @@ NvmExpressDriverBindingStart (
Status = gBS->OpenProtocol (
Controller,
&gEfiDevicePathProtocolGuid,
(VOID **) &ParentDevicePath,
(VOID **)&ParentDevicePath,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_BY_DRIVER
@@ -927,7 +937,7 @@ NvmExpressDriverBindingStart (
Status = gBS->OpenProtocol (
Controller,
&gEfiPciIoProtocolGuid,
(VOID **) &PciIo,
(VOID **)&PciIo,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_BY_DRIVER
@@ -965,14 +975,14 @@ NvmExpressDriverBindingStart (
AllocateAnyPages,
EfiBootServicesData,
6,
(VOID**)&Private->Buffer,
(VOID **)&Private->Buffer,
0
);
if (EFI_ERROR (Status)) {
goto Exit;
}
Bytes = EFI_PAGES_TO_SIZE (6);
Bytes = EFI_PAGES_TO_SIZE (6);
Status = PciIo->Map (
PciIo,
EfiPciIoOperationBusMasterCommonBuffer,
@@ -988,7 +998,7 @@ NvmExpressDriverBindingStart (
Private->BufferPciAddr = (UINT8 *)(UINTN)MappedAddr;
Private->Signature = NVME_CONTROLLER_PRIVATE_DATA_SIGNATURE;
Private->Signature = NVME_CONTROLLER_PRIVATE_DATA_SIGNATURE;
Private->ControllerHandle = Controller;
Private->ImageHandle = This->DriverBindingHandle;
Private->DriverBindingHandle = This->DriverBindingHandle;
@@ -1004,7 +1014,7 @@ NvmExpressDriverBindingStart (
InitializeListHead (&Private->UnsubmittedSubtasks);
Status = NvmeControllerInit (Private);
if (EFI_ERROR(Status)) {
if (EFI_ERROR (Status)) {
goto Exit;
}
@@ -1046,7 +1056,7 @@ NvmExpressDriverBindingStart (
Status = gBS->OpenProtocol (
Controller,
&gEfiNvmExpressPassThruProtocolGuid,
(VOID **) &Passthru,
(VOID **)&Passthru,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_GET_PROTOCOL
@@ -1065,7 +1075,6 @@ NvmExpressDriverBindingStart (
Status = DiscoverAllNamespaces (
Private
);
} else if (!IsDevicePathEnd (RemainingDevicePath)) {
//
// Enumerate the specified NVME namespace
@@ -1127,7 +1136,6 @@ Exit:
return Status;
}
/**
Stops a device controller or a bus controller.
@@ -1157,10 +1165,10 @@ Exit:
EFI_STATUS
EFIAPI
NvmExpressDriverBindingStop (
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN UINTN NumberOfChildren,
IN EFI_HANDLE *ChildHandleBuffer
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN UINTN NumberOfChildren,
IN EFI_HANDLE *ChildHandleBuffer
)
{
EFI_STATUS Status;
@@ -1175,7 +1183,7 @@ NvmExpressDriverBindingStop (
Status = gBS->OpenProtocol (
Controller,
&gEfiNvmExpressPassThruProtocolGuid,
(VOID **) &PassThru,
(VOID **)&PassThru,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_GET_PROTOCOL
@@ -1201,11 +1209,11 @@ NvmExpressDriverBindingStop (
}
gBS->UninstallMultipleProtocolInterfaces (
Controller,
&gEfiNvmExpressPassThruProtocolGuid,
PassThru,
NULL
);
Controller,
&gEfiNvmExpressPassThruProtocolGuid,
PassThru,
NULL
);
if (Private->TimerEvent != NULL) {
gBS->CloseEvent (Private->TimerEvent);
@@ -1224,17 +1232,17 @@ NvmExpressDriverBindingStop (
}
gBS->CloseProtocol (
Controller,
&gEfiPciIoProtocolGuid,
This->DriverBindingHandle,
Controller
);
Controller,
&gEfiPciIoProtocolGuid,
This->DriverBindingHandle,
Controller
);
gBS->CloseProtocol (
Controller,
&gEfiDevicePathProtocolGuid,
This->DriverBindingHandle,
Controller
);
Controller,
&gEfiDevicePathProtocolGuid,
This->DriverBindingHandle,
Controller
);
NvmeUnregisterShutdownNotification ();
@@ -1272,15 +1280,15 @@ NvmExpressDriverBindingStop (
EFI_STATUS
EFIAPI
NvmExpressUnload (
IN EFI_HANDLE ImageHandle
IN EFI_HANDLE ImageHandle
)
{
EFI_STATUS Status;
EFI_HANDLE *DeviceHandleBuffer;
UINTN DeviceHandleCount;
UINTN Index;
EFI_COMPONENT_NAME_PROTOCOL *ComponentName;
EFI_COMPONENT_NAME2_PROTOCOL *ComponentName2;
EFI_STATUS Status;
EFI_HANDLE *DeviceHandleBuffer;
UINTN DeviceHandleCount;
UINTN Index;
EFI_COMPONENT_NAME_PROTOCOL *ComponentName;
EFI_COMPONENT_NAME2_PROTOCOL *ComponentName2;
//
// Get the list of the device handles managed by this driver.
@@ -1289,13 +1297,13 @@ NvmExpressUnload (
// those protocols installed at image handle.
//
DeviceHandleBuffer = NULL;
Status = gBS->LocateHandleBuffer (
ByProtocol,
&gEfiNvmExpressPassThruProtocolGuid,
NULL,
&DeviceHandleCount,
&DeviceHandleBuffer
);
Status = gBS->LocateHandleBuffer (
ByProtocol,
&gEfiNvmExpressPassThruProtocolGuid,
NULL,
&DeviceHandleCount,
&DeviceHandleBuffer
);
if (!EFI_ERROR (Status)) {
//
@@ -1342,7 +1350,7 @@ NvmExpressUnload (
Status = gBS->HandleProtocol (
ImageHandle,
&gEfiComponentNameProtocolGuid,
(VOID **) &ComponentName
(VOID **)&ComponentName
);
if (!EFI_ERROR (Status)) {
gBS->UninstallProtocolInterface (
@@ -1355,7 +1363,7 @@ NvmExpressUnload (
Status = gBS->HandleProtocol (
ImageHandle,
&gEfiComponentName2ProtocolGuid,
(VOID **) &ComponentName2
(VOID **)&ComponentName2
);
if (!EFI_ERROR (Status)) {
gBS->UninstallProtocolInterface (
@@ -1374,6 +1382,7 @@ EXIT:
if (DeviceHandleBuffer != NULL) {
gBS->FreePool (DeviceHandleBuffer);
}
return Status;
}
@@ -1394,7 +1403,7 @@ NvmExpressDriverEntry (
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
EFI_STATUS Status;
Status = EfiLibInstallDriverBindingComponentName2 (
ImageHandle,
@@ -1411,12 +1420,12 @@ NvmExpressDriverEntry (
// EFI drivers that are on PCI and other plug in cards.
//
gNvmExpressDriverSupportedEfiVersion.FirmwareVersion = 0x00020028;
Status = gBS->InstallMultipleProtocolInterfaces (
&ImageHandle,
&gEfiDriverSupportedEfiVersionProtocolGuid,
&gNvmExpressDriverSupportedEfiVersion,
NULL
);
Status = gBS->InstallMultipleProtocolInterfaces (
&ImageHandle,
&gEfiDriverSupportedEfiVersionProtocolGuid,
&gNvmExpressDriverSupportedEfiVersion,
NULL
);
ASSERT_EFI_ERROR (Status);
return Status;
}

185
MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.h
View File

@@ -41,8 +41,8 @@
#include <Library/UefiDriverEntryPoint.h>
#include <Library/ReportStatusCodeLib.h>
typedef struct _NVME_CONTROLLER_PRIVATE_DATA NVME_CONTROLLER_PRIVATE_DATA;
typedef struct _NVME_DEVICE_PRIVATE_DATA NVME_DEVICE_PRIVATE_DATA;
typedef struct _NVME_CONTROLLER_PRIVATE_DATA NVME_CONTROLLER_PRIVATE_DATA;
typedef struct _NVME_DEVICE_PRIVATE_DATA NVME_DEVICE_PRIVATE_DATA;
#include "NvmExpressBlockIo.h"
#include "NvmExpressDiskInfo.h"
@@ -53,67 +53,67 @@ extern EFI_COMPONENT_NAME_PROTOCOL gNvmExpressComponentName;
extern EFI_COMPONENT_NAME2_PROTOCOL gNvmExpressComponentName2;
extern EFI_DRIVER_SUPPORTED_EFI_VERSION_PROTOCOL gNvmExpressDriverSupportedEfiVersion;
#define PCI_CLASS_MASS_STORAGE_NVM 0x08 // mass storage sub-class non-volatile memory.
#define PCI_IF_NVMHCI 0x02 // mass storage programming interface NVMHCI.
#define PCI_CLASS_MASS_STORAGE_NVM 0x08 // mass storage sub-class non-volatile memory.
#define PCI_IF_NVMHCI 0x02 // mass storage programming interface NVMHCI.
#define NVME_ASQ_SIZE 1 // Number of admin submission queue entries, which is 0-based
#define NVME_ACQ_SIZE 1 // Number of admin completion queue entries, which is 0-based
#define NVME_ASQ_SIZE 1 // Number of admin submission queue entries, which is 0-based
#define NVME_ACQ_SIZE 1 // Number of admin completion queue entries, which is 0-based
#define NVME_CSQ_SIZE 1 // Number of I/O submission queue entries, which is 0-based
#define NVME_CCQ_SIZE 1 // Number of I/O completion queue entries, which is 0-based
#define NVME_CSQ_SIZE 1 // Number of I/O submission queue entries, which is 0-based
#define NVME_CCQ_SIZE 1 // Number of I/O completion queue entries, which is 0-based
//
// Number of asynchronous I/O submission queue entries, which is 0-based.
// The asynchronous I/O submission queue size is 4kB in total.
//
#define NVME_ASYNC_CSQ_SIZE 63
#define NVME_ASYNC_CSQ_SIZE 63
//
// Number of asynchronous I/O completion queue entries, which is 0-based.
// The asynchronous I/O completion queue size is 4kB in total.
//
#define NVME_ASYNC_CCQ_SIZE 255
#define NVME_ASYNC_CCQ_SIZE 255
#define NVME_MAX_QUEUES 3 // Number of queues supported by the driver
#define NVME_MAX_QUEUES 3 // Number of queues supported by the driver
#define NVME_CONTROLLER_ID 0
#define NVME_CONTROLLER_ID 0
//
// Time out value for Nvme transaction execution
//
#define NVME_GENERIC_TIMEOUT EFI_TIMER_PERIOD_SECONDS (5)
#define NVME_GENERIC_TIMEOUT EFI_TIMER_PERIOD_SECONDS (5)
//
// Nvme async transfer timer interval, set by experience.
//
#define NVME_HC_ASYNC_TIMER EFI_TIMER_PERIOD_MILLISECONDS (1)
#define NVME_HC_ASYNC_TIMER EFI_TIMER_PERIOD_MILLISECONDS (1)
//
// Unique signature for private data structure.
//
#define NVME_CONTROLLER_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('N','V','M','E')
#define NVME_CONTROLLER_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('N','V','M','E')
//
// Nvme private data structure.
//
struct _NVME_CONTROLLER_PRIVATE_DATA {
UINT32 Signature;
UINT32 Signature;
EFI_HANDLE ControllerHandle;
EFI_HANDLE ImageHandle;
EFI_HANDLE DriverBindingHandle;
EFI_HANDLE ControllerHandle;
EFI_HANDLE ImageHandle;
EFI_HANDLE DriverBindingHandle;
EFI_PCI_IO_PROTOCOL *PciIo;
UINT64 PciAttributes;
EFI_PCI_IO_PROTOCOL *PciIo;
UINT64 PciAttributes;
EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath;
EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath;
EFI_NVM_EXPRESS_PASS_THRU_MODE PassThruMode;
EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL Passthru;
EFI_NVM_EXPRESS_PASS_THRU_MODE PassThruMode;
EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL Passthru;
//
// pointer to identify controller data
//
NVME_ADMIN_CONTROLLER_DATA *ControllerData;
NVME_ADMIN_CONTROLLER_DATA *ControllerData;
//
// 6 x 4kB aligned buffers will be carved out of this buffer.
@@ -124,45 +124,45 @@ struct _NVME_CONTROLLER_PRIVATE_DATA {
// 5th 4kB boundary is the start of I/O submission queue #2.
// 6th 4kB boundary is the start of I/O completion queue #2.
//
UINT8 *Buffer;
UINT8 *BufferPciAddr;
UINT8 *Buffer;
UINT8 *BufferPciAddr;
//
// Pointers to 4kB aligned submission & completion queues.
//
NVME_SQ *SqBuffer[NVME_MAX_QUEUES];
NVME_CQ *CqBuffer[NVME_MAX_QUEUES];
NVME_SQ *SqBufferPciAddr[NVME_MAX_QUEUES];
NVME_CQ *CqBufferPciAddr[NVME_MAX_QUEUES];
NVME_SQ *SqBuffer[NVME_MAX_QUEUES];
NVME_CQ *CqBuffer[NVME_MAX_QUEUES];
NVME_SQ *SqBufferPciAddr[NVME_MAX_QUEUES];
NVME_CQ *CqBufferPciAddr[NVME_MAX_QUEUES];
//
// Submission and completion queue indices.
//
NVME_SQTDBL SqTdbl[NVME_MAX_QUEUES];
NVME_CQHDBL CqHdbl[NVME_MAX_QUEUES];
UINT16 AsyncSqHead;
NVME_SQTDBL SqTdbl[NVME_MAX_QUEUES];
NVME_CQHDBL CqHdbl[NVME_MAX_QUEUES];
UINT16 AsyncSqHead;
//
// Flag to indicate internal IO queue creation.
//
BOOLEAN CreateIoQueue;
BOOLEAN CreateIoQueue;
UINT8 Pt[NVME_MAX_QUEUES];
UINT16 Cid[NVME_MAX_QUEUES];
UINT8 Pt[NVME_MAX_QUEUES];
UINT16 Cid[NVME_MAX_QUEUES];
//
// Nvme controller capabilities
//
NVME_CAP Cap;
NVME_CAP Cap;
VOID *Mapping;
VOID *Mapping;
//
// For Non-blocking operations.
//
EFI_EVENT TimerEvent;
LIST_ENTRY AsyncPassThruQueue;
LIST_ENTRY UnsubmittedSubtasks;
EFI_EVENT TimerEvent;
LIST_ENTRY AsyncPassThruQueue;
LIST_ENTRY UnsubmittedSubtasks;
};
#define NVME_CONTROLLER_PRIVATE_DATA_FROM_PASS_THRU(a) \
@@ -175,7 +175,7 @@ struct _NVME_CONTROLLER_PRIVATE_DATA {
//
// Unique signature for private data structure.
//
#define NVME_DEVICE_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('X','S','S','D')
#define NVME_DEVICE_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('X','S','S','D')
//
// Nvme device private data structure
@@ -208,7 +208,6 @@ struct _NVME_DEVICE_PRIVATE_DATA {
NVME_ADMIN_NAMESPACE_DATA NamespaceData;
NVME_CONTROLLER_PRIVATE_DATA *Controller;
};
//
@@ -235,7 +234,7 @@ struct _NVME_DEVICE_PRIVATE_DATA {
NVME_DEVICE_PRIVATE_DATA_SIGNATURE \
)
#define NVME_DEVICE_PRIVATE_DATA_FROM_STORAGE_SECURITY(a)\
#define NVME_DEVICE_PRIVATE_DATA_FROM_STORAGE_SECURITY(a) \
CR (a, \
NVME_DEVICE_PRIVATE_DATA, \
StorageSecurity, \
@@ -245,38 +244,38 @@ struct _NVME_DEVICE_PRIVATE_DATA {
//
// Nvme block I/O 2 request.
//
#define NVME_BLKIO2_REQUEST_SIGNATURE SIGNATURE_32 ('N', 'B', '2', 'R')
#define NVME_BLKIO2_REQUEST_SIGNATURE SIGNATURE_32 ('N', 'B', '2', 'R')
typedef struct {
UINT32 Signature;
LIST_ENTRY Link;
UINT32 Signature;
LIST_ENTRY Link;
EFI_BLOCK_IO2_TOKEN *Token;
UINTN UnsubmittedSubtaskNum;
BOOLEAN LastSubtaskSubmitted;
EFI_BLOCK_IO2_TOKEN *Token;
UINTN UnsubmittedSubtaskNum;
BOOLEAN LastSubtaskSubmitted;
//
// The queue for Nvme read/write sub-tasks of a BlockIo2 request.
//
LIST_ENTRY SubtasksQueue;
LIST_ENTRY SubtasksQueue;
} NVME_BLKIO2_REQUEST;
#define NVME_BLKIO2_REQUEST_FROM_LINK(a) \
CR (a, NVME_BLKIO2_REQUEST, Link, NVME_BLKIO2_REQUEST_SIGNATURE)
#define NVME_BLKIO2_SUBTASK_SIGNATURE SIGNATURE_32 ('N', 'B', '2', 'S')
#define NVME_BLKIO2_SUBTASK_SIGNATURE SIGNATURE_32 ('N', 'B', '2', 'S')
typedef struct {
UINT32 Signature;
LIST_ENTRY Link;
UINT32 Signature;
LIST_ENTRY Link;
BOOLEAN IsLast;
UINT32 NamespaceId;
EFI_EVENT Event;
EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET *CommandPacket;
BOOLEAN IsLast;
UINT32 NamespaceId;
EFI_EVENT Event;
EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET *CommandPacket;
//
// The BlockIo2 request this subtask belongs to
//
NVME_BLKIO2_REQUEST *BlockIo2Request;
NVME_BLKIO2_REQUEST *BlockIo2Request;
} NVME_BLKIO2_SUBTASK;
#define NVME_BLKIO2_SUBTASK_FROM_LINK(a) \
@@ -285,20 +284,20 @@ typedef struct {
//
// Nvme asynchronous passthru request.
//
#define NVME_PASS_THRU_ASYNC_REQ_SIG SIGNATURE_32 ('N', 'P', 'A', 'R')
#define NVME_PASS_THRU_ASYNC_REQ_SIG SIGNATURE_32 ('N', 'P', 'A', 'R')
typedef struct {
UINT32 Signature;
LIST_ENTRY Link;
UINT32 Signature;
LIST_ENTRY Link;
EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET *Packet;
UINT16 CommandId;
VOID *MapPrpList;
UINTN PrpListNo;
VOID *PrpListHost;
VOID *MapData;
VOID *MapMeta;
EFI_EVENT CallerEvent;
EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET *Packet;
UINT16 CommandId;
VOID *MapPrpList;
UINTN PrpListNo;
VOID *PrpListHost;
VOID *MapData;
VOID *MapMeta;
EFI_EVENT CallerEvent;
} NVME_PASS_THRU_ASYNC_REQ;
#define NVME_PASS_THRU_ASYNC_REQ_FROM_THIS(a) \
@@ -426,11 +425,11 @@ NvmExpressComponentNameGetDriverName (
EFI_STATUS
EFIAPI
NvmExpressComponentNameGetControllerName (
IN EFI_COMPONENT_NAME_PROTOCOL *This,
IN EFI_HANDLE ControllerHandle,
IN EFI_HANDLE ChildHandle OPTIONAL,
IN CHAR8 *Language,
OUT CHAR16 **ControllerName
IN EFI_COMPONENT_NAME_PROTOCOL *This,
IN EFI_HANDLE ControllerHandle,
IN EFI_HANDLE ChildHandle OPTIONAL,
IN CHAR8 *Language,
OUT CHAR16 **ControllerName
);
/**
@@ -555,10 +554,10 @@ NvmExpressDriverBindingStart (
EFI_STATUS
EFIAPI
NvmExpressDriverBindingStop (
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN UINTN NumberOfChildren,
IN EFI_HANDLE *ChildHandleBuffer
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN UINTN NumberOfChildren,
IN EFI_HANDLE *ChildHandleBuffer
);
/**
@@ -594,10 +593,10 @@ NvmExpressDriverBindingStop (
EFI_STATUS
EFIAPI
NvmExpressPassThru (
IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,
IN UINT32 NamespaceId,
IN OUT EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET *Packet,
IN EFI_EVENT Event OPTIONAL
IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,
IN UINT32 NamespaceId,
IN OUT EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET *Packet,
IN EFI_EVENT Event OPTIONAL
);
/**
@@ -636,8 +635,8 @@ NvmExpressPassThru (
EFI_STATUS
EFIAPI
NvmExpressGetNextNamespace (
IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,
IN OUT UINT32 *NamespaceId
IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,
IN OUT UINT32 *NamespaceId
);
/**
@@ -667,9 +666,9 @@ NvmExpressGetNextNamespace (
EFI_STATUS
EFIAPI
NvmExpressGetNamespace (
IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,
IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
OUT UINT32 *NamespaceId
IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,
IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
OUT UINT32 *NamespaceId
);
/**
@@ -706,9 +705,9 @@ NvmExpressGetNamespace (
EFI_STATUS
EFIAPI
NvmExpressBuildDevicePath (
IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,
IN UINT32 NamespaceId,
IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath
IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,
IN UINT32 NamespaceId,
IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath
);
/**
@@ -719,7 +718,7 @@ NvmExpressBuildDevicePath (
**/
VOID
NvmeDumpStatus (
IN NVME_CQ *Cq
IN NVME_CQ *Cq
);
/**

621
MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressBlockIo.c
View File

File diff suppressed because it is too large Load Diff

82
MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressBlockIo.h
View File

@@ -23,8 +23,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
EFI_STATUS
EFIAPI
NvmeBlockIoReset (
IN EFI_BLOCK_IO_PROTOCOL *This,
IN BOOLEAN ExtendedVerification
IN EFI_BLOCK_IO_PROTOCOL *This,
IN BOOLEAN ExtendedVerification
);
/**
@@ -49,11 +49,11 @@ NvmeBlockIoReset (
EFI_STATUS
EFIAPI
NvmeBlockIoReadBlocks (
IN EFI_BLOCK_IO_PROTOCOL *This,
IN UINT32 MediaId,
IN EFI_LBA Lba,
IN UINTN BufferSize,
OUT VOID *Buffer
IN EFI_BLOCK_IO_PROTOCOL *This,
IN UINT32 MediaId,
IN EFI_LBA Lba,
IN UINTN BufferSize,
OUT VOID *Buffer
);
/**
@@ -79,11 +79,11 @@ NvmeBlockIoReadBlocks (
EFI_STATUS
EFIAPI
NvmeBlockIoWriteBlocks (
IN EFI_BLOCK_IO_PROTOCOL *This,
IN UINT32 MediaId,
IN EFI_LBA Lba,
IN UINTN BufferSize,
IN VOID *Buffer
IN EFI_BLOCK_IO_PROTOCOL *This,
IN UINT32 MediaId,
IN EFI_LBA Lba,
IN UINTN BufferSize,
IN VOID *Buffer
);
/**
@@ -99,7 +99,7 @@ NvmeBlockIoWriteBlocks (
EFI_STATUS
EFIAPI
NvmeBlockIoFlushBlocks (
IN EFI_BLOCK_IO_PROTOCOL *This
IN EFI_BLOCK_IO_PROTOCOL *This
);
/**
@@ -162,12 +162,12 @@ NvmeBlockIoResetEx (
EFI_STATUS
EFIAPI
NvmeBlockIoReadBlocksEx (
IN EFI_BLOCK_IO2_PROTOCOL *This,
IN UINT32 MediaId,
IN EFI_LBA Lba,
IN OUT EFI_BLOCK_IO2_TOKEN *Token,
IN UINTN BufferSize,
OUT VOID *Buffer
IN EFI_BLOCK_IO2_PROTOCOL *This,
IN UINT32 MediaId,
IN EFI_LBA Lba,
IN OUT EFI_BLOCK_IO2_TOKEN *Token,
IN UINTN BufferSize,
OUT VOID *Buffer
);
/**
@@ -212,11 +212,11 @@ EFI_STATUS
EFIAPI
NvmeBlockIoWriteBlocksEx (
IN EFI_BLOCK_IO2_PROTOCOL *This,
IN UINT32 MediaId,
IN EFI_LBA Lba,
IN OUT EFI_BLOCK_IO2_TOKEN *Token,
IN UINTN BufferSize,
IN VOID *Buffer
IN UINT32 MediaId,
IN EFI_LBA Lba,
IN OUT EFI_BLOCK_IO2_TOKEN *Token,
IN UINTN BufferSize,
IN VOID *Buffer
);
/**
@@ -246,8 +246,8 @@ NvmeBlockIoWriteBlocksEx (
EFI_STATUS
EFIAPI
NvmeBlockIoFlushBlocksEx (
IN EFI_BLOCK_IO2_PROTOCOL *This,
IN OUT EFI_BLOCK_IO2_TOKEN *Token
IN EFI_BLOCK_IO2_PROTOCOL *This,
IN OUT EFI_BLOCK_IO2_TOKEN *Token
);
/**
@@ -325,14 +325,14 @@ NvmeBlockIoFlushBlocksEx (
EFI_STATUS
EFIAPI
NvmeStorageSecurityReceiveData (
IN EFI_STORAGE_SECURITY_COMMAND_PROTOCOL *This,
IN UINT32 MediaId,
IN UINT64 Timeout,
IN UINT8 SecurityProtocolId,
IN UINT16 SecurityProtocolSpecificData,
IN UINTN PayloadBufferSize,
OUT VOID *PayloadBuffer,
OUT UINTN *PayloadTransferSize
IN EFI_STORAGE_SECURITY_COMMAND_PROTOCOL *This,
IN UINT32 MediaId,
IN UINT64 Timeout,
IN UINT8 SecurityProtocolId,
IN UINT16 SecurityProtocolSpecificData,
IN UINTN PayloadBufferSize,
OUT VOID *PayloadBuffer,
OUT UINTN *PayloadTransferSize
);
/**
@@ -399,13 +399,13 @@ NvmeStorageSecurityReceiveData (
EFI_STATUS
EFIAPI
NvmeStorageSecuritySendData (
IN EFI_STORAGE_SECURITY_COMMAND_PROTOCOL *This,
IN UINT32 MediaId,
IN UINT64 Timeout,
IN UINT8 SecurityProtocolId,
IN UINT16 SecurityProtocolSpecificData,
IN UINTN PayloadBufferSize,
IN VOID *PayloadBuffer
IN EFI_STORAGE_SECURITY_COMMAND_PROTOCOL *This,
IN UINT32 MediaId,
IN UINT64 Timeout,
IN UINT8 SecurityProtocolId,
IN UINT16 SecurityProtocolSpecificData,
IN UINTN PayloadBufferSize,
IN VOID *PayloadBuffer
);
#endif

39
MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDiskInfo.c
View File

@@ -8,7 +8,7 @@
#include "NvmExpress.h"
EFI_DISK_INFO_PROTOCOL gNvmExpressDiskInfoProtocolTemplate = {
EFI_DISK_INFO_PROTOCOL gNvmExpressDiskInfoProtocolTemplate = {
EFI_DISK_INFO_NVME_INTERFACE_GUID,
NvmExpressDiskInfoInquiry,
NvmExpressDiskInfoIdentify,
@@ -27,13 +27,12 @@ EFI_DISK_INFO_PROTOCOL gNvmExpressDiskInfoProtocolTemplate = {
**/
VOID
InitializeDiskInfo (
IN NVME_DEVICE_PRIVATE_DATA *Device
IN NVME_DEVICE_PRIVATE_DATA *Device
)
{
CopyMem (&Device->DiskInfo, &gNvmExpressDiskInfoProtocolTemplate, sizeof (EFI_DISK_INFO_PROTOCOL));
}
/**
Provides inquiry information for the controller type.
@@ -53,15 +52,14 @@ InitializeDiskInfo (
EFI_STATUS
EFIAPI
NvmExpressDiskInfoInquiry (
IN EFI_DISK_INFO_PROTOCOL *This,
IN OUT VOID *InquiryData,
IN OUT UINT32 *InquiryDataSize
IN EFI_DISK_INFO_PROTOCOL *This,
IN OUT VOID *InquiryData,
IN OUT UINT32 *InquiryDataSize
)
{
return EFI_NOT_FOUND;
}
/**
Provides identify information for the controller type.
@@ -83,13 +81,13 @@ NvmExpressDiskInfoInquiry (
EFI_STATUS
EFIAPI
NvmExpressDiskInfoIdentify (
IN EFI_DISK_INFO_PROTOCOL *This,
IN OUT VOID *IdentifyData,
IN OUT UINT32 *IdentifyDataSize
IN EFI_DISK_INFO_PROTOCOL *This,
IN OUT VOID *IdentifyData,
IN OUT UINT32 *IdentifyDataSize
)
{
EFI_STATUS Status;
NVME_DEVICE_PRIVATE_DATA *Device;
EFI_STATUS Status;
NVME_DEVICE_PRIVATE_DATA *Device;
Device = NVME_DEVICE_PRIVATE_DATA_FROM_DISK_INFO (This);
@@ -98,6 +96,7 @@ NvmExpressDiskInfoIdentify (
Status = EFI_SUCCESS;
CopyMem (IdentifyData, &Device->NamespaceData, sizeof (Device->NamespaceData));
}
*IdentifyDataSize = sizeof (Device->NamespaceData);
return Status;
}
@@ -122,16 +121,15 @@ NvmExpressDiskInfoIdentify (
EFI_STATUS
EFIAPI
NvmExpressDiskInfoSenseData (
IN EFI_DISK_INFO_PROTOCOL *This,
IN OUT VOID *SenseData,
IN OUT UINT32 *SenseDataSize,
OUT UINT8 *SenseDataNumber
IN EFI_DISK_INFO_PROTOCOL *This,
IN OUT VOID *SenseData,
IN OUT UINT32 *SenseDataSize,
OUT UINT8 *SenseDataNumber
)
{
return EFI_NOT_FOUND;
}
/**
This function is used to get controller information.
@@ -146,11 +144,10 @@ NvmExpressDiskInfoSenseData (
EFI_STATUS
EFIAPI
NvmExpressDiskInfoWhichIde (
IN EFI_DISK_INFO_PROTOCOL *This,
OUT UINT32 *IdeChannel,
OUT UINT32 *IdeDevice
IN EFI_DISK_INFO_PROTOCOL *This,
OUT UINT32 *IdeChannel,
OUT UINT32 *IdeDevice
)
{
return EFI_UNSUPPORTED;
}

30
MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDiskInfo.h
View File

@@ -20,10 +20,9 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
VOID
InitializeDiskInfo (
IN NVME_DEVICE_PRIVATE_DATA *Device
IN NVME_DEVICE_PRIVATE_DATA *Device
);
/**
Provides inquiry information for the controller type.
@@ -43,9 +42,9 @@ InitializeDiskInfo (
EFI_STATUS
EFIAPI
NvmExpressDiskInfoInquiry (
IN EFI_DISK_INFO_PROTOCOL *This,
IN OUT VOID *InquiryData,
IN OUT UINT32 *InquiryDataSize
IN EFI_DISK_INFO_PROTOCOL *This,
IN OUT VOID *InquiryData,
IN OUT UINT32 *InquiryDataSize
);
/**
@@ -69,9 +68,9 @@ NvmExpressDiskInfoInquiry (
EFI_STATUS
EFIAPI
NvmExpressDiskInfoIdentify (
IN EFI_DISK_INFO_PROTOCOL *This,
IN OUT VOID *IdentifyData,
IN OUT UINT32 *IdentifyDataSize
IN EFI_DISK_INFO_PROTOCOL *This,
IN OUT VOID *IdentifyData,
IN OUT UINT32 *IdentifyDataSize
);
/**
@@ -94,13 +93,12 @@ NvmExpressDiskInfoIdentify (
EFI_STATUS
EFIAPI
NvmExpressDiskInfoSenseData (
IN EFI_DISK_INFO_PROTOCOL *This,
IN OUT VOID *SenseData,
IN OUT UINT32 *SenseDataSize,
OUT UINT8 *SenseDataNumber
IN EFI_DISK_INFO_PROTOCOL *This,
IN OUT VOID *SenseData,
IN OUT UINT32 *SenseDataSize,
OUT UINT8 *SenseDataNumber
);
/**
This function is used to get controller information.
@@ -115,9 +113,9 @@ NvmExpressDiskInfoSenseData (
EFI_STATUS
EFIAPI
NvmExpressDiskInfoWhichIde (
IN EFI_DISK_INFO_PROTOCOL *This,
OUT UINT32 *IdeChannel,
OUT UINT32 *IdeDevice
IN EFI_DISK_INFO_PROTOCOL *This,
OUT UINT32 *IdeChannel,
OUT UINT32 *IdeDevice
);
#endif

382
MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c
View File

@@ -9,13 +9,13 @@
#include "NvmExpress.h"
#define NVME_SHUTDOWN_PROCESS_TIMEOUT 45
#define NVME_SHUTDOWN_PROCESS_TIMEOUT 45
//
// The number of NVME controllers managed by this driver, used by
// NvmeRegisterShutdownNotification() and NvmeUnregisterShutdownNotification().
//
UINTN mNvmeControllerNumber = 0;
UINTN mNvmeControllerNumber = 0;
/**
Read Nvm Express controller capability register.
@@ -29,13 +29,13 @@ UINTN mNvmeControllerNumber = 0;
**/
EFI_STATUS
ReadNvmeControllerCapabilities (
IN NVME_CONTROLLER_PRIVATE_DATA *Private,
IN NVME_CAP *Cap
IN NVME_CONTROLLER_PRIVATE_DATA *Private,
IN NVME_CAP *Cap
)
{
EFI_PCI_IO_PROTOCOL *PciIo;
EFI_STATUS Status;
UINT64 Data;
EFI_PCI_IO_PROTOCOL *PciIo;
EFI_STATUS Status;
UINT64 Data;
PciIo = Private->PciIo;
Status = PciIo->Mem.Read (
@@ -47,11 +47,11 @@ ReadNvmeControllerCapabilities (
&Data
);
if (EFI_ERROR(Status)) {
if (EFI_ERROR (Status)) {
return Status;
}
WriteUnaligned64 ((UINT64*)Cap, Data);
WriteUnaligned64 ((UINT64 *)Cap, Data);
return EFI_SUCCESS;
}
@@ -67,13 +67,13 @@ ReadNvmeControllerCapabilities (
**/
EFI_STATUS
ReadNvmeControllerConfiguration (
IN NVME_CONTROLLER_PRIVATE_DATA *Private,
IN NVME_CC *Cc
IN NVME_CONTROLLER_PRIVATE_DATA *Private,
IN NVME_CC *Cc
)
{
EFI_PCI_IO_PROTOCOL *PciIo;
EFI_STATUS Status;
UINT32 Data;
EFI_PCI_IO_PROTOCOL *PciIo;
EFI_STATUS Status;
UINT32 Data;
PciIo = Private->PciIo;
Status = PciIo->Mem.Read (
@@ -85,11 +85,11 @@ ReadNvmeControllerConfiguration (
&Data
);
if (EFI_ERROR(Status)) {
if (EFI_ERROR (Status)) {
return Status;
}
WriteUnaligned32 ((UINT32*)Cc, Data);
WriteUnaligned32 ((UINT32 *)Cc, Data);
return EFI_SUCCESS;
}
@@ -105,16 +105,16 @@ ReadNvmeControllerConfiguration (
**/
EFI_STATUS
WriteNvmeControllerConfiguration (
IN NVME_CONTROLLER_PRIVATE_DATA *Private,
IN NVME_CC *Cc
IN NVME_CONTROLLER_PRIVATE_DATA *Private,
IN NVME_CC *Cc
)
{
EFI_PCI_IO_PROTOCOL *PciIo;
EFI_STATUS Status;
UINT32 Data;
EFI_PCI_IO_PROTOCOL *PciIo;
EFI_STATUS Status;
UINT32 Data;
PciIo = Private->PciIo;
Data = ReadUnaligned32 ((UINT32*)Cc);
Data = ReadUnaligned32 ((UINT32 *)Cc);
Status = PciIo->Mem.Write (
PciIo,
EfiPciIoWidthUint32,
@@ -124,7 +124,7 @@ WriteNvmeControllerConfiguration (
&Data
);
if (EFI_ERROR(Status)) {
if (EFI_ERROR (Status)) {
return Status;
}
@@ -151,13 +151,13 @@ WriteNvmeControllerConfiguration (
**/
EFI_STATUS
ReadNvmeControllerStatus (
IN NVME_CONTROLLER_PRIVATE_DATA *Private,
IN NVME_CSTS *Csts
IN NVME_CONTROLLER_PRIVATE_DATA *Private,
IN NVME_CSTS *Csts
)
{
EFI_PCI_IO_PROTOCOL *PciIo;
EFI_STATUS Status;
UINT32 Data;
EFI_PCI_IO_PROTOCOL *PciIo;
EFI_STATUS Status;
UINT32 Data;
PciIo = Private->PciIo;
Status = PciIo->Mem.Read (
@@ -169,16 +169,14 @@ ReadNvmeControllerStatus (
&Data
);
if (EFI_ERROR(Status)) {
if (EFI_ERROR (Status)) {
return Status;
}
WriteUnaligned32 ((UINT32*)Csts, Data);
WriteUnaligned32 ((UINT32 *)Csts, Data);
return EFI_SUCCESS;
}
/**
Write Nvm Express admin queue attributes register.
@@ -191,16 +189,16 @@ ReadNvmeControllerStatus (
**/
EFI_STATUS
WriteNvmeAdminQueueAttributes (
IN NVME_CONTROLLER_PRIVATE_DATA *Private,
IN NVME_AQA *Aqa
IN NVME_CONTROLLER_PRIVATE_DATA *Private,
IN NVME_AQA *Aqa
)
{
EFI_PCI_IO_PROTOCOL *PciIo;
EFI_STATUS Status;
UINT32 Data;
EFI_PCI_IO_PROTOCOL *PciIo;
EFI_STATUS Status;
UINT32 Data;
PciIo = Private->PciIo;
Data = ReadUnaligned32 ((UINT32*)Aqa);
Data = ReadUnaligned32 ((UINT32 *)Aqa);
Status = PciIo->Mem.Write (
PciIo,
EfiPciIoWidthUint32,
@@ -210,7 +208,7 @@ WriteNvmeAdminQueueAttributes (
&Data
);
if (EFI_ERROR(Status)) {
if (EFI_ERROR (Status)) {
return Status;
}
@@ -220,7 +218,6 @@ WriteNvmeAdminQueueAttributes (
return EFI_SUCCESS;
}
/**
Write Nvm Express admin submission queue base address register.
@@ -233,16 +230,16 @@ WriteNvmeAdminQueueAttributes (
**/
EFI_STATUS
WriteNvmeAdminSubmissionQueueBaseAddress (
IN NVME_CONTROLLER_PRIVATE_DATA *Private,
IN NVME_ASQ *Asq
IN NVME_CONTROLLER_PRIVATE_DATA *Private,
IN NVME_ASQ *Asq
)
{
EFI_PCI_IO_PROTOCOL *PciIo;
EFI_STATUS Status;
UINT64 Data;
EFI_PCI_IO_PROTOCOL *PciIo;
EFI_STATUS Status;
UINT64 Data;
PciIo = Private->PciIo;
Data = ReadUnaligned64 ((UINT64*)Asq);
PciIo = Private->PciIo;
Data = ReadUnaligned64 ((UINT64 *)Asq);
Status = PciIo->Mem.Write (
PciIo,
@@ -253,7 +250,7 @@ WriteNvmeAdminSubmissionQueueBaseAddress (
&Data
);
if (EFI_ERROR(Status)) {
if (EFI_ERROR (Status)) {
return Status;
}
@@ -262,8 +259,6 @@ WriteNvmeAdminSubmissionQueueBaseAddress (
return EFI_SUCCESS;
}
/**
Write Nvm Express admin completion queue base address register.
@@ -276,16 +271,16 @@ WriteNvmeAdminSubmissionQueueBaseAddress (
**/
EFI_STATUS
WriteNvmeAdminCompletionQueueBaseAddress (
IN NVME_CONTROLLER_PRIVATE_DATA *Private,
IN NVME_ACQ *Acq
IN NVME_CONTROLLER_PRIVATE_DATA *Private,
IN NVME_ACQ *Acq
)
{
EFI_PCI_IO_PROTOCOL *PciIo;
EFI_STATUS Status;
UINT64 Data;
EFI_PCI_IO_PROTOCOL *PciIo;
EFI_STATUS Status;
UINT64 Data;
PciIo = Private->PciIo;
Data = ReadUnaligned64 ((UINT64*)Acq);
PciIo = Private->PciIo;
Data = ReadUnaligned64 ((UINT64 *)Acq);
Status = PciIo->Mem.Write (
PciIo,
@@ -296,7 +291,7 @@ WriteNvmeAdminCompletionQueueBaseAddress (
&Data
);
if (EFI_ERROR(Status)) {
if (EFI_ERROR (Status)) {
return Status;
}
@@ -316,20 +311,20 @@ WriteNvmeAdminCompletionQueueBaseAddress (
**/
EFI_STATUS
NvmeDisableController (
IN NVME_CONTROLLER_PRIVATE_DATA *Private
IN NVME_CONTROLLER_PRIVATE_DATA *Private
)
{
NVME_CC Cc;
NVME_CSTS Csts;
EFI_STATUS Status;
UINT32 Index;
UINT8 Timeout;
NVME_CC Cc;
NVME_CSTS Csts;
EFI_STATUS Status;
UINT32 Index;
UINT8 Timeout;
//
// Read Controller Configuration Register.
//
Status = ReadNvmeControllerConfiguration (Private, &Cc);
if (EFI_ERROR(Status)) {
if (EFI_ERROR (Status)) {
return Status;
}
@@ -340,7 +335,7 @@ NvmeDisableController (
//
Status = WriteNvmeControllerConfiguration (Private, &Cc);
if (EFI_ERROR(Status)) {
if (EFI_ERROR (Status)) {
return Status;
}
@@ -354,15 +349,15 @@ NvmeDisableController (
Timeout = Private->Cap.To;
}
for(Index = (Timeout * 500); Index != 0; --Index) {
gBS->Stall(1000);
for (Index = (Timeout * 500); Index != 0; --Index) {
gBS->Stall (1000);
//
// Check if the controller is initialized
//
Status = ReadNvmeControllerStatus (Private, &Csts);
if (EFI_ERROR(Status)) {
if (EFI_ERROR (Status)) {
return Status;
}
@@ -395,14 +390,14 @@ NvmeDisableController (
**/
EFI_STATUS
NvmeEnableController (
IN NVME_CONTROLLER_PRIVATE_DATA *Private
IN NVME_CONTROLLER_PRIVATE_DATA *Private
)
{
NVME_CC Cc;
NVME_CSTS Csts;
EFI_STATUS Status;
UINT32 Index;
UINT8 Timeout;
NVME_CC Cc;
NVME_CSTS Csts;
EFI_STATUS Status;
UINT32 Index;
UINT8 Timeout;
//
// Enable the controller.
@@ -414,7 +409,7 @@ NvmeEnableController (
Cc.Iocqes = 4;
Status = WriteNvmeControllerConfiguration (Private, &Cc);
if (EFI_ERROR(Status)) {
if (EFI_ERROR (Status)) {
return Status;
}
@@ -428,15 +423,15 @@ NvmeEnableController (
Timeout = Private->Cap.To;
}
for(Index = (Timeout * 500); Index != 0; --Index) {
gBS->Stall(1000);
for (Index = (Timeout * 500); Index != 0; --Index) {
gBS->Stall (1000);
//
// Check if the controller is initialized
//
Status = ReadNvmeControllerStatus (Private, &Csts);
if (EFI_ERROR(Status)) {
if (EFI_ERROR (Status)) {
return Status;
}
@@ -469,25 +464,25 @@ NvmeEnableController (
**/
EFI_STATUS
NvmeIdentifyController (
IN NVME_CONTROLLER_PRIVATE_DATA *Private,
IN VOID *Buffer
IN NVME_CONTROLLER_PRIVATE_DATA *Private,
IN VOID *Buffer
)
{
EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
EFI_NVM_EXPRESS_COMMAND Command;
EFI_NVM_EXPRESS_COMPLETION Completion;
EFI_STATUS Status;
EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
EFI_NVM_EXPRESS_COMMAND Command;
EFI_NVM_EXPRESS_COMPLETION Completion;
EFI_STATUS Status;
ZeroMem (&CommandPacket, sizeof(EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
ZeroMem (&Command, sizeof(EFI_NVM_EXPRESS_COMMAND));
ZeroMem (&Completion, sizeof(EFI_NVM_EXPRESS_COMPLETION));
ZeroMem (&CommandPacket, sizeof (EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
ZeroMem (&Command, sizeof (EFI_NVM_EXPRESS_COMMAND));
ZeroMem (&Completion, sizeof (EFI_NVM_EXPRESS_COMPLETION));
Command.Cdw0.Opcode = NVME_ADMIN_IDENTIFY_CMD;
//
// According to Nvm Express 1.1 spec Figure 38, When not used, the field shall be cleared to 0h.
// For the Identify command, the Namespace Identifier is only used for the Namespace data structure.
//
Command.Nsid = 0;
Command.Nsid = 0;
CommandPacket.NvmeCmd = &Command;
CommandPacket.NvmeCompletion = &Completion;
@@ -498,8 +493,8 @@ NvmeIdentifyController (
//
// Set bit 0 (Cns bit) to 1 to identify a controller
//
Command.Cdw10 = 1;
Command.Flags = CDW10_VALID;
Command.Cdw10 = 1;
Command.Flags = CDW10_VALID;
Status = Private->Passthru.PassThru (
&Private->Passthru,
@@ -524,25 +519,25 @@ NvmeIdentifyController (
**/
EFI_STATUS
NvmeIdentifyNamespace (
IN NVME_CONTROLLER_PRIVATE_DATA *Private,
IN UINT32 NamespaceId,
IN VOID *Buffer
IN NVME_CONTROLLER_PRIVATE_DATA *Private,
IN UINT32 NamespaceId,
IN VOID *Buffer
)
{
EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
EFI_NVM_EXPRESS_COMMAND Command;
EFI_NVM_EXPRESS_COMPLETION Completion;
EFI_STATUS Status;
EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
EFI_NVM_EXPRESS_COMMAND Command;
EFI_NVM_EXPRESS_COMPLETION Completion;
EFI_STATUS Status;
ZeroMem (&CommandPacket, sizeof(EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
ZeroMem (&Command, sizeof(EFI_NVM_EXPRESS_COMMAND));
ZeroMem (&Completion, sizeof(EFI_NVM_EXPRESS_COMPLETION));
ZeroMem (&CommandPacket, sizeof (EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
ZeroMem (&Command, sizeof (EFI_NVM_EXPRESS_COMMAND));
ZeroMem (&Completion, sizeof (EFI_NVM_EXPRESS_COMPLETION));
CommandPacket.NvmeCmd = &Command;
CommandPacket.NvmeCompletion = &Completion;
Command.Cdw0.Opcode = NVME_ADMIN_IDENTIFY_CMD;
Command.Nsid = NamespaceId;
Command.Cdw0.Opcode = NVME_ADMIN_IDENTIFY_CMD;
Command.Nsid = NamespaceId;
CommandPacket.TransferBuffer = Buffer;
CommandPacket.TransferLength = sizeof (NVME_ADMIN_NAMESPACE_DATA);
CommandPacket.CommandTimeout = NVME_GENERIC_TIMEOUT;
@@ -574,30 +569,30 @@ NvmeIdentifyNamespace (
**/
EFI_STATUS
NvmeCreateIoCompletionQueue (
IN NVME_CONTROLLER_PRIVATE_DATA *Private
IN NVME_CONTROLLER_PRIVATE_DATA *Private
)
{
EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
EFI_NVM_EXPRESS_COMMAND Command;
EFI_NVM_EXPRESS_COMPLETION Completion;
EFI_STATUS Status;
NVME_ADMIN_CRIOCQ CrIoCq;
UINT32 Index;
UINT16 QueueSize;
EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
EFI_NVM_EXPRESS_COMMAND Command;
EFI_NVM_EXPRESS_COMPLETION Completion;
EFI_STATUS Status;
NVME_ADMIN_CRIOCQ CrIoCq;
UINT32 Index;
UINT16 QueueSize;
Status = EFI_SUCCESS;
Status = EFI_SUCCESS;
Private->CreateIoQueue = TRUE;
for (Index = 1; Index < NVME_MAX_QUEUES; Index++) {
ZeroMem (&CommandPacket, sizeof(EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
ZeroMem (&Command, sizeof(EFI_NVM_EXPRESS_COMMAND));
ZeroMem (&Completion, sizeof(EFI_NVM_EXPRESS_COMPLETION));
ZeroMem (&CrIoCq, sizeof(NVME_ADMIN_CRIOCQ));
ZeroMem (&CommandPacket, sizeof (EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
ZeroMem (&Command, sizeof (EFI_NVM_EXPRESS_COMMAND));
ZeroMem (&Completion, sizeof (EFI_NVM_EXPRESS_COMPLETION));
ZeroMem (&CrIoCq, sizeof (NVME_ADMIN_CRIOCQ));
CommandPacket.NvmeCmd = &Command;
CommandPacket.NvmeCompletion = &Completion;
Command.Cdw0.Opcode = NVME_ADMIN_CRIOCQ_CMD;
Command.Cdw0.Opcode = NVME_ADMIN_CRIOCQ_CMD;
CommandPacket.TransferBuffer = Private->CqBufferPciAddr[Index];
CommandPacket.TransferLength = EFI_PAGE_SIZE;
CommandPacket.CommandTimeout = NVME_GENERIC_TIMEOUT;
@@ -646,30 +641,30 @@ NvmeCreateIoCompletionQueue (
**/
EFI_STATUS
NvmeCreateIoSubmissionQueue (
IN NVME_CONTROLLER_PRIVATE_DATA *Private
IN NVME_CONTROLLER_PRIVATE_DATA *Private
)
{
EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
EFI_NVM_EXPRESS_COMMAND Command;
EFI_NVM_EXPRESS_COMPLETION Completion;
EFI_STATUS Status;
NVME_ADMIN_CRIOSQ CrIoSq;
UINT32 Index;
UINT16 QueueSize;
EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
EFI_NVM_EXPRESS_COMMAND Command;
EFI_NVM_EXPRESS_COMPLETION Completion;
EFI_STATUS Status;
NVME_ADMIN_CRIOSQ CrIoSq;
UINT32 Index;
UINT16 QueueSize;
Status = EFI_SUCCESS;
Status = EFI_SUCCESS;
Private->CreateIoQueue = TRUE;
for (Index = 1; Index < NVME_MAX_QUEUES; Index++) {
ZeroMem (&CommandPacket, sizeof(EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
ZeroMem (&Command, sizeof(EFI_NVM_EXPRESS_COMMAND));
ZeroMem (&Completion, sizeof(EFI_NVM_EXPRESS_COMPLETION));
ZeroMem (&CrIoSq, sizeof(NVME_ADMIN_CRIOSQ));
ZeroMem (&CommandPacket, sizeof (EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
ZeroMem (&Command, sizeof (EFI_NVM_EXPRESS_COMMAND));
ZeroMem (&Completion, sizeof (EFI_NVM_EXPRESS_COMPLETION));
ZeroMem (&CrIoSq, sizeof (NVME_ADMIN_CRIOSQ));
CommandPacket.NvmeCmd = &Command;
CommandPacket.NvmeCompletion = &Completion;
Command.Cdw0.Opcode = NVME_ADMIN_CRIOSQ_CMD;
Command.Cdw0.Opcode = NVME_ADMIN_CRIOSQ_CMD;
CommandPacket.TransferBuffer = Private->SqBufferPciAddr[Index];
CommandPacket.TransferLength = EFI_PAGE_SIZE;
CommandPacket.CommandTimeout = NVME_GENERIC_TIMEOUT;
@@ -720,17 +715,18 @@ NvmeCreateIoSubmissionQueue (
**/
EFI_STATUS
NvmeControllerInit (
IN NVME_CONTROLLER_PRIVATE_DATA *Private
IN NVME_CONTROLLER_PRIVATE_DATA *Private
)
{
EFI_STATUS Status;
EFI_PCI_IO_PROTOCOL *PciIo;
UINT64 Supports;
NVME_AQA Aqa;
NVME_ASQ Asq;
NVME_ACQ Acq;
UINT8 Sn[21];
UINT8 Mn[41];
EFI_STATUS Status;
EFI_PCI_IO_PROTOCOL *PciIo;
UINT64 Supports;
NVME_AQA Aqa;
NVME_ASQ Asq;
NVME_ACQ Acq;
UINT8 Sn[21];
UINT8 Mn[41];
//
// Save original PCI attributes and enable this controller.
//
@@ -799,12 +795,12 @@ NvmeControllerInit (
//
ASSERT ((Private->Cap.Mpsmin + 12) <= EFI_PAGE_SHIFT);
Private->Cid[0] = 0;
Private->Cid[1] = 0;
Private->Cid[2] = 0;
Private->Pt[0] = 0;
Private->Pt[1] = 0;
Private->Pt[2] = 0;
Private->Cid[0] = 0;
Private->Cid[1] = 0;
Private->Cid[2] = 0;
Private->Pt[0] = 0;
Private->Pt[1] = 0;
Private->Pt[2] = 0;
Private->SqTdbl[0].Sqt = 0;
Private->SqTdbl[1].Sqt = 0;
Private->SqTdbl[2].Sqt = 0;
@@ -815,7 +811,7 @@ NvmeControllerInit (
Status = NvmeDisableController (Private);
if (EFI_ERROR(Status)) {
if (EFI_ERROR (Status)) {
return Status;
}
@@ -869,7 +865,7 @@ NvmeControllerInit (
//
Status = WriteNvmeAdminQueueAttributes (Private, &Aqa);
if (EFI_ERROR(Status)) {
if (EFI_ERROR (Status)) {
return Status;
}
@@ -878,7 +874,7 @@ NvmeControllerInit (
//
Status = WriteNvmeAdminSubmissionQueueBaseAddress (Private, &Asq);
if (EFI_ERROR(Status)) {
if (EFI_ERROR (Status)) {
return Status;
}
@@ -887,12 +883,12 @@ NvmeControllerInit (
//
Status = WriteNvmeAdminCompletionQueueBaseAddress (Private, &Acq);
if (EFI_ERROR(Status)) {
if (EFI_ERROR (Status)) {
return Status;
}
Status = NvmeEnableController (Private);
if (EFI_ERROR(Status)) {
if (EFI_ERROR (Status)) {
return Status;
}
@@ -900,7 +896,7 @@ NvmeControllerInit (
// Allocate buffer for Identify Controller data
//
if (Private->ControllerData == NULL) {
Private->ControllerData = (NVME_ADMIN_CONTROLLER_DATA *)AllocateZeroPool (sizeof(NVME_ADMIN_CONTROLLER_DATA));
Private->ControllerData = (NVME_ADMIN_CONTROLLER_DATA *)AllocateZeroPool (sizeof (NVME_ADMIN_CONTROLLER_DATA));
if (Private->ControllerData == NULL) {
return EFI_OUT_OF_RESOURCES;
@@ -912,8 +908,8 @@ NvmeControllerInit (
//
Status = NvmeIdentifyController (Private, Private->ControllerData);
if (EFI_ERROR(Status)) {
FreePool(Private->ControllerData);
if (EFI_ERROR (Status)) {
FreePool (Private->ControllerData);
Private->ControllerData = NULL;
return EFI_NOT_FOUND;
}
@@ -928,13 +924,13 @@ NvmeControllerInit (
DEBUG ((DEBUG_INFO, " == NVME IDENTIFY CONTROLLER DATA ==\n"));
DEBUG ((DEBUG_INFO, " PCI VID : 0x%x\n", Private->ControllerData->Vid));
DEBUG ((DEBUG_INFO, " PCI SSVID : 0x%x\n", Private->ControllerData->Ssvid));
DEBUG ((DEBUG_INFO, " SN : %a\n", Sn));
DEBUG ((DEBUG_INFO, " MN : %a\n", Mn));
DEBUG ((DEBUG_INFO, " FR : 0x%x\n", *((UINT64*)Private->ControllerData->Fr)));
DEBUG ((DEBUG_INFO, " TNVMCAP (high 8-byte) : 0x%lx\n", *((UINT64*)(Private->ControllerData->Tnvmcap + 8))));
DEBUG ((DEBUG_INFO, " TNVMCAP (low 8-byte) : 0x%lx\n", *((UINT64*)Private->ControllerData->Tnvmcap)));
DEBUG ((DEBUG_INFO, " SN : %a\n", Sn));
DEBUG ((DEBUG_INFO, " MN : %a\n", Mn));
DEBUG ((DEBUG_INFO, " FR : 0x%x\n", *((UINT64 *)Private->ControllerData->Fr)));
DEBUG ((DEBUG_INFO, " TNVMCAP (high 8-byte) : 0x%lx\n", *((UINT64 *)(Private->ControllerData->Tnvmcap + 8))));
DEBUG ((DEBUG_INFO, " TNVMCAP (low 8-byte) : 0x%lx\n", *((UINT64 *)Private->ControllerData->Tnvmcap)));
DEBUG ((DEBUG_INFO, " RAB : 0x%x\n", Private->ControllerData->Rab));
DEBUG ((DEBUG_INFO, " IEEE : 0x%x\n", *(UINT32*)Private->ControllerData->Ieee_oui));
DEBUG ((DEBUG_INFO, " IEEE : 0x%x\n", *(UINT32 *)Private->ControllerData->Ieee_oui));
DEBUG ((DEBUG_INFO, " AERL : 0x%x\n", Private->ControllerData->Aerl));
DEBUG ((DEBUG_INFO, " SQES : 0x%x\n", Private->ControllerData->Sqes));
DEBUG ((DEBUG_INFO, " CQES : 0x%x\n", Private->ControllerData->Cqes));
@@ -945,8 +941,8 @@ NvmeControllerInit (
// One for blocking I/O, one for non-blocking I/O.
//
Status = NvmeCreateIoCompletionQueue (Private);
if (EFI_ERROR(Status)) {
return Status;
if (EFI_ERROR (Status)) {
return Status;
}
//
@@ -976,24 +972,24 @@ NvmeControllerInit (
VOID
EFIAPI
NvmeShutdownAllControllers (
IN EFI_RESET_TYPE ResetType,
IN EFI_STATUS ResetStatus,
IN UINTN DataSize,
IN VOID *ResetData OPTIONAL
IN EFI_RESET_TYPE ResetType,
IN EFI_STATUS ResetStatus,
IN UINTN DataSize,
IN VOID *ResetData OPTIONAL
)
{
EFI_STATUS Status;
EFI_HANDLE *Handles;
UINTN HandleCount;
UINTN HandleIndex;
EFI_OPEN_PROTOCOL_INFORMATION_ENTRY *OpenInfos;
UINTN OpenInfoCount;
UINTN OpenInfoIndex;
EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *NvmePassThru;
NVME_CC Cc;
NVME_CSTS Csts;
UINTN Index;
NVME_CONTROLLER_PRIVATE_DATA *Private;
EFI_STATUS Status;
EFI_HANDLE *Handles;
UINTN HandleCount;
UINTN HandleIndex;
EFI_OPEN_PROTOCOL_INFORMATION_ENTRY *OpenInfos;
UINTN OpenInfoCount;
UINTN OpenInfoIndex;
EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *NvmePassThru;
NVME_CC Cc;
NVME_CSTS Csts;
UINTN Index;
NVME_CONTROLLER_PRIVATE_DATA *Private;
Status = gBS->LocateHandleBuffer (
ByProtocol,
@@ -1023,11 +1019,12 @@ NvmeShutdownAllControllers (
// gImageHandle equals to DriverBinding handle for this driver.
//
if (((OpenInfos[OpenInfoIndex].Attributes & EFI_OPEN_PROTOCOL_BY_DRIVER) != 0) &&
(OpenInfos[OpenInfoIndex].AgentHandle == gImageHandle)) {
(OpenInfos[OpenInfoIndex].AgentHandle == gImageHandle))
{
Status = gBS->OpenProtocol (
OpenInfos[OpenInfoIndex].ControllerHandle,
&gEfiNvmExpressPassThruProtocolGuid,
(VOID **) &NvmePassThru,
(VOID **)&NvmePassThru,
NULL,
NULL,
EFI_OPEN_PROTOCOL_GET_PROTOCOL
@@ -1035,22 +1032,24 @@ NvmeShutdownAllControllers (
if (EFI_ERROR (Status)) {
continue;
}
Private = NVME_CONTROLLER_PRIVATE_DATA_FROM_PASS_THRU (NvmePassThru);
//
// Read Controller Configuration Register.
//
Status = ReadNvmeControllerConfiguration (Private, &Cc);
if (EFI_ERROR(Status)) {
if (EFI_ERROR (Status)) {
continue;
}
//
// The host should set the Shutdown Notification (CC.SHN) field to 01b
// to indicate a normal shutdown operation.
//
Cc.Shn = NVME_CC_SHN_NORMAL_SHUTDOWN;
Status = WriteNvmeControllerConfiguration (Private, &Cc);
if (EFI_ERROR(Status)) {
if (EFI_ERROR (Status)) {
continue;
}
@@ -1061,10 +1060,11 @@ NvmeShutdownAllControllers (
//
for (Index = 0; Index < NVME_SHUTDOWN_PROCESS_TIMEOUT * 100; Index++) {
Status = ReadNvmeControllerStatus (Private, &Csts);
if (!EFI_ERROR(Status) && (Csts.Shst == NVME_CSTS_SHST_SHUTDOWN_COMPLETED)) {
DEBUG((DEBUG_INFO, "NvmeShutdownController: shutdown processing is completed after %dms.\n", Index * 10));
if (!EFI_ERROR (Status) && (Csts.Shst == NVME_CSTS_SHST_SHUTDOWN_COMPLETED)) {
DEBUG ((DEBUG_INFO, "NvmeShutdownController: shutdown processing is completed after %dms.\n", Index * 10));
break;
}
//
// Stall for 10ms
//
@@ -1072,7 +1072,7 @@ NvmeShutdownAllControllers (
}
if (Index == NVME_SHUTDOWN_PROCESS_TIMEOUT * 100) {
DEBUG((DEBUG_ERROR, "NvmeShutdownController: shutdown processing is timed out\n"));
DEBUG ((DEBUG_ERROR, "NvmeShutdownController: shutdown processing is timed out\n"));
}
}
}
@@ -1089,12 +1089,12 @@ NvmeRegisterShutdownNotification (
VOID
)
{
EFI_STATUS Status;
EFI_RESET_NOTIFICATION_PROTOCOL *ResetNotify;
EFI_STATUS Status;
EFI_RESET_NOTIFICATION_PROTOCOL *ResetNotify;
mNvmeControllerNumber++;
if (mNvmeControllerNumber == 1) {
Status = gBS->LocateProtocol (&gEfiResetNotificationProtocolGuid, NULL, (VOID **) &ResetNotify);
Status = gBS->LocateProtocol (&gEfiResetNotificationProtocolGuid, NULL, (VOID **)&ResetNotify);
if (!EFI_ERROR (Status)) {
Status = ResetNotify->RegisterResetNotify (ResetNotify, NvmeShutdownAllControllers);
ASSERT_EFI_ERROR (Status);
@@ -1114,12 +1114,12 @@ NvmeUnregisterShutdownNotification (
VOID
)
{
EFI_STATUS Status;
EFI_RESET_NOTIFICATION_PROTOCOL *ResetNotify;
EFI_STATUS Status;
EFI_RESET_NOTIFICATION_PROTOCOL *ResetNotify;
mNvmeControllerNumber--;
if (mNvmeControllerNumber == 0) {
Status = gBS->LocateProtocol (&gEfiResetNotificationProtocolGuid, NULL, (VOID **) &ResetNotify);
Status = gBS->LocateProtocol (&gEfiResetNotificationProtocolGuid, NULL, (VOID **)&ResetNotify);
if (!EFI_ERROR (Status)) {
Status = ResetNotify->UnregisterResetNotify (ResetNotify, NvmeShutdownAllControllers);
ASSERT_EFI_ERROR (Status);

17
MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.h
View File

@@ -11,12 +11,12 @@
#ifndef _NVME_HCI_H_
#define _NVME_HCI_H_
#define NVME_BAR 0
#define NVME_BAR 0
//
// Offset from the beginning of private data queue buffer
//
#define NVME_ASQ_BUF_OFFSET EFI_PAGE_SIZE
#define NVME_ASQ_BUF_OFFSET EFI_PAGE_SIZE
/**
Initialize the Nvm Express controller.
@@ -29,7 +29,7 @@
**/
EFI_STATUS
NvmeControllerInit (
IN NVME_CONTROLLER_PRIVATE_DATA *Private
IN NVME_CONTROLLER_PRIVATE_DATA *Private
);
/**
@@ -44,8 +44,8 @@ NvmeControllerInit (
**/
EFI_STATUS
NvmeIdentifyController (
IN NVME_CONTROLLER_PRIVATE_DATA *Private,
IN VOID *Buffer
IN NVME_CONTROLLER_PRIVATE_DATA *Private,
IN VOID *Buffer
);
/**
@@ -61,10 +61,9 @@ NvmeIdentifyController (
**/
EFI_STATUS
NvmeIdentifyNamespace (
IN NVME_CONTROLLER_PRIVATE_DATA *Private,
IN UINT32 NamespaceId,
IN VOID *Buffer
IN NVME_CONTROLLER_PRIVATE_DATA *Private,
IN UINT32 NamespaceId,
IN VOID *Buffer
);
#endif

320
MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressPassthru.c
View File

@@ -18,7 +18,7 @@
**/
VOID
NvmeDumpStatus (
IN NVME_CQ *Cq
IN NVME_CQ *Cq
)
{
DEBUG ((DEBUG_VERBOSE, "Dump NVMe Completion Entry Status from [0x%x]:\n", Cq));
@@ -97,6 +97,7 @@ NvmeDumpStatus (
DEBUG ((DEBUG_VERBOSE, "Reservation Conflict\n"));
break;
}
break;
case 0x1:
@@ -159,6 +160,7 @@ NvmeDumpStatus (
DEBUG ((DEBUG_VERBOSE, "Attempted Write to Read Only Range\n"));
break;
}
break;
case 0x2:
@@ -185,6 +187,7 @@ NvmeDumpStatus (
DEBUG ((DEBUG_VERBOSE, "Access Denied\n"));
break;
}
break;
default:
@@ -206,24 +209,24 @@ NvmeDumpStatus (
@retval The pointer to the first PRP List of the PRP lists.
**/
VOID*
VOID *
NvmeCreatePrpList (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN EFI_PHYSICAL_ADDRESS PhysicalAddr,
IN UINTN Pages,
OUT VOID **PrpListHost,
IN OUT UINTN *PrpListNo,
OUT VOID **Mapping
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN EFI_PHYSICAL_ADDRESS PhysicalAddr,
IN UINTN Pages,
OUT VOID **PrpListHost,
IN OUT UINTN *PrpListNo,
OUT VOID **Mapping
)
{
UINTN PrpEntryNo;
UINT64 PrpListBase;
UINTN PrpListIndex;
UINTN PrpEntryIndex;
UINT64 Remainder;
EFI_PHYSICAL_ADDRESS PrpListPhyAddr;
UINTN Bytes;
EFI_STATUS Status;
UINTN PrpEntryNo;
UINT64 PrpListBase;
UINTN PrpListIndex;
UINTN PrpEntryIndex;
UINT64 Remainder;
EFI_PHYSICAL_ADDRESS PrpListPhyAddr;
UINTN Bytes;
EFI_STATUS Status;
//
// The number of Prp Entry in a memory page.
@@ -257,7 +260,7 @@ NvmeCreatePrpList (
return NULL;
}
Bytes = EFI_PAGES_TO_SIZE (*PrpListNo);
Bytes = EFI_PAGES_TO_SIZE (*PrpListNo);
Status = PciIo->Map (
PciIo,
EfiPciIoOperationBusMasterCommonBuffer,
@@ -271,45 +274,46 @@ NvmeCreatePrpList (
DEBUG ((DEBUG_ERROR, "NvmeCreatePrpList: create PrpList failure!\n"));
goto EXIT;
}
//
// Fill all PRP lists except of last one.
//
ZeroMem (*PrpListHost, Bytes);
for (PrpListIndex = 0; PrpListIndex < *PrpListNo - 1; ++PrpListIndex) {
PrpListBase = *(UINT64*)PrpListHost + PrpListIndex * EFI_PAGE_SIZE;
PrpListBase = *(UINT64 *)PrpListHost + PrpListIndex * EFI_PAGE_SIZE;
for (PrpEntryIndex = 0; PrpEntryIndex < PrpEntryNo; ++PrpEntryIndex) {
if (PrpEntryIndex != PrpEntryNo - 1) {
//
// Fill all PRP entries except of last one.
//
*((UINT64*)(UINTN)PrpListBase + PrpEntryIndex) = PhysicalAddr;
PhysicalAddr += EFI_PAGE_SIZE;
*((UINT64 *)(UINTN)PrpListBase + PrpEntryIndex) = PhysicalAddr;
PhysicalAddr += EFI_PAGE_SIZE;
} else {
//
// Fill last PRP entries with next PRP List pointer.
//
*((UINT64*)(UINTN)PrpListBase + PrpEntryIndex) = PrpListPhyAddr + (PrpListIndex + 1) * EFI_PAGE_SIZE;
*((UINT64 *)(UINTN)PrpListBase + PrpEntryIndex) = PrpListPhyAddr + (PrpListIndex + 1) * EFI_PAGE_SIZE;
}
}
}
//
// Fill last PRP list.
//
PrpListBase = *(UINT64*)PrpListHost + PrpListIndex * EFI_PAGE_SIZE;
PrpListBase = *(UINT64 *)PrpListHost + PrpListIndex * EFI_PAGE_SIZE;
for (PrpEntryIndex = 0; PrpEntryIndex < Remainder; ++PrpEntryIndex) {
*((UINT64*)(UINTN)PrpListBase + PrpEntryIndex) = PhysicalAddr;
PhysicalAddr += EFI_PAGE_SIZE;
*((UINT64 *)(UINTN)PrpListBase + PrpEntryIndex) = PhysicalAddr;
PhysicalAddr += EFI_PAGE_SIZE;
}
return (VOID*)(UINTN)PrpListPhyAddr;
return (VOID *)(UINTN)PrpListPhyAddr;
EXIT:
PciIo->FreeBuffer (PciIo, *PrpListNo, *PrpListHost);
return NULL;
}
/**
Aborts the asynchronous PassThru requests.
@@ -322,18 +326,18 @@ EXIT:
**/
EFI_STATUS
AbortAsyncPassThruTasks (
IN NVME_CONTROLLER_PRIVATE_DATA *Private
IN NVME_CONTROLLER_PRIVATE_DATA *Private
)
{
EFI_PCI_IO_PROTOCOL *PciIo;
LIST_ENTRY *Link;
LIST_ENTRY *NextLink;
NVME_BLKIO2_SUBTASK *Subtask;
NVME_BLKIO2_REQUEST *BlkIo2Request;
NVME_PASS_THRU_ASYNC_REQ *AsyncRequest;
EFI_BLOCK_IO2_TOKEN *Token;
EFI_TPL OldTpl;
EFI_STATUS Status;
EFI_PCI_IO_PROTOCOL *PciIo;
LIST_ENTRY *Link;
LIST_ENTRY *NextLink;
NVME_BLKIO2_SUBTASK *Subtask;
NVME_BLKIO2_REQUEST *BlkIo2Request;
NVME_PASS_THRU_ASYNC_REQ *AsyncRequest;
EFI_BLOCK_IO2_TOKEN *Token;
EFI_TPL OldTpl;
EFI_STATUS Status;
PciIo = Private->PciIo;
OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
@@ -343,7 +347,8 @@ AbortAsyncPassThruTasks (
//
for (Link = GetFirstNode (&Private->UnsubmittedSubtasks);
!IsNull (&Private->UnsubmittedSubtasks, Link);
Link = NextLink) {
Link = NextLink)
{
NextLink = GetNextNode (&Private->UnsubmittedSubtasks, Link);
Subtask = NVME_BLKIO2_SUBTASK_FROM_LINK (Link);
BlkIo2Request = Subtask->BlockIo2Request;
@@ -353,6 +358,7 @@ AbortAsyncPassThruTasks (
if (Subtask->IsLast) {
BlkIo2Request->LastSubtaskSubmitted = TRUE;
}
Token->TransactionStatus = EFI_ABORTED;
RemoveEntryList (Link);
@@ -365,19 +371,23 @@ AbortAsyncPassThruTasks (
//
for (Link = GetFirstNode (&Private->AsyncPassThruQueue);
!IsNull (&Private->AsyncPassThruQueue, Link);
Link = NextLink) {
NextLink = GetNextNode (&Private->AsyncPassThruQueue, Link);
Link = NextLink)
{
NextLink = GetNextNode (&Private->AsyncPassThruQueue, Link);
AsyncRequest = NVME_PASS_THRU_ASYNC_REQ_FROM_THIS (Link);
if (AsyncRequest->MapData != NULL) {
PciIo->Unmap (PciIo, AsyncRequest->MapData);
}
if (AsyncRequest->MapMeta != NULL) {
PciIo->Unmap (PciIo, AsyncRequest->MapMeta);
}
if (AsyncRequest->MapPrpList != NULL) {
PciIo->Unmap (PciIo, AsyncRequest->MapPrpList);
}
if (AsyncRequest->PrpListHost != NULL) {
PciIo->FreeBuffer (
PciIo,
@@ -392,7 +402,8 @@ AbortAsyncPassThruTasks (
}
if (IsListEmpty (&Private->AsyncPassThruQueue) &&
IsListEmpty (&Private->UnsubmittedSubtasks)) {
IsListEmpty (&Private->UnsubmittedSubtasks))
{
Status = EFI_SUCCESS;
} else {
Status = EFI_DEVICE_ERROR;
@@ -403,7 +414,6 @@ AbortAsyncPassThruTasks (
return Status;
}
/**
Sends an NVM Express Command Packet to an NVM Express controller or namespace. This function supports
both blocking I/O and non-blocking I/O. The blocking I/O functionality is required, and the non-blocking
@@ -439,10 +449,10 @@ AbortAsyncPassThruTasks (
EFI_STATUS
EFIAPI
NvmExpressPassThru (
IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,
IN UINT32 NamespaceId,
IN OUT EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET *Packet,
IN EFI_EVENT Event OPTIONAL
IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,
IN UINT32 NamespaceId,
IN OUT EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET *Packet,
IN EFI_EVENT Event OPTIONAL
)
{
NVME_CONTROLLER_PRIVATE_DATA *Private;
@@ -483,7 +493,7 @@ NvmExpressPassThru (
return EFI_INVALID_PARAMETER;
}
if (Packet->QueueType != NVME_ADMIN_QUEUE && Packet->QueueType != NVME_IO_QUEUE) {
if ((Packet->QueueType != NVME_ADMIN_QUEUE) && (Packet->QueueType != NVME_IO_QUEUE)) {
return EFI_INVALID_PARAMETER;
}
@@ -492,31 +502,33 @@ NvmExpressPassThru (
// EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_PHYSICAL set is an illegal
// configuration.
//
Attributes = This->Mode->Attributes;
Attributes = This->Mode->Attributes;
if ((Attributes & (EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_PHYSICAL |
EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_LOGICAL)) == 0) {
EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_LOGICAL)) == 0)
{
return EFI_INVALID_PARAMETER;
}
//
// Buffer alignment check for TransferBuffer & MetadataBuffer.
//
IoAlign = This->Mode->IoAlign;
if (IoAlign > 0 && (((UINTN) Packet->TransferBuffer & (IoAlign - 1)) != 0)) {
IoAlign = This->Mode->IoAlign;
if ((IoAlign > 0) && (((UINTN)Packet->TransferBuffer & (IoAlign - 1)) != 0)) {
return EFI_INVALID_PARAMETER;
}
if (IoAlign > 0 && (((UINTN) Packet->MetadataBuffer & (IoAlign - 1)) != 0)) {
if ((IoAlign > 0) && (((UINTN)Packet->MetadataBuffer & (IoAlign - 1)) != 0)) {
return EFI_INVALID_PARAMETER;
}
Private = NVME_CONTROLLER_PRIVATE_DATA_FROM_PASS_THRU (This);
Private = NVME_CONTROLLER_PRIVATE_DATA_FROM_PASS_THRU (This);
//
// Check NamespaceId is valid or not.
//
if ((NamespaceId > Private->ControllerData->Nn) &&
(NamespaceId != (UINT32) -1)) {
(NamespaceId != (UINT32)-1))
{
return EFI_INVALID_PARAMETER;
}
@@ -555,13 +567,15 @@ NvmExpressPassThru (
// Submission queue full check.
//
if ((Private->SqTdbl[QueueId].Sqt + 1) % QueueSize ==
Private->AsyncSqHead) {
Private->AsyncSqHead)
{
return EFI_NOT_READY;
}
}
}
Sq = Private->SqBuffer[QueueId] + Private->SqTdbl[QueueId].Sqt;
Cq = Private->CqBuffer[QueueId] + Private->CqHdbl[QueueId].Cqh;
Sq = Private->SqBuffer[QueueId] + Private->SqTdbl[QueueId].Sqt;
Cq = Private->CqBuffer[QueueId] + Private->CqHdbl[QueueId].Cqh;
if (Packet->NvmeCmd->Nsid != NamespaceId) {
return EFI_INVALID_PARAMETER;
@@ -584,7 +598,8 @@ NvmExpressPassThru (
Sq->Prp[0] = (UINT64)(UINTN)Packet->TransferBuffer;
if ((Packet->QueueType == NVME_ADMIN_QUEUE) &&
((Sq->Opc == NVME_ADMIN_CRIOCQ_CMD) || (Sq->Opc == NVME_ADMIN_CRIOSQ_CMD))) {
((Sq->Opc == NVME_ADMIN_CRIOCQ_CMD) || (Sq->Opc == NVME_ADMIN_CRIOSQ_CMD)))
{
//
// Currently, we only use the IO Completion/Submission queues created internally
// by this driver during controller initialization. Any other IO queues created
@@ -601,7 +616,8 @@ NvmExpressPassThru (
// If the NVMe cmd has data in or out, then mapping the user buffer to the PCI controller specific addresses.
//
if (((Packet->TransferLength != 0) && (Packet->TransferBuffer == NULL)) ||
((Packet->TransferLength == 0) && (Packet->TransferBuffer != NULL))) {
((Packet->TransferLength == 0) && (Packet->TransferBuffer != NULL)))
{
return EFI_INVALID_PARAMETER;
}
@@ -613,14 +629,14 @@ NvmExpressPassThru (
if ((Packet->TransferLength != 0) && (Packet->TransferBuffer != NULL)) {
MapLength = Packet->TransferLength;
Status = PciIo->Map (
PciIo,
Flag,
Packet->TransferBuffer,
&MapLength,
&PhyAddr,
&MapData
);
Status = PciIo->Map (
PciIo,
Flag,
Packet->TransferBuffer,
&MapLength,
&PhyAddr,
&MapData
);
if (EFI_ERROR (Status) || (Packet->TransferLength != MapLength)) {
return EFI_OUT_OF_RESOURCES;
}
@@ -629,16 +645,16 @@ NvmExpressPassThru (
Sq->Prp[1] = 0;
}
if((Packet->MetadataLength != 0) && (Packet->MetadataBuffer != NULL)) {
if ((Packet->MetadataLength != 0) && (Packet->MetadataBuffer != NULL)) {
MapLength = Packet->MetadataLength;
Status = PciIo->Map (
PciIo,
Flag,
Packet->MetadataBuffer,
&MapLength,
&PhyAddr,
&MapMeta
);
Status = PciIo->Map (
PciIo,
Flag,
Packet->MetadataBuffer,
&MapLength,
&PhyAddr,
&MapMeta
);
if (EFI_ERROR (Status) || (Packet->MetadataLength != MapLength)) {
PciIo->Unmap (
PciIo,
@@ -647,9 +663,11 @@ NvmExpressPassThru (
return EFI_OUT_OF_RESOURCES;
}
Sq->Mptr = PhyAddr;
}
}
//
// If the buffer size spans more than two memory pages (page size as defined in CC.Mps),
// then build a PRP list in the second PRP submission queue entry.
@@ -662,7 +680,7 @@ NvmExpressPassThru (
// Create PrpList for remaining data buffer.
//
PhyAddr = (Sq->Prp[0] + EFI_PAGE_SIZE) & ~(EFI_PAGE_SIZE - 1);
Prp = NvmeCreatePrpList (PciIo, PhyAddr, EFI_SIZE_TO_PAGES(Offset + Bytes) - 1, &PrpListHost, &PrpListNo, &MapPrpList);
Prp = NvmeCreatePrpList (PciIo, PhyAddr, EFI_SIZE_TO_PAGES (Offset + Bytes) - 1, &PrpListHost, &PrpListNo, &MapPrpList);
if (Prp == NULL) {
Status = EFI_OUT_OF_RESOURCES;
goto EXIT;
@@ -673,28 +691,35 @@ NvmExpressPassThru (
Sq->Prp[1] = (Sq->Prp[0] + EFI_PAGE_SIZE) & ~(EFI_PAGE_SIZE - 1);
}
if(Packet->NvmeCmd->Flags & CDW2_VALID) {
if (Packet->NvmeCmd->Flags & CDW2_VALID) {
Sq->Rsvd2 = (UINT64)Packet->NvmeCmd->Cdw2;
}
if(Packet->NvmeCmd->Flags & CDW3_VALID) {
if (Packet->NvmeCmd->Flags & CDW3_VALID) {
Sq->Rsvd2 |= LShiftU64 ((UINT64)Packet->NvmeCmd->Cdw3, 32);
}
if(Packet->NvmeCmd->Flags & CDW10_VALID) {
if (Packet->NvmeCmd->Flags & CDW10_VALID) {
Sq->Payload.Raw.Cdw10 = Packet->NvmeCmd->Cdw10;
}
if(Packet->NvmeCmd->Flags & CDW11_VALID) {
if (Packet->NvmeCmd->Flags & CDW11_VALID) {
Sq->Payload.Raw.Cdw11 = Packet->NvmeCmd->Cdw11;
}
if(Packet->NvmeCmd->Flags & CDW12_VALID) {
if (Packet->NvmeCmd->Flags & CDW12_VALID) {
Sq->Payload.Raw.Cdw12 = Packet->NvmeCmd->Cdw12;
}
if(Packet->NvmeCmd->Flags & CDW13_VALID) {
if (Packet->NvmeCmd->Flags & CDW13_VALID) {
Sq->Payload.Raw.Cdw13 = Packet->NvmeCmd->Cdw13;
}
if(Packet->NvmeCmd->Flags & CDW14_VALID) {
if (Packet->NvmeCmd->Flags & CDW14_VALID) {
Sq->Payload.Raw.Cdw14 = Packet->NvmeCmd->Cdw14;
}
if(Packet->NvmeCmd->Flags & CDW15_VALID) {
if (Packet->NvmeCmd->Flags & CDW15_VALID) {
Sq->Payload.Raw.Cdw15 = Packet->NvmeCmd->Cdw15;
}
@@ -707,15 +732,16 @@ NvmExpressPassThru (
} else {
Private->SqTdbl[QueueId].Sqt ^= 1;
}
Data = ReadUnaligned32 ((UINT32*)&Private->SqTdbl[QueueId]);
Data = ReadUnaligned32 ((UINT32 *)&Private->SqTdbl[QueueId]);
Status = PciIo->Mem.Write (
PciIo,
EfiPciIoWidthUint32,
NVME_BAR,
NVME_SQTDBL_OFFSET(QueueId, Private->Cap.Dstrd),
1,
&Data
);
PciIo,
EfiPciIoWidthUint32,
NVME_BAR,
NVME_SQTDBL_OFFSET (QueueId, Private->Cap.Dstrd),
1,
&Data
);
if (EFI_ERROR (Status)) {
goto EXIT;
@@ -732,15 +758,15 @@ NvmExpressPassThru (
goto EXIT;
}
AsyncRequest->Signature = NVME_PASS_THRU_ASYNC_REQ_SIG;
AsyncRequest->Packet = Packet;
AsyncRequest->CommandId = Sq->Cid;
AsyncRequest->CallerEvent = Event;
AsyncRequest->MapData = MapData;
AsyncRequest->MapMeta = MapMeta;
AsyncRequest->MapPrpList = MapPrpList;
AsyncRequest->PrpListNo = PrpListNo;
AsyncRequest->PrpListHost = PrpListHost;
AsyncRequest->Signature = NVME_PASS_THRU_ASYNC_REQ_SIG;
AsyncRequest->Packet = Packet;
AsyncRequest->CommandId = Sq->Cid;
AsyncRequest->CallerEvent = Event;
AsyncRequest->MapData = MapData;
AsyncRequest->MapMeta = MapMeta;
AsyncRequest->MapPrpList = MapPrpList;
AsyncRequest->PrpListNo = PrpListNo;
AsyncRequest->PrpListHost = PrpListHost;
OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
InsertTailList (&Private->AsyncPassThruQueue, &AsyncRequest->Link);
@@ -760,9 +786,9 @@ NvmExpressPassThru (
goto EXIT;
}
Status = gBS->SetTimer(TimerEvent, TimerRelative, Packet->CommandTimeout);
Status = gBS->SetTimer (TimerEvent, TimerRelative, Packet->CommandTimeout);
if (EFI_ERROR(Status)) {
if (EFI_ERROR (Status)) {
goto EXIT;
}
@@ -788,14 +814,15 @@ NvmExpressPassThru (
//
// Dump every completion entry status for debugging.
//
DEBUG_CODE_BEGIN();
NvmeDumpStatus(Cq);
DEBUG_CODE_END();
DEBUG_CODE_BEGIN ();
NvmeDumpStatus (Cq);
DEBUG_CODE_END ();
}
//
// Copy the Respose Queue entry for this command to the callers response buffer
//
CopyMem(Packet->NvmeCompletion, Cq, sizeof(EFI_NVM_EXPRESS_COMPLETION));
CopyMem (Packet->NvmeCompletion, Cq, sizeof (EFI_NVM_EXPRESS_COMPLETION));
} else {
//
// Timeout occurs for an NVMe command. Reset the controller to abort the
@@ -840,16 +867,16 @@ NvmExpressPassThru (
Private->Pt[QueueId] ^= 1;
}
Data = ReadUnaligned32 ((UINT32*)&Private->CqHdbl[QueueId]);
Data = ReadUnaligned32 ((UINT32 *)&Private->CqHdbl[QueueId]);
PreviousStatus = Status;
Status = PciIo->Mem.Write (
PciIo,
EfiPciIoWidthUint32,
NVME_BAR,
NVME_CQHDBL_OFFSET(QueueId, Private->Cap.Dstrd),
1,
&Data
);
Status = PciIo->Mem.Write (
PciIo,
EfiPciIoWidthUint32,
NVME_BAR,
NVME_CQHDBL_OFFSET (QueueId, Private->Cap.Dstrd),
1,
&Data
);
// The return status of PciIo->Mem.Write should not override
// previous status if previous status contains error.
Status = EFI_ERROR (PreviousStatus) ? PreviousStatus : Status;
@@ -892,6 +919,7 @@ EXIT:
if (TimerEvent != NULL) {
gBS->CloseEvent (TimerEvent);
}
return Status;
}
@@ -931,14 +959,14 @@ EXIT:
EFI_STATUS
EFIAPI
NvmExpressGetNextNamespace (
IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,
IN OUT UINT32 *NamespaceId
IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,
IN OUT UINT32 *NamespaceId
)
{
NVME_CONTROLLER_PRIVATE_DATA *Private;
NVME_ADMIN_NAMESPACE_DATA *NamespaceData;
UINT32 NextNamespaceId;
EFI_STATUS Status;
NVME_CONTROLLER_PRIVATE_DATA *Private;
NVME_ADMIN_NAMESPACE_DATA *NamespaceData;
UINT32 NextNamespaceId;
EFI_STATUS Status;
if ((This == NULL) || (NamespaceId == NULL)) {
return EFI_INVALID_PARAMETER;
@@ -966,7 +994,7 @@ NvmExpressGetNextNamespace (
}
Status = NvmeIdentifyNamespace (Private, NextNamespaceId, NamespaceData);
if (EFI_ERROR(Status)) {
if (EFI_ERROR (Status)) {
goto Done;
}
@@ -990,7 +1018,7 @@ NvmExpressGetNextNamespace (
}
Status = NvmeIdentifyNamespace (Private, NextNamespaceId, NamespaceData);
if (EFI_ERROR(Status)) {
if (EFI_ERROR (Status)) {
goto Done;
}
@@ -999,7 +1027,7 @@ NvmExpressGetNextNamespace (
Done:
if (NamespaceData != NULL) {
FreePool(NamespaceData);
FreePool (NamespaceData);
}
return Status;
@@ -1032,13 +1060,13 @@ Done:
EFI_STATUS
EFIAPI
NvmExpressGetNamespace (
IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,
IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
OUT UINT32 *NamespaceId
IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,
IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
OUT UINT32 *NamespaceId
)
{
NVME_NAMESPACE_DEVICE_PATH *Node;
NVME_CONTROLLER_PRIVATE_DATA *Private;
NVME_NAMESPACE_DEVICE_PATH *Node;
NVME_CONTROLLER_PRIVATE_DATA *Private;
if ((This == NULL) || (DevicePath == NULL) || (NamespaceId == NULL)) {
return EFI_INVALID_PARAMETER;
@@ -1052,7 +1080,7 @@ NvmExpressGetNamespace (
Private = NVME_CONTROLLER_PRIVATE_DATA_FROM_PASS_THRU (This);
if (DevicePath->SubType == MSG_NVME_NAMESPACE_DP) {
if (DevicePathNodeLength(DevicePath) != sizeof(NVME_NAMESPACE_DEVICE_PATH)) {
if (DevicePathNodeLength (DevicePath) != sizeof (NVME_NAMESPACE_DEVICE_PATH)) {
return EFI_NOT_FOUND;
}
@@ -1060,7 +1088,8 @@ NvmExpressGetNamespace (
// Check NamespaceId in the device path node is valid or not.
//
if ((Node->NamespaceId == 0) ||
(Node->NamespaceId > Private->ControllerData->Nn)) {
(Node->NamespaceId > Private->ControllerData->Nn))
{
return EFI_NOT_FOUND;
}
@@ -1106,15 +1135,15 @@ NvmExpressGetNamespace (
EFI_STATUS
EFIAPI
NvmExpressBuildDevicePath (
IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,
IN UINT32 NamespaceId,
IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath
IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,
IN UINT32 NamespaceId,
IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath
)
{
NVME_NAMESPACE_DEVICE_PATH *Node;
NVME_CONTROLLER_PRIVATE_DATA *Private;
EFI_STATUS Status;
NVME_ADMIN_NAMESPACE_DATA *NamespaceData;
NVME_NAMESPACE_DEVICE_PATH *Node;
NVME_CONTROLLER_PRIVATE_DATA *Private;
EFI_STATUS Status;
NVME_ADMIN_NAMESPACE_DATA *NamespaceData;
//
// Validate parameters
@@ -1130,7 +1159,8 @@ NvmExpressBuildDevicePath (
// Check NamespaceId is valid or not.
//
if ((NamespaceId == 0) ||
(NamespaceId > Private->ControllerData->Nn)) {
(NamespaceId > Private->ControllerData->Nn))
{
return EFI_NOT_FOUND;
}
@@ -1142,14 +1172,14 @@ NvmExpressBuildDevicePath (
Node->Header.Type = MESSAGING_DEVICE_PATH;
Node->Header.SubType = MSG_NVME_NAMESPACE_DP;
SetDevicePathNodeLength (&Node->Header, sizeof (NVME_NAMESPACE_DEVICE_PATH));
Node->NamespaceId = NamespaceId;
Node->NamespaceId = NamespaceId;
//
// Allocate a buffer for Identify Namespace data.
//
NamespaceData = NULL;
NamespaceData = AllocateZeroPool(sizeof (NVME_ADMIN_NAMESPACE_DATA));
if(NamespaceData == NULL) {
NamespaceData = AllocateZeroPool (sizeof (NVME_ADMIN_NAMESPACE_DATA));
if (NamespaceData == NULL) {
Status = EFI_OUT_OF_RESOURCES;
goto Exit;
}
@@ -1163,7 +1193,7 @@ NvmExpressBuildDevicePath (
(VOID *)NamespaceData
);
if (EFI_ERROR(Status)) {
if (EFI_ERROR (Status)) {
goto Exit;
}
@@ -1172,7 +1202,7 @@ NvmExpressBuildDevicePath (
*DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)Node;
Exit:
if(NamespaceData != NULL) {
if (NamespaceData != NULL) {
FreePool (NamespaceData);
}

66
MdeModulePkg/Bus/Pci/NvmExpressPei/DevicePath.c
View File

@@ -17,8 +17,8 @@ NVME_NAMESPACE_DEVICE_PATH mNvmeDevicePathNodeTemplate = {
MESSAGING_DEVICE_PATH,
MSG_NVME_NAMESPACE_DP,
{
(UINT8) (sizeof (NVME_NAMESPACE_DEVICE_PATH)),
(UINT8) ((sizeof (NVME_NAMESPACE_DEVICE_PATH)) >> 8)
(UINT8)(sizeof (NVME_NAMESPACE_DEVICE_PATH)),
(UINT8)((sizeof (NVME_NAMESPACE_DEVICE_PATH)) >> 8)
}
},
0x0, // NamespaceId
@@ -32,8 +32,8 @@ EFI_DEVICE_PATH_PROTOCOL mNvmeEndDevicePathNodeTemplate = {
END_DEVICE_PATH_TYPE,
END_ENTIRE_DEVICE_PATH_SUBTYPE,
{
(UINT8) (sizeof (EFI_DEVICE_PATH_PROTOCOL)),
(UINT8) ((sizeof (EFI_DEVICE_PATH_PROTOCOL)) >> 8)
(UINT8)(sizeof (EFI_DEVICE_PATH_PROTOCOL)),
(UINT8)((sizeof (EFI_DEVICE_PATH_PROTOCOL)) >> 8)
}
};
@@ -78,7 +78,7 @@ NextDevicePathNode (
)
{
ASSERT (Node != NULL);
return (EFI_DEVICE_PATH_PROTOCOL *)((UINT8 *)(Node) + DevicePathNodeLength(Node));
return (EFI_DEVICE_PATH_PROTOCOL *)((UINT8 *)(Node) + DevicePathNodeLength (Node));
}
/**
@@ -96,14 +96,14 @@ NextDevicePathNode (
**/
EFI_STATUS
GetDevicePathInstanceSize (
IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
OUT UINTN *InstanceSize,
OUT BOOLEAN *EntireDevicePathEnd
IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
OUT UINTN *InstanceSize,
OUT BOOLEAN *EntireDevicePathEnd
)
{
EFI_DEVICE_PATH_PROTOCOL *Walker;
EFI_DEVICE_PATH_PROTOCOL *Walker;
if (DevicePath == NULL || InstanceSize == NULL || EntireDevicePathEnd == NULL) {
if ((DevicePath == NULL) || (InstanceSize == NULL) || (EntireDevicePathEnd == NULL)) {
return EFI_INVALID_PARAMETER;
}
@@ -129,7 +129,7 @@ GetDevicePathInstanceSize (
//
// Compute the size of the device path instance
//
*InstanceSize = ((UINTN) Walker - (UINTN) (DevicePath)) + sizeof (EFI_DEVICE_PATH_PROTOCOL);
*InstanceSize = ((UINTN)Walker - (UINTN)(DevicePath)) + sizeof (EFI_DEVICE_PATH_PROTOCOL);
return EFI_SUCCESS;
}
@@ -147,12 +147,12 @@ GetDevicePathInstanceSize (
**/
EFI_STATUS
NvmeIsHcDevicePathValid (
IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
IN UINTN DevicePathLength
IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
IN UINTN DevicePathLength
)
{
EFI_DEVICE_PATH_PROTOCOL *Start;
UINTN Size;
EFI_DEVICE_PATH_PROTOCOL *Start;
UINTN Size;
if (DevicePath == NULL) {
return EFI_INVALID_PARAMETER;
@@ -167,22 +167,24 @@ NvmeIsHcDevicePathValid (
Start = DevicePath;
while (!(DevicePath->Type == END_DEVICE_PATH_TYPE &&
DevicePath->SubType == END_ENTIRE_DEVICE_PATH_SUBTYPE)) {
DevicePath->SubType == END_ENTIRE_DEVICE_PATH_SUBTYPE))
{
DevicePath = NextDevicePathNode (DevicePath);
//
// Prevent overflow and invalid zero in the 'Length' field of a device path
// node.
//
if ((UINTN) DevicePath <= (UINTN) Start) {
if ((UINTN)DevicePath <= (UINTN)Start) {
return EFI_INVALID_PARAMETER;
}
//
// Prevent touching memory beyond given DevicePathLength.
//
if ((UINTN) DevicePath - (UINTN) Start >
DevicePathLength - sizeof (EFI_DEVICE_PATH_PROTOCOL)) {
if ((UINTN)DevicePath - (UINTN)Start >
DevicePathLength - sizeof (EFI_DEVICE_PATH_PROTOCOL))
{
return EFI_INVALID_PARAMETER;
}
}
@@ -190,7 +192,7 @@ NvmeIsHcDevicePathValid (
//
// Check if the device path and its size match exactly with each other.
//
Size = ((UINTN) DevicePath - (UINTN) Start) + sizeof (EFI_DEVICE_PATH_PROTOCOL);
Size = ((UINTN)DevicePath - (UINTN)Start) + sizeof (EFI_DEVICE_PATH_PROTOCOL);
if (Size != DevicePathLength) {
return EFI_INVALID_PARAMETER;
}
@@ -217,17 +219,17 @@ NvmeIsHcDevicePathValid (
**/
EFI_STATUS
NvmeBuildDevicePath (
IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,
IN UINT32 NamespaceId,
IN UINT64 NamespaceUuid,
OUT UINTN *DevicePathLength,
OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath
IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,
IN UINT32 NamespaceId,
IN UINT64 NamespaceUuid,
OUT UINTN *DevicePathLength,
OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath
)
{
EFI_DEVICE_PATH_PROTOCOL *DevicePathWalker;
NVME_NAMESPACE_DEVICE_PATH *NvmeDeviceNode;
EFI_DEVICE_PATH_PROTOCOL *DevicePathWalker;
NVME_NAMESPACE_DEVICE_PATH *NvmeDeviceNode;
if (DevicePathLength == NULL || DevicePath == NULL) {
if ((DevicePathLength == NULL) || (DevicePath == NULL)) {
return EFI_INVALID_PARAMETER;
}
@@ -251,8 +253,8 @@ NvmeBuildDevicePath (
//
// Construct the Nvm Express device node
//
DevicePathWalker = (EFI_DEVICE_PATH_PROTOCOL *) ((UINT8 *)DevicePathWalker +
(Private->DevicePathLength - sizeof (EFI_DEVICE_PATH_PROTOCOL)));
DevicePathWalker = (EFI_DEVICE_PATH_PROTOCOL *)((UINT8 *)DevicePathWalker +
(Private->DevicePathLength - sizeof (EFI_DEVICE_PATH_PROTOCOL)));
CopyMem (
DevicePathWalker,
&mNvmeDevicePathNodeTemplate,
@@ -265,8 +267,8 @@ NvmeBuildDevicePath (
//
// Construct the end device node
//
DevicePathWalker = (EFI_DEVICE_PATH_PROTOCOL *) ((UINT8 *)DevicePathWalker +
sizeof (NVME_NAMESPACE_DEVICE_PATH));
DevicePathWalker = (EFI_DEVICE_PATH_PROTOCOL *)((UINT8 *)DevicePathWalker +
sizeof (NVME_NAMESPACE_DEVICE_PATH));
CopyMem (
DevicePathWalker,
&mNvmeEndDevicePathNodeTemplate,

118
MdeModulePkg/Bus/Pci/NvmExpressPei/DmaMem.c
View File

@@ -20,15 +20,15 @@ GetIoMmu (
VOID
)
{
EFI_STATUS Status;
EDKII_IOMMU_PPI *IoMmu;
EFI_STATUS Status;
EDKII_IOMMU_PPI *IoMmu;
IoMmu = NULL;
Status = PeiServicesLocatePpi (
&gEdkiiIoMmuPpiGuid,
0,
NULL,
(VOID **) &IoMmu
(VOID **)&IoMmu
);
if (!EFI_ERROR (Status) && (IoMmu != NULL)) {
return IoMmu;
@@ -58,48 +58,50 @@ GetIoMmu (
**/
EFI_STATUS
IoMmuMap (
IN EDKII_IOMMU_OPERATION Operation,
IN VOID *HostAddress,
IN OUT UINTN *NumberOfBytes,
OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
OUT VOID **Mapping
IN EDKII_IOMMU_OPERATION Operation,
IN VOID *HostAddress,
IN OUT UINTN *NumberOfBytes,
OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
OUT VOID **Mapping
)
{
EFI_STATUS Status;
UINT64 Attribute;
EDKII_IOMMU_PPI *IoMmu;
EFI_STATUS Status;
UINT64 Attribute;
EDKII_IOMMU_PPI *IoMmu;
IoMmu = GetIoMmu ();
if (IoMmu != NULL) {
Status = IoMmu->Map (
IoMmu,
Operation,
HostAddress,
NumberOfBytes,
DeviceAddress,
Mapping
);
IoMmu,
Operation,
HostAddress,
NumberOfBytes,
DeviceAddress,
Mapping
);
if (EFI_ERROR (Status)) {
return EFI_OUT_OF_RESOURCES;
}
switch (Operation) {
case EdkiiIoMmuOperationBusMasterRead:
case EdkiiIoMmuOperationBusMasterRead64:
Attribute = EDKII_IOMMU_ACCESS_READ;
break;
case EdkiiIoMmuOperationBusMasterWrite:
case EdkiiIoMmuOperationBusMasterWrite64:
Attribute = EDKII_IOMMU_ACCESS_WRITE;
break;
case EdkiiIoMmuOperationBusMasterCommonBuffer:
case EdkiiIoMmuOperationBusMasterCommonBuffer64:
Attribute = EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE;
break;
default:
ASSERT(FALSE);
return EFI_INVALID_PARAMETER;
case EdkiiIoMmuOperationBusMasterRead:
case EdkiiIoMmuOperationBusMasterRead64:
Attribute = EDKII_IOMMU_ACCESS_READ;
break;
case EdkiiIoMmuOperationBusMasterWrite:
case EdkiiIoMmuOperationBusMasterWrite64:
Attribute = EDKII_IOMMU_ACCESS_WRITE;
break;
case EdkiiIoMmuOperationBusMasterCommonBuffer:
case EdkiiIoMmuOperationBusMasterCommonBuffer64:
Attribute = EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE;
break;
default:
ASSERT (FALSE);
return EFI_INVALID_PARAMETER;
}
Status = IoMmu->SetAttribute (
IoMmu,
*Mapping,
@@ -110,9 +112,10 @@ IoMmuMap (
}
} else {
*DeviceAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)HostAddress;
*Mapping = NULL;
Status = EFI_SUCCESS;
*Mapping = NULL;
Status = EFI_SUCCESS;
}
return Status;
}
@@ -127,11 +130,11 @@ IoMmuMap (
**/
EFI_STATUS
IoMmuUnmap (
IN VOID *Mapping
IN VOID *Mapping
)
{
EFI_STATUS Status;
EDKII_IOMMU_PPI *IoMmu;
EFI_STATUS Status;
EDKII_IOMMU_PPI *IoMmu;
IoMmu = GetIoMmu ();
@@ -141,6 +144,7 @@ IoMmuUnmap (
} else {
Status = EFI_SUCCESS;
}
return Status;
}
@@ -175,7 +179,7 @@ IoMmuAllocateBuffer (
EFI_PHYSICAL_ADDRESS HostPhyAddress;
EDKII_IOMMU_PPI *IoMmu;
*HostAddress = NULL;
*HostAddress = NULL;
*DeviceAddress = 0;
IoMmu = GetIoMmu ();
@@ -192,18 +196,19 @@ IoMmuAllocateBuffer (
return EFI_OUT_OF_RESOURCES;
}
NumberOfBytes = EFI_PAGES_TO_SIZE(Pages);
Status = IoMmu->Map (
IoMmu,
EdkiiIoMmuOperationBusMasterCommonBuffer,
*HostAddress,
&NumberOfBytes,
DeviceAddress,
Mapping
);
NumberOfBytes = EFI_PAGES_TO_SIZE (Pages);
Status = IoMmu->Map (
IoMmu,
EdkiiIoMmuOperationBusMasterCommonBuffer,
*HostAddress,
&NumberOfBytes,
DeviceAddress,
Mapping
);
if (EFI_ERROR (Status)) {
return EFI_OUT_OF_RESOURCES;
}
Status = IoMmu->SetAttribute (
IoMmu,
*Mapping,
@@ -221,10 +226,12 @@ IoMmuAllocateBuffer (
if (EFI_ERROR (Status)) {
return EFI_OUT_OF_RESOURCES;
}
*HostAddress = (VOID *)(UINTN)HostPhyAddress;
*HostAddress = (VOID *)(UINTN)HostPhyAddress;
*DeviceAddress = HostPhyAddress;
*Mapping = NULL;
*Mapping = NULL;
}
return Status;
}
@@ -242,13 +249,13 @@ IoMmuAllocateBuffer (
**/
EFI_STATUS
IoMmuFreeBuffer (
IN UINTN Pages,
IN VOID *HostAddress,
IN VOID *Mapping
IN UINTN Pages,
IN VOID *HostAddress,
IN VOID *Mapping
)
{
EFI_STATUS Status;
EDKII_IOMMU_PPI *IoMmu;
EFI_STATUS Status;
EDKII_IOMMU_PPI *IoMmu;
IoMmu = GetIoMmu ();
@@ -259,5 +266,6 @@ IoMmuFreeBuffer (
} else {
Status = EFI_SUCCESS;
}
return Status;
}

146
MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPei.c
View File

@@ -53,19 +53,19 @@ EFI_PEI_NOTIFY_DESCRIPTOR mNvmeEndOfPeiNotifyListTemplate = {
**/
EFI_STATUS
EnumerateNvmeDevNamespace (
IN OUT PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,
IN UINT32 NamespaceId
IN OUT PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,
IN UINT32 NamespaceId
)
{
EFI_STATUS Status;
NVME_ADMIN_NAMESPACE_DATA *NamespaceData;
PEI_NVME_NAMESPACE_INFO *NamespaceInfo;
UINT32 DeviceIndex;
UINT32 Lbads;
UINT32 Flbas;
UINT32 LbaFmtIdx;
EFI_STATUS Status;
NVME_ADMIN_NAMESPACE_DATA *NamespaceData;
PEI_NVME_NAMESPACE_INFO *NamespaceInfo;
UINT32 DeviceIndex;
UINT32 Lbads;
UINT32 Flbas;
UINT32 LbaFmtIdx;
NamespaceData = (NVME_ADMIN_NAMESPACE_DATA *) AllocateZeroPool (sizeof (NVME_ADMIN_NAMESPACE_DATA));
NamespaceData = (NVME_ADMIN_NAMESPACE_DATA *)AllocateZeroPool (sizeof (NVME_ADMIN_NAMESPACE_DATA));
if (NamespaceData == NULL) {
return EFI_OUT_OF_RESOURCES;
}
@@ -92,8 +92,8 @@ EnumerateNvmeDevNamespace (
goto Exit;
}
DeviceIndex = Private->ActiveNamespaceNum;
NamespaceInfo = &Private->NamespaceInfo[DeviceIndex];
DeviceIndex = Private->ActiveNamespaceNum;
NamespaceInfo = &Private->NamespaceInfo[DeviceIndex];
NamespaceInfo->NamespaceId = NamespaceId;
NamespaceInfo->NamespaceUuid = NamespaceData->Eui64;
NamespaceInfo->Controller = Private;
@@ -110,8 +110,8 @@ EnumerateNvmeDevNamespace (
NamespaceInfo->Media.RemovableMedia = FALSE;
NamespaceInfo->Media.MediaPresent = TRUE;
NamespaceInfo->Media.ReadOnly = FALSE;
NamespaceInfo->Media.BlockSize = (UINT32) 1 << Lbads;
NamespaceInfo->Media.LastBlock = (EFI_PEI_LBA) NamespaceData->Nsze - 1;
NamespaceInfo->Media.BlockSize = (UINT32)1 << Lbads;
NamespaceInfo->Media.LastBlock = (EFI_PEI_LBA)NamespaceData->Nsze - 1;
DEBUG ((
DEBUG_INFO,
"%a: Namespace ID %d - BlockSize = 0x%x, LastBlock = 0x%lx\n",
@@ -140,10 +140,10 @@ Exit:
**/
EFI_STATUS
NvmeDiscoverNamespaces (
IN OUT PEI_NVME_CONTROLLER_PRIVATE_DATA *Private
IN OUT PEI_NVME_CONTROLLER_PRIVATE_DATA *Private
)
{
UINT32 NamespaceId;
UINT32 NamespaceId;
Private->ActiveNamespaceNum = 0;
Private->NamespaceInfo = AllocateZeroPool (Private->ControllerData->Nn * sizeof (PEI_NVME_NAMESPACE_INFO));
@@ -161,6 +161,7 @@ NvmeDiscoverNamespaces (
//
EnumerateNvmeDevNamespace (Private, NamespaceId);
}
if (Private->ActiveNamespaceNum == 0) {
return EFI_NOT_FOUND;
}
@@ -187,7 +188,7 @@ NvmePeimEndOfPei (
IN VOID *Ppi
)
{
PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
Private = GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_NOTIFY (NotifyDescriptor);
NvmeFreeDmaResource (Private);
@@ -207,19 +208,19 @@ NvmePeimEndOfPei (
EFI_STATUS
EFIAPI
NvmExpressPeimEntry (
IN EFI_PEI_FILE_HANDLE FileHandle,
IN CONST EFI_PEI_SERVICES **PeiServices
IN EFI_PEI_FILE_HANDLE FileHandle,
IN CONST EFI_PEI_SERVICES **PeiServices
)
{
EFI_STATUS Status;
EFI_BOOT_MODE BootMode;
EDKII_NVM_EXPRESS_HOST_CONTROLLER_PPI *NvmeHcPpi;
UINT8 Controller;
UINTN MmioBase;
UINTN DevicePathLength;
EFI_DEVICE_PATH_PROTOCOL *DevicePath;
PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
EFI_PHYSICAL_ADDRESS DeviceAddress;
EFI_STATUS Status;
EFI_BOOT_MODE BootMode;
EDKII_NVM_EXPRESS_HOST_CONTROLLER_PPI *NvmeHcPpi;
UINT8 Controller;
UINTN MmioBase;
UINTN DevicePathLength;
EFI_DEVICE_PATH_PROTOCOL *DevicePath;
PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
EFI_PHYSICAL_ADDRESS DeviceAddress;
DEBUG ((DEBUG_INFO, "%a: Enters.\n", __FUNCTION__));
@@ -239,7 +240,7 @@ NvmExpressPeimEntry (
&gEdkiiPeiNvmExpressHostControllerPpiGuid,
0,
NULL,
(VOID **) &NvmeHcPpi
(VOID **)&NvmeHcPpi
);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "%a: Fail to locate NvmeHostControllerPpi.\n", __FUNCTION__));
@@ -269,8 +270,10 @@ NvmExpressPeimEntry (
);
if (EFI_ERROR (Status)) {
DEBUG ((
DEBUG_ERROR, "%a: Fail to allocate get the device path for Controller %d.\n",
__FUNCTION__, Controller
DEBUG_ERROR,
"%a: Fail to allocate get the device path for Controller %d.\n",
__FUNCTION__,
Controller
));
return Status;
}
@@ -281,8 +284,10 @@ NvmExpressPeimEntry (
Status = NvmeIsHcDevicePathValid (DevicePath, DevicePathLength);
if (EFI_ERROR (Status)) {
DEBUG ((
DEBUG_ERROR, "%a: The device path is invalid for Controller %d.\n",
__FUNCTION__, Controller
DEBUG_ERROR,
"%a: The device path is invalid for Controller %d.\n",
__FUNCTION__,
Controller
));
Controller++;
continue;
@@ -295,10 +300,13 @@ NvmExpressPeimEntry (
// during S3 resume.
//
if ((BootMode == BOOT_ON_S3_RESUME) &&
(NvmeS3SkipThisController (DevicePath, DevicePathLength))) {
(NvmeS3SkipThisController (DevicePath, DevicePathLength)))
{
DEBUG ((
DEBUG_ERROR, "%a: Controller %d is skipped during S3.\n",
__FUNCTION__, Controller
DEBUG_ERROR,
"%a: Controller %d is skipped during S3.\n",
__FUNCTION__,
Controller
));
Controller++;
continue;
@@ -310,8 +318,10 @@ NvmExpressPeimEntry (
Private = AllocateZeroPool (sizeof (PEI_NVME_CONTROLLER_PRIVATE_DATA));
if (Private == NULL) {
DEBUG ((
DEBUG_ERROR, "%a: Fail to allocate private data for Controller %d.\n",
__FUNCTION__, Controller
DEBUG_ERROR,
"%a: Fail to allocate private data for Controller %d.\n",
__FUNCTION__,
Controller
));
return EFI_OUT_OF_RESOURCES;
}
@@ -327,12 +337,15 @@ NvmExpressPeimEntry (
);
if (EFI_ERROR (Status)) {
DEBUG ((
DEBUG_ERROR, "%a: Fail to allocate DMA buffers for Controller %d.\n",
__FUNCTION__, Controller
DEBUG_ERROR,
"%a: Fail to allocate DMA buffers for Controller %d.\n",
__FUNCTION__,
Controller
));
return Status;
}
ASSERT (DeviceAddress == ((EFI_PHYSICAL_ADDRESS) (UINTN) Private->Buffer));
ASSERT (DeviceAddress == ((EFI_PHYSICAL_ADDRESS)(UINTN)Private->Buffer));
DEBUG ((DEBUG_INFO, "%a: DMA buffer base at 0x%x\n", __FUNCTION__, Private->Buffer));
//
@@ -351,7 +364,9 @@ NvmExpressPeimEntry (
DEBUG ((
DEBUG_ERROR,
"%a: Controller initialization fail for Controller %d with Status - %r.\n",
__FUNCTION__, Controller, Status
__FUNCTION__,
Controller,
Status
));
NvmeFreeDmaResource (Private);
Controller++;
@@ -369,7 +384,9 @@ NvmExpressPeimEntry (
DEBUG ((
DEBUG_ERROR,
"%a: Namespaces discovery fail for Controller %d with Status - %r.\n",
__FUNCTION__, Controller, Status
__FUNCTION__,
Controller,
Status
));
NvmeFreeDmaResource (Private);
Controller++;
@@ -379,35 +396,35 @@ NvmExpressPeimEntry (
//
// Nvm Express Pass Thru PPI
//
Private->PassThruMode.Attributes = EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_PHYSICAL |
EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_LOGICAL |
EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_CMD_SET_NVM;
Private->PassThruMode.IoAlign = sizeof (UINTN);
Private->PassThruMode.NvmeVersion = EDKII_PEI_NVM_EXPRESS_PASS_THRU_PPI_REVISION;
Private->NvmePassThruPpi.Mode = &Private->PassThruMode;
Private->NvmePassThruPpi.GetDevicePath = NvmePassThruGetDevicePath;
Private->NvmePassThruPpi.GetNextNameSpace = NvmePassThruGetNextNameSpace;
Private->NvmePassThruPpi.PassThru = NvmePassThru;
Private->PassThruMode.Attributes = EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_PHYSICAL |
EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_LOGICAL |
EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_CMD_SET_NVM;
Private->PassThruMode.IoAlign = sizeof (UINTN);
Private->PassThruMode.NvmeVersion = EDKII_PEI_NVM_EXPRESS_PASS_THRU_PPI_REVISION;
Private->NvmePassThruPpi.Mode = &Private->PassThruMode;
Private->NvmePassThruPpi.GetDevicePath = NvmePassThruGetDevicePath;
Private->NvmePassThruPpi.GetNextNameSpace = NvmePassThruGetNextNameSpace;
Private->NvmePassThruPpi.PassThru = NvmePassThru;
CopyMem (
&Private->NvmePassThruPpiList,
&mNvmePassThruPpiListTemplate,
sizeof (EFI_PEI_PPI_DESCRIPTOR)
);
Private->NvmePassThruPpiList.Ppi = &Private->NvmePassThruPpi;
Private->NvmePassThruPpiList.Ppi = &Private->NvmePassThruPpi;
PeiServicesInstallPpi (&Private->NvmePassThruPpiList);
//
// Block Io PPI
//
Private->BlkIoPpi.GetNumberOfBlockDevices = NvmeBlockIoPeimGetDeviceNo;
Private->BlkIoPpi.GetBlockDeviceMediaInfo = NvmeBlockIoPeimGetMediaInfo;
Private->BlkIoPpi.ReadBlocks = NvmeBlockIoPeimReadBlocks;
Private->BlkIoPpi.GetNumberOfBlockDevices = NvmeBlockIoPeimGetDeviceNo;
Private->BlkIoPpi.GetBlockDeviceMediaInfo = NvmeBlockIoPeimGetMediaInfo;
Private->BlkIoPpi.ReadBlocks = NvmeBlockIoPeimReadBlocks;
CopyMem (
&Private->BlkIoPpiList,
&mNvmeBlkIoPpiListTemplate,
sizeof (EFI_PEI_PPI_DESCRIPTOR)
);
Private->BlkIoPpiList.Ppi = &Private->BlkIoPpi;
Private->BlkIoPpiList.Ppi = &Private->BlkIoPpi;
Private->BlkIo2Ppi.Revision = EFI_PEI_RECOVERY_BLOCK_IO2_PPI_REVISION;
Private->BlkIo2Ppi.GetNumberOfBlockDevices = NvmeBlockIoPeimGetDeviceNo2;
@@ -418,7 +435,7 @@ NvmExpressPeimEntry (
&mNvmeBlkIo2PpiListTemplate,
sizeof (EFI_PEI_PPI_DESCRIPTOR)
);
Private->BlkIo2PpiList.Ppi = &Private->BlkIo2Ppi;
Private->BlkIo2PpiList.Ppi = &Private->BlkIo2Ppi;
PeiServicesInstallPpi (&Private->BlkIoPpiList);
//
@@ -428,7 +445,8 @@ NvmExpressPeimEntry (
DEBUG ((
DEBUG_INFO,
"%a: Security Security Command PPI will be produced for Controller %d.\n",
__FUNCTION__, Controller
__FUNCTION__,
Controller
));
Private->StorageSecurityPpi.Revision = EDKII_STORAGE_SECURITY_PPI_REVISION;
Private->StorageSecurityPpi.GetNumberofDevices = NvmeStorageSecurityGetDeviceNo;
@@ -440,7 +458,7 @@ NvmExpressPeimEntry (
&mNvmeStorageSecurityPpiListTemplate,
sizeof (EFI_PEI_PPI_DESCRIPTOR)
);
Private->StorageSecurityPpiList.Ppi = &Private->StorageSecurityPpi;
Private->StorageSecurityPpiList.Ppi = &Private->StorageSecurityPpi;
PeiServicesInstallPpi (&Private->StorageSecurityPpiList);
}
@@ -449,11 +467,13 @@ NvmExpressPeimEntry (
&mNvmeEndOfPeiNotifyListTemplate,
sizeof (EFI_PEI_NOTIFY_DESCRIPTOR)
);
PeiServicesNotifyPpi (&Private->EndOfPeiNotifyList);
PeiServicesNotifyPpi (&Private->EndOfPeiNotifyList);
DEBUG ((
DEBUG_INFO, "%a: Controller %d has been successfully initialized.\n",
__FUNCTION__, Controller
DEBUG_INFO,
"%a: Controller %d has been successfully initialized.\n",
__FUNCTION__,
Controller
));
Controller++;
}

135
MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPei.h
View File

@@ -44,68 +44,68 @@ typedef struct _PEI_NVME_CONTROLLER_PRIVATE_DATA PEI_NVME_CONTROLLER_PRIVATE_DA
//
// NVME PEI driver implementation related definitions
//
#define NVME_MAX_QUEUES 2 // Number of I/O queues supported by the driver, 1 for AQ, 1 for CQ
#define NVME_ASQ_SIZE 1 // Number of admin submission queue entries, which is 0-based
#define NVME_ACQ_SIZE 1 // Number of admin completion queue entries, which is 0-based
#define NVME_CSQ_SIZE 63 // Number of I/O submission queue entries, which is 0-based
#define NVME_CCQ_SIZE 63 // Number of I/O completion queue entries, which is 0-based
#define NVME_PRP_SIZE (8) // Pages of PRP list
#define NVME_MAX_QUEUES 2 // Number of I/O queues supported by the driver, 1 for AQ, 1 for CQ
#define NVME_ASQ_SIZE 1 // Number of admin submission queue entries, which is 0-based
#define NVME_ACQ_SIZE 1 // Number of admin completion queue entries, which is 0-based
#define NVME_CSQ_SIZE 63 // Number of I/O submission queue entries, which is 0-based
#define NVME_CCQ_SIZE 63 // Number of I/O completion queue entries, which is 0-based
#define NVME_PRP_SIZE (8) // Pages of PRP list
#define NVME_MEM_MAX_PAGES \
( \
1 /* ASQ */ + \
1 /* ACQ */ + \
1 /* SQs */ + \
1 /* CQs */ + \
1 /* ASQ */ + \
1 /* ACQ */ + \
1 /* SQs */ + \
1 /* CQs */ + \
NVME_PRP_SIZE) /* PRPs */
#define NVME_ADMIN_QUEUE 0x00
#define NVME_IO_QUEUE 0x01
#define NVME_GENERIC_TIMEOUT 5000000 // Generic PassThru command timeout value, in us unit
#define NVME_POLL_INTERVAL 100 // Poll interval for PassThru command, in us unit
#define NVME_ADMIN_QUEUE 0x00
#define NVME_IO_QUEUE 0x01
#define NVME_GENERIC_TIMEOUT 5000000 // Generic PassThru command timeout value, in us unit
#define NVME_POLL_INTERVAL 100 // Poll interval for PassThru command, in us unit
//
// Nvme namespace data structure.
//
struct _PEI_NVME_NAMESPACE_INFO {
UINT32 NamespaceId;
UINT64 NamespaceUuid;
EFI_PEI_BLOCK_IO2_MEDIA Media;
UINT32 NamespaceId;
UINT64 NamespaceUuid;
EFI_PEI_BLOCK_IO2_MEDIA Media;
PEI_NVME_CONTROLLER_PRIVATE_DATA *Controller;
PEI_NVME_CONTROLLER_PRIVATE_DATA *Controller;
};
#define NVME_CONTROLLER_NSID 0
#define NVME_CONTROLLER_NSID 0
//
// Unique signature for private data structure.
//
#define NVME_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('N','V','P','C')
#define NVME_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('N','V','P','C')
//
// Nvme controller private data structure.
//
struct _PEI_NVME_CONTROLLER_PRIVATE_DATA {
UINT32 Signature;
UINTN MmioBase;
EFI_NVM_EXPRESS_PASS_THRU_MODE PassThruMode;
UINTN DevicePathLength;
EFI_DEVICE_PATH_PROTOCOL *DevicePath;
UINT32 Signature;
UINTN MmioBase;
EFI_NVM_EXPRESS_PASS_THRU_MODE PassThruMode;
UINTN DevicePathLength;
EFI_DEVICE_PATH_PROTOCOL *DevicePath;
EFI_PEI_RECOVERY_BLOCK_IO_PPI BlkIoPpi;
EFI_PEI_RECOVERY_BLOCK_IO2_PPI BlkIo2Ppi;
EDKII_PEI_STORAGE_SECURITY_CMD_PPI StorageSecurityPpi;
EDKII_PEI_NVM_EXPRESS_PASS_THRU_PPI NvmePassThruPpi;
EFI_PEI_PPI_DESCRIPTOR BlkIoPpiList;
EFI_PEI_PPI_DESCRIPTOR BlkIo2PpiList;
EFI_PEI_PPI_DESCRIPTOR StorageSecurityPpiList;
EFI_PEI_PPI_DESCRIPTOR NvmePassThruPpiList;
EFI_PEI_NOTIFY_DESCRIPTOR EndOfPeiNotifyList;
EFI_PEI_RECOVERY_BLOCK_IO_PPI BlkIoPpi;
EFI_PEI_RECOVERY_BLOCK_IO2_PPI BlkIo2Ppi;
EDKII_PEI_STORAGE_SECURITY_CMD_PPI StorageSecurityPpi;
EDKII_PEI_NVM_EXPRESS_PASS_THRU_PPI NvmePassThruPpi;
EFI_PEI_PPI_DESCRIPTOR BlkIoPpiList;
EFI_PEI_PPI_DESCRIPTOR BlkIo2PpiList;
EFI_PEI_PPI_DESCRIPTOR StorageSecurityPpiList;
EFI_PEI_PPI_DESCRIPTOR NvmePassThruPpiList;
EFI_PEI_NOTIFY_DESCRIPTOR EndOfPeiNotifyList;
//
// Pointer to identify controller data
//
NVME_ADMIN_CONTROLLER_DATA *ControllerData;
NVME_ADMIN_CONTROLLER_DATA *ControllerData;
//
// (4 + NVME_PRP_SIZE) x 4kB aligned buffers will be carved out of this buffer
@@ -115,34 +115,34 @@ struct _PEI_NVME_CONTROLLER_PRIVATE_DATA {
// 4th 4kB boundary is the start of I/O completion queue
// 5th 4kB boundary is the start of PRP list buffers
//
VOID *Buffer;
VOID *BufferMapping;
VOID *Buffer;
VOID *BufferMapping;
//
// Pointers to 4kB aligned submission & completion queues
//
NVME_SQ *SqBuffer[NVME_MAX_QUEUES];
NVME_CQ *CqBuffer[NVME_MAX_QUEUES];
NVME_SQ *SqBuffer[NVME_MAX_QUEUES];
NVME_CQ *CqBuffer[NVME_MAX_QUEUES];
//
// Submission and completion queue indices
//
NVME_SQTDBL SqTdbl[NVME_MAX_QUEUES];
NVME_CQHDBL CqHdbl[NVME_MAX_QUEUES];
NVME_SQTDBL SqTdbl[NVME_MAX_QUEUES];
NVME_CQHDBL CqHdbl[NVME_MAX_QUEUES];
UINT8 Pt[NVME_MAX_QUEUES];
UINT16 Cid[NVME_MAX_QUEUES];
UINT8 Pt[NVME_MAX_QUEUES];
UINT16 Cid[NVME_MAX_QUEUES];
//
// Nvme controller capabilities
//
NVME_CAP Cap;
NVME_CAP Cap;
//
// Namespaces information on the controller
//
UINT32 ActiveNamespaceNum;
PEI_NVME_NAMESPACE_INFO *NamespaceInfo;
UINT32 ActiveNamespaceNum;
PEI_NVME_NAMESPACE_INFO *NamespaceInfo;
};
#define GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_BLKIO(a) \
@@ -156,7 +156,6 @@ struct _PEI_NVME_CONTROLLER_PRIVATE_DATA {
#define GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_NOTIFY(a) \
CR (a, PEI_NVME_CONTROLLER_PRIVATE_DATA, EndOfPeiNotifyList, NVME_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)
//
// Internal functions
//
@@ -201,9 +200,9 @@ IoMmuAllocateBuffer (
**/
EFI_STATUS
IoMmuFreeBuffer (
IN UINTN Pages,
IN VOID *HostAddress,
IN VOID *Mapping
IN UINTN Pages,
IN VOID *HostAddress,
IN VOID *Mapping
);
/**
@@ -227,11 +226,11 @@ IoMmuFreeBuffer (
**/
EFI_STATUS
IoMmuMap (
IN EDKII_IOMMU_OPERATION Operation,
IN VOID *HostAddress,
IN OUT UINTN *NumberOfBytes,
OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
OUT VOID **Mapping
IN EDKII_IOMMU_OPERATION Operation,
IN VOID *HostAddress,
IN OUT UINTN *NumberOfBytes,
OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
OUT VOID **Mapping
);
/**
@@ -245,7 +244,7 @@ IoMmuMap (
**/
EFI_STATUS
IoMmuUnmap (
IN VOID *Mapping
IN VOID *Mapping
);
/**
@@ -282,9 +281,9 @@ NvmePeimEndOfPei (
**/
EFI_STATUS
GetDevicePathInstanceSize (
IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
OUT UINTN *InstanceSize,
OUT BOOLEAN *EntireDevicePathEnd
IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
OUT UINTN *InstanceSize,
OUT BOOLEAN *EntireDevicePathEnd
);
/**
@@ -300,8 +299,8 @@ GetDevicePathInstanceSize (
**/
EFI_STATUS
NvmeIsHcDevicePathValid (
IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
IN UINTN DevicePathLength
IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
IN UINTN DevicePathLength
);
/**
@@ -323,11 +322,11 @@ NvmeIsHcDevicePathValid (
**/
EFI_STATUS
NvmeBuildDevicePath (
IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,
IN UINT32 NamespaceId,
IN UINT64 NamespaceUuid,
OUT UINTN *DevicePathLength,
OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath
IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,
IN UINT32 NamespaceId,
IN UINT64 NamespaceUuid,
OUT UINTN *DevicePathLength,
OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath
);
/**
@@ -342,8 +341,8 @@ NvmeBuildDevicePath (
**/
BOOLEAN
NvmeS3SkipThisController (
IN EFI_DEVICE_PATH_PROTOCOL *HcDevicePath,
IN UINTN HcDevicePathLength
IN EFI_DEVICE_PATH_PROTOCOL *HcDevicePath,
IN UINTN HcDevicePathLength
);
#endif

132
MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiBlockIo.c
View File

@@ -24,29 +24,29 @@
**/
EFI_STATUS
ReadSectors (
IN PEI_NVME_NAMESPACE_INFO *NamespaceInfo,
OUT UINTN Buffer,
IN UINT64 Lba,
IN UINT32 Blocks
IN PEI_NVME_NAMESPACE_INFO *NamespaceInfo,
OUT UINTN Buffer,
IN UINT64 Lba,
IN UINT32 Blocks
)
{
EFI_STATUS Status;
UINT32 BlockSize;
PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
UINT32 Bytes;
EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
EFI_NVM_EXPRESS_COMMAND Command;
EFI_NVM_EXPRESS_COMPLETION Completion;
EDKII_PEI_NVM_EXPRESS_PASS_THRU_PPI *NvmePassThru;
EFI_STATUS Status;
UINT32 BlockSize;
PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
UINT32 Bytes;
EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
EFI_NVM_EXPRESS_COMMAND Command;
EFI_NVM_EXPRESS_COMPLETION Completion;
EDKII_PEI_NVM_EXPRESS_PASS_THRU_PPI *NvmePassThru;
Private = NamespaceInfo->Controller;
Private = NamespaceInfo->Controller;
NvmePassThru = &Private->NvmePassThruPpi;
BlockSize = NamespaceInfo->Media.BlockSize;
Bytes = Blocks * BlockSize;
BlockSize = NamespaceInfo->Media.BlockSize;
Bytes = Blocks * BlockSize;
ZeroMem (&CommandPacket, sizeof(EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
ZeroMem (&Command, sizeof(EFI_NVM_EXPRESS_COMMAND));
ZeroMem (&Completion, sizeof(EFI_NVM_EXPRESS_COMPLETION));
ZeroMem (&CommandPacket, sizeof (EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
ZeroMem (&Command, sizeof (EFI_NVM_EXPRESS_COMMAND));
ZeroMem (&Completion, sizeof (EFI_NVM_EXPRESS_COMPLETION));
CommandPacket.NvmeCmd = &Command;
CommandPacket.NvmeCompletion = &Completion;
@@ -60,7 +60,7 @@ ReadSectors (
CommandPacket.QueueType = NVME_IO_QUEUE;
CommandPacket.NvmeCmd->Cdw10 = (UINT32)Lba;
CommandPacket.NvmeCmd->Cdw11 = (UINT32)RShiftU64(Lba, 32);
CommandPacket.NvmeCmd->Cdw11 = (UINT32)RShiftU64 (Lba, 32);
CommandPacket.NvmeCmd->Cdw12 = (Blocks - 1) & 0xFFFF;
CommandPacket.NvmeCmd->Flags = CDW10_VALID | CDW11_VALID | CDW12_VALID;
@@ -88,18 +88,18 @@ ReadSectors (
**/
EFI_STATUS
NvmeRead (
IN PEI_NVME_NAMESPACE_INFO *NamespaceInfo,
OUT UINTN Buffer,
IN UINT64 Lba,
IN UINTN Blocks
IN PEI_NVME_NAMESPACE_INFO *NamespaceInfo,
OUT UINTN Buffer,
IN UINT64 Lba,
IN UINTN Blocks
)
{
EFI_STATUS Status;
UINT32 Retries;
UINT32 BlockSize;
PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
UINT32 MaxTransferBlocks;
UINTN OrginalBlocks;
EFI_STATUS Status;
UINT32 Retries;
UINT32 BlockSize;
PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
UINT32 MaxTransferBlocks;
UINTN OrginalBlocks;
Status = EFI_SUCCESS;
Retries = 0;
@@ -120,14 +120,15 @@ NvmeRead (
Lba,
Blocks > MaxTransferBlocks ? MaxTransferBlocks : (UINT32)Blocks
);
if (EFI_ERROR(Status)) {
if (EFI_ERROR (Status)) {
Retries++;
MaxTransferBlocks = MaxTransferBlocks >> 1;
if (Retries > NVME_READ_MAX_RETRY || MaxTransferBlocks < 1) {
if ((Retries > NVME_READ_MAX_RETRY) || (MaxTransferBlocks < 1)) {
DEBUG ((DEBUG_ERROR, "%a: ReadSectors fail, Status - %r\n", __FUNCTION__, Status));
break;
}
DEBUG ((
DEBUG_BLKIO,
"%a: ReadSectors fail, retry with smaller transfer block number - 0x%x\n",
@@ -142,13 +143,21 @@ NvmeRead (
Buffer += (MaxTransferBlocks * BlockSize);
Lba += MaxTransferBlocks;
} else {
Blocks = 0;
Blocks = 0;
}
}
DEBUG ((DEBUG_BLKIO, "%a: Lba = 0x%08Lx, Original = 0x%08Lx, "
"Remaining = 0x%08Lx, BlockSize = 0x%x, Status = %r\n", __FUNCTION__, Lba,
(UINT64)OrginalBlocks, (UINT64)Blocks, BlockSize, Status));
DEBUG ((
DEBUG_BLKIO,
"%a: Lba = 0x%08Lx, Original = 0x%08Lx, "
"Remaining = 0x%08Lx, BlockSize = 0x%x, Status = %r\n",
__FUNCTION__,
Lba,
(UINT64)OrginalBlocks,
(UINT64)Blocks,
BlockSize,
Status
));
return Status;
}
@@ -176,13 +185,13 @@ NvmeBlockIoPeimGetDeviceNo (
OUT UINTN *NumberBlockDevices
)
{
PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
if (This == NULL || NumberBlockDevices == NULL) {
if ((This == NULL) || (NumberBlockDevices == NULL)) {
return EFI_INVALID_PARAMETER;
}
Private = GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_BLKIO (This);
Private = GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_BLKIO (This);
*NumberBlockDevices = Private->ActiveNamespaceNum;
return EFI_SUCCESS;
@@ -238,9 +247,9 @@ NvmeBlockIoPeimGetMediaInfo (
OUT EFI_PEI_BLOCK_IO_MEDIA *MediaInfo
)
{
PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
if (This == NULL || MediaInfo == NULL) {
if ((This == NULL) || (MediaInfo == NULL)) {
return EFI_INVALID_PARAMETER;
}
@@ -250,7 +259,7 @@ NvmeBlockIoPeimGetMediaInfo (
return EFI_INVALID_PARAMETER;
}
MediaInfo->DeviceType = (EFI_PEI_BLOCK_DEVICE_TYPE) EDKII_PEI_BLOCK_DEVICE_TYPE_NVME;
MediaInfo->DeviceType = (EFI_PEI_BLOCK_DEVICE_TYPE)EDKII_PEI_BLOCK_DEVICE_TYPE_NVME;
MediaInfo->MediaPresent = TRUE;
MediaInfo->LastBlock = (UINTN)Private->NamespaceInfo[DeviceIndex-1].Media.LastBlock;
MediaInfo->BlockSize = Private->NamespaceInfo[DeviceIndex-1].Media.BlockSize;
@@ -303,17 +312,17 @@ NvmeBlockIoPeimReadBlocks (
OUT VOID *Buffer
)
{
PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
PEI_NVME_NAMESPACE_INFO *NamespaceInfo;
UINT32 BlockSize;
UINTN NumberOfBlocks;
PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
PEI_NVME_NAMESPACE_INFO *NamespaceInfo;
UINT32 BlockSize;
UINTN NumberOfBlocks;
Private = GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_BLKIO (This);
//
// Check parameters
//
if (This == NULL || Buffer == NULL) {
if ((This == NULL) || (Buffer == NULL)) {
return EFI_INVALID_PARAMETER;
}
@@ -329,7 +338,7 @@ NvmeBlockIoPeimReadBlocks (
// Check BufferSize and StartLBA
//
NamespaceInfo = &(Private->NamespaceInfo[DeviceIndex - 1]);
BlockSize = NamespaceInfo->Media.BlockSize;
BlockSize = NamespaceInfo->Media.BlockSize;
if (BufferSize % BlockSize != 0) {
return EFI_BAD_BUFFER_SIZE;
}
@@ -337,6 +346,7 @@ NvmeBlockIoPeimReadBlocks (
if (StartLBA > NamespaceInfo->Media.LastBlock) {
return EFI_INVALID_PARAMETER;
}
NumberOfBlocks = BufferSize / BlockSize;
if (NumberOfBlocks - 1 > NamespaceInfo->Media.LastBlock - StartLBA) {
return EFI_INVALID_PARAMETER;
@@ -369,13 +379,13 @@ NvmeBlockIoPeimGetDeviceNo2 (
OUT UINTN *NumberBlockDevices
)
{
PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
if (This == NULL || NumberBlockDevices == NULL) {
if ((This == NULL) || (NumberBlockDevices == NULL)) {
return EFI_INVALID_PARAMETER;
}
Private = GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_BLKIO2 (This);
Private = GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_BLKIO2 (This);
*NumberBlockDevices = Private->ActiveNamespaceNum;
return EFI_SUCCESS;
@@ -431,22 +441,22 @@ NvmeBlockIoPeimGetMediaInfo2 (
OUT EFI_PEI_BLOCK_IO2_MEDIA *MediaInfo
)
{
EFI_STATUS Status;
PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
EFI_PEI_BLOCK_IO_MEDIA Media;
EFI_STATUS Status;
PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
EFI_PEI_BLOCK_IO_MEDIA Media;
if (This == NULL || MediaInfo == NULL) {
if ((This == NULL) || (MediaInfo == NULL)) {
return EFI_INVALID_PARAMETER;
}
Private = GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_BLKIO2 (This);
Status = NvmeBlockIoPeimGetMediaInfo (
PeiServices,
&Private->BlkIoPpi,
DeviceIndex,
&Media
);
Status = NvmeBlockIoPeimGetMediaInfo (
PeiServices,
&Private->BlkIoPpi,
DeviceIndex,
&Media
);
if (EFI_ERROR (Status)) {
return Status;
}
@@ -505,7 +515,7 @@ NvmeBlockIoPeimReadBlocks2 (
OUT VOID *Buffer
)
{
PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
if (This == NULL) {
return EFI_INVALID_PARAMETER;

4
MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiBlockIo.h
View File

@@ -14,9 +14,9 @@
//
// Nvme device for EFI_PEI_BLOCK_DEVICE_TYPE
//
#define EDKII_PEI_BLOCK_DEVICE_TYPE_NVME 7
#define EDKII_PEI_BLOCK_DEVICE_TYPE_NVME 7
#define NVME_READ_MAX_RETRY 3
#define NVME_READ_MAX_RETRY 3
/**
Gets the count of block I/O devices that one specific block driver detects.

204
MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiHci.c
View File

@@ -22,14 +22,14 @@
**/
EFI_STATUS
NvmeMmioRead (
IN OUT VOID *MemBuffer,
IN UINTN MmioAddr,
IN UINTN Size
IN OUT VOID *MemBuffer,
IN UINTN MmioAddr,
IN UINTN Size
)
{
UINTN Offset;
UINT8 Data;
UINT8 *Ptr;
UINTN Offset;
UINT8 Data;
UINT8 *Ptr;
// priority has adjusted
switch (Size) {
@@ -52,9 +52,10 @@ NvmeMmioRead (
default:
Ptr = (UINT8 *)MemBuffer;
for (Offset = 0; Offset < Size; Offset += 1) {
Data = MmioRead8 (MmioAddr + Offset);
Data = MmioRead8 (MmioAddr + Offset);
Ptr[Offset] = Data;
}
break;
}
@@ -73,14 +74,14 @@ NvmeMmioRead (
**/
EFI_STATUS
NvmeMmioWrite (
IN OUT UINTN MmioAddr,
IN VOID *MemBuffer,
IN UINTN Size
IN OUT UINTN MmioAddr,
IN VOID *MemBuffer,
IN UINTN Size
)
{
UINTN Offset;
UINT8 Data;
UINT8 *Ptr;
UINTN Offset;
UINT8 Data;
UINT8 *Ptr;
// priority has adjusted
switch (Size) {
@@ -106,6 +107,7 @@ NvmeMmioWrite (
Data = Ptr[Offset];
MmioWrite8 (MmioAddr + Offset, Data);
}
break;
}
@@ -122,18 +124,18 @@ NvmeMmioWrite (
**/
UINT32
NvmeBaseMemPageOffset (
IN UINTN BaseMemIndex
IN UINTN BaseMemIndex
)
{
UINT32 Pages;
UINTN Index;
UINT32 PageSizeList[5];
UINT32 Pages;
UINTN Index;
UINT32 PageSizeList[5];
PageSizeList[0] = 1; /* ASQ */
PageSizeList[1] = 1; /* ACQ */
PageSizeList[2] = 1; /* SQs */
PageSizeList[3] = 1; /* CQs */
PageSizeList[4] = NVME_PRP_SIZE; /* PRPs */
PageSizeList[0] = 1; /* ASQ */
PageSizeList[1] = 1; /* ACQ */
PageSizeList[2] = 1; /* SQs */
PageSizeList[3] = 1; /* CQs */
PageSizeList[4] = NVME_PRP_SIZE; /* PRPs */
if (BaseMemIndex > MAX_BASEMEM_COUNT) {
DEBUG ((DEBUG_ERROR, "%a: The input BaseMem index is invalid.\n", __FUNCTION__));
@@ -161,14 +163,14 @@ NvmeBaseMemPageOffset (
**/
EFI_STATUS
NvmeWaitController (
IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,
IN BOOLEAN WaitReady
IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,
IN BOOLEAN WaitReady
)
{
NVME_CSTS Csts;
EFI_STATUS Status;
UINT32 Index;
UINT8 Timeout;
NVME_CSTS Csts;
EFI_STATUS Status;
UINT32 Index;
UINT8 Timeout;
//
// Cap.To specifies max delay time in 500ms increments for Csts.Rdy to set after
@@ -181,19 +183,19 @@ NvmeWaitController (
}
Status = EFI_SUCCESS;
for(Index = (Timeout * 500); Index != 0; --Index) {
for (Index = (Timeout * 500); Index != 0; --Index) {
MicroSecondDelay (1000);
//
// Check if the controller is initialized
//
Status = NVME_GET_CSTS (Private, &Csts);
if (EFI_ERROR(Status)) {
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "%a: NVME_GET_CSTS fail, Status - %r\n", __FUNCTION__, Status));
return Status;
}
if ((BOOLEAN) Csts.Rdy == WaitReady) {
if ((BOOLEAN)Csts.Rdy == WaitReady) {
break;
}
}
@@ -216,12 +218,12 @@ NvmeWaitController (
**/
EFI_STATUS
NvmeDisableController (
IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private
IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private
)
{
NVME_CC Cc;
NVME_CSTS Csts;
EFI_STATUS Status;
NVME_CC Cc;
NVME_CSTS Csts;
EFI_STATUS Status;
Status = NVME_GET_CSTS (Private, &Csts);
@@ -271,11 +273,11 @@ ErrorExit:
**/
EFI_STATUS
NvmeEnableController (
IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private
IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private
)
{
NVME_CC Cc;
EFI_STATUS Status;
NVME_CC Cc;
EFI_STATUS Status;
//
// Enable the controller
@@ -316,25 +318,25 @@ ErrorExit:
**/
EFI_STATUS
NvmeIdentifyController (
IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,
IN VOID *Buffer
IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,
IN VOID *Buffer
)
{
EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
EFI_NVM_EXPRESS_COMMAND Command;
EFI_NVM_EXPRESS_COMPLETION Completion;
EFI_STATUS Status;
EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
EFI_NVM_EXPRESS_COMMAND Command;
EFI_NVM_EXPRESS_COMPLETION Completion;
EFI_STATUS Status;
ZeroMem (&CommandPacket, sizeof(EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
ZeroMem (&Command, sizeof(EFI_NVM_EXPRESS_COMMAND));
ZeroMem (&Completion, sizeof(EFI_NVM_EXPRESS_COMPLETION));
ZeroMem (&CommandPacket, sizeof (EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
ZeroMem (&Command, sizeof (EFI_NVM_EXPRESS_COMMAND));
ZeroMem (&Completion, sizeof (EFI_NVM_EXPRESS_COMPLETION));
Command.Cdw0.Opcode = NVME_ADMIN_IDENTIFY_CMD;
//
// According to Nvm Express 1.1 spec Figure 38, When not used, the field shall be cleared to 0h.
// For the Identify command, the Namespace Identifier is only used for the Namespace Data structure.
//
Command.Nsid = 0;
Command.Nsid = 0;
CommandPacket.NvmeCmd = &Command;
CommandPacket.NvmeCompletion = &Completion;
@@ -369,19 +371,19 @@ NvmeIdentifyController (
**/
EFI_STATUS
NvmeIdentifyNamespace (
IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,
IN UINT32 NamespaceId,
IN VOID *Buffer
IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,
IN UINT32 NamespaceId,
IN VOID *Buffer
)
{
EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
EFI_NVM_EXPRESS_COMMAND Command;
EFI_NVM_EXPRESS_COMPLETION Completion;
EFI_STATUS Status;
EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
EFI_NVM_EXPRESS_COMMAND Command;
EFI_NVM_EXPRESS_COMPLETION Completion;
EFI_STATUS Status;
ZeroMem (&CommandPacket, sizeof(EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
ZeroMem (&Command, sizeof(EFI_NVM_EXPRESS_COMMAND));
ZeroMem (&Completion, sizeof(EFI_NVM_EXPRESS_COMPLETION));
ZeroMem (&CommandPacket, sizeof (EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
ZeroMem (&Command, sizeof (EFI_NVM_EXPRESS_COMMAND));
ZeroMem (&Completion, sizeof (EFI_NVM_EXPRESS_COMPLETION));
Command.Cdw0.Opcode = NVME_ADMIN_IDENTIFY_CMD;
Command.Nsid = NamespaceId;
@@ -414,11 +416,11 @@ NvmeIdentifyNamespace (
**/
VOID
NvmeDumpControllerData (
IN NVME_ADMIN_CONTROLLER_DATA *ControllerData
IN NVME_ADMIN_CONTROLLER_DATA *ControllerData
)
{
UINT8 Sn[21];
UINT8 Mn[41];
UINT8 Sn[21];
UINT8 Mn[41];
CopyMem (Sn, ControllerData->Sn, sizeof (ControllerData->Sn));
Sn[20] = 0;
@@ -428,11 +430,11 @@ NvmeDumpControllerData (
DEBUG ((DEBUG_INFO, " == NVME IDENTIFY CONTROLLER DATA ==\n"));
DEBUG ((DEBUG_INFO, " PCI VID : 0x%x\n", ControllerData->Vid));
DEBUG ((DEBUG_INFO, " PCI SSVID : 0x%x\n", ControllerData->Ssvid));
DEBUG ((DEBUG_INFO, " SN : %a\n", Sn));
DEBUG ((DEBUG_INFO, " MN : %a\n", Mn));
DEBUG ((DEBUG_INFO, " FR : 0x%lx\n", *((UINT64*)ControllerData->Fr)));
DEBUG ((DEBUG_INFO, " SN : %a\n", Sn));
DEBUG ((DEBUG_INFO, " MN : %a\n", Mn));
DEBUG ((DEBUG_INFO, " FR : 0x%lx\n", *((UINT64 *)ControllerData->Fr)));
DEBUG ((DEBUG_INFO, " RAB : 0x%x\n", ControllerData->Rab));
DEBUG ((DEBUG_INFO, " IEEE : 0x%x\n", *(UINT32*)ControllerData->Ieee_oui));
DEBUG ((DEBUG_INFO, " IEEE : 0x%x\n", *(UINT32 *)ControllerData->Ieee_oui));
DEBUG ((DEBUG_INFO, " AERL : 0x%x\n", ControllerData->Aerl));
DEBUG ((DEBUG_INFO, " SQES : 0x%x\n", ControllerData->Sqes));
DEBUG ((DEBUG_INFO, " CQES : 0x%x\n", ControllerData->Cqes));
@@ -451,24 +453,24 @@ NvmeDumpControllerData (
**/
EFI_STATUS
NvmeCreateIoCompletionQueue (
IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private
IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private
)
{
EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
EFI_NVM_EXPRESS_COMMAND Command;
EFI_NVM_EXPRESS_COMPLETION Completion;
EFI_STATUS Status;
NVME_ADMIN_CRIOCQ CrIoCq;
EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
EFI_NVM_EXPRESS_COMMAND Command;
EFI_NVM_EXPRESS_COMPLETION Completion;
EFI_STATUS Status;
NVME_ADMIN_CRIOCQ CrIoCq;
ZeroMem (&CommandPacket, sizeof(EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
ZeroMem (&Command, sizeof(EFI_NVM_EXPRESS_COMMAND));
ZeroMem (&Completion, sizeof(EFI_NVM_EXPRESS_COMPLETION));
ZeroMem (&CrIoCq, sizeof(NVME_ADMIN_CRIOCQ));
ZeroMem (&CommandPacket, sizeof (EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
ZeroMem (&Command, sizeof (EFI_NVM_EXPRESS_COMMAND));
ZeroMem (&Completion, sizeof (EFI_NVM_EXPRESS_COMPLETION));
ZeroMem (&CrIoCq, sizeof (NVME_ADMIN_CRIOCQ));
CommandPacket.NvmeCmd = &Command;
CommandPacket.NvmeCompletion = &Completion;
Command.Cdw0.Opcode = NVME_ADMIN_CRIOCQ_CMD;
Command.Cdw0.Opcode = NVME_ADMIN_CRIOCQ_CMD;
CommandPacket.TransferBuffer = Private->CqBuffer[NVME_IO_QUEUE];
CommandPacket.TransferLength = EFI_PAGE_SIZE;
CommandPacket.CommandTimeout = NVME_GENERIC_TIMEOUT;
@@ -499,24 +501,24 @@ NvmeCreateIoCompletionQueue (
**/
EFI_STATUS
NvmeCreateIoSubmissionQueue (
IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private
IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private
)
{
EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
EFI_NVM_EXPRESS_COMMAND Command;
EFI_NVM_EXPRESS_COMPLETION Completion;
EFI_STATUS Status;
NVME_ADMIN_CRIOSQ CrIoSq;
EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
EFI_NVM_EXPRESS_COMMAND Command;
EFI_NVM_EXPRESS_COMPLETION Completion;
EFI_STATUS Status;
NVME_ADMIN_CRIOSQ CrIoSq;
ZeroMem (&CommandPacket, sizeof(EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
ZeroMem (&Command, sizeof(EFI_NVM_EXPRESS_COMMAND));
ZeroMem (&Completion, sizeof(EFI_NVM_EXPRESS_COMPLETION));
ZeroMem (&CrIoSq, sizeof(NVME_ADMIN_CRIOSQ));
ZeroMem (&CommandPacket, sizeof (EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
ZeroMem (&Command, sizeof (EFI_NVM_EXPRESS_COMMAND));
ZeroMem (&Completion, sizeof (EFI_NVM_EXPRESS_COMPLETION));
ZeroMem (&CrIoSq, sizeof (NVME_ADMIN_CRIOSQ));
CommandPacket.NvmeCmd = &Command;
CommandPacket.NvmeCompletion = &Completion;
Command.Cdw0.Opcode = NVME_ADMIN_CRIOSQ_CMD;
Command.Cdw0.Opcode = NVME_ADMIN_CRIOSQ_CMD;
CommandPacket.TransferBuffer = Private->SqBuffer[NVME_IO_QUEUE];
CommandPacket.TransferLength = EFI_PAGE_SIZE;
CommandPacket.CommandTimeout = NVME_GENERIC_TIMEOUT;
@@ -549,15 +551,15 @@ NvmeCreateIoSubmissionQueue (
**/
EFI_STATUS
NvmeControllerInit (
IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private
IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private
)
{
EFI_STATUS Status;
UINTN Index;
NVME_AQA Aqa;
NVME_ASQ Asq;
NVME_ACQ Acq;
NVME_VER Ver;
EFI_STATUS Status;
UINTN Index;
NVME_AQA Aqa;
NVME_ASQ Asq;
NVME_ACQ Acq;
NVME_VER Ver;
//
// Dump the NVME controller implementation version
@@ -589,6 +591,7 @@ NvmeControllerInit (
ZeroMem ((VOID *)(UINTN)(&Private->SqTdbl[Index]), sizeof (NVME_SQTDBL));
ZeroMem ((VOID *)(UINTN)(&Private->CqHdbl[Index]), sizeof (NVME_CQHDBL));
}
ZeroMem (Private->Buffer, EFI_PAGE_SIZE * NVME_MEM_MAX_PAGES);
//
@@ -657,11 +660,13 @@ NvmeControllerInit (
return EFI_OUT_OF_RESOURCES;
}
}
Status = NvmeIdentifyController (Private, Private->ControllerData);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "%a: NvmeIdentifyController fail, Status - %r\n", __FUNCTION__, Status));
return Status;
}
NvmeDumpControllerData (Private->ControllerData);
//
@@ -684,6 +689,7 @@ NvmeControllerInit (
DEBUG ((DEBUG_ERROR, "%a: Create IO completion queue fail, Status - %r\n", __FUNCTION__, Status));
return Status;
}
Status = NvmeCreateIoSubmissionQueue (Private);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "%a: Create IO submission queue fail, Status - %r\n", __FUNCTION__, Status));
@@ -700,17 +706,17 @@ NvmeControllerInit (
**/
VOID
NvmeFreeDmaResource (
IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private
IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private
)
{
ASSERT (Private != NULL);
if (Private->BufferMapping != NULL) {
IoMmuFreeBuffer (
NVME_MEM_MAX_PAGES,
Private->Buffer,
Private->BufferMapping
);
NVME_MEM_MAX_PAGES,
Private->Buffer,
Private->BufferMapping
);
}
return;

39
MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiHci.h
View File

@@ -43,14 +43,13 @@ enum {
//
// All of base memories are 4K(0x1000) alignment
//
#define ALIGN(v, a) (UINTN)((((v) - 1) | ((a) - 1)) + 1)
#define NVME_MEM_BASE(Private) ((UINTN)(Private->Buffer))
#define NVME_ASQ_BASE(Private) (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_ASQ)) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))
#define NVME_ACQ_BASE(Private) (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_ACQ)) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))
#define NVME_SQ_BASE(Private, Index) (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_SQ) + ((Index)*(NVME_MAX_QUEUES-1))) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))
#define NVME_CQ_BASE(Private, Index) (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_CQ) + ((Index)*(NVME_MAX_QUEUES-1))) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))
#define NVME_PRP_BASE(Private) (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_PRP)) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))
#define ALIGN(v, a) (UINTN)((((v) - 1) | ((a) - 1)) + 1)
#define NVME_MEM_BASE(Private) ((UINTN)(Private->Buffer))
#define NVME_ASQ_BASE(Private) (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_ASQ)) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))
#define NVME_ACQ_BASE(Private) (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_ACQ)) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))
#define NVME_SQ_BASE(Private, Index) (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_SQ) + ((Index)*(NVME_MAX_QUEUES-1))) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))
#define NVME_CQ_BASE(Private, Index) (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_CQ) + ((Index)*(NVME_MAX_QUEUES-1))) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))
#define NVME_PRP_BASE(Private) (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_PRP)) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))
/**
Transfer MMIO Data to memory.
@@ -64,9 +63,9 @@ enum {
**/
EFI_STATUS
NvmeMmioRead (
IN OUT VOID *MemBuffer,
IN UINTN MmioAddr,
IN UINTN Size
IN OUT VOID *MemBuffer,
IN UINTN MmioAddr,
IN UINTN Size
);
/**
@@ -81,9 +80,9 @@ NvmeMmioRead (
**/
EFI_STATUS
NvmeMmioWrite (
IN OUT UINTN MmioAddr,
IN VOID *MemBuffer,
IN UINTN Size
IN OUT UINTN MmioAddr,
IN VOID *MemBuffer,
IN UINTN Size
);
/**
@@ -96,7 +95,7 @@ NvmeMmioWrite (
**/
UINT32
NvmeBaseMemPageOffset (
IN UINTN BaseMemIndex
IN UINTN BaseMemIndex
);
/**
@@ -110,7 +109,7 @@ NvmeBaseMemPageOffset (
**/
EFI_STATUS
NvmeControllerInit (
IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private
IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private
);
/**
@@ -126,9 +125,9 @@ NvmeControllerInit (
**/
EFI_STATUS
NvmeIdentifyNamespace (
IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,
IN UINT32 NamespaceId,
IN VOID *Buffer
IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,
IN UINT32 NamespaceId,
IN VOID *Buffer
);
/**
@@ -139,7 +138,7 @@ NvmeIdentifyNamespace (
**/
VOID
NvmeFreeDmaResource (
IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private
IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private
);
#endif

191
MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiPassThru.c
View File

@@ -22,22 +22,22 @@
**/
UINT64
NvmeCreatePrpList (
IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,
IN EFI_PHYSICAL_ADDRESS PhysicalAddr,
IN UINTN Pages
IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,
IN EFI_PHYSICAL_ADDRESS PhysicalAddr,
IN UINTN Pages
)
{
UINTN PrpEntryNo;
UINTN PrpListNo;
UINT64 PrpListBase;
VOID *PrpListHost;
UINTN PrpListIndex;
UINTN PrpEntryIndex;
UINT64 Remainder;
EFI_PHYSICAL_ADDRESS PrpListPhyAddr;
UINTN Bytes;
UINT8 *PrpEntry;
EFI_PHYSICAL_ADDRESS NewPhyAddr;
UINTN PrpEntryNo;
UINTN PrpListNo;
UINT64 PrpListBase;
VOID *PrpListHost;
UINTN PrpListIndex;
UINTN PrpEntryIndex;
UINT64 Remainder;
EFI_PHYSICAL_ADDRESS PrpListPhyAddr;
UINTN Bytes;
UINT8 *PrpEntry;
EFI_PHYSICAL_ADDRESS NewPhyAddr;
//
// The number of Prp Entry in a memory page.
@@ -47,7 +47,7 @@ NvmeCreatePrpList (
//
// Calculate total PrpList number.
//
PrpListNo = (UINTN) DivU64x64Remainder ((UINT64)Pages, (UINT64)PrpEntryNo, &Remainder);
PrpListNo = (UINTN)DivU64x64Remainder ((UINT64)Pages, (UINT64)PrpEntryNo, &Remainder);
if (Remainder != 0) {
PrpListNo += 1;
}
@@ -62,9 +62,10 @@ NvmeCreatePrpList (
));
return 0;
}
PrpListHost = (VOID *)(UINTN) NVME_PRP_BASE (Private);
Bytes = EFI_PAGES_TO_SIZE (PrpListNo);
PrpListHost = (VOID *)(UINTN)NVME_PRP_BASE (Private);
Bytes = EFI_PAGES_TO_SIZE (PrpListNo);
PrpListPhyAddr = (UINT64)(UINTN)(PrpListHost);
//
@@ -75,19 +76,19 @@ NvmeCreatePrpList (
PrpListBase = (UINTN)PrpListHost + PrpListIndex * EFI_PAGE_SIZE;
for (PrpEntryIndex = 0; PrpEntryIndex < PrpEntryNo; ++PrpEntryIndex) {
PrpEntry = (UINT8 *)(UINTN) (PrpListBase + PrpEntryIndex * sizeof(UINT64));
PrpEntry = (UINT8 *)(UINTN)(PrpListBase + PrpEntryIndex * sizeof (UINT64));
if (PrpEntryIndex != PrpEntryNo - 1) {
//
// Fill all PRP entries except of last one.
//
CopyMem (PrpEntry, (VOID *)(UINTN) (&PhysicalAddr), sizeof (UINT64));
CopyMem (PrpEntry, (VOID *)(UINTN)(&PhysicalAddr), sizeof (UINT64));
PhysicalAddr += EFI_PAGE_SIZE;
} else {
//
// Fill last PRP entries with next PRP List pointer.
//
NewPhyAddr = (PrpListPhyAddr + (PrpListIndex + 1) * EFI_PAGE_SIZE);
CopyMem (PrpEntry, (VOID *)(UINTN) (&NewPhyAddr), sizeof (UINT64));
CopyMem (PrpEntry, (VOID *)(UINTN)(&NewPhyAddr), sizeof (UINT64));
}
}
}
@@ -97,8 +98,8 @@ NvmeCreatePrpList (
//
PrpListBase = (UINTN)PrpListHost + PrpListIndex * EFI_PAGE_SIZE;
for (PrpEntryIndex = 0; PrpEntryIndex < ((Remainder != 0) ? Remainder : PrpEntryNo); ++PrpEntryIndex) {
PrpEntry = (UINT8 *)(UINTN) (PrpListBase + PrpEntryIndex * sizeof(UINT64));
CopyMem (PrpEntry, (VOID *)(UINTN) (&PhysicalAddr), sizeof (UINT64));
PrpEntry = (UINT8 *)(UINTN)(PrpListBase + PrpEntryIndex * sizeof (UINT64));
CopyMem (PrpEntry, (VOID *)(UINTN)(&PhysicalAddr), sizeof (UINT64));
PhysicalAddr += EFI_PAGE_SIZE;
}
@@ -114,10 +115,10 @@ NvmeCreatePrpList (
**/
EFI_STATUS
NvmeCheckCqStatus (
IN NVME_CQ *Cq
IN NVME_CQ *Cq
)
{
if (Cq->Sct == 0x0 && Cq->Sc == 0x0) {
if ((Cq->Sct == 0x0) && (Cq->Sc == 0x0)) {
return EFI_SUCCESS;
}
@@ -202,6 +203,7 @@ NvmeCheckCqStatus (
DEBUG ((DEBUG_INFO, "Reservation Conflict\n"));
break;
}
break;
case 0x1:
@@ -264,6 +266,7 @@ NvmeCheckCqStatus (
DEBUG ((DEBUG_INFO, "Attempted Write to Read Only Range\n"));
break;
}
break;
case 0x2:
@@ -290,6 +293,7 @@ NvmeCheckCqStatus (
DEBUG ((DEBUG_INFO, "Access Denied\n"));
break;
}
break;
default:
@@ -333,26 +337,26 @@ NvmeCheckCqStatus (
**/
EFI_STATUS
NvmePassThruExecute (
IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,
IN UINT32 NamespaceId,
IN OUT EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET *Packet
IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,
IN UINT32 NamespaceId,
IN OUT EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET *Packet
)
{
EFI_STATUS Status;
NVME_SQ *Sq;
NVME_CQ *Cq;
UINT8 QueueId;
UINTN SqSize;
UINTN CqSize;
EDKII_IOMMU_OPERATION MapOp;
UINTN MapLength;
EFI_PHYSICAL_ADDRESS PhyAddr;
VOID *MapData;
VOID *MapMeta;
UINT32 Bytes;
UINT32 Offset;
UINT32 Data32;
UINT64 Timer;
EFI_STATUS Status;
NVME_SQ *Sq;
NVME_CQ *Cq;
UINT8 QueueId;
UINTN SqSize;
UINTN CqSize;
EDKII_IOMMU_OPERATION MapOp;
UINTN MapLength;
EFI_PHYSICAL_ADDRESS PhyAddr;
VOID *MapData;
VOID *MapMeta;
UINT32 Bytes;
UINT32 Offset;
UINT32 Data32;
UINT64 Timer;
//
// Check the data fields in Packet parameter
@@ -378,7 +382,7 @@ NvmePassThruExecute (
return EFI_INVALID_PARAMETER;
}
if (Packet->QueueType != NVME_ADMIN_QUEUE && Packet->QueueType != NVME_IO_QUEUE) {
if ((Packet->QueueType != NVME_ADMIN_QUEUE) && (Packet->QueueType != NVME_IO_QUEUE)) {
DEBUG ((
DEBUG_ERROR,
"%a, Invalid parameter: QueueId(%lx)\n",
@@ -413,7 +417,7 @@ NvmePassThruExecute (
ZeroMem (Sq, sizeof (NVME_SQ));
Sq->Opc = (UINT8)Packet->NvmeCmd->Cdw0.Opcode;
Sq->Fuse = (UINT8)Packet->NvmeCmd->Cdw0.FusedOperation;
Sq->Cid = Private->Cid[QueueId]++;;
Sq->Cid = Private->Cid[QueueId]++;
Sq->Nsid = Packet->NvmeCmd->Nsid;
//
@@ -436,7 +440,8 @@ NvmePassThruExecute (
//
if ((Sq->Opc & (BIT0 | BIT1)) != 0) {
if (((Packet->TransferLength != 0) && (Packet->TransferBuffer == NULL)) ||
((Packet->TransferLength == 0) && (Packet->TransferBuffer != NULL))) {
((Packet->TransferLength == 0) && (Packet->TransferBuffer != NULL)))
{
return EFI_INVALID_PARAMETER;
}
@@ -445,9 +450,11 @@ NvmePassThruExecute (
// allocated internally by the driver.
//
if ((Packet->QueueType == NVME_ADMIN_QUEUE) &&
((Sq->Opc == NVME_ADMIN_CRIOCQ_CMD) || (Sq->Opc == NVME_ADMIN_CRIOSQ_CMD))) {
((Sq->Opc == NVME_ADMIN_CRIOCQ_CMD) || (Sq->Opc == NVME_ADMIN_CRIOSQ_CMD)))
{
if ((Packet->TransferBuffer != Private->SqBuffer[NVME_IO_QUEUE]) &&
(Packet->TransferBuffer != Private->CqBuffer[NVME_IO_QUEUE])) {
(Packet->TransferBuffer != Private->CqBuffer[NVME_IO_QUEUE]))
{
DEBUG ((
DEBUG_ERROR,
"%a: Does not support external IO queues creation request.\n",
@@ -464,13 +471,13 @@ NvmePassThruExecute (
if ((Packet->TransferLength != 0) && (Packet->TransferBuffer != NULL)) {
MapLength = Packet->TransferLength;
Status = IoMmuMap (
MapOp,
Packet->TransferBuffer,
&MapLength,
&PhyAddr,
&MapData
);
Status = IoMmuMap (
MapOp,
Packet->TransferBuffer,
&MapLength,
&PhyAddr,
&MapData
);
if (EFI_ERROR (Status) || (MapLength != Packet->TransferLength)) {
Status = EFI_OUT_OF_RESOURCES;
DEBUG ((DEBUG_ERROR, "%a: Fail to map data buffer.\n", __FUNCTION__));
@@ -480,20 +487,21 @@ NvmePassThruExecute (
Sq->Prp[0] = PhyAddr;
}
if((Packet->MetadataLength != 0) && (Packet->MetadataBuffer != NULL)) {
if ((Packet->MetadataLength != 0) && (Packet->MetadataBuffer != NULL)) {
MapLength = Packet->MetadataLength;
Status = IoMmuMap (
MapOp,
Packet->MetadataBuffer,
&MapLength,
&PhyAddr,
&MapMeta
);
Status = IoMmuMap (
MapOp,
Packet->MetadataBuffer,
&MapLength,
&PhyAddr,
&MapMeta
);
if (EFI_ERROR (Status) || (MapLength != Packet->MetadataLength)) {
Status = EFI_OUT_OF_RESOURCES;
DEBUG ((DEBUG_ERROR, "%a: Fail to map meta data buffer.\n", __FUNCTION__));
goto Exit;
}
Sq->Mptr = PhyAddr;
}
}
@@ -510,18 +518,17 @@ NvmePassThruExecute (
//
// Create PrpList for remaining Data Buffer.
//
PhyAddr = (Sq->Prp[0] + EFI_PAGE_SIZE) & ~(EFI_PAGE_SIZE - 1);
PhyAddr = (Sq->Prp[0] + EFI_PAGE_SIZE) & ~(EFI_PAGE_SIZE - 1);
Sq->Prp[1] = NvmeCreatePrpList (
Private,
PhyAddr,
EFI_SIZE_TO_PAGES(Offset + Bytes) - 1
EFI_SIZE_TO_PAGES (Offset + Bytes) - 1
);
if (Sq->Prp[1] == 0) {
Status = EFI_OUT_OF_RESOURCES;
DEBUG ((DEBUG_ERROR, "%a: Create PRP list fail, Status - %r\n", __FUNCTION__, Status));
goto Exit;
}
} else if ((Offset + Bytes) > EFI_PAGE_SIZE) {
Sq->Prp[1] = (Sq->Prp[0] + EFI_PAGE_SIZE) & ~(EFI_PAGE_SIZE - 1);
}
@@ -529,18 +536,23 @@ NvmePassThruExecute (
if (Packet->NvmeCmd->Flags & CDW10_VALID) {
Sq->Payload.Raw.Cdw10 = Packet->NvmeCmd->Cdw10;
}
if (Packet->NvmeCmd->Flags & CDW11_VALID) {
Sq->Payload.Raw.Cdw11 = Packet->NvmeCmd->Cdw11;
}
if (Packet->NvmeCmd->Flags & CDW12_VALID) {
Sq->Payload.Raw.Cdw12 = Packet->NvmeCmd->Cdw12;
}
if (Packet->NvmeCmd->Flags & CDW13_VALID) {
Sq->Payload.Raw.Cdw13 = Packet->NvmeCmd->Cdw13;
}
if (Packet->NvmeCmd->Flags & CDW14_VALID) {
Sq->Payload.Raw.Cdw14 = Packet->NvmeCmd->Cdw14;
}
if (Packet->NvmeCmd->Flags & CDW15_VALID) {
Sq->Payload.Raw.Cdw15 = Packet->NvmeCmd->Cdw15;
}
@@ -552,6 +564,7 @@ NvmePassThruExecute (
if (Private->SqTdbl[QueueId].Sqt == SqSize) {
Private->SqTdbl[QueueId].Sqt = 0;
}
Data32 = ReadUnaligned32 ((UINT32 *)&Private->SqTdbl[QueueId]);
Status = NVME_SET_SQTDBL (Private, QueueId, &Data32);
if (EFI_ERROR (Status)) {
@@ -588,6 +601,7 @@ NvmePassThruExecute (
//
Status = EFI_TIMEOUT;
}
goto Exit;
}
@@ -597,7 +611,7 @@ NvmePassThruExecute (
Private->CqHdbl[QueueId].Cqh++;
if (Private->CqHdbl[QueueId].Cqh == CqSize) {
Private->CqHdbl[QueueId].Cqh = 0;
Private->Pt[QueueId] ^= 1;
Private->Pt[QueueId] ^= 1;
}
//
@@ -643,14 +657,14 @@ Exit:
EFI_STATUS
EFIAPI
NvmePassThruGetDevicePath (
IN EDKII_PEI_NVM_EXPRESS_PASS_THRU_PPI *This,
OUT UINTN *DevicePathLength,
OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath
IN EDKII_PEI_NVM_EXPRESS_PASS_THRU_PPI *This,
OUT UINTN *DevicePathLength,
OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath
)
{
PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
if (This == NULL || DevicePathLength == NULL || DevicePath == NULL) {
if ((This == NULL) || (DevicePathLength == NULL) || (DevicePath == NULL)) {
return EFI_INVALID_PARAMETER;
}
@@ -705,15 +719,15 @@ NvmePassThruGetDevicePath (
EFI_STATUS
EFIAPI
NvmePassThruGetNextNameSpace (
IN EDKII_PEI_NVM_EXPRESS_PASS_THRU_PPI *This,
IN OUT UINT32 *NamespaceId
IN EDKII_PEI_NVM_EXPRESS_PASS_THRU_PPI *This,
IN OUT UINT32 *NamespaceId
)
{
PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
UINT32 DeviceIndex;
EFI_STATUS Status;
PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
UINT32 DeviceIndex;
EFI_STATUS Status;
if (This == NULL || NamespaceId == NULL) {
if ((This == NULL) || (NamespaceId == NULL)) {
return EFI_INVALID_PARAMETER;
}
@@ -736,7 +750,7 @@ NvmePassThruGetNextNameSpace (
// Start with the first namespace ID
//
*NamespaceId = Private->NamespaceInfo[0].NamespaceId;
Status = EFI_SUCCESS;
Status = EFI_SUCCESS;
} else {
if (*NamespaceId > Private->ControllerData->Nn) {
return EFI_INVALID_PARAMETER;
@@ -750,15 +764,15 @@ NvmePassThruGetNextNameSpace (
if (*NamespaceId == Private->NamespaceInfo[DeviceIndex].NamespaceId) {
if ((DeviceIndex + 1) < Private->ActiveNamespaceNum) {
*NamespaceId = Private->NamespaceInfo[DeviceIndex + 1].NamespaceId;
Status = EFI_SUCCESS;
Status = EFI_SUCCESS;
}
break;
}
}
}
return Status;
}
/**
@@ -795,15 +809,15 @@ NvmePassThruGetNextNameSpace (
EFI_STATUS
EFIAPI
NvmePassThru (
IN EDKII_PEI_NVM_EXPRESS_PASS_THRU_PPI *This,
IN UINT32 NamespaceId,
IN OUT EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET *Packet
IN EDKII_PEI_NVM_EXPRESS_PASS_THRU_PPI *This,
IN UINT32 NamespaceId,
IN OUT EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET *Packet
)
{
PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
EFI_STATUS Status;
PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
EFI_STATUS Status;
if (This == NULL || Packet == NULL) {
if ((This == NULL) || (Packet == NULL)) {
return EFI_INVALID_PARAMETER;
}
@@ -812,7 +826,8 @@ NvmePassThru (
// Check NamespaceId is valid or not.
//
if ((NamespaceId > Private->ControllerData->Nn) &&
(NamespaceId != (UINT32) -1)) {
(NamespaceId != (UINT32)-1))
{
return EFI_INVALID_PARAMETER;
}
@@ -823,6 +838,4 @@ NvmePassThru (
);
return Status;
}

24
MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiPassThru.h
View File

@@ -11,8 +11,6 @@
#ifndef _NVM_EXPRESS_PEI_PASSTHRU_H_
#define _NVM_EXPRESS_PEI_PASSTHRU_H_
/**
Sends an NVM Express Command Packet to an NVM Express controller or namespace. This function only
supports blocking execution of the command.
@@ -46,9 +44,9 @@
**/
EFI_STATUS
NvmePassThruExecute (
IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,
IN UINT32 NamespaceId,
IN OUT EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET *Packet
IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,
IN UINT32 NamespaceId,
IN OUT EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET *Packet
);
/**
@@ -71,9 +69,9 @@ NvmePassThruExecute (
EFI_STATUS
EFIAPI
NvmePassThruGetDevicePath (
IN EDKII_PEI_NVM_EXPRESS_PASS_THRU_PPI *This,
OUT UINTN *DevicePathLength,
OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath
IN EDKII_PEI_NVM_EXPRESS_PASS_THRU_PPI *This,
OUT UINTN *DevicePathLength,
OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath
);
/**
@@ -115,8 +113,8 @@ NvmePassThruGetDevicePath (
EFI_STATUS
EFIAPI
NvmePassThruGetNextNameSpace (
IN EDKII_PEI_NVM_EXPRESS_PASS_THRU_PPI *This,
IN OUT UINT32 *NamespaceId
IN EDKII_PEI_NVM_EXPRESS_PASS_THRU_PPI *This,
IN OUT UINT32 *NamespaceId
);
/**
@@ -153,9 +151,9 @@ NvmePassThruGetNextNameSpace (
EFI_STATUS
EFIAPI
NvmePassThru (
IN EDKII_PEI_NVM_EXPRESS_PASS_THRU_PPI *This,
IN UINT32 NamespaceId,
IN OUT EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET *Packet
IN EDKII_PEI_NVM_EXPRESS_PASS_THRU_PPI *This,
IN UINT32 NamespaceId,
IN OUT EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET *Packet
);
#endif

27
MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiS3.c
View File

@@ -26,18 +26,18 @@
**/
BOOLEAN
NvmeS3SkipThisController (
IN EFI_DEVICE_PATH_PROTOCOL *HcDevicePath,
IN UINTN HcDevicePathLength
IN EFI_DEVICE_PATH_PROTOCOL *HcDevicePath,
IN UINTN HcDevicePathLength
)
{
EFI_STATUS Status;
UINT8 DummyData;
UINTN S3InitDevicesLength;
EFI_DEVICE_PATH_PROTOCOL *S3InitDevices;
EFI_DEVICE_PATH_PROTOCOL *DevicePathInst;
UINTN DevicePathInstLength;
BOOLEAN EntireEnd;
BOOLEAN Skip;
EFI_STATUS Status;
UINT8 DummyData;
UINTN S3InitDevicesLength;
EFI_DEVICE_PATH_PROTOCOL *S3InitDevices;
EFI_DEVICE_PATH_PROTOCOL *DevicePathInst;
UINTN DevicePathInstLength;
BOOLEAN EntireEnd;
BOOLEAN Skip;
//
// From the LockBox, get the list of device paths for devices need to be
@@ -47,7 +47,7 @@ NvmeS3SkipThisController (
S3InitDevicesLength = sizeof (DummyData);
EntireEnd = FALSE;
Skip = TRUE;
Status = RestoreLockBox (&gS3StorageDeviceInitListGuid, &DummyData, &S3InitDevicesLength);
Status = RestoreLockBox (&gS3StorageDeviceInitListGuid, &DummyData, &S3InitDevicesLength);
if (Status != EFI_BUFFER_TOO_SMALL) {
return Skip;
} else {
@@ -83,7 +83,7 @@ NvmeS3SkipThisController (
}
DevicePathInst = S3InitDevices;
S3InitDevices = (EFI_DEVICE_PATH_PROTOCOL *)((UINTN) S3InitDevices + DevicePathInstLength);
S3InitDevices = (EFI_DEVICE_PATH_PROTOCOL *)((UINTN)S3InitDevices + DevicePathInstLength);
if (HcDevicePathLength >= DevicePathInstLength) {
continue;
@@ -97,7 +97,8 @@ NvmeS3SkipThisController (
DevicePathInst,
HcDevicePath,
HcDevicePathLength - sizeof (EFI_DEVICE_PATH_PROTOCOL)
) == 0) {
) == 0)
{
Skip = FALSE;
break;
}

60
MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiStorageSecurity.c
View File

@@ -47,27 +47,27 @@
**/
EFI_STATUS
TrustTransferNvmeDevice (
IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,
IN OUT VOID *Buffer,
IN UINT8 SecurityProtocolId,
IN UINT16 SecurityProtocolSpecificData,
IN UINTN TransferLength,
IN BOOLEAN IsTrustSend,
IN UINT64 Timeout,
OUT UINTN *TransferLengthOut
IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,
IN OUT VOID *Buffer,
IN UINT8 SecurityProtocolId,
IN UINT16 SecurityProtocolSpecificData,
IN UINTN TransferLength,
IN BOOLEAN IsTrustSend,
IN UINT64 Timeout,
OUT UINTN *TransferLengthOut
)
{
EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
EFI_NVM_EXPRESS_COMMAND Command;
EFI_NVM_EXPRESS_COMPLETION Completion;
EFI_STATUS Status;
UINT16 SpecificData;
EDKII_PEI_NVM_EXPRESS_PASS_THRU_PPI *NvmePassThru;
EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
EFI_NVM_EXPRESS_COMMAND Command;
EFI_NVM_EXPRESS_COMPLETION Completion;
EFI_STATUS Status;
UINT16 SpecificData;
EDKII_PEI_NVM_EXPRESS_PASS_THRU_PPI *NvmePassThru;
NvmePassThru = &Private->NvmePassThruPpi;
ZeroMem (&CommandPacket, sizeof(EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
ZeroMem (&Command, sizeof(EFI_NVM_EXPRESS_COMMAND));
ZeroMem (&Completion, sizeof(EFI_NVM_EXPRESS_COMPLETION));
ZeroMem (&CommandPacket, sizeof (EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
ZeroMem (&Command, sizeof (EFI_NVM_EXPRESS_COMMAND));
ZeroMem (&Completion, sizeof (EFI_NVM_EXPRESS_COMPLETION));
CommandPacket.NvmeCmd = &Command;
CommandPacket.NvmeCompletion = &Completion;
@@ -103,10 +103,10 @@ TrustTransferNvmeDevice (
);
if (!IsTrustSend) {
if (EFI_ERROR (Status)) {
if (EFI_ERROR (Status)) {
*TransferLengthOut = 0;
} else {
*TransferLengthOut = (UINTN) TransferLength;
*TransferLengthOut = (UINTN)TransferLength;
}
}
@@ -126,17 +126,17 @@ TrustTransferNvmeDevice (
EFI_STATUS
EFIAPI
NvmeStorageSecurityGetDeviceNo (
IN EDKII_PEI_STORAGE_SECURITY_CMD_PPI *This,
OUT UINTN *NumberofDevices
IN EDKII_PEI_STORAGE_SECURITY_CMD_PPI *This,
OUT UINTN *NumberofDevices
)
{
PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
if (This == NULL || NumberofDevices == NULL) {
if ((This == NULL) || (NumberofDevices == NULL)) {
return EFI_INVALID_PARAMETER;
}
Private = GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_STROAGE_SECURITY (This);
Private = GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_STROAGE_SECURITY (This);
*NumberofDevices = Private->ActiveNamespaceNum;
return EFI_SUCCESS;
@@ -176,9 +176,9 @@ NvmeStorageSecurityGetDevicePath (
OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath
)
{
PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
if (This == NULL || DevicePathLength == NULL || DevicePath == NULL) {
if ((This == NULL) || (DevicePathLength == NULL) || (DevicePath == NULL)) {
return EFI_INVALID_PARAMETER;
}
@@ -295,8 +295,8 @@ NvmeStorageSecurityReceiveData (
OUT UINTN *PayloadTransferSize
)
{
PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
EFI_STATUS Status;
PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
EFI_STATUS Status;
if ((PayloadBuffer == NULL) || (PayloadTransferSize == NULL) || (PayloadBufferSize == 0)) {
return EFI_INVALID_PARAMETER;
@@ -394,8 +394,8 @@ NvmeStorageSecuritySendData (
IN VOID *PayloadBuffer
)
{
PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
EFI_STATUS Status;
PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
EFI_STATUS Status;
if ((PayloadBuffer == NULL) && (PayloadBufferSize != 0)) {
return EFI_INVALID_PARAMETER;

4
MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiStorageSecurity.h
View File

@@ -24,8 +24,8 @@
EFI_STATUS
EFIAPI
NvmeStorageSecurityGetDeviceNo (
IN EDKII_PEI_STORAGE_SECURITY_CMD_PPI *This,
OUT UINTN *NumberofDevices
IN EDKII_PEI_STORAGE_SECURITY_CMD_PPI *This,
OUT UINTN *NumberofDevices
);
/**

23
MdeModulePkg/Bus/Pci/PciBusDxe/ComponentName.c
View File

@@ -20,16 +20,15 @@ GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME_PROTOCOL gPciBusComponentName
//
// EFI Component Name 2 Protocol
//
GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gPciBusComponentName2 = {
(EFI_COMPONENT_NAME2_GET_DRIVER_NAME) PciBusComponentNameGetDriverName,
(EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME) PciBusComponentNameGetControllerName,
GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gPciBusComponentName2 = {
(EFI_COMPONENT_NAME2_GET_DRIVER_NAME)PciBusComponentNameGetDriverName,
(EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME)PciBusComponentNameGetControllerName,
"en"
};
GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mPciBusDriverNameTable[] = {
{ "eng;en", (CHAR16 *) L"PCI Bus Driver" },
{ NULL , NULL }
GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mPciBusDriverNameTable[] = {
{ "eng;en", (CHAR16 *)L"PCI Bus Driver" },
{ NULL, NULL }
};
/**
@@ -159,11 +158,11 @@ PciBusComponentNameGetDriverName (
EFI_STATUS
EFIAPI
PciBusComponentNameGetControllerName (
IN EFI_COMPONENT_NAME_PROTOCOL *This,
IN EFI_HANDLE ControllerHandle,
IN EFI_HANDLE ChildHandle OPTIONAL,
IN CHAR8 *Language,
OUT CHAR16 **ControllerName
IN EFI_COMPONENT_NAME_PROTOCOL *This,
IN EFI_HANDLE ControllerHandle,
IN EFI_HANDLE ChildHandle OPTIONAL,
IN CHAR8 *Language,
OUT CHAR16 **ControllerName
)
{
return EFI_UNSUPPORTED;

14
MdeModulePkg/Bus/Pci/PciBusDxe/ComponentName.h
View File

@@ -6,7 +6,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _EFI_PCI_BUS_COMPONENT_NAME_H_
#define _EFI_PCI_BUS_COMPONENT_NAME_H_
@@ -16,6 +15,7 @@ extern EFI_COMPONENT_NAME2_PROTOCOL gPciBusComponentName2;
//
// EFI Component Name Functions
//
/**
Retrieves a Unicode string that is the user readable name of the driver.
@@ -63,7 +63,6 @@ PciBusComponentNameGetDriverName (
OUT CHAR16 **DriverName
);
/**
Retrieves a Unicode string that is the user readable name of the controller
that is being managed by a driver.
@@ -135,12 +134,11 @@ PciBusComponentNameGetDriverName (
EFI_STATUS
EFIAPI
PciBusComponentNameGetControllerName (
IN EFI_COMPONENT_NAME_PROTOCOL *This,
IN EFI_HANDLE ControllerHandle,
IN EFI_HANDLE ChildHandle OPTIONAL,
IN CHAR8 *Language,
OUT CHAR16 **ControllerName
IN EFI_COMPONENT_NAME_PROTOCOL *This,
IN EFI_HANDLE ControllerHandle,
IN EFI_HANDLE ChildHandle OPTIONAL,
IN CHAR8 *Language,
OUT CHAR16 **ControllerName
);
#endif

145
MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c
View File

@@ -18,7 +18,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
//
// PCI Bus Driver Global Variables
//
EFI_DRIVER_BINDING_PROTOCOL gPciBusDriverBinding = {
EFI_DRIVER_BINDING_PROTOCOL gPciBusDriverBinding = {
PciBusDriverBindingSupported,
PciBusDriverBindingStart,
PciBusDriverBindingStop,
@@ -29,17 +29,17 @@ EFI_DRIVER_BINDING_PROTOCOL gPciBusDriverBinding = {
EFI_HANDLE gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM];
EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *gIncompatiblePciDeviceSupport = NULL;
UINTN gPciHostBridgeNumber = 0;
BOOLEAN gFullEnumeration = TRUE;
UINT64 gAllOne = 0xFFFFFFFFFFFFFFFFULL;
UINT64 gAllZero = 0;
UINTN gPciHostBridgeNumber = 0;
BOOLEAN gFullEnumeration = TRUE;
UINT64 gAllOne = 0xFFFFFFFFFFFFFFFFULL;
UINT64 gAllZero = 0;
EFI_PCI_PLATFORM_PROTOCOL *gPciPlatformProtocol;
EFI_PCI_OVERRIDE_PROTOCOL *gPciOverrideProtocol;
EDKII_IOMMU_PROTOCOL *mIoMmuProtocol;
EDKII_DEVICE_SECURITY_PROTOCOL *mDeviceSecurityProtocol;
EFI_PCI_PLATFORM_PROTOCOL *gPciPlatformProtocol;
EFI_PCI_OVERRIDE_PROTOCOL *gPciOverrideProtocol;
EDKII_IOMMU_PROTOCOL *mIoMmuProtocol;
EDKII_DEVICE_SECURITY_PROTOCOL *mDeviceSecurityProtocol;
GLOBAL_REMOVE_IF_UNREFERENCED EFI_PCI_HOTPLUG_REQUEST_PROTOCOL mPciHotPlugRequest = {
GLOBAL_REMOVE_IF_UNREFERENCED EFI_PCI_HOTPLUG_REQUEST_PROTOCOL mPciHotPlugRequest = {
PciHotPlugRequestNotify
};
@@ -61,8 +61,8 @@ GLOBAL_REMOVE_IF_UNREFERENCED EFI_PCI_HOTPLUG_REQUEST_PROTOCOL mPciHotPlugReques
EFI_STATUS
EFIAPI
PciBusEntryPoint (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
@@ -119,15 +119,15 @@ PciBusEntryPoint (
EFI_STATUS
EFIAPI
PciBusDriverBindingSupported (
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
)
{
EFI_STATUS Status;
EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath;
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
EFI_DEV_PATH_PTR Node;
EFI_STATUS Status;
EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath;
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
EFI_DEV_PATH_PTR Node;
//
// Check RemainingDevicePath validation
@@ -143,9 +143,10 @@ PciBusDriverBindingSupported (
// check its validation
//
Node.DevPath = RemainingDevicePath;
if (Node.DevPath->Type != HARDWARE_DEVICE_PATH ||
Node.DevPath->SubType != HW_PCI_DP ||
DevicePathNodeLength(Node.DevPath) != sizeof(PCI_DEVICE_PATH)) {
if ((Node.DevPath->Type != HARDWARE_DEVICE_PATH) ||
(Node.DevPath->SubType != HW_PCI_DP) ||
(DevicePathNodeLength (Node.DevPath) != sizeof (PCI_DEVICE_PATH)))
{
return EFI_UNSUPPORTED;
}
}
@@ -157,7 +158,7 @@ PciBusDriverBindingSupported (
Status = gBS->OpenProtocol (
Controller,
&gEfiPciRootBridgeIoProtocolGuid,
(VOID **) &PciRootBridgeIo,
(VOID **)&PciRootBridgeIo,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_BY_DRIVER
@@ -174,11 +175,11 @@ PciBusDriverBindingSupported (
// Close the I/O Abstraction(s) used to perform the supported test
//
gBS->CloseProtocol (
Controller,
&gEfiPciRootBridgeIoProtocolGuid,
This->DriverBindingHandle,
Controller
);
Controller,
&gEfiPciRootBridgeIoProtocolGuid,
This->DriverBindingHandle,
Controller
);
//
// Open the EFI Device Path protocol needed to perform the supported test
@@ -186,7 +187,7 @@ PciBusDriverBindingSupported (
Status = gBS->OpenProtocol (
Controller,
&gEfiDevicePathProtocolGuid,
(VOID **) &ParentDevicePath,
(VOID **)&ParentDevicePath,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_BY_DRIVER
@@ -203,11 +204,11 @@ PciBusDriverBindingSupported (
// Close protocol, don't use device path protocol in the Support() function
//
gBS->CloseProtocol (
Controller,
&gEfiDevicePathProtocolGuid,
This->DriverBindingHandle,
Controller
);
Controller,
&gEfiDevicePathProtocolGuid,
This->DriverBindingHandle,
Controller
);
return EFI_SUCCESS;
}
@@ -234,9 +235,9 @@ PciBusDriverBindingStart (
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
)
{
EFI_STATUS Status;
EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath;
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
EFI_STATUS Status;
EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath;
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
//
// Initialize PciRootBridgeIo to suppress incorrect compiler warning.
@@ -259,7 +260,7 @@ PciBusDriverBindingStart (
gBS->LocateProtocol (
&gEfiIncompatiblePciDeviceSupportProtocolGuid,
NULL,
(VOID **) &gIncompatiblePciDeviceSupport
(VOID **)&gIncompatiblePciDeviceSupport
);
//
@@ -268,10 +269,10 @@ PciBusDriverBindingStart (
//
gPciPlatformProtocol = NULL;
gBS->LocateProtocol (
&gEfiPciPlatformProtocolGuid,
NULL,
(VOID **) &gPciPlatformProtocol
);
&gEfiPciPlatformProtocolGuid,
NULL,
(VOID **)&gPciPlatformProtocol
);
//
// If PCI Platform protocol doesn't exist, try to Pci Override Protocol.
@@ -279,32 +280,32 @@ PciBusDriverBindingStart (
if (gPciPlatformProtocol == NULL) {
gPciOverrideProtocol = NULL;
gBS->LocateProtocol (
&gEfiPciOverrideProtocolGuid,
NULL,
(VOID **) &gPciOverrideProtocol
);
&gEfiPciOverrideProtocolGuid,
NULL,
(VOID **)&gPciOverrideProtocol
);
}
if (mIoMmuProtocol == NULL) {
gBS->LocateProtocol (
&gEdkiiIoMmuProtocolGuid,
NULL,
(VOID **) &mIoMmuProtocol
);
&gEdkiiIoMmuProtocolGuid,
NULL,
(VOID **)&mIoMmuProtocol
);
}
if (mDeviceSecurityProtocol == NULL) {
gBS->LocateProtocol (
&gEdkiiDeviceSecurityProtocolGuid,
NULL,
(VOID **) &mDeviceSecurityProtocol
);
&gEdkiiDeviceSecurityProtocolGuid,
NULL,
(VOID **)&mDeviceSecurityProtocol
);
}
if (PcdGetBool (PcdPciDisableBusEnumeration)) {
gFullEnumeration = FALSE;
} else {
gFullEnumeration = (BOOLEAN) ((SearchHostBridgeHandle (Controller) ? FALSE : TRUE));
gFullEnumeration = (BOOLEAN)((SearchHostBridgeHandle (Controller) ? FALSE : TRUE));
}
//
@@ -313,7 +314,7 @@ PciBusDriverBindingStart (
Status = gBS->OpenProtocol (
Controller,
&gEfiDevicePathProtocolGuid,
(VOID **) &ParentDevicePath,
(VOID **)&ParentDevicePath,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_GET_PROTOCOL
@@ -342,7 +343,7 @@ PciBusDriverBindingStart (
Status = gBS->OpenProtocol (
Controller,
&gEfiPciRootBridgeIoProtocolGuid,
(VOID **) &PciRootBridgeIo,
(VOID **)&PciRootBridgeIo,
gPciBusDriverBinding.DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_GET_PROTOCOL
@@ -399,10 +400,10 @@ PciBusDriverBindingStart (
EFI_STATUS
EFIAPI
PciBusDriverBindingStop (
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN UINTN NumberOfChildren,
IN EFI_HANDLE *ChildHandleBuffer
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN UINTN NumberOfChildren,
IN EFI_HANDLE *ChildHandleBuffer
)
{
EFI_STATUS Status;
@@ -414,17 +415,17 @@ PciBusDriverBindingStop (
// Close the bus driver
//
gBS->CloseProtocol (
Controller,
&gEfiDevicePathProtocolGuid,
This->DriverBindingHandle,
Controller
);
Controller,
&gEfiDevicePathProtocolGuid,
This->DriverBindingHandle,
Controller
);
gBS->CloseProtocol (
Controller,
&gEfiPciRootBridgeIoProtocolGuid,
This->DriverBindingHandle,
Controller
);
Controller,
&gEfiPciRootBridgeIoProtocolGuid,
This->DriverBindingHandle,
Controller
);
DestroyRootBridgeByHandle (
Controller
@@ -440,7 +441,6 @@ PciBusDriverBindingStop (
AllChildrenStopped = TRUE;
for (Index = 0; Index < NumberOfChildren; Index++) {
//
// De register all the pci device
//
@@ -457,4 +457,3 @@ PciBusDriverBindingStop (
return EFI_SUCCESS;
}

245
MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h
View File

@@ -6,7 +6,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _EFI_PCI_BUS_H_
#define _EFI_PCI_BUS_H_
@@ -44,15 +43,15 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <IndustryStandard/PeImage.h>
#include <IndustryStandard/Acpi.h>
typedef struct _PCI_IO_DEVICE PCI_IO_DEVICE;
typedef struct _PCI_BAR PCI_BAR;
typedef struct _PCI_IO_DEVICE PCI_IO_DEVICE;
typedef struct _PCI_BAR PCI_BAR;
#define EFI_PCI_RID(Bus, Device, Function) (((UINT32)Bus << 8) + ((UINT32)Device << 3) + (UINT32)Function)
#define EFI_PCI_BUS_OF_RID(RID) ((UINT32)RID >> 8)
#define EFI_PCI_IOV_POLICY_ARI 0x0001
#define EFI_PCI_IOV_POLICY_SRIOV 0x0002
#define EFI_PCI_IOV_POLICY_MRIOV 0x0004
#define EFI_PCI_IOV_POLICY_ARI 0x0001
#define EFI_PCI_IOV_POLICY_SRIOV 0x0002
#define EFI_PCI_IOV_POLICY_MRIOV 0x0004
typedef enum {
PciBarTypeUnknown = 0,
@@ -81,11 +80,11 @@ typedef enum {
#include "PciHotPlugSupport.h"
#include "PciLib.h"
#define VGABASE1 0x3B0
#define VGALIMIT1 0x3BB
#define VGABASE1 0x3B0
#define VGALIMIT1 0x3BB
#define VGABASE2 0x3C0
#define VGALIMIT2 0x3DF
#define VGABASE2 0x3C0
#define VGALIMIT2 0x3DF
#define ISABASE 0x100
#define ISALIMIT 0x3FF
@@ -94,63 +93,63 @@ typedef enum {
// PCI BAR parameters
//
struct _PCI_BAR {
UINT64 BaseAddress;
UINT64 Length;
UINT64 Alignment;
PCI_BAR_TYPE BarType;
BOOLEAN BarTypeFixed;
UINT16 Offset;
UINT64 BaseAddress;
UINT64 Length;
UINT64 Alignment;
PCI_BAR_TYPE BarType;
BOOLEAN BarTypeFixed;
UINT16 Offset;
};
//
// defined in PCI Card Specification, 8.0
//
#define PCI_CARD_MEMORY_BASE_0 0x1C
#define PCI_CARD_MEMORY_LIMIT_0 0x20
#define PCI_CARD_MEMORY_BASE_1 0x24
#define PCI_CARD_MEMORY_LIMIT_1 0x28
#define PCI_CARD_IO_BASE_0_LOWER 0x2C
#define PCI_CARD_IO_BASE_0_UPPER 0x2E
#define PCI_CARD_IO_LIMIT_0_LOWER 0x30
#define PCI_CARD_IO_LIMIT_0_UPPER 0x32
#define PCI_CARD_IO_BASE_1_LOWER 0x34
#define PCI_CARD_IO_BASE_1_UPPER 0x36
#define PCI_CARD_IO_LIMIT_1_LOWER 0x38
#define PCI_CARD_IO_LIMIT_1_UPPER 0x3A
#define PCI_CARD_BRIDGE_CONTROL 0x3E
#define PCI_CARD_MEMORY_BASE_0 0x1C
#define PCI_CARD_MEMORY_LIMIT_0 0x20
#define PCI_CARD_MEMORY_BASE_1 0x24
#define PCI_CARD_MEMORY_LIMIT_1 0x28
#define PCI_CARD_IO_BASE_0_LOWER 0x2C
#define PCI_CARD_IO_BASE_0_UPPER 0x2E
#define PCI_CARD_IO_LIMIT_0_LOWER 0x30
#define PCI_CARD_IO_LIMIT_0_UPPER 0x32
#define PCI_CARD_IO_BASE_1_LOWER 0x34
#define PCI_CARD_IO_BASE_1_UPPER 0x36
#define PCI_CARD_IO_LIMIT_1_LOWER 0x38
#define PCI_CARD_IO_LIMIT_1_UPPER 0x3A
#define PCI_CARD_BRIDGE_CONTROL 0x3E
#define PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE BIT8
#define PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE BIT9
#define PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE BIT8
#define PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE BIT9
#define RB_IO_RANGE 1
#define RB_MEM32_RANGE 2
#define RB_PMEM32_RANGE 3
#define RB_MEM64_RANGE 4
#define RB_PMEM64_RANGE 5
#define RB_IO_RANGE 1
#define RB_MEM32_RANGE 2
#define RB_PMEM32_RANGE 3
#define RB_MEM64_RANGE 4
#define RB_PMEM64_RANGE 5
#define PPB_BAR_0 0
#define PPB_BAR_1 1
#define PPB_IO_RANGE 2
#define PPB_MEM32_RANGE 3
#define PPB_PMEM32_RANGE 4
#define PPB_PMEM64_RANGE 5
#define PPB_MEM64_RANGE 0xFF
#define PPB_BAR_0 0
#define PPB_BAR_1 1
#define PPB_IO_RANGE 2
#define PPB_MEM32_RANGE 3
#define PPB_PMEM32_RANGE 4
#define PPB_PMEM64_RANGE 5
#define PPB_MEM64_RANGE 0xFF
#define P2C_BAR_0 0
#define P2C_MEM_1 1
#define P2C_MEM_2 2
#define P2C_IO_1 3
#define P2C_IO_2 4
#define P2C_BAR_0 0
#define P2C_MEM_1 1
#define P2C_MEM_2 2
#define P2C_IO_1 3
#define P2C_IO_2 4
#define EFI_BRIDGE_IO32_DECODE_SUPPORTED 0x0001
#define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED 0x0002
#define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED 0x0004
#define EFI_BRIDGE_IO16_DECODE_SUPPORTED 0x0008
#define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED 0x0010
#define EFI_BRIDGE_MEM64_DECODE_SUPPORTED 0x0020
#define EFI_BRIDGE_MEM32_DECODE_SUPPORTED 0x0040
#define EFI_BRIDGE_IO32_DECODE_SUPPORTED 0x0001
#define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED 0x0002
#define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED 0x0004
#define EFI_BRIDGE_IO16_DECODE_SUPPORTED 0x0008
#define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED 0x0010
#define EFI_BRIDGE_MEM64_DECODE_SUPPORTED 0x0020
#define EFI_BRIDGE_MEM32_DECODE_SUPPORTED 0x0040
#define PCI_MAX_HOST_BRIDGE_NUM 0x0010
#define PCI_MAX_HOST_BRIDGE_NUM 0x0010
//
// Define option for attribute
@@ -158,130 +157,130 @@ struct _PCI_BAR {
#define EFI_SET_SUPPORTS 0
#define EFI_SET_ATTRIBUTES 1
#define PCI_IO_DEVICE_SIGNATURE SIGNATURE_32 ('p', 'c', 'i', 'o')
#define PCI_IO_DEVICE_SIGNATURE SIGNATURE_32 ('p', 'c', 'i', 'o')
struct _PCI_IO_DEVICE {
UINT32 Signature;
EFI_HANDLE Handle;
EFI_PCI_IO_PROTOCOL PciIo;
LIST_ENTRY Link;
UINT32 Signature;
EFI_HANDLE Handle;
EFI_PCI_IO_PROTOCOL PciIo;
LIST_ENTRY Link;
EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL PciDriverOverride;
EFI_DEVICE_PATH_PROTOCOL *DevicePath;
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
EFI_LOAD_FILE2_PROTOCOL LoadFile2;
EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL PciDriverOverride;
EFI_DEVICE_PATH_PROTOCOL *DevicePath;
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
EFI_LOAD_FILE2_PROTOCOL LoadFile2;
//
// PCI configuration space header type
//
PCI_TYPE00 Pci;
PCI_TYPE00 Pci;
//
// Bus number, Device number, Function number
//
UINT8 BusNumber;
UINT8 DeviceNumber;
UINT8 FunctionNumber;
UINT8 BusNumber;
UINT8 DeviceNumber;
UINT8 FunctionNumber;
//
// BAR for this PCI Device
//
PCI_BAR PciBar[PCI_MAX_BAR];
PCI_BAR PciBar[PCI_MAX_BAR];
//
// The bridge device this pci device is subject to
//
PCI_IO_DEVICE *Parent;
PCI_IO_DEVICE *Parent;
//
// A linked list for children Pci Device if it is bridge device
//
LIST_ENTRY ChildList;
LIST_ENTRY ChildList;
//
// TRUE if the PCI bus driver creates the handle for this PCI device
//
BOOLEAN Registered;
BOOLEAN Registered;
//
// TRUE if the PCI bus driver successfully allocates the resource required by
// this PCI device
//
BOOLEAN Allocated;
BOOLEAN Allocated;
//
// The attribute this PCI device currently set
//
UINT64 Attributes;
UINT64 Attributes;
//
// The attributes this PCI device actually supports
//
UINT64 Supports;
UINT64 Supports;
//
// The resource decode the bridge supports
//
UINT32 Decodes;
UINT32 Decodes;
//
// TRUE if the ROM image is from the PCI Option ROM BAR
//
BOOLEAN EmbeddedRom;
BOOLEAN EmbeddedRom;
//
// The OptionRom Size
//
UINT32 RomSize;
UINT32 RomSize;
//
// TRUE if all OpROM (in device or in platform specific position) have been processed
//
BOOLEAN AllOpRomProcessed;
BOOLEAN AllOpRomProcessed;
//
// TRUE if there is any EFI driver in the OptionRom
//
BOOLEAN BusOverride;
BOOLEAN BusOverride;
//
// A list tracking reserved resource on a bridge device
//
LIST_ENTRY ReservedResourceList;
LIST_ENTRY ReservedResourceList;
//
// A list tracking image handle of platform specific overriding driver
//
LIST_ENTRY OptionRomDriverList;
LIST_ENTRY OptionRomDriverList;
EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *ResourcePaddingDescriptors;
EFI_HPC_PADDING_ATTRIBUTES PaddingAttributes;
EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *ResourcePaddingDescriptors;
EFI_HPC_PADDING_ATTRIBUTES PaddingAttributes;
//
// Bus number ranges for a PCI Root Bridge device
//
EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *BusNumberRanges;
EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *BusNumberRanges;
BOOLEAN IsPciExp;
BOOLEAN IsPciExp;
//
// For SR-IOV
//
UINT8 PciExpressCapabilityOffset;
UINT32 AriCapabilityOffset;
UINT32 SrIovCapabilityOffset;
UINT32 MrIovCapabilityOffset;
PCI_BAR VfPciBar[PCI_MAX_BAR];
UINT32 SystemPageSize;
UINT16 InitialVFs;
UINT16 ReservedBusNum;
UINT8 PciExpressCapabilityOffset;
UINT32 AriCapabilityOffset;
UINT32 SrIovCapabilityOffset;
UINT32 MrIovCapabilityOffset;
PCI_BAR VfPciBar[PCI_MAX_BAR];
UINT32 SystemPageSize;
UINT16 InitialVFs;
UINT16 ReservedBusNum;
//
// Per PCI to PCI Bridge spec, I/O window is 4K aligned,
// but some chipsets support non-standard I/O window alignments less than 4K.
// This field is used to support this case.
//
UINT16 BridgeIoAlignment;
UINT32 ResizableBarOffset;
UINT32 ResizableBarNumber;
UINT16 BridgeIoAlignment;
UINT32 ResizableBarOffset;
UINT32 ResizableBarNumber;
};
#define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \
@@ -296,24 +295,22 @@ struct _PCI_IO_DEVICE {
#define PCI_IO_DEVICE_FROM_LOAD_FILE2_THIS(a) \
CR (a, PCI_IO_DEVICE, LoadFile2, PCI_IO_DEVICE_SIGNATURE)
//
// Global Variables
//
extern EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *gIncompatiblePciDeviceSupport;
extern EFI_DRIVER_BINDING_PROTOCOL gPciBusDriverBinding;
extern EFI_COMPONENT_NAME_PROTOCOL gPciBusComponentName;
extern EFI_COMPONENT_NAME2_PROTOCOL gPciBusComponentName2;
extern BOOLEAN gFullEnumeration;
extern UINTN gPciHostBridgeNumber;
extern EFI_HANDLE gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM];
extern UINT64 gAllOne;
extern UINT64 gAllZero;
extern EFI_PCI_PLATFORM_PROTOCOL *gPciPlatformProtocol;
extern EFI_PCI_OVERRIDE_PROTOCOL *gPciOverrideProtocol;
extern BOOLEAN mReserveIsaAliases;
extern BOOLEAN mReserveVgaAliases;
extern EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *gIncompatiblePciDeviceSupport;
extern EFI_DRIVER_BINDING_PROTOCOL gPciBusDriverBinding;
extern EFI_COMPONENT_NAME_PROTOCOL gPciBusComponentName;
extern EFI_COMPONENT_NAME2_PROTOCOL gPciBusComponentName2;
extern BOOLEAN gFullEnumeration;
extern UINTN gPciHostBridgeNumber;
extern EFI_HANDLE gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM];
extern UINT64 gAllOne;
extern UINT64 gAllZero;
extern EFI_PCI_PLATFORM_PROTOCOL *gPciPlatformProtocol;
extern EFI_PCI_OVERRIDE_PROTOCOL *gPciOverrideProtocol;
extern BOOLEAN mReserveIsaAliases;
extern BOOLEAN mReserveVgaAliases;
/**
Macro that checks whether device is a GFX device.
@@ -324,7 +321,7 @@ extern BOOLEAN mReserveVgaAliases;
@retval FALSE Device is not a GFX device.
**/
#define IS_PCI_GFX(_p) IS_CLASS2 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_OTHER)
#define IS_PCI_GFX(_p) IS_CLASS2 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_OTHER)
/**
Test to see if this driver supports ControllerHandle. Any ControllerHandle
@@ -343,9 +340,9 @@ extern BOOLEAN mReserveVgaAliases;
EFI_STATUS
EFIAPI
PciBusDriverBindingSupported (
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
);
/**
@@ -365,9 +362,9 @@ PciBusDriverBindingSupported (
EFI_STATUS
EFIAPI
PciBusDriverBindingStart (
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
);
/**
@@ -387,10 +384,10 @@ PciBusDriverBindingStart (
EFI_STATUS
EFIAPI
PciBusDriverBindingStop (
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN UINTN NumberOfChildren,
IN EFI_HANDLE *ChildHandleBuffer
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN UINTN NumberOfChildren,
IN EFI_HANDLE *ChildHandleBuffer
);
#endif

67
MdeModulePkg/Bus/Pci/PciBusDxe/PciCommand.c
View File

@@ -22,19 +22,19 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
EFI_STATUS
PciOperateRegister (
IN PCI_IO_DEVICE *PciIoDevice,
IN UINT16 Command,
IN UINT8 Offset,
IN UINT8 Operation,
OUT UINT16 *PtrCommand
IN PCI_IO_DEVICE *PciIoDevice,
IN UINT16 Command,
IN UINT8 Offset,
IN UINT8 Operation,
OUT UINT16 *PtrCommand
)
{
UINT16 OldCommand;
EFI_STATUS Status;
EFI_PCI_IO_PROTOCOL *PciIo;
UINT16 OldCommand;
EFI_STATUS Status;
EFI_PCI_IO_PROTOCOL *PciIo;
OldCommand = 0;
PciIo = &PciIoDevice->PciIo;
OldCommand = 0;
PciIo = &PciIoDevice->PciIo;
if (Operation != EFI_SET_REGISTER) {
Status = PciIo->Pci.Read (
@@ -52,9 +52,9 @@ PciOperateRegister (
}
if (Operation == EFI_ENABLE_REGISTER) {
OldCommand = (UINT16) (OldCommand | Command);
OldCommand = (UINT16)(OldCommand | Command);
} else if (Operation == EFI_DISABLE_REGISTER) {
OldCommand = (UINT16) (OldCommand & ~(Command));
OldCommand = (UINT16)(OldCommand & ~(Command));
} else {
OldCommand = Command;
}
@@ -124,10 +124,8 @@ LocateCapabilityRegBlock (
if (*Offset != 0) {
CapabilityPtr = *Offset;
} else {
CapabilityPtr = 0;
if (IS_CARDBUS_BRIDGE (&PciIoDevice->Pci)) {
PciIoDevice->PciIo.Pci.Read (
&PciIoDevice->PciIo,
EfiPciIoWidthUint8,
@@ -136,7 +134,6 @@ LocateCapabilityRegBlock (
&CapabilityPtr
);
} else {
PciIoDevice->PciIo.Pci.Read (
&PciIoDevice->PciIo,
EfiPciIoWidthUint8,
@@ -156,12 +153,12 @@ LocateCapabilityRegBlock (
&CapabilityEntry
);
CapabilityID = (UINT8) CapabilityEntry;
CapabilityID = (UINT8)CapabilityEntry;
if (CapabilityID == CapId) {
*Offset = CapabilityPtr;
if (NextRegBlock != NULL) {
*NextRegBlock = (UINT8) (CapabilityEntry >> 8);
*NextRegBlock = (UINT8)(CapabilityEntry >> 8);
}
return EFI_SUCCESS;
@@ -171,11 +168,11 @@ LocateCapabilityRegBlock (
// Certain PCI device may incorrectly have capability pointing to itself,
// break to avoid dead loop.
//
if (CapabilityPtr == (UINT8) (CapabilityEntry >> 8)) {
if (CapabilityPtr == (UINT8)(CapabilityEntry >> 8)) {
break;
}
CapabilityPtr = (UINT8) (CapabilityEntry >> 8);
CapabilityPtr = (UINT8)(CapabilityEntry >> 8);
}
return EFI_NOT_FOUND;
@@ -196,16 +193,16 @@ LocateCapabilityRegBlock (
**/
EFI_STATUS
LocatePciExpressCapabilityRegBlock (
IN PCI_IO_DEVICE *PciIoDevice,
IN UINT16 CapId,
IN OUT UINT32 *Offset,
OUT UINT32 *NextRegBlock OPTIONAL
IN PCI_IO_DEVICE *PciIoDevice,
IN UINT16 CapId,
IN OUT UINT32 *Offset,
OUT UINT32 *NextRegBlock OPTIONAL
)
{
EFI_STATUS Status;
UINT32 CapabilityPtr;
UINT32 CapabilityEntry;
UINT16 CapabilityID;
EFI_STATUS Status;
UINT32 CapabilityPtr;
UINT32 CapabilityEntry;
UINT16 CapabilityID;
//
// To check the capability of this device supports
@@ -225,13 +222,13 @@ LocatePciExpressCapabilityRegBlock (
// Mask it to DWORD alignment per PCI spec
//
CapabilityPtr &= 0xFFC;
Status = PciIoDevice->PciIo.Pci.Read (
&PciIoDevice->PciIo,
EfiPciIoWidthUint32,
CapabilityPtr,
1,
&CapabilityEntry
);
Status = PciIoDevice->PciIo.Pci.Read (
&PciIoDevice->PciIo,
EfiPciIoWidthUint32,
CapabilityPtr,
1,
&CapabilityEntry
);
if (EFI_ERROR (Status)) {
break;
}
@@ -249,7 +246,7 @@ LocatePciExpressCapabilityRegBlock (
break;
}
CapabilityID = (UINT16) CapabilityEntry;
CapabilityID = (UINT16)CapabilityEntry;
if (CapabilityID == CapId) {
*Offset = CapabilityPtr;

42
MdeModulePkg/Bus/Pci/PciBusDxe/PciCommand.h
View File

@@ -6,7 +6,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _EFI_PCI_COMMAND_H_
#define _EFI_PCI_COMMAND_H_
@@ -16,7 +15,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
// They should be cleared at the beginning. The other registers
// are owned by chipset, we should not touch them.
//
#define EFI_PCI_COMMAND_BITS_OWNED ( \
#define EFI_PCI_COMMAND_BITS_OWNED ( \
EFI_PCI_COMMAND_IO_SPACE | \
EFI_PCI_COMMAND_MEMORY_SPACE | \
EFI_PCI_COMMAND_BUS_MASTER | \
@@ -31,7 +30,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
// They should be cleared at the beginning. The other registers
// are owned by chipset, we should not touch them.
//
#define EFI_PCI_BRIDGE_CONTROL_BITS_OWNED ( \
#define EFI_PCI_BRIDGE_CONTROL_BITS_OWNED ( \
EFI_PCI_BRIDGE_CONTROL_ISA | \
EFI_PCI_BRIDGE_CONTROL_VGA | \
EFI_PCI_BRIDGE_CONTROL_VGA_16 | \
@@ -44,13 +43,12 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
// They should be cleared at the beginning. The other registers
// are owned by chipset, we should not touch them.
//
#define EFI_PCCARD_BRIDGE_CONTROL_BITS_OWNED ( \
#define EFI_PCCARD_BRIDGE_CONTROL_BITS_OWNED ( \
EFI_PCI_BRIDGE_CONTROL_ISA | \
EFI_PCI_BRIDGE_CONTROL_VGA | \
EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK \
)
#define EFI_GET_REGISTER 1
#define EFI_SET_REGISTER 2
#define EFI_ENABLE_REGISTER 3
@@ -70,11 +68,11 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
EFI_STATUS
PciOperateRegister (
IN PCI_IO_DEVICE *PciIoDevice,
IN UINT16 Command,
IN UINT8 Offset,
IN UINT8 Operation,
OUT UINT16 *PtrCommand
IN PCI_IO_DEVICE *PciIoDevice,
IN UINT16 Command,
IN UINT8 Offset,
IN UINT8 Operation,
OUT UINT16 *PtrCommand
);
/**
@@ -127,10 +125,10 @@ LocateCapabilityRegBlock (
**/
EFI_STATUS
LocatePciExpressCapabilityRegBlock (
IN PCI_IO_DEVICE *PciIoDevice,
IN UINT16 CapId,
IN OUT UINT32 *Offset,
OUT UINT32 *NextRegBlock OPTIONAL
IN PCI_IO_DEVICE *PciIoDevice,
IN UINT16 CapId,
IN OUT UINT32 *Offset,
OUT UINT32 *NextRegBlock OPTIONAL
);
/**
@@ -142,7 +140,7 @@ LocatePciExpressCapabilityRegBlock (
@return status of PciIo operation
**/
#define PCI_READ_COMMAND_REGISTER(a,b) \
#define PCI_READ_COMMAND_REGISTER(a, b) \
PciOperateRegister (a, 0, PCI_COMMAND_OFFSET, EFI_GET_REGISTER, b)
/**
@@ -154,7 +152,7 @@ LocatePciExpressCapabilityRegBlock (
@return status of PciIo operation
**/
#define PCI_SET_COMMAND_REGISTER(a,b) \
#define PCI_SET_COMMAND_REGISTER(a, b) \
PciOperateRegister (a, b, PCI_COMMAND_OFFSET, EFI_SET_REGISTER, NULL)
/**
@@ -166,7 +164,7 @@ LocatePciExpressCapabilityRegBlock (
@return status of PciIo operation
**/
#define PCI_ENABLE_COMMAND_REGISTER(a,b) \
#define PCI_ENABLE_COMMAND_REGISTER(a, b) \
PciOperateRegister (a, b, PCI_COMMAND_OFFSET, EFI_ENABLE_REGISTER, NULL)
/**
@@ -178,7 +176,7 @@ LocatePciExpressCapabilityRegBlock (
@return status of PciIo operation
**/
#define PCI_DISABLE_COMMAND_REGISTER(a,b) \
#define PCI_DISABLE_COMMAND_REGISTER(a, b) \
PciOperateRegister (a, b, PCI_COMMAND_OFFSET, EFI_DISABLE_REGISTER, NULL)
/**
@@ -190,7 +188,7 @@ LocatePciExpressCapabilityRegBlock (
@return status of PciIo operation
**/
#define PCI_READ_BRIDGE_CONTROL_REGISTER(a,b) \
#define PCI_READ_BRIDGE_CONTROL_REGISTER(a, b) \
PciOperateRegister (a, 0, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_GET_REGISTER, b)
/**
@@ -202,7 +200,7 @@ LocatePciExpressCapabilityRegBlock (
@return status of PciIo operation
**/
#define PCI_SET_BRIDGE_CONTROL_REGISTER(a,b) \
#define PCI_SET_BRIDGE_CONTROL_REGISTER(a, b) \
PciOperateRegister (a, b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_SET_REGISTER, NULL)
/**
@@ -214,7 +212,7 @@ LocatePciExpressCapabilityRegBlock (
@return status of PciIo operation
**/
#define PCI_ENABLE_BRIDGE_CONTROL_REGISTER(a,b) \
#define PCI_ENABLE_BRIDGE_CONTROL_REGISTER(a, b) \
PciOperateRegister (a, b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_ENABLE_REGISTER, NULL)
/**
@@ -226,7 +224,7 @@ LocatePciExpressCapabilityRegBlock (
@return status of PciIo operation
**/
#define PCI_DISABLE_BRIDGE_CONTROL_REGISTER(a,b) \
#define PCI_DISABLE_BRIDGE_CONTROL_REGISTER(a, b) \
PciOperateRegister (a, b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_DISABLE_REGISTER, NULL)
#endif

214
MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c
View File

@@ -35,7 +35,7 @@ InitializePciDevicePool (
**/
VOID
InsertRootBridge (
IN PCI_IO_DEVICE *RootBridge
IN PCI_IO_DEVICE *RootBridge
)
{
InsertTailList (&mPciDevicePool, &(RootBridge->Link));
@@ -51,8 +51,8 @@ InsertRootBridge (
**/
VOID
InsertPciDevice (
IN PCI_IO_DEVICE *Bridge,
IN PCI_IO_DEVICE *PciDeviceNode
IN PCI_IO_DEVICE *Bridge,
IN PCI_IO_DEVICE *PciDeviceNode
)
{
InsertTailList (&Bridge->ChildList, &(PciDeviceNode->Link));
@@ -67,7 +67,7 @@ InsertPciDevice (
**/
VOID
DestroyRootBridge (
IN PCI_IO_DEVICE *RootBridge
IN PCI_IO_DEVICE *RootBridge
)
{
DestroyPciDeviceTree (RootBridge);
@@ -85,7 +85,7 @@ DestroyRootBridge (
**/
VOID
FreePciDevice (
IN PCI_IO_DEVICE *PciIoDevice
IN PCI_IO_DEVICE *PciIoDevice
)
{
ASSERT (PciIoDevice != NULL);
@@ -116,14 +116,13 @@ FreePciDevice (
**/
VOID
DestroyPciDeviceTree (
IN PCI_IO_DEVICE *Bridge
IN PCI_IO_DEVICE *Bridge
)
{
LIST_ENTRY *CurrentLink;
PCI_IO_DEVICE *Temp;
LIST_ENTRY *CurrentLink;
PCI_IO_DEVICE *Temp;
while (!IsListEmpty (&Bridge->ChildList)) {
CurrentLink = Bridge->ChildList.ForwardLink;
//
@@ -156,12 +155,11 @@ DestroyPciDeviceTree (
**/
EFI_STATUS
DestroyRootBridgeByHandle (
IN EFI_HANDLE Controller
IN EFI_HANDLE Controller
)
{
LIST_ENTRY *CurrentLink;
PCI_IO_DEVICE *Temp;
LIST_ENTRY *CurrentLink;
PCI_IO_DEVICE *Temp;
CurrentLink = mPciDevicePool.ForwardLink;
@@ -169,7 +167,6 @@ DestroyRootBridgeByHandle (
Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
if (Temp->Handle == Controller) {
RemoveEntryList (CurrentLink);
DestroyPciDeviceTree (Temp);
@@ -202,17 +199,17 @@ DestroyRootBridgeByHandle (
**/
EFI_STATUS
RegisterPciDevice (
IN EFI_HANDLE Controller,
IN PCI_IO_DEVICE *PciIoDevice,
OUT EFI_HANDLE *Handle OPTIONAL
IN EFI_HANDLE Controller,
IN PCI_IO_DEVICE *PciIoDevice,
OUT EFI_HANDLE *Handle OPTIONAL
)
{
EFI_STATUS Status;
VOID *PlatformOpRomBuffer;
UINTN PlatformOpRomSize;
EFI_PCI_IO_PROTOCOL *PciIo;
UINT8 Data8;
BOOLEAN HasEfiImage;
EFI_STATUS Status;
VOID *PlatformOpRomBuffer;
UINTN PlatformOpRomSize;
EFI_PCI_IO_PROTOCOL *PciIo;
UINT8 Data8;
BOOLEAN HasEfiImage;
//
// Install the pciio protocol, device path protocol
@@ -240,7 +237,6 @@ RegisterPciDevice (
// Process OpRom
//
if (!PciIoDevice->AllOpRomProcessed) {
//
// Get the OpRom provided by platform
//
@@ -253,7 +249,7 @@ RegisterPciDevice (
);
if (!EFI_ERROR (Status)) {
PciIoDevice->EmbeddedRom = FALSE;
PciIoDevice->RomSize = (UINT32) PlatformOpRomSize;
PciIoDevice->RomSize = (UINT32)PlatformOpRomSize;
PciIoDevice->PciIo.RomSize = PlatformOpRomSize;
PciIoDevice->PciIo.RomImage = PlatformOpRomBuffer;
//
@@ -279,7 +275,7 @@ RegisterPciDevice (
);
if (!EFI_ERROR (Status)) {
PciIoDevice->EmbeddedRom = FALSE;
PciIoDevice->RomSize = (UINT32) PlatformOpRomSize;
PciIoDevice->RomSize = (UINT32)PlatformOpRomSize;
PciIoDevice->PciIo.RomSize = PlatformOpRomSize;
PciIoDevice->PciIo.RomImage = PlatformOpRomBuffer;
//
@@ -324,9 +320,7 @@ RegisterPciDevice (
}
}
if (!PciIoDevice->AllOpRomProcessed) {
PciIoDevice->AllOpRomProcessed = TRUE;
//
@@ -374,7 +368,7 @@ RegisterPciDevice (
Status = gBS->OpenProtocol (
Controller,
&gEfiPciRootBridgeIoProtocolGuid,
(VOID **) &(PciIoDevice->PciRootBridgeIo),
(VOID **)&(PciIoDevice->PciRootBridgeIo),
gPciBusDriverBinding.DriverBindingHandle,
PciIoDevice->Handle,
EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER
@@ -405,15 +399,14 @@ RegisterPciDevice (
**/
VOID
RemoveAllPciDeviceOnBridge (
EFI_HANDLE RootBridgeHandle,
PCI_IO_DEVICE *Bridge
EFI_HANDLE RootBridgeHandle,
PCI_IO_DEVICE *Bridge
)
{
LIST_ENTRY *CurrentLink;
PCI_IO_DEVICE *Temp;
LIST_ENTRY *CurrentLink;
PCI_IO_DEVICE *Temp;
while (!IsListEmpty (&Bridge->ChildList)) {
CurrentLink = Bridge->ChildList.ForwardLink;
Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
@@ -453,22 +446,22 @@ RemoveAllPciDeviceOnBridge (
**/
EFI_STATUS
DeRegisterPciDevice (
IN EFI_HANDLE Controller,
IN EFI_HANDLE Handle
IN EFI_HANDLE Controller,
IN EFI_HANDLE Handle
)
{
EFI_PCI_IO_PROTOCOL *PciIo;
EFI_STATUS Status;
PCI_IO_DEVICE *PciIoDevice;
PCI_IO_DEVICE *Node;
LIST_ENTRY *CurrentLink;
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
EFI_PCI_IO_PROTOCOL *PciIo;
EFI_STATUS Status;
PCI_IO_DEVICE *PciIoDevice;
PCI_IO_DEVICE *Node;
LIST_ENTRY *CurrentLink;
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
Status = gBS->OpenProtocol (
Handle,
&gEfiPciIoProtocolGuid,
(VOID **) &PciIo,
(VOID **)&PciIo,
gPciBusDriverBinding.DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_GET_PROTOCOL
@@ -488,12 +481,11 @@ DeRegisterPciDevice (
//
if (!IsListEmpty (&PciIoDevice->ChildList)) {
CurrentLink = PciIoDevice->ChildList.ForwardLink;
while (CurrentLink != NULL && CurrentLink != &PciIoDevice->ChildList) {
Node = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
Status = DeRegisterPciDevice (Controller, Node->Handle);
Node = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
Status = DeRegisterPciDevice (Controller, Node->Handle);
if (EFI_ERROR (Status)) {
return Status;
@@ -559,22 +551,22 @@ DeRegisterPciDevice (
NULL
);
}
//
// Restore Status
//
Status = EFI_SUCCESS;
}
if (EFI_ERROR (Status)) {
gBS->OpenProtocol (
Controller,
&gEfiPciRootBridgeIoProtocolGuid,
(VOID **) &PciRootBridgeIo,
gPciBusDriverBinding.DriverBindingHandle,
Handle,
EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER
);
Controller,
&gEfiPciRootBridgeIoProtocolGuid,
(VOID **)&PciRootBridgeIo,
gPciBusDriverBinding.DriverBindingHandle,
Handle,
EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER
);
return Status;
}
@@ -586,7 +578,6 @@ DeRegisterPciDevice (
PciIoDevice->Registered = FALSE;
PciIoDevice->Handle = NULL;
} else {
//
// Handle may be closed before
//
@@ -613,11 +604,11 @@ DeRegisterPciDevice (
**/
EFI_STATUS
StartPciDevicesOnBridge (
IN EFI_HANDLE Controller,
IN PCI_IO_DEVICE *RootBridge,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath,
IN OUT UINT8 *NumberOfChildren,
IN OUT EFI_HANDLE *ChildHandleBuffer
IN EFI_HANDLE Controller,
IN PCI_IO_DEVICE *RootBridge,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath,
IN OUT UINT8 *NumberOfChildren,
IN OUT EFI_HANDLE *ChildHandleBuffer
)
{
@@ -632,14 +623,13 @@ StartPciDevicesOnBridge (
CurrentLink = RootBridge->ChildList.ForwardLink;
while (CurrentLink != NULL && CurrentLink != &RootBridge->ChildList) {
PciIoDevice = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
if (RemainingDevicePath != NULL) {
Node.DevPath = RemainingDevicePath;
if (Node.Pci->Device != PciIoDevice->DeviceNumber ||
Node.Pci->Function != PciIoDevice->FunctionNumber) {
if ((Node.Pci->Device != PciIoDevice->DeviceNumber) ||
(Node.Pci->Function != PciIoDevice->FunctionNumber))
{
CurrentLink = CurrentLink->ForwardLink;
continue;
}
@@ -661,10 +651,9 @@ StartPciDevicesOnBridge (
PciIoDevice,
NULL
);
}
if (NumberOfChildren != NULL && ChildHandleBuffer != NULL && PciIoDevice->Registered) {
if ((NumberOfChildren != NULL) && (ChildHandleBuffer != NULL) && PciIoDevice->Registered) {
ChildHandleBuffer[*NumberOfChildren] = PciIoDevice->Handle;
(*NumberOfChildren)++;
}
@@ -705,15 +694,12 @@ StartPciDevicesOnBridge (
return Status;
} else {
//
// Currently, the PCI bus driver only support PCI-PCI bridge
//
return EFI_UNSUPPORTED;
}
} else {
//
// If remaining device path is NULL,
// try to enable all the pci devices under this bridge
@@ -724,10 +710,9 @@ StartPciDevicesOnBridge (
PciIoDevice,
NULL
);
}
if (NumberOfChildren != NULL && ChildHandleBuffer != NULL && PciIoDevice->Registered) {
if ((NumberOfChildren != NULL) && (ChildHandleBuffer != NULL) && PciIoDevice->Registered) {
ChildHandleBuffer[*NumberOfChildren] = PciIoDevice->Handle;
(*NumberOfChildren)++;
}
@@ -754,7 +739,6 @@ StartPciDevicesOnBridge (
Supports,
NULL
);
}
CurrentLink = CurrentLink->ForwardLink;
@@ -780,12 +764,12 @@ StartPciDevicesOnBridge (
**/
EFI_STATUS
StartPciDevices (
IN EFI_HANDLE Controller
IN EFI_HANDLE Controller
)
{
PCI_IO_DEVICE *RootBridge;
EFI_HANDLE ThisHostBridge;
LIST_ENTRY *CurrentLink;
PCI_IO_DEVICE *RootBridge;
EFI_HANDLE ThisHostBridge;
LIST_ENTRY *CurrentLink;
RootBridge = GetRootBridgeByHandle (Controller);
ASSERT (RootBridge != NULL);
@@ -794,19 +778,18 @@ StartPciDevices (
CurrentLink = mPciDevicePool.ForwardLink;
while (CurrentLink != NULL && CurrentLink != &mPciDevicePool) {
RootBridge = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
//
// Locate the right root bridge to start
//
if (RootBridge->PciRootBridgeIo->ParentHandle == ThisHostBridge) {
StartPciDevicesOnBridge (
RootBridge->Handle,
RootBridge,
NULL,
NULL,
NULL
);
RootBridge->Handle,
RootBridge,
NULL,
NULL,
NULL
);
}
CurrentLink = CurrentLink->ForwardLink;
@@ -826,27 +809,27 @@ StartPciDevices (
**/
PCI_IO_DEVICE *
CreateRootBridge (
IN EFI_HANDLE RootBridgeHandle
IN EFI_HANDLE RootBridgeHandle
)
{
EFI_STATUS Status;
PCI_IO_DEVICE *Dev;
EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath;
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
EFI_STATUS Status;
PCI_IO_DEVICE *Dev;
EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath;
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
Dev = AllocateZeroPool (sizeof (PCI_IO_DEVICE));
if (Dev == NULL) {
return NULL;
}
Dev->Signature = PCI_IO_DEVICE_SIGNATURE;
Dev->Handle = RootBridgeHandle;
Dev->Signature = PCI_IO_DEVICE_SIGNATURE;
Dev->Handle = RootBridgeHandle;
InitializeListHead (&Dev->ChildList);
Status = gBS->OpenProtocol (
RootBridgeHandle,
&gEfiDevicePathProtocolGuid,
(VOID **) &ParentDevicePath,
(VOID **)&ParentDevicePath,
gPciBusDriverBinding.DriverBindingHandle,
RootBridgeHandle,
EFI_OPEN_PROTOCOL_GET_PROTOCOL
@@ -868,7 +851,7 @@ CreateRootBridge (
Status = gBS->OpenProtocol (
RootBridgeHandle,
&gEfiPciRootBridgeIoProtocolGuid,
(VOID **) &PciRootBridgeIo,
(VOID **)&PciRootBridgeIo,
gPciBusDriverBinding.DriverBindingHandle,
RootBridgeHandle,
EFI_OPEN_PROTOCOL_GET_PROTOCOL
@@ -909,16 +892,15 @@ CreateRootBridge (
**/
PCI_IO_DEVICE *
GetRootBridgeByHandle (
EFI_HANDLE RootBridgeHandle
EFI_HANDLE RootBridgeHandle
)
{
PCI_IO_DEVICE *RootBridgeDev;
LIST_ENTRY *CurrentLink;
PCI_IO_DEVICE *RootBridgeDev;
LIST_ENTRY *CurrentLink;
CurrentLink = mPciDevicePool.ForwardLink;
while (CurrentLink != NULL && CurrentLink != &mPciDevicePool) {
RootBridgeDev = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
if (RootBridgeDev->Handle == RootBridgeHandle) {
return RootBridgeDev;
@@ -942,18 +924,16 @@ GetRootBridgeByHandle (
**/
BOOLEAN
PciDeviceExisted (
IN PCI_IO_DEVICE *Bridge,
IN PCI_IO_DEVICE *PciIoDevice
IN PCI_IO_DEVICE *Bridge,
IN PCI_IO_DEVICE *PciIoDevice
)
{
PCI_IO_DEVICE *Temp;
LIST_ENTRY *CurrentLink;
PCI_IO_DEVICE *Temp;
LIST_ENTRY *CurrentLink;
CurrentLink = Bridge->ChildList.ForwardLink;
while (CurrentLink != NULL && CurrentLink != &Bridge->ChildList) {
Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
if (Temp == PciIoDevice) {
@@ -982,20 +962,18 @@ PciDeviceExisted (
**/
PCI_IO_DEVICE *
LocateVgaDeviceOnHostBridge (
IN EFI_HANDLE HostBridgeHandle
IN EFI_HANDLE HostBridgeHandle
)
{
LIST_ENTRY *CurrentLink;
PCI_IO_DEVICE *PciIoDevice;
LIST_ENTRY *CurrentLink;
PCI_IO_DEVICE *PciIoDevice;
CurrentLink = mPciDevicePool.ForwardLink;
while (CurrentLink != NULL && CurrentLink != &mPciDevicePool) {
PciIoDevice = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
if (PciIoDevice->PciRootBridgeIo->ParentHandle== HostBridgeHandle) {
if (PciIoDevice->PciRootBridgeIo->ParentHandle == HostBridgeHandle) {
PciIoDevice = LocateVgaDevice (PciIoDevice);
if (PciIoDevice != NULL) {
@@ -1019,28 +997,27 @@ LocateVgaDeviceOnHostBridge (
**/
PCI_IO_DEVICE *
LocateVgaDevice (
IN PCI_IO_DEVICE *Bridge
IN PCI_IO_DEVICE *Bridge
)
{
LIST_ENTRY *CurrentLink;
PCI_IO_DEVICE *PciIoDevice;
LIST_ENTRY *CurrentLink;
PCI_IO_DEVICE *PciIoDevice;
CurrentLink = Bridge->ChildList.ForwardLink;
while (CurrentLink != NULL && CurrentLink != &Bridge->ChildList) {
PciIoDevice = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
if (IS_PCI_VGA(&PciIoDevice->Pci) &&
(PciIoDevice->Attributes &
(EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY |
EFI_PCI_IO_ATTRIBUTE_VGA_IO |
EFI_PCI_IO_ATTRIBUTE_VGA_IO_16)) != 0) {
if (IS_PCI_VGA (&PciIoDevice->Pci) &&
((PciIoDevice->Attributes &
(EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY |
EFI_PCI_IO_ATTRIBUTE_VGA_IO |
EFI_PCI_IO_ATTRIBUTE_VGA_IO_16)) != 0))
{
return PciIoDevice;
}
if (IS_PCI_BRIDGE (&PciIoDevice->Pci)) {
PciIoDevice = LocateVgaDevice (PciIoDevice);
if (PciIoDevice != NULL) {
@@ -1053,4 +1030,3 @@ LocateVgaDevice (
return NULL;
}

54
MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.h
View File

@@ -26,7 +26,7 @@ InitializePciDevicePool (
**/
VOID
InsertRootBridge (
IN PCI_IO_DEVICE *RootBridge
IN PCI_IO_DEVICE *RootBridge
);
/**
@@ -39,8 +39,8 @@ InsertRootBridge (
**/
VOID
InsertPciDevice (
IN PCI_IO_DEVICE *Bridge,
IN PCI_IO_DEVICE *PciDeviceNode
IN PCI_IO_DEVICE *Bridge,
IN PCI_IO_DEVICE *PciDeviceNode
);
/**
@@ -51,7 +51,7 @@ InsertPciDevice (
**/
VOID
DestroyRootBridge (
IN PCI_IO_DEVICE *RootBridge
IN PCI_IO_DEVICE *RootBridge
);
/**
@@ -63,7 +63,7 @@ DestroyRootBridge (
**/
VOID
DestroyPciDeviceTree (
IN PCI_IO_DEVICE *Bridge
IN PCI_IO_DEVICE *Bridge
);
/**
@@ -81,7 +81,7 @@ DestroyPciDeviceTree (
**/
EFI_STATUS
DestroyRootBridgeByHandle (
IN EFI_HANDLE Controller
IN EFI_HANDLE Controller
);
/**
@@ -101,9 +101,9 @@ DestroyRootBridgeByHandle (
**/
EFI_STATUS
RegisterPciDevice (
IN EFI_HANDLE Controller,
IN PCI_IO_DEVICE *PciIoDevice,
OUT EFI_HANDLE *Handle OPTIONAL
IN EFI_HANDLE Controller,
IN PCI_IO_DEVICE *PciIoDevice,
OUT EFI_HANDLE *Handle OPTIONAL
);
/**
@@ -116,8 +116,8 @@ RegisterPciDevice (
**/
VOID
RemoveAllPciDeviceOnBridge (
EFI_HANDLE RootBridgeHandle,
PCI_IO_DEVICE *Bridge
EFI_HANDLE RootBridgeHandle,
PCI_IO_DEVICE *Bridge
);
/**
@@ -135,8 +135,8 @@ RemoveAllPciDeviceOnBridge (
**/
EFI_STATUS
DeRegisterPciDevice (
IN EFI_HANDLE Controller,
IN EFI_HANDLE Handle
IN EFI_HANDLE Controller,
IN EFI_HANDLE Handle
);
/**
@@ -156,11 +156,11 @@ DeRegisterPciDevice (
**/
EFI_STATUS
StartPciDevicesOnBridge (
IN EFI_HANDLE Controller,
IN PCI_IO_DEVICE *RootBridge,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath,
IN OUT UINT8 *NumberOfChildren,
IN OUT EFI_HANDLE *ChildHandleBuffer
IN EFI_HANDLE Controller,
IN PCI_IO_DEVICE *RootBridge,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath,
IN OUT UINT8 *NumberOfChildren,
IN OUT EFI_HANDLE *ChildHandleBuffer
);
/**
@@ -175,7 +175,7 @@ StartPciDevicesOnBridge (
**/
EFI_STATUS
StartPciDevices (
IN EFI_HANDLE Controller
IN EFI_HANDLE Controller
);
/**
@@ -189,7 +189,7 @@ StartPciDevices (
**/
PCI_IO_DEVICE *
CreateRootBridge (
IN EFI_HANDLE RootBridgeHandle
IN EFI_HANDLE RootBridgeHandle
);
/**
@@ -203,10 +203,9 @@ CreateRootBridge (
**/
PCI_IO_DEVICE *
GetRootBridgeByHandle (
EFI_HANDLE RootBridgeHandle
EFI_HANDLE RootBridgeHandle
);
/**
Judge whether Pci device existed.
@@ -219,8 +218,8 @@ GetRootBridgeByHandle (
**/
BOOLEAN
PciDeviceExisted (
IN PCI_IO_DEVICE *Bridge,
IN PCI_IO_DEVICE *PciIoDevice
IN PCI_IO_DEVICE *Bridge,
IN PCI_IO_DEVICE *PciIoDevice
);
/**
@@ -233,7 +232,7 @@ PciDeviceExisted (
**/
PCI_IO_DEVICE *
LocateVgaDeviceOnHostBridge (
IN EFI_HANDLE HostBridgeHandle
IN EFI_HANDLE HostBridgeHandle
);
/**
@@ -246,10 +245,9 @@ LocateVgaDeviceOnHostBridge (
**/
PCI_IO_DEVICE *
LocateVgaDevice (
IN PCI_IO_DEVICE *Bridge
IN PCI_IO_DEVICE *Bridge
);
/**
Destroy a pci device node.
@@ -260,7 +258,7 @@ LocateVgaDevice (
**/
VOID
FreePciDevice (
IN PCI_IO_DEVICE *PciIoDevice
IN PCI_IO_DEVICE *PciIoDevice
);
#endif

49
MdeModulePkg/Bus/Pci/PciBusDxe/PciDriverOverride.c
View File

@@ -16,7 +16,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
VOID
InitializePciDriverOverrideInstance (
IN OUT PCI_IO_DEVICE *PciIoDevice
IN OUT PCI_IO_DEVICE *PciIoDevice
)
{
PciIoDevice->PciDriverOverride.GetDriver = GetDriver;
@@ -31,16 +31,16 @@ InitializePciDriverOverrideInstance (
**/
EFI_HANDLE
LocateImageHandle (
IN EFI_DEVICE_PATH_PROTOCOL *ImagePath
IN EFI_DEVICE_PATH_PROTOCOL *ImagePath
)
{
EFI_STATUS Status;
EFI_HANDLE *Handles;
UINTN Index;
UINTN HandleNum;
EFI_DEVICE_PATH_PROTOCOL *DevicePath;
UINTN ImagePathSize;
EFI_HANDLE ImageHandle;
EFI_STATUS Status;
EFI_HANDLE *Handles;
UINTN Index;
UINTN HandleNum;
EFI_DEVICE_PATH_PROTOCOL *DevicePath;
UINTN ImagePathSize;
EFI_HANDLE ImageHandle;
Status = gBS->LocateHandleBuffer (
ByProtocol,
@@ -57,13 +57,15 @@ LocateImageHandle (
ImagePathSize = GetDevicePathSize (ImagePath);
for (Index = 0; Index < HandleNum; Index++) {
Status = gBS->HandleProtocol (Handles[Index], &gEfiLoadedImageDevicePathProtocolGuid, (VOID **) &DevicePath);
Status = gBS->HandleProtocol (Handles[Index], &gEfiLoadedImageDevicePathProtocolGuid, (VOID **)&DevicePath);
if (EFI_ERROR (Status)) {
continue;
}
if ((ImagePathSize == GetDevicePathSize (DevicePath)) &&
(CompareMem (ImagePath, DevicePath, ImagePathSize) == 0)
) {
)
{
ImageHandle = Handles[Index];
break;
}
@@ -92,8 +94,8 @@ LocateImageHandle (
EFI_STATUS
EFIAPI
GetDriver (
IN EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL *This,
IN OUT EFI_HANDLE *DriverImageHandle
IN EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL *This,
IN OUT EFI_HANDLE *DriverImageHandle
)
{
PCI_IO_DEVICE *PciIoDevice;
@@ -103,12 +105,12 @@ GetDriver (
Override = NULL;
PciIoDevice = PCI_IO_DEVICE_FROM_PCI_DRIVER_OVERRIDE_THIS (This);
ReturnNext = (BOOLEAN) (*DriverImageHandle == NULL);
ReturnNext = (BOOLEAN)(*DriverImageHandle == NULL);
for ( Link = GetFirstNode (&PciIoDevice->OptionRomDriverList)
; !IsNull (&PciIoDevice->OptionRomDriverList, Link)
; Link = GetNextNode (&PciIoDevice->OptionRomDriverList, Link)
) {
; !IsNull (&PciIoDevice->OptionRomDriverList, Link)
; Link = GetNextNode (&PciIoDevice->OptionRomDriverList, Link)
)
{
Override = DRIVER_OVERRIDE_FROM_LINK (Link);
if (ReturnNext) {
@@ -159,12 +161,12 @@ GetDriver (
**/
EFI_STATUS
AddDriver (
IN PCI_IO_DEVICE *PciIoDevice,
IN EFI_HANDLE DriverImageHandle,
IN EFI_DEVICE_PATH_PROTOCOL *DriverImagePath
IN PCI_IO_DEVICE *PciIoDevice,
IN EFI_HANDLE DriverImageHandle,
IN EFI_DEVICE_PATH_PROTOCOL *DriverImagePath
)
{
PCI_DRIVER_OVERRIDE_LIST *Node;
PCI_DRIVER_OVERRIDE_LIST *Node;
//
// Caller should pass in either Image Handle or Image Path, but not both.
@@ -182,7 +184,6 @@ AddDriver (
InsertTailList (&PciIoDevice->OptionRomDriverList, &Node->Link);
PciIoDevice->BusOverride = TRUE;
PciIoDevice->BusOverride = TRUE;
return EFI_SUCCESS;
}

25
MdeModulePkg/Bus/Pci/PciBusDxe/PciDriverOverride.h
View File

@@ -6,23 +6,21 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _EFI_PCI_DRIVER_OVERRRIDE_H_
#define _EFI_PCI_DRIVER_OVERRRIDE_H_
#define DRIVER_OVERRIDE_SIGNATURE SIGNATURE_32 ('d', 'r', 'o', 'v')
#define DRIVER_OVERRIDE_SIGNATURE SIGNATURE_32 ('d', 'r', 'o', 'v')
//
// PCI driver override driver image list
//
typedef struct {
UINT32 Signature;
LIST_ENTRY Link;
EFI_HANDLE DriverImageHandle;
EFI_DEVICE_PATH_PROTOCOL *DriverImagePath;
UINT32 Signature;
LIST_ENTRY Link;
EFI_HANDLE DriverImageHandle;
EFI_DEVICE_PATH_PROTOCOL *DriverImagePath;
} PCI_DRIVER_OVERRIDE_LIST;
#define DRIVER_OVERRIDE_FROM_LINK(a) \
CR (a, PCI_DRIVER_OVERRIDE_LIST, Link, DRIVER_OVERRIDE_SIGNATURE)
@@ -34,7 +32,7 @@ typedef struct {
**/
VOID
InitializePciDriverOverrideInstance (
IN OUT PCI_IO_DEVICE *PciIoDevice
IN OUT PCI_IO_DEVICE *PciIoDevice
);
/**
@@ -51,12 +49,11 @@ InitializePciDriverOverrideInstance (
**/
EFI_STATUS
AddDriver (
IN PCI_IO_DEVICE *PciIoDevice,
IN EFI_HANDLE DriverImageHandle,
IN EFI_DEVICE_PATH_PROTOCOL *DriverImagePath
IN PCI_IO_DEVICE *PciIoDevice,
IN EFI_HANDLE DriverImageHandle,
IN EFI_DEVICE_PATH_PROTOCOL *DriverImagePath
);
/**
Uses a bus specific algorithm to retrieve a driver image handle for a controller.
@@ -76,8 +73,8 @@ AddDriver (
EFI_STATUS
EFIAPI
GetDriver (
IN EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL *This,
IN OUT EFI_HANDLE *DriverImageHandle
IN EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL *This,
IN OUT EFI_HANDLE *DriverImageHandle
);
#endif

726
MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.c
View File

File diff suppressed because it is too large Load Diff

100
MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.h
View File

@@ -24,8 +24,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
EFI_STATUS
PciEnumerator (
IN EFI_HANDLE Controller,
IN EFI_HANDLE HostBridgeHandle
IN EFI_HANDLE Controller,
IN EFI_HANDLE HostBridgeHandle
);
/**
@@ -55,9 +55,9 @@ PciRootBridgeEnumerator (
**/
VOID
ProcessOptionRom (
IN PCI_IO_DEVICE *Bridge,
IN UINT64 RomBase,
IN UINT64 MaxLength
IN PCI_IO_DEVICE *Bridge,
IN UINT64 RomBase,
IN UINT64 MaxLength
);
/**
@@ -73,9 +73,9 @@ ProcessOptionRom (
**/
EFI_STATUS
PciAssignBusNumber (
IN PCI_IO_DEVICE *Bridge,
IN UINT8 StartBusNumber,
OUT UINT8 *SubBusNumber
IN PCI_IO_DEVICE *Bridge,
IN UINT8 StartBusNumber,
OUT UINT8 *SubBusNumber
);
/**
@@ -91,8 +91,8 @@ PciAssignBusNumber (
**/
EFI_STATUS
DetermineRootBridgeAttributes (
IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc,
IN PCI_IO_DEVICE *RootBridgeDev
IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc,
IN PCI_IO_DEVICE *RootBridgeDev
);
/**
@@ -105,7 +105,7 @@ DetermineRootBridgeAttributes (
**/
UINT32
GetMaxOptionRomSize (
IN PCI_IO_DEVICE *Bridge
IN PCI_IO_DEVICE *Bridge
);
/**
@@ -120,7 +120,7 @@ GetMaxOptionRomSize (
**/
EFI_STATUS
PciHostBridgeDeviceAttribute (
IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc
IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc
);
/**
@@ -155,7 +155,7 @@ GetResourceAllocationStatus (
**/
EFI_STATUS
RejectPciDevice (
IN PCI_IO_DEVICE *PciDevice
IN PCI_IO_DEVICE *PciDevice
);
/**
@@ -169,7 +169,7 @@ RejectPciDevice (
**/
BOOLEAN
IsRejectiveDevice (
IN PCI_RESOURCE_NODE *PciResNode
IN PCI_RESOURCE_NODE *PciResNode
);
/**
@@ -183,8 +183,8 @@ IsRejectiveDevice (
**/
PCI_RESOURCE_NODE *
GetLargerConsumerDevice (
IN PCI_RESOURCE_NODE *PciResNode1,
IN PCI_RESOURCE_NODE *PciResNode2
IN PCI_RESOURCE_NODE *PciResNode1,
IN PCI_RESOURCE_NODE *PciResNode2
);
/**
@@ -197,7 +197,7 @@ GetLargerConsumerDevice (
**/
PCI_RESOURCE_NODE *
GetMaxResourceConsumerDevice (
IN PCI_RESOURCE_NODE *ResPool
IN PCI_RESOURCE_NODE *ResPool
);
/**
@@ -220,16 +220,16 @@ GetMaxResourceConsumerDevice (
**/
EFI_STATUS
PciHostBridgeAdjustAllocation (
IN PCI_RESOURCE_NODE *IoPool,
IN PCI_RESOURCE_NODE *Mem32Pool,
IN PCI_RESOURCE_NODE *PMem32Pool,
IN PCI_RESOURCE_NODE *Mem64Pool,
IN PCI_RESOURCE_NODE *PMem64Pool,
IN UINT64 IoResStatus,
IN UINT64 Mem32ResStatus,
IN UINT64 PMem32ResStatus,
IN UINT64 Mem64ResStatus,
IN UINT64 PMem64ResStatus
IN PCI_RESOURCE_NODE *IoPool,
IN PCI_RESOURCE_NODE *Mem32Pool,
IN PCI_RESOURCE_NODE *PMem32Pool,
IN PCI_RESOURCE_NODE *Mem64Pool,
IN PCI_RESOURCE_NODE *PMem64Pool,
IN UINT64 IoResStatus,
IN UINT64 Mem32ResStatus,
IN UINT64 PMem32ResStatus,
IN UINT64 Mem64ResStatus,
IN UINT64 PMem64ResStatus
);
/**
@@ -292,7 +292,7 @@ GetResourceBase (
**/
EFI_STATUS
PciBridgeEnumerator (
IN PCI_IO_DEVICE *BridgeDev
IN PCI_IO_DEVICE *BridgeDev
);
/**
@@ -325,12 +325,12 @@ PciBridgeResourceAllocator (
**/
EFI_STATUS
GetResourceBaseFromBridge (
IN PCI_IO_DEVICE *Bridge,
OUT UINT64 *IoBase,
OUT UINT64 *Mem32Base,
OUT UINT64 *PMem32Base,
OUT UINT64 *Mem64Base,
OUT UINT64 *PMem64Base
IN PCI_IO_DEVICE *Bridge,
OUT UINT64 *IoBase,
OUT UINT64 *Mem32Base,
OUT UINT64 *PMem32Base,
OUT UINT64 *Mem64Base,
OUT UINT64 *PMem64Base
);
/**
@@ -343,7 +343,7 @@ GetResourceBaseFromBridge (
**/
EFI_STATUS
PciHostBridgeP2CProcess (
IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc
IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc
);
/**
@@ -412,8 +412,8 @@ PciHostBridgeP2CProcess (
**/
EFI_STATUS
NotifyPhase (
IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc,
EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase
IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc,
EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase
);
/**
@@ -442,11 +442,11 @@ NotifyPhase (
**/
EFI_STATUS
PreprocessController (
IN PCI_IO_DEVICE *Bridge,
IN UINT8 Bus,
IN UINT8 Device,
IN UINT8 Func,
IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase
IN PCI_IO_DEVICE *Bridge,
IN UINT8 Bus,
IN UINT8 Device,
IN UINT8 Func,
IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase
);
/**
@@ -475,12 +475,12 @@ PreprocessController (
EFI_STATUS
EFIAPI
PciHotPlugRequestNotify (
IN EFI_PCI_HOTPLUG_REQUEST_PROTOCOL * This,
IN EFI_PCI_HOTPLUG_OPERATION Operation,
IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL * RemainingDevicePath OPTIONAL,
IN OUT UINT8 *NumberOfChildren,
IN OUT EFI_HANDLE * ChildHandleBuffer
IN EFI_PCI_HOTPLUG_REQUEST_PROTOCOL *This,
IN EFI_PCI_HOTPLUG_OPERATION Operation,
IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath OPTIONAL,
IN OUT UINT8 *NumberOfChildren,
IN OUT EFI_HANDLE *ChildHandleBuffer
);
/**
@@ -494,7 +494,7 @@ PciHotPlugRequestNotify (
**/
BOOLEAN
SearchHostBridgeHandle (
IN EFI_HANDLE RootBridgeHandle
IN EFI_HANDLE RootBridgeHandle
);
/**
@@ -509,7 +509,7 @@ SearchHostBridgeHandle (
**/
EFI_STATUS
AddHostBridgeEnumerator (
IN EFI_HANDLE HostBridgeHandle
IN EFI_HANDLE HostBridgeHandle
);
#endif

1298
MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
View File

File diff suppressed because it is too large Load Diff

138
MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.h
View File

@@ -24,11 +24,11 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
EFI_STATUS
PciDevicePresent (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,
OUT PCI_TYPE00 *Pci,
IN UINT8 Bus,
IN UINT8 Device,
IN UINT8 Func
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,
OUT PCI_TYPE00 *Pci,
IN UINT8 Bus,
IN UINT8 Device,
IN UINT8 Func
);
/**
@@ -46,8 +46,8 @@ PciDevicePresent (
**/
EFI_STATUS
PciPciDeviceInfoCollector (
IN PCI_IO_DEVICE *Bridge,
IN UINT8 StartBusNumber
IN PCI_IO_DEVICE *Bridge,
IN UINT8 StartBusNumber
);
/**
@@ -66,12 +66,12 @@ PciPciDeviceInfoCollector (
**/
EFI_STATUS
PciSearchDevice (
IN PCI_IO_DEVICE *Bridge,
IN PCI_TYPE00 *Pci,
IN UINT8 Bus,
IN UINT8 Device,
IN UINT8 Func,
OUT PCI_IO_DEVICE **PciDevice
IN PCI_IO_DEVICE *Bridge,
IN PCI_TYPE00 *Pci,
IN UINT8 Bus,
IN UINT8 Device,
IN UINT8 Func,
OUT PCI_IO_DEVICE **PciDevice
);
/**
@@ -88,11 +88,11 @@ PciSearchDevice (
**/
PCI_IO_DEVICE *
GatherDeviceInfo (
IN PCI_IO_DEVICE *Bridge,
IN PCI_TYPE00 *Pci,
IN UINT8 Bus,
IN UINT8 Device,
IN UINT8 Func
IN PCI_IO_DEVICE *Bridge,
IN PCI_TYPE00 *Pci,
IN UINT8 Bus,
IN UINT8 Device,
IN UINT8 Func
);
/**
@@ -109,11 +109,11 @@ GatherDeviceInfo (
**/
PCI_IO_DEVICE *
GatherPpbInfo (
IN PCI_IO_DEVICE *Bridge,
IN PCI_TYPE00 *Pci,
IN UINT8 Bus,
IN UINT8 Device,
IN UINT8 Func
IN PCI_IO_DEVICE *Bridge,
IN PCI_TYPE00 *Pci,
IN UINT8 Bus,
IN UINT8 Device,
IN UINT8 Func
);
/**
@@ -130,11 +130,11 @@ GatherPpbInfo (
**/
PCI_IO_DEVICE *
GatherP2CInfo (
IN PCI_IO_DEVICE *Bridge,
IN PCI_TYPE00 *Pci,
IN UINT8 Bus,
IN UINT8 Device,
IN UINT8 Func
IN PCI_IO_DEVICE *Bridge,
IN PCI_TYPE00 *Pci,
IN UINT8 Bus,
IN UINT8 Device,
IN UINT8 Func
);
/**
@@ -148,8 +148,8 @@ GatherP2CInfo (
**/
EFI_DEVICE_PATH_PROTOCOL *
CreatePciDevicePath (
IN EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath,
IN PCI_IO_DEVICE *PciIoDevice
IN EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath,
IN PCI_IO_DEVICE *PciIoDevice
);
/**
@@ -166,10 +166,10 @@ CreatePciDevicePath (
**/
EFI_STATUS
VfBarExisted (
IN PCI_IO_DEVICE *PciIoDevice,
IN UINTN Offset,
OUT UINT32 *BarLengthValue,
OUT UINT32 *OriginalBarValue
IN PCI_IO_DEVICE *PciIoDevice,
IN UINTN Offset,
OUT UINT32 *BarLengthValue,
OUT UINT32 *OriginalBarValue
);
/**
@@ -186,10 +186,10 @@ VfBarExisted (
**/
EFI_STATUS
BarExisted (
IN PCI_IO_DEVICE *PciIoDevice,
IN UINTN Offset,
OUT UINT32 *BarLengthValue,
OUT UINT32 *OriginalBarValue
IN PCI_IO_DEVICE *PciIoDevice,
IN UINTN Offset,
OUT UINT32 *BarLengthValue,
OUT UINT32 *OriginalBarValue
);
/**
@@ -206,11 +206,11 @@ BarExisted (
**/
VOID
PciTestSupportedAttribute (
IN PCI_IO_DEVICE *PciIoDevice,
IN OUT UINT16 *Command,
IN OUT UINT16 *BridgeControl,
OUT UINT16 *OldCommand,
OUT UINT16 *OldBridgeControl
IN PCI_IO_DEVICE *PciIoDevice,
IN OUT UINT16 *Command,
IN OUT UINT16 *BridgeControl,
OUT UINT16 *OldCommand,
OUT UINT16 *OldBridgeControl
);
/**
@@ -224,10 +224,10 @@ PciTestSupportedAttribute (
**/
VOID
PciSetDeviceAttribute (
IN PCI_IO_DEVICE *PciIoDevice,
IN UINT16 Command,
IN UINT16 BridgeControl,
IN UINTN Option
IN PCI_IO_DEVICE *PciIoDevice,
IN UINT16 Command,
IN UINT16 BridgeControl,
IN UINTN Option
);
/**
@@ -242,8 +242,8 @@ PciSetDeviceAttribute (
**/
EFI_STATUS
GetFastBackToBackSupport (
IN PCI_IO_DEVICE *PciIoDevice,
IN UINT8 StatusIndex
IN PCI_IO_DEVICE *PciIoDevice,
IN UINT8 StatusIndex
);
/**
@@ -254,7 +254,7 @@ GetFastBackToBackSupport (
**/
EFI_STATUS
DetermineDeviceAttribute (
IN PCI_IO_DEVICE *PciIoDevice
IN PCI_IO_DEVICE *PciIoDevice
);
/**
@@ -269,7 +269,7 @@ DetermineDeviceAttribute (
**/
EFI_STATUS
UpdatePciInfo (
IN OUT PCI_IO_DEVICE *PciIoDevice
IN OUT PCI_IO_DEVICE *PciIoDevice
);
/**
@@ -281,8 +281,8 @@ UpdatePciInfo (
**/
VOID
SetNewAlign (
IN OUT UINT64 *Alignment,
IN UINT64 NewAlignment
IN OUT UINT64 *Alignment,
IN UINT64 NewAlignment
);
/**
@@ -329,7 +329,7 @@ PciIovParseVfBar (
**/
VOID
InitializePciDevice (
IN PCI_IO_DEVICE *PciIoDevice
IN PCI_IO_DEVICE *PciIoDevice
);
/**
@@ -340,7 +340,7 @@ InitializePciDevice (
**/
VOID
InitializePpb (
IN PCI_IO_DEVICE *PciIoDevice
IN PCI_IO_DEVICE *PciIoDevice
);
/**
@@ -351,7 +351,7 @@ InitializePpb (
**/
VOID
InitializeP2C (
IN PCI_IO_DEVICE *PciIoDevice
IN PCI_IO_DEVICE *PciIoDevice
);
/**
@@ -369,11 +369,11 @@ InitializeP2C (
**/
PCI_IO_DEVICE *
CreatePciIoDevice (
IN PCI_IO_DEVICE *Bridge,
IN PCI_TYPE00 *Pci,
IN UINT8 Bus,
IN UINT8 Device,
IN UINT8 Func
IN PCI_IO_DEVICE *Bridge,
IN PCI_TYPE00 *Pci,
IN UINT8 Bus,
IN UINT8 Device,
IN UINT8 Func
);
/**
@@ -390,7 +390,7 @@ CreatePciIoDevice (
**/
EFI_STATUS
PciEnumeratorLight (
IN EFI_HANDLE Controller
IN EFI_HANDLE Controller
);
/**
@@ -424,7 +424,7 @@ PciGetBusRange (
**/
EFI_STATUS
StartManagingRootBridge (
IN PCI_IO_DEVICE *RootBridgeDev
IN PCI_IO_DEVICE *RootBridgeDev
);
/**
@@ -438,7 +438,7 @@ StartManagingRootBridge (
**/
BOOLEAN
IsPciDeviceRejected (
IN PCI_IO_DEVICE *PciIoDevice
IN PCI_IO_DEVICE *PciIoDevice
);
/**
@@ -450,8 +450,8 @@ IsPciDeviceRejected (
**/
VOID
ResetAllPpbBusNumber (
IN PCI_IO_DEVICE *Bridge,
IN UINT8 StartBusNumber
IN PCI_IO_DEVICE *Bridge,
IN UINT8 StartBusNumber
);
/**
@@ -463,8 +463,8 @@ ResetAllPpbBusNumber (
**/
VOID
DumpPpbPaddingResource (
IN PCI_IO_DEVICE *PciIoDevice,
IN PCI_BAR_TYPE ResourceType
IN PCI_IO_DEVICE *PciIoDevice,
IN PCI_BAR_TYPE ResourceType
);
/**
@@ -474,7 +474,7 @@ DumpPpbPaddingResource (
**/
VOID
DumpPciBars (
IN PCI_IO_DEVICE *PciIoDevice
IN PCI_IO_DEVICE *PciIoDevice
);
#endif

121
MdeModulePkg/Bus/Pci/PciBusDxe/PciHotPlugSupport.c
View File

@@ -13,7 +13,6 @@ EFI_HPC_LOCATION *gPciRootHpcPool = NULL;
UINTN gPciRootHpcCount = 0;
ROOT_HPC_DATA *gPciRootHpcData = NULL;
/**
Event notification function to set Hot Plug controller status.
@@ -24,14 +23,14 @@ ROOT_HPC_DATA *gPciRootHpcData = NULL;
VOID
EFIAPI
PciHPCInitialized (
IN EFI_EVENT Event,
IN VOID *Context
IN EFI_EVENT Event,
IN VOID *Context
)
{
ROOT_HPC_DATA *HpcData;
ROOT_HPC_DATA *HpcData;
HpcData = (ROOT_HPC_DATA *) Context;
HpcData->Initialized = TRUE;
HpcData = (ROOT_HPC_DATA *)Context;
HpcData->Initialized = TRUE;
}
/**
@@ -46,12 +45,12 @@ PciHPCInitialized (
**/
BOOLEAN
EfiCompareDevicePath (
IN EFI_DEVICE_PATH_PROTOCOL *DevicePath1,
IN EFI_DEVICE_PATH_PROTOCOL *DevicePath2
IN EFI_DEVICE_PATH_PROTOCOL *DevicePath1,
IN EFI_DEVICE_PATH_PROTOCOL *DevicePath2
)
{
UINTN Size1;
UINTN Size2;
UINTN Size1;
UINTN Size2;
Size1 = GetDevicePathSize (DevicePath1);
Size2 = GetDevicePathSize (DevicePath2);
@@ -100,7 +99,7 @@ InitializeHotPlugSupport (
Status = gBS->LocateProtocol (
&gEfiPciHotPlugInitProtocolGuid,
NULL,
(VOID **) &gPciHotPlugInit
(VOID **)&gPciHotPlugInit
);
if (EFI_ERROR (Status)) {
@@ -114,10 +113,9 @@ InitializeHotPlugSupport (
);
if (!EFI_ERROR (Status)) {
gPciRootHpcPool = HpcList;
gPciRootHpcCount = HpcCount;
gPciRootHpcData = AllocateZeroPool (sizeof (ROOT_HPC_DATA) * gPciRootHpcCount);
gPciRootHpcPool = HpcList;
gPciRootHpcCount = HpcCount;
gPciRootHpcData = AllocateZeroPool (sizeof (ROOT_HPC_DATA) * gPciRootHpcCount);
if (gPciRootHpcData == NULL) {
return EFI_OUT_OF_RESOURCES;
}
@@ -139,16 +137,14 @@ InitializeHotPlugSupport (
**/
BOOLEAN
IsRootPciHotPlugBus (
IN EFI_DEVICE_PATH_PROTOCOL *HpbDevicePath,
OUT UINTN *HpIndex OPTIONAL
IN EFI_DEVICE_PATH_PROTOCOL *HpbDevicePath,
OUT UINTN *HpIndex OPTIONAL
)
{
UINTN Index;
UINTN Index;
for (Index = 0; Index < gPciRootHpcCount; Index++) {
if (EfiCompareDevicePath (gPciRootHpcPool[Index].HpbDevicePath, HpbDevicePath)) {
if (HpIndex != NULL) {
*HpIndex = Index;
}
@@ -173,16 +169,14 @@ IsRootPciHotPlugBus (
**/
BOOLEAN
IsRootPciHotPlugController (
IN EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath,
OUT UINTN *HpIndex
IN EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath,
OUT UINTN *HpIndex
)
{
UINTN Index;
UINTN Index;
for (Index = 0; Index < gPciRootHpcCount; Index++) {
if (EfiCompareDevicePath (gPciRootHpcPool[Index].HpcDevicePath, HpcDevicePath)) {
if (HpIndex != NULL) {
*HpIndex = Index;
}
@@ -237,17 +231,16 @@ CreateEventForHpc (
**/
EFI_STATUS
AllRootHPCInitialized (
IN UINTN TimeoutInMicroSeconds
IN UINTN TimeoutInMicroSeconds
)
{
UINT32 Delay;
UINTN Index;
Delay = (UINT32) ((TimeoutInMicroSeconds / 30) + 1);
Delay = (UINT32)((TimeoutInMicroSeconds / 30) + 1);
do {
for (Index = 0; Index < gPciRootHpcCount; Index++) {
if (gPciRootHpcData[Index].Found && !gPciRootHpcData[Index].Initialized) {
break;
}
@@ -263,7 +256,6 @@ AllRootHPCInitialized (
gBS->Stall (30);
Delay--;
} while (Delay > 0);
return EFI_TIMEOUT;
@@ -280,10 +272,9 @@ AllRootHPCInitialized (
**/
BOOLEAN
IsSHPC (
IN PCI_IO_DEVICE *PciIoDevice
IN PCI_IO_DEVICE *PciIoDevice
)
{
EFI_STATUS Status;
UINT8 Offset;
@@ -293,11 +284,11 @@ IsSHPC (
Offset = 0;
Status = LocateCapabilityRegBlock (
PciIoDevice,
EFI_PCI_CAPABILITY_ID_SHPC,
&Offset,
NULL
);
PciIoDevice,
EFI_PCI_CAPABILITY_ID_SHPC,
&Offset,
NULL
);
//
// If the PCI-PCI bridge has the hot plug controller build-in,
@@ -328,13 +319,13 @@ IsSHPC (
**/
BOOLEAN
SupportsPcieHotplug (
IN PCI_IO_DEVICE *PciIoDevice
IN PCI_IO_DEVICE *PciIoDevice
)
{
UINT32 Offset;
EFI_STATUS Status;
PCI_REG_PCIE_CAPABILITY Capability;
PCI_REG_PCIE_SLOT_CAPABILITY SlotCapability;
UINT32 Offset;
EFI_STATUS Status;
PCI_REG_PCIE_CAPABILITY Capability;
PCI_REG_PCIE_SLOT_CAPABILITY SlotCapability;
if (PciIoDevice == NULL) {
return FALSE;
@@ -346,6 +337,7 @@ SupportsPcieHotplug (
if (!PciIoDevice->IsPciExp) {
return FALSE;
}
Offset = PciIoDevice->PciExpressCapabilityOffset +
OFFSET_OF (PCI_CAPABILITY_PCIEXP, Capability);
Status = PciIoDevice->PciIo.Pci.Read (
@@ -363,12 +355,13 @@ SupportsPcieHotplug (
// Check the contents of the register
//
switch (Capability.Bits.DevicePortType) {
case PCIE_DEVICE_PORT_TYPE_ROOT_PORT:
case PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT:
break;
default:
return FALSE;
case PCIE_DEVICE_PORT_TYPE_ROOT_PORT:
case PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT:
break;
default:
return FALSE;
}
if (!Capability.Bits.SlotImplemented) {
return FALSE;
}
@@ -395,6 +388,7 @@ SupportsPcieHotplug (
if (SlotCapability.Bits.HotPlugCapable) {
return TRUE;
}
return FALSE;
}
@@ -406,34 +400,34 @@ SupportsPcieHotplug (
**/
VOID
GetResourcePaddingForHpb (
IN PCI_IO_DEVICE *PciIoDevice
IN PCI_IO_DEVICE *PciIoDevice
)
{
EFI_STATUS Status;
EFI_HPC_STATE State;
UINT64 PciAddress;
EFI_HPC_PADDING_ATTRIBUTES Attributes;
EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;
EFI_STATUS Status;
EFI_HPC_STATE State;
UINT64 PciAddress;
EFI_HPC_PADDING_ATTRIBUTES Attributes;
EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;
if (IsPciHotPlugBus (PciIoDevice)) {
//
// If PCI-PCI bridge device is PCI Hot Plug bus.
//
PciAddress = EFI_PCI_ADDRESS (PciIoDevice->BusNumber, PciIoDevice->DeviceNumber, PciIoDevice->FunctionNumber, 0);
Status = gPciHotPlugInit->GetResourcePadding (
gPciHotPlugInit,
PciIoDevice->DevicePath,
PciAddress,
&State,
(VOID **) &Descriptors,
&Attributes
);
Status = gPciHotPlugInit->GetResourcePadding (
gPciHotPlugInit,
PciIoDevice->DevicePath,
PciAddress,
&State,
(VOID **)&Descriptors,
&Attributes
);
if (EFI_ERROR (Status)) {
return;
}
if ((State & EFI_HPC_STATE_ENABLED) != 0 && (State & EFI_HPC_STATE_INITIALIZED) != 0) {
if (((State & EFI_HPC_STATE_ENABLED) != 0) && ((State & EFI_HPC_STATE_INITIALIZED) != 0)) {
PciIoDevice->ResourcePaddingDescriptors = Descriptors;
PciIoDevice->PaddingAttributes = Attributes;
}
@@ -453,7 +447,7 @@ GetResourcePaddingForHpb (
**/
BOOLEAN
IsPciHotPlugBus (
PCI_IO_DEVICE *PciIoDevice
PCI_IO_DEVICE *PciIoDevice
)
{
if (IsSHPC (PciIoDevice)) {
@@ -475,10 +469,9 @@ IsPciHotPlugBus (
//
// Otherwise, see if it is a Root HPC
//
if(IsRootPciHotPlugBus (PciIoDevice->DevicePath, NULL)) {
if (IsRootPciHotPlugBus (PciIoDevice->DevicePath, NULL)) {
return TRUE;
}
return FALSE;
}

42
MdeModulePkg/Bus/Pci/PciBusDxe/PciHotPlugSupport.h
View File

@@ -12,24 +12,24 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
//
// stall 1 second, its unit is 100ns
//
#define STALL_1_SECOND 1000000
#define STALL_1_SECOND 1000000
//
// PCI Hot Plug controller private data
//
typedef struct {
EFI_EVENT Event;
BOOLEAN Found;
BOOLEAN Initialized;
VOID *Padding;
EFI_EVENT Event;
BOOLEAN Found;
BOOLEAN Initialized;
VOID *Padding;
} ROOT_HPC_DATA;
//
// Reference of some global variables
//
extern EFI_PCI_HOT_PLUG_INIT_PROTOCOL *gPciHotPlugInit;
extern EFI_HPC_LOCATION *gPciRootHpcPool;
extern ROOT_HPC_DATA *gPciRootHpcData;
extern EFI_PCI_HOT_PLUG_INIT_PROTOCOL *gPciHotPlugInit;
extern EFI_HPC_LOCATION *gPciRootHpcPool;
extern ROOT_HPC_DATA *gPciRootHpcData;
/**
Event notification function to set Hot Plug controller status.
@@ -41,8 +41,8 @@ extern ROOT_HPC_DATA *gPciRootHpcData;
VOID
EFIAPI
PciHPCInitialized (
IN EFI_EVENT Event,
IN VOID *Context
IN EFI_EVENT Event,
IN VOID *Context
);
/**
@@ -57,8 +57,8 @@ PciHPCInitialized (
**/
BOOLEAN
EfiCompareDevicePath (
IN EFI_DEVICE_PATH_PROTOCOL *DevicePath1,
IN EFI_DEVICE_PATH_PROTOCOL *DevicePath2
IN EFI_DEVICE_PATH_PROTOCOL *DevicePath1,
IN EFI_DEVICE_PATH_PROTOCOL *DevicePath2
);
/**
@@ -90,7 +90,7 @@ InitializeHotPlugSupport (
**/
BOOLEAN
IsPciHotPlugBus (
PCI_IO_DEVICE *PciIoDevice
PCI_IO_DEVICE *PciIoDevice
);
/**
@@ -106,8 +106,8 @@ IsPciHotPlugBus (
**/
BOOLEAN
IsRootPciHotPlugBus (
IN EFI_DEVICE_PATH_PROTOCOL *HpbDevicePath,
OUT UINTN *HpIndex OPTIONAL
IN EFI_DEVICE_PATH_PROTOCOL *HpbDevicePath,
OUT UINTN *HpIndex OPTIONAL
);
/**
@@ -123,8 +123,8 @@ IsRootPciHotPlugBus (
**/
BOOLEAN
IsRootPciHotPlugController (
IN EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath,
OUT UINTN *HpIndex
IN EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath,
OUT UINTN *HpIndex
);
/**
@@ -153,7 +153,7 @@ CreateEventForHpc (
**/
EFI_STATUS
AllRootHPCInitialized (
IN UINTN TimeoutInMicroSeconds
IN UINTN TimeoutInMicroSeconds
);
/**
@@ -167,7 +167,7 @@ AllRootHPCInitialized (
**/
BOOLEAN
IsSHPC (
IN PCI_IO_DEVICE *PciIoDevice
IN PCI_IO_DEVICE *PciIoDevice
);
/**
@@ -188,7 +188,7 @@ IsSHPC (
**/
BOOLEAN
SupportsPcieHotplug (
IN PCI_IO_DEVICE *PciIoDevice
IN PCI_IO_DEVICE *PciIoDevice
);
/**
@@ -199,7 +199,7 @@ SupportsPcieHotplug (
**/
VOID
GetResourcePaddingForHpb (
IN PCI_IO_DEVICE *PciIoDevice
IN PCI_IO_DEVICE *PciIoDevice
);
#endif

692
MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c
View File

File diff suppressed because it is too large Load Diff

77
MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.h
View File

@@ -17,7 +17,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
VOID
InitializePciIoInstance (
IN PCI_IO_DEVICE *PciIoDevice
IN PCI_IO_DEVICE *PciIoDevice
);
/**
@@ -37,12 +37,12 @@ InitializePciIoInstance (
**/
EFI_STATUS
PciIoVerifyBarAccess (
IN PCI_IO_DEVICE *PciIoDevice,
IN UINT8 BarIndex,
IN PCI_BAR_TYPE Type,
IN IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
IN IN UINTN Count,
IN UINT64 *Offset
IN PCI_IO_DEVICE *PciIoDevice,
IN UINT8 BarIndex,
IN PCI_BAR_TYPE Type,
IN IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
IN IN UINTN Count,
IN UINT64 *Offset
);
/**
@@ -347,13 +347,13 @@ PciIoConfigWrite (
EFI_STATUS
EFIAPI
PciIoCopyMem (
IN EFI_PCI_IO_PROTOCOL *This,
IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
IN UINT8 DestBarIndex,
IN UINT64 DestOffset,
IN UINT8 SrcBarIndex,
IN UINT64 SrcOffset,
IN UINTN Count
IN EFI_PCI_IO_PROTOCOL *This,
IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
IN UINT8 DestBarIndex,
IN UINT64 DestOffset,
IN UINT8 SrcBarIndex,
IN UINT64 SrcOffset,
IN UINTN Count
);
/**
@@ -426,12 +426,12 @@ PciIoUnmap (
EFI_STATUS
EFIAPI
PciIoAllocateBuffer (
IN EFI_PCI_IO_PROTOCOL *This,
IN EFI_ALLOCATE_TYPE Type,
IN EFI_MEMORY_TYPE MemoryType,
IN UINTN Pages,
OUT VOID **HostAddress,
IN UINT64 Attributes
IN EFI_PCI_IO_PROTOCOL *This,
IN EFI_ALLOCATE_TYPE Type,
IN EFI_MEMORY_TYPE MemoryType,
IN UINTN Pages,
OUT VOID **HostAddress,
IN UINT64 Attributes
);
/**
@@ -449,9 +449,9 @@ PciIoAllocateBuffer (
EFI_STATUS
EFIAPI
PciIoFreeBuffer (
IN EFI_PCI_IO_PROTOCOL *This,
IN UINTN Pages,
IN VOID *HostAddress
IN EFI_PCI_IO_PROTOCOL *This,
IN UINTN Pages,
IN VOID *HostAddress
);
/**
@@ -508,9 +508,9 @@ PciIoGetLocation (
**/
BOOLEAN
CheckBarType (
IN PCI_IO_DEVICE *PciIoDevice,
IN UINT8 BarIndex,
IN PCI_BAR_TYPE BarType
IN PCI_IO_DEVICE *PciIoDevice,
IN UINT8 BarIndex,
IN PCI_BAR_TYPE BarType
);
/**
@@ -569,7 +569,7 @@ SupportPaletteSnoopAttributes (
EFI_STATUS
EFIAPI
PciIoAttributes (
IN EFI_PCI_IO_PROTOCOL * This,
IN EFI_PCI_IO_PROTOCOL *This,
IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation,
IN UINT64 Attributes,
OUT UINT64 *Result OPTIONAL
@@ -600,10 +600,10 @@ PciIoAttributes (
EFI_STATUS
EFIAPI
PciIoGetBarAttributes (
IN EFI_PCI_IO_PROTOCOL * This,
IN UINT8 BarIndex,
OUT UINT64 *Supports OPTIONAL,
OUT VOID **Resources OPTIONAL
IN EFI_PCI_IO_PROTOCOL *This,
IN UINT8 BarIndex,
OUT UINT64 *Supports OPTIONAL,
OUT VOID **Resources OPTIONAL
);
/**
@@ -633,14 +633,13 @@ PciIoGetBarAttributes (
EFI_STATUS
EFIAPI
PciIoSetBarAttributes (
IN EFI_PCI_IO_PROTOCOL *This,
IN UINT64 Attributes,
IN UINT8 BarIndex,
IN OUT UINT64 *Offset,
IN OUT UINT64 *Length
IN EFI_PCI_IO_PROTOCOL *This,
IN UINT64 Attributes,
IN UINT8 BarIndex,
IN OUT UINT64 *Offset,
IN OUT UINT64 *Length
);
/**
Test whether two Pci devices has same parent bridge.
@@ -653,8 +652,8 @@ PciIoSetBarAttributes (
**/
BOOLEAN
PciDevicesOnTheSamePath (
IN PCI_IO_DEVICE *PciDevice1,
IN PCI_IO_DEVICE *PciDevice2
IN PCI_IO_DEVICE *PciDevice1,
IN PCI_IO_DEVICE *PciDevice2
);
#endif

629
MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c
View File

File diff suppressed because it is too large Load Diff

46
MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.h
View File

@@ -9,19 +9,18 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#ifndef _EFI_PCI_LIB_H_
#define _EFI_PCI_LIB_H_
typedef struct {
EFI_HANDLE Handle;
EFI_HANDLE Handle;
} EFI_DEVICE_HANDLE_EXTENDED_DATA_PAYLOAD;
typedef struct {
UINT32 Bar;
UINT16 DevicePathSize;
UINT16 ReqResSize;
UINT16 AllocResSize;
UINT8 *DevicePath;
UINT8 *ReqRes;
UINT8 *AllocRes;
UINT32 Bar;
UINT16 DevicePathSize;
UINT16 ReqResSize;
UINT16 AllocResSize;
UINT8 *DevicePath;
UINT8 *ReqRes;
UINT8 *AllocRes;
} EFI_RESOURCE_ALLOC_FAILURE_ERROR_DATA_PAYLOAD;
typedef enum {
@@ -37,7 +36,7 @@ typedef enum {
**/
VOID
GetBackPcCardBar (
IN PCI_IO_DEVICE *PciIoDevice
IN PCI_IO_DEVICE *PciIoDevice
);
/**
@@ -50,8 +49,8 @@ GetBackPcCardBar (
**/
VOID
RemoveRejectedPciDevices (
IN EFI_HANDLE RootBridgeHandle,
IN PCI_IO_DEVICE *Bridge
IN EFI_HANDLE RootBridgeHandle,
IN PCI_IO_DEVICE *Bridge
);
/**
@@ -69,7 +68,7 @@ RemoveRejectedPciDevices (
**/
EFI_STATUS
PciHostBridgeResourceAllocator (
IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc
IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc
);
/**
@@ -87,10 +86,10 @@ PciHostBridgeResourceAllocator (
**/
EFI_STATUS
PciAllocateBusNumber (
IN PCI_IO_DEVICE *Bridge,
IN UINT8 StartBusNumber,
IN UINT8 NumberOfBuses,
OUT UINT8 *NextBusNumber
IN PCI_IO_DEVICE *Bridge,
IN UINT8 StartBusNumber,
IN UINT8 NumberOfBuses,
OUT UINT8 *NextBusNumber
);
/**
@@ -109,10 +108,10 @@ PciAllocateBusNumber (
**/
EFI_STATUS
PciScanBus (
IN PCI_IO_DEVICE *Bridge,
IN UINT8 StartBusNumber,
OUT UINT8 *SubBusNumber,
OUT UINT8 *PaddedBusRange
IN PCI_IO_DEVICE *Bridge,
IN UINT8 StartBusNumber,
OUT UINT8 *SubBusNumber,
OUT UINT8 *PaddedBusRange
);
/**
@@ -126,7 +125,7 @@ PciScanBus (
**/
EFI_STATUS
PciRootBridgeP2CProcess (
IN PCI_IO_DEVICE *Bridge
IN PCI_IO_DEVICE *Bridge
);
/**
@@ -141,7 +140,7 @@ PciRootBridgeP2CProcess (
**/
EFI_STATUS
PciHostBridgeP2CProcess (
IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc
IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc
);
/**
@@ -176,4 +175,5 @@ PciProgramResizableBar (
IN PCI_IO_DEVICE *PciIoDevice,
IN PCI_RESIZABLE_BAR_OPERATION ResizableBarOp
);
#endif

242
MdeModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.c
View File

@@ -30,26 +30,26 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
EFI_STATUS
LocalLoadFile2 (
IN PCI_IO_DEVICE *PciIoDevice,
IN EFI_DEVICE_PATH_PROTOCOL *FilePath,
IN OUT UINTN *BufferSize,
IN VOID *Buffer OPTIONAL
IN PCI_IO_DEVICE *PciIoDevice,
IN EFI_DEVICE_PATH_PROTOCOL *FilePath,
IN OUT UINTN *BufferSize,
IN VOID *Buffer OPTIONAL
)
{
EFI_STATUS Status;
MEDIA_RELATIVE_OFFSET_RANGE_DEVICE_PATH *EfiOpRomImageNode;
EFI_PCI_EXPANSION_ROM_HEADER *EfiRomHeader;
PCI_DATA_STRUCTURE *Pcir;
UINT32 ImageSize;
UINT8 *ImageBuffer;
UINT32 ImageLength;
UINT32 DestinationSize;
UINT32 ScratchSize;
VOID *Scratch;
EFI_DECOMPRESS_PROTOCOL *Decompress;
UINT32 InitializationSize;
EFI_STATUS Status;
MEDIA_RELATIVE_OFFSET_RANGE_DEVICE_PATH *EfiOpRomImageNode;
EFI_PCI_EXPANSION_ROM_HEADER *EfiRomHeader;
PCI_DATA_STRUCTURE *Pcir;
UINT32 ImageSize;
UINT8 *ImageBuffer;
UINT32 ImageLength;
UINT32 DestinationSize;
UINT32 ScratchSize;
VOID *Scratch;
EFI_DECOMPRESS_PROTOCOL *Decompress;
UINT32 InitializationSize;
EfiOpRomImageNode = (MEDIA_RELATIVE_OFFSET_RANGE_DEVICE_PATH *) FilePath;
EfiOpRomImageNode = (MEDIA_RELATIVE_OFFSET_RANGE_DEVICE_PATH *)FilePath;
if ((EfiOpRomImageNode == NULL) ||
(DevicePathType (FilePath) != MEDIA_DEVICE_PATH) ||
(DevicePathSubType (FilePath) != MEDIA_RELATIVE_OFFSET_RANGE_DP) ||
@@ -58,19 +58,19 @@ LocalLoadFile2 (
(EfiOpRomImageNode->StartingOffset > EfiOpRomImageNode->EndingOffset) ||
(EfiOpRomImageNode->EndingOffset >= PciIoDevice->RomSize) ||
(BufferSize == NULL)
) {
)
{
return EFI_INVALID_PARAMETER;
}
EfiRomHeader = (EFI_PCI_EXPANSION_ROM_HEADER *) (
(UINT8 *) PciIoDevice->PciIo.RomImage + EfiOpRomImageNode->StartingOffset
);
EfiRomHeader = (EFI_PCI_EXPANSION_ROM_HEADER *)(
(UINT8 *)PciIoDevice->PciIo.RomImage + EfiOpRomImageNode->StartingOffset
);
if (EfiRomHeader->Signature != PCI_EXPANSION_ROM_HEADER_SIGNATURE) {
return EFI_NOT_FOUND;
}
Pcir = (PCI_DATA_STRUCTURE *) ((UINT8 *) EfiRomHeader + EfiRomHeader->PcirOffset);
Pcir = (PCI_DATA_STRUCTURE *)((UINT8 *)EfiRomHeader + EfiRomHeader->PcirOffset);
ASSERT (Pcir->Signature == PCI_DATA_STRUCTURE_SIGNATURE);
if ((Pcir->CodeType == PCI_CODE_TYPE_EFI_IMAGE) &&
@@ -78,22 +78,22 @@ LocalLoadFile2 (
((EfiRomHeader->EfiSubsystem == EFI_IMAGE_SUBSYSTEM_EFI_BOOT_SERVICE_DRIVER) ||
(EfiRomHeader->EfiSubsystem == EFI_IMAGE_SUBSYSTEM_EFI_RUNTIME_DRIVER)) &&
(EfiRomHeader->CompressionType <= EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED)
) {
ImageSize = Pcir->ImageLength * 512;
InitializationSize = (UINT32) EfiRomHeader->InitializationSize * 512;
if (InitializationSize > ImageSize || EfiRomHeader->EfiImageHeaderOffset >= InitializationSize) {
)
{
ImageSize = Pcir->ImageLength * 512;
InitializationSize = (UINT32)EfiRomHeader->InitializationSize * 512;
if ((InitializationSize > ImageSize) || (EfiRomHeader->EfiImageHeaderOffset >= InitializationSize)) {
return EFI_NOT_FOUND;
}
ImageBuffer = (UINT8 *) EfiRomHeader + EfiRomHeader->EfiImageHeaderOffset;
ImageLength = InitializationSize - EfiRomHeader->EfiImageHeaderOffset;
ImageBuffer = (UINT8 *)EfiRomHeader + EfiRomHeader->EfiImageHeaderOffset;
ImageLength = InitializationSize - EfiRomHeader->EfiImageHeaderOffset;
if (EfiRomHeader->CompressionType != EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED) {
//
// Uncompressed: Copy the EFI Image directly to user's buffer
//
if (Buffer == NULL || *BufferSize < ImageLength) {
if ((Buffer == NULL) || (*BufferSize < ImageLength)) {
*BufferSize = ImageLength;
return EFI_BUFFER_TOO_SMALL;
}
@@ -101,15 +101,15 @@ LocalLoadFile2 (
*BufferSize = ImageLength;
CopyMem (Buffer, ImageBuffer, ImageLength);
return EFI_SUCCESS;
} else {
//
// Compressed: Uncompress before copying
//
Status = gBS->LocateProtocol (&gEfiDecompressProtocolGuid, NULL, (VOID **) &Decompress);
Status = gBS->LocateProtocol (&gEfiDecompressProtocolGuid, NULL, (VOID **)&Decompress);
if (EFI_ERROR (Status)) {
return EFI_DEVICE_ERROR;
}
Status = Decompress->GetInfo (
Decompress,
ImageBuffer,
@@ -121,13 +121,13 @@ LocalLoadFile2 (
return EFI_DEVICE_ERROR;
}
if (Buffer == NULL || *BufferSize < DestinationSize) {
if ((Buffer == NULL) || (*BufferSize < DestinationSize)) {
*BufferSize = DestinationSize;
return EFI_BUFFER_TOO_SMALL;
}
*BufferSize = DestinationSize;
Scratch = AllocatePool (ScratchSize);
Scratch = AllocatePool (ScratchSize);
if (Scratch == NULL) {
return EFI_DEVICE_ERROR;
}
@@ -146,6 +146,7 @@ LocalLoadFile2 (
if (EFI_ERROR (Status)) {
return EFI_DEVICE_ERROR;
}
return EFI_SUCCESS;
}
}
@@ -161,7 +162,7 @@ LocalLoadFile2 (
**/
VOID
InitializePciLoadFile2 (
IN PCI_IO_DEVICE *PciIoDevice
IN PCI_IO_DEVICE *PciIoDevice
)
{
PciIoDevice->LoadFile2.LoadFile = LoadFile2;
@@ -193,18 +194,19 @@ InitializePciLoadFile2 (
EFI_STATUS
EFIAPI
LoadFile2 (
IN EFI_LOAD_FILE2_PROTOCOL *This,
IN EFI_DEVICE_PATH_PROTOCOL *FilePath,
IN BOOLEAN BootPolicy,
IN OUT UINTN *BufferSize,
IN VOID *Buffer OPTIONAL
IN EFI_LOAD_FILE2_PROTOCOL *This,
IN EFI_DEVICE_PATH_PROTOCOL *FilePath,
IN BOOLEAN BootPolicy,
IN OUT UINTN *BufferSize,
IN VOID *Buffer OPTIONAL
)
{
PCI_IO_DEVICE *PciIoDevice;
PCI_IO_DEVICE *PciIoDevice;
if (BootPolicy) {
return EFI_UNSUPPORTED;
}
PciIoDevice = PCI_IO_DEVICE_FROM_LOAD_FILE2_THIS (This);
return LocalLoadFile2 (
@@ -227,21 +229,21 @@ LoadFile2 (
**/
EFI_STATUS
GetOpRomInfo (
IN OUT PCI_IO_DEVICE *PciIoDevice
IN OUT PCI_IO_DEVICE *PciIoDevice
)
{
UINT8 RomBarIndex;
UINT32 AllOnes;
UINT64 Address;
EFI_STATUS Status;
UINT8 Bus;
UINT8 Device;
UINT8 Function;
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
UINT8 RomBarIndex;
UINT32 AllOnes;
UINT64 Address;
EFI_STATUS Status;
UINT8 Bus;
UINT8 Device;
UINT8 Function;
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
Bus = PciIoDevice->BusNumber;
Device = PciIoDevice->DeviceNumber;
Function = PciIoDevice->FunctionNumber;
Bus = PciIoDevice->BusNumber;
Device = PciIoDevice->DeviceNumber;
Function = PciIoDevice->FunctionNumber;
PciRootBridgeIo = PciIoDevice->PciRootBridgeIo;
@@ -260,6 +262,7 @@ GetOpRomInfo (
//
RomBarIndex = PCI_BRIDGE_ROMBAR;
}
//
// The bit0 is 0 to prevent the enabling of the Rom address decoder
//
@@ -280,7 +283,7 @@ GetOpRomInfo (
//
// Read back
//
Status = PciRootBridgeIo->Pci.Read(
Status = PciRootBridgeIo->Pci.Read (
PciRootBridgeIo,
EfiPciWidthUint32,
Address,
@@ -315,8 +318,8 @@ GetOpRomInfo (
**/
BOOLEAN
ContainEfiImage (
IN VOID *RomImage,
IN UINT64 RomSize
IN VOID *RomImage,
IN UINT64 RomSize
)
{
PCI_EXPANSION_ROM_HEADER *RomHeader;
@@ -331,20 +334,21 @@ ContainEfiImage (
do {
if (RomHeader->Signature != PCI_EXPANSION_ROM_HEADER_SIGNATURE) {
RomHeader = (PCI_EXPANSION_ROM_HEADER *) ((UINT8 *) RomHeader + 512);
RomHeader = (PCI_EXPANSION_ROM_HEADER *)((UINT8 *)RomHeader + 512);
continue;
}
//
// The PCI Data Structure must be DWORD aligned.
//
if (RomHeader->PcirOffset == 0 ||
(RomHeader->PcirOffset & 3) != 0 ||
(UINT8 *) RomHeader + RomHeader->PcirOffset + sizeof (PCI_DATA_STRUCTURE) > (UINT8 *) RomImage + RomSize) {
if ((RomHeader->PcirOffset == 0) ||
((RomHeader->PcirOffset & 3) != 0) ||
((UINT8 *)RomHeader + RomHeader->PcirOffset + sizeof (PCI_DATA_STRUCTURE) > (UINT8 *)RomImage + RomSize))
{
break;
}
RomPcir = (PCI_DATA_STRUCTURE *) ((UINT8 *) RomHeader + RomHeader->PcirOffset);
RomPcir = (PCI_DATA_STRUCTURE *)((UINT8 *)RomHeader + RomHeader->PcirOffset);
if (RomPcir->Signature != PCI_DATA_STRUCTURE_SIGNATURE) {
break;
}
@@ -354,8 +358,8 @@ ContainEfiImage (
}
Indicator = RomPcir->Indicator;
RomHeader = (PCI_EXPANSION_ROM_HEADER *) ((UINT8 *) RomHeader + RomPcir->ImageLength * 512);
} while (((UINT8 *) RomHeader < (UINT8 *) RomImage + RomSize) && ((Indicator & 0x80) == 0x00));
RomHeader = (PCI_EXPANSION_ROM_HEADER *)((UINT8 *)RomHeader + RomPcir->ImageLength * 512);
} while (((UINT8 *)RomHeader < (UINT8 *)RomImage + RomSize) && ((Indicator & 0x80) == 0x00));
return FALSE;
}
@@ -372,8 +376,8 @@ ContainEfiImage (
**/
EFI_STATUS
LoadOpRomImage (
IN PCI_IO_DEVICE *PciDevice,
IN UINT64 RomBase
IN PCI_IO_DEVICE *PciDevice,
IN UINT64 RomBase
)
{
UINT8 RomBarIndex;
@@ -392,12 +396,12 @@ LoadOpRomImage (
UINT8 *RomInMemory;
UINT8 CodeType;
RomSize = PciDevice->RomSize;
RomSize = PciDevice->RomSize;
Indicator = 0;
RomImageSize = 0;
RomInMemory = NULL;
CodeType = 0xFF;
Indicator = 0;
RomImageSize = 0;
RomInMemory = NULL;
CodeType = 0xFF;
//
// Get the RomBarIndex
@@ -417,6 +421,7 @@ LoadOpRomImage (
//
RomBarIndex = PCI_BRIDGE_ROMBAR;
}
//
// Allocate memory for Rom header and PCIR
//
@@ -431,16 +436,16 @@ LoadOpRomImage (
return EFI_OUT_OF_RESOURCES;
}
RomBar = (UINT32) RomBase;
RomBar = (UINT32)RomBase;
//
// Enable RomBar
//
RomDecode (PciDevice, RomBarIndex, RomBar, TRUE);
RomBarOffset = RomBar;
RetStatus = EFI_NOT_FOUND;
FirstCheck = TRUE;
RomBarOffset = RomBar;
RetStatus = EFI_NOT_FOUND;
FirstCheck = TRUE;
LegacyImageLength = 0;
do {
@@ -449,7 +454,7 @@ LoadOpRomImage (
EfiPciWidthUint8,
RomBarOffset,
sizeof (PCI_EXPANSION_ROM_HEADER),
(UINT8 *) RomHeader
(UINT8 *)RomHeader
);
if (RomHeader->Signature != PCI_EXPANSION_ROM_HEADER_SIGNATURE) {
@@ -462,23 +467,25 @@ LoadOpRomImage (
}
}
FirstCheck = FALSE;
OffsetPcir = RomHeader->PcirOffset;
FirstCheck = FALSE;
OffsetPcir = RomHeader->PcirOffset;
//
// If the pointer to the PCI Data Structure is invalid, no further images can be located.
// The PCI Data Structure must be DWORD aligned.
//
if (OffsetPcir == 0 ||
(OffsetPcir & 3) != 0 ||
RomImageSize + OffsetPcir + sizeof (PCI_DATA_STRUCTURE) > RomSize) {
if ((OffsetPcir == 0) ||
((OffsetPcir & 3) != 0) ||
(RomImageSize + OffsetPcir + sizeof (PCI_DATA_STRUCTURE) > RomSize))
{
break;
}
PciDevice->PciRootBridgeIo->Mem.Read (
PciDevice->PciRootBridgeIo,
EfiPciWidthUint8,
RomBarOffset + OffsetPcir,
sizeof (PCI_DATA_STRUCTURE),
(UINT8 *) RomPcir
(UINT8 *)RomPcir
);
//
// If a valid signature is not present in the PCI Data Structure, no further images can be located.
@@ -486,16 +493,19 @@ LoadOpRomImage (
if (RomPcir->Signature != PCI_DATA_STRUCTURE_SIGNATURE) {
break;
}
if (RomImageSize + RomPcir->ImageLength * 512 > RomSize) {
break;
}
if (RomPcir->CodeType == PCI_CODE_TYPE_PCAT_IMAGE) {
CodeType = PCI_CODE_TYPE_PCAT_IMAGE;
CodeType = PCI_CODE_TYPE_PCAT_IMAGE;
LegacyImageLength = ((UINT32)((EFI_LEGACY_EXPANSION_ROM_HEADER *)RomHeader)->Size512) * 512;
}
Indicator = RomPcir->Indicator;
RomImageSize = RomImageSize + RomPcir->ImageLength * 512;
RomBarOffset = RomBarOffset + RomPcir->ImageLength * 512;
Indicator = RomPcir->Indicator;
RomImageSize = RomImageSize + RomPcir->ImageLength * 512;
RomBarOffset = RomBarOffset + RomPcir->ImageLength * 512;
} while (((Indicator & 0x80) == 0x00) && ((RomBarOffset - RomBar) < RomSize));
//
@@ -508,7 +518,7 @@ LoadOpRomImage (
if (RomImageSize > 0) {
RetStatus = EFI_SUCCESS;
Image = AllocatePool ((UINT32) RomImageSize);
Image = AllocatePool ((UINT32)RomImageSize);
if (Image == NULL) {
RomDecode (PciDevice, RomBarIndex, RomBar, FALSE);
FreePool (RomHeader);
@@ -523,7 +533,7 @@ LoadOpRomImage (
PciDevice->PciRootBridgeIo,
EfiPciWidthUint32,
RomBar,
(UINT32) RomImageSize/sizeof(UINT32),
(UINT32)RomImageSize/sizeof (UINT32),
Image
);
RomInMemory = Image;
@@ -570,18 +580,17 @@ LoadOpRomImage (
**/
VOID
RomDecode (
IN PCI_IO_DEVICE *PciDevice,
IN UINT8 RomBarIndex,
IN UINT32 RomBar,
IN BOOLEAN Enable
IN PCI_IO_DEVICE *PciDevice,
IN UINT8 RomBarIndex,
IN UINT32 RomBar,
IN BOOLEAN Enable
)
{
UINT32 Value32;
EFI_PCI_IO_PROTOCOL *PciIo;
UINT32 Value32;
EFI_PCI_IO_PROTOCOL *PciIo;
PciIo = &PciDevice->PciIo;
if (Enable) {
//
// set the Rom base address: now is hardcode
// enable its decoder
@@ -589,7 +598,7 @@ RomDecode (
Value32 = RomBar | 0x1;
PciIo->Pci.Write (
PciIo,
(EFI_PCI_IO_PROTOCOL_WIDTH) EfiPciWidthUint32,
(EFI_PCI_IO_PROTOCOL_WIDTH)EfiPciWidthUint32,
RomBarIndex,
1,
&Value32
@@ -603,14 +612,12 @@ RomDecode (
//
// Setting the memory space bit in the function's command register
//
PCI_ENABLE_COMMAND_REGISTER(PciDevice, EFI_PCI_COMMAND_MEMORY_SPACE);
PCI_ENABLE_COMMAND_REGISTER (PciDevice, EFI_PCI_COMMAND_MEMORY_SPACE);
} else {
//
// disable command register decode to memory
//
PCI_DISABLE_COMMAND_REGISTER(PciDevice, EFI_PCI_COMMAND_MEMORY_SPACE);
PCI_DISABLE_COMMAND_REGISTER (PciDevice, EFI_PCI_COMMAND_MEMORY_SPACE);
//
// Destroy the programmed bar in all the upstream bridge.
@@ -623,12 +630,11 @@ RomDecode (
Value32 = 0xFFFFFFFE;
PciIo->Pci.Write (
PciIo,
(EFI_PCI_IO_PROTOCOL_WIDTH) EfiPciWidthUint32,
(EFI_PCI_IO_PROTOCOL_WIDTH)EfiPciWidthUint32,
RomBarIndex,
1,
&Value32
);
}
}
@@ -643,7 +649,7 @@ RomDecode (
**/
EFI_STATUS
ProcessOpRomImage (
IN PCI_IO_DEVICE *PciDevice
IN PCI_IO_DEVICE *PciDevice
)
{
UINT8 Indicator;
@@ -665,26 +671,27 @@ ProcessOpRomImage (
//
// Get the Address of the Option Rom image
//
RomBar = PciDevice->PciIo.RomImage;
RomBarOffset = (UINT8 *) RomBar;
RetStatus = EFI_NOT_FOUND;
RomBar = PciDevice->PciIo.RomImage;
RomBarOffset = (UINT8 *)RomBar;
RetStatus = EFI_NOT_FOUND;
if (RomBar == NULL) {
return RetStatus;
}
ASSERT (((EFI_PCI_EXPANSION_ROM_HEADER *) RomBarOffset)->Signature == PCI_EXPANSION_ROM_HEADER_SIGNATURE);
ASSERT (((EFI_PCI_EXPANSION_ROM_HEADER *)RomBarOffset)->Signature == PCI_EXPANSION_ROM_HEADER_SIGNATURE);
do {
EfiRomHeader = (EFI_PCI_EXPANSION_ROM_HEADER *) RomBarOffset;
EfiRomHeader = (EFI_PCI_EXPANSION_ROM_HEADER *)RomBarOffset;
if (EfiRomHeader->Signature != PCI_EXPANSION_ROM_HEADER_SIGNATURE) {
RomBarOffset += 512;
continue;
}
Pcir = (PCI_DATA_STRUCTURE *) (RomBarOffset + EfiRomHeader->PcirOffset);
Pcir = (PCI_DATA_STRUCTURE *)(RomBarOffset + EfiRomHeader->PcirOffset);
ASSERT (Pcir->Signature == PCI_DATA_STRUCTURE_SIGNATURE);
ImageSize = (UINT32) (Pcir->ImageLength * 512);
Indicator = Pcir->Indicator;
ImageSize = (UINT32)(Pcir->ImageLength * 512);
Indicator = Pcir->Indicator;
//
// Skip the image if it is not an EFI PCI Option ROM image
@@ -703,11 +710,11 @@ ProcessOpRomImage (
//
// Create Pci Option Rom Image device path header
//
EfiOpRomImageNode.Header.Type = MEDIA_DEVICE_PATH;
EfiOpRomImageNode.Header.SubType = MEDIA_RELATIVE_OFFSET_RANGE_DP;
EfiOpRomImageNode.Header.Type = MEDIA_DEVICE_PATH;
EfiOpRomImageNode.Header.SubType = MEDIA_RELATIVE_OFFSET_RANGE_DP;
SetDevicePathNodeLength (&EfiOpRomImageNode.Header, sizeof (EfiOpRomImageNode));
EfiOpRomImageNode.StartingOffset = (UINTN) RomBarOffset - (UINTN) RomBar;
EfiOpRomImageNode.EndingOffset = (UINTN) RomBarOffset + ImageSize - 1 - (UINTN) RomBar;
EfiOpRomImageNode.StartingOffset = (UINTN)RomBarOffset - (UINTN)RomBar;
EfiOpRomImageNode.EndingOffset = (UINTN)RomBarOffset + ImageSize - 1 - (UINTN)RomBar;
PciOptionRomImageDevicePath = AppendDevicePathNode (PciDevice->DevicePath, &EfiOpRomImageNode.Header);
ASSERT (PciOptionRomImageDevicePath != NULL);
@@ -752,13 +759,12 @@ ProcessOpRomImage (
RetStatus = EFI_SUCCESS;
}
}
FreePool (PciOptionRomImageDevicePath);
NextImage:
RomBarOffset += ImageSize;
} while (((Indicator & 0x80) == 0x00) && (((UINTN) RomBarOffset - (UINTN) RomBar) < PciDevice->RomSize));
} while (((Indicator & 0x80) == 0x00) && (((UINTN)RomBarOffset - (UINTN)RomBar) < PciDevice->RomSize));
return RetStatus;
}

33
MdeModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.h
View File

@@ -9,7 +9,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#ifndef _EFI_PCI_OPTION_ROM_SUPPORT_H_
#define _EFI_PCI_OPTION_ROM_SUPPORT_H_
/**
Initialize a PCI LoadFile2 instance.
@@ -18,7 +17,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
VOID
InitializePciLoadFile2 (
IN PCI_IO_DEVICE *PciIoDevice
IN PCI_IO_DEVICE *PciIoDevice
);
/**
@@ -47,11 +46,11 @@ InitializePciLoadFile2 (
EFI_STATUS
EFIAPI
LoadFile2 (
IN EFI_LOAD_FILE2_PROTOCOL *This,
IN EFI_DEVICE_PATH_PROTOCOL *FilePath,
IN BOOLEAN BootPolicy,
IN OUT UINTN *BufferSize,
IN VOID *Buffer OPTIONAL
IN EFI_LOAD_FILE2_PROTOCOL *This,
IN EFI_DEVICE_PATH_PROTOCOL *FilePath,
IN BOOLEAN BootPolicy,
IN OUT UINTN *BufferSize,
IN VOID *Buffer OPTIONAL
);
/**
@@ -66,8 +65,8 @@ LoadFile2 (
**/
BOOLEAN
ContainEfiImage (
IN VOID *RomImage,
IN UINT64 RomSize
IN VOID *RomImage,
IN UINT64 RomSize
);
/**
@@ -82,7 +81,7 @@ ContainEfiImage (
**/
EFI_STATUS
GetOpRomInfo (
IN OUT PCI_IO_DEVICE *PciIoDevice
IN OUT PCI_IO_DEVICE *PciIoDevice
);
/**
@@ -97,8 +96,8 @@ GetOpRomInfo (
**/
EFI_STATUS
LoadOpRomImage (
IN PCI_IO_DEVICE *PciDevice,
IN UINT64 RomBase
IN PCI_IO_DEVICE *PciDevice,
IN UINT64 RomBase
);
/**
@@ -113,10 +112,10 @@ LoadOpRomImage (
**/
VOID
RomDecode (
IN PCI_IO_DEVICE *PciDevice,
IN UINT8 RomBarIndex,
IN UINT32 RomBar,
IN BOOLEAN Enable
IN PCI_IO_DEVICE *PciDevice,
IN UINT8 RomBarIndex,
IN UINT32 RomBar,
IN BOOLEAN Enable
);
/**
@@ -130,7 +129,7 @@ RomDecode (
**/
EFI_STATUS
ProcessOpRomImage (
IN PCI_IO_DEVICE *PciDevice
IN PCI_IO_DEVICE *PciDevice
);
#endif

14
MdeModulePkg/Bus/Pci/PciBusDxe/PciPowerManagement.c
View File

@@ -21,7 +21,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
EFI_STATUS
ResetPowerManagementFeature (
IN PCI_IO_DEVICE *PciIoDevice
IN PCI_IO_DEVICE *PciIoDevice
)
{
EFI_STATUS Status;
@@ -31,11 +31,11 @@ ResetPowerManagementFeature (
PowerManagementRegBlock = 0;
Status = LocateCapabilityRegBlock (
PciIoDevice,
EFI_PCI_CAPABILITY_ID_PMI,
&PowerManagementRegBlock,
NULL
);
PciIoDevice,
EFI_PCI_CAPABILITY_ID_PMI,
&PowerManagementRegBlock,
NULL
);
if (EFI_ERROR (Status)) {
return EFI_UNSUPPORTED;
@@ -77,6 +77,6 @@ ResetPowerManagementFeature (
&PowerManagementCSR
);
}
return Status;
}

2
MdeModulePkg/Bus/Pci/PciBusDxe/PciPowerManagement.h
View File

@@ -22,7 +22,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
EFI_STATUS
ResetPowerManagementFeature (
IN PCI_IO_DEVICE *PciIoDevice
IN PCI_IO_DEVICE *PciIoDevice
);
#endif

1539
MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c
View File

File diff suppressed because it is too large Load Diff

180
MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.h
View File

@@ -17,18 +17,18 @@ typedef enum {
#define PCI_RESOURCE_SIGNATURE SIGNATURE_32 ('p', 'c', 'r', 'c')
typedef struct {
UINT32 Signature;
LIST_ENTRY Link;
LIST_ENTRY ChildList;
PCI_IO_DEVICE *PciDev;
UINT64 Alignment;
UINT64 Offset;
UINT8 Bar;
PCI_BAR_TYPE ResType;
UINT64 Length;
BOOLEAN Reserved;
PCI_RESOURCE_USAGE ResourceUsage;
BOOLEAN Virtual;
UINT32 Signature;
LIST_ENTRY Link;
LIST_ENTRY ChildList;
PCI_IO_DEVICE *PciDev;
UINT64 Alignment;
UINT64 Offset;
UINT8 Bar;
PCI_BAR_TYPE ResType;
UINT64 Length;
BOOLEAN Reserved;
PCI_RESOURCE_USAGE ResourceUsage;
BOOLEAN Virtual;
} PCI_RESOURCE_NODE;
#define RESOURCE_NODE_FROM_LINK(a) \
@@ -43,8 +43,8 @@ typedef struct {
**/
VOID
SkipVGAAperture (
OUT UINT64 *Start,
IN UINT64 Length
OUT UINT64 *Start,
IN UINT64 Length
);
/**
@@ -56,8 +56,8 @@ SkipVGAAperture (
**/
VOID
SkipIsaAliasAperture (
OUT UINT64 *Start,
IN UINT64 Length
OUT UINT64 *Start,
IN UINT64 Length
);
/**
@@ -70,8 +70,8 @@ SkipIsaAliasAperture (
**/
VOID
InsertResourceNode (
IN OUT PCI_RESOURCE_NODE *Bridge,
IN PCI_RESOURCE_NODE *ResNode
IN OUT PCI_RESOURCE_NODE *Bridge,
IN PCI_RESOURCE_NODE *ResNode
);
/**
@@ -94,9 +94,9 @@ InsertResourceNode (
**/
VOID
MergeResourceTree (
IN PCI_RESOURCE_NODE *Dst,
IN PCI_RESOURCE_NODE *Res,
IN BOOLEAN TypeMerge
IN PCI_RESOURCE_NODE *Dst,
IN PCI_RESOURCE_NODE *Res,
IN BOOLEAN TypeMerge
);
/**
@@ -108,7 +108,7 @@ MergeResourceTree (
**/
VOID
CalculateApertureIo16 (
IN PCI_RESOURCE_NODE *Bridge
IN PCI_RESOURCE_NODE *Bridge
);
/**
@@ -120,7 +120,7 @@ CalculateApertureIo16 (
**/
VOID
CalculateResourceAperture (
IN PCI_RESOURCE_NODE *Bridge
IN PCI_RESOURCE_NODE *Bridge
);
/**
@@ -136,12 +136,12 @@ CalculateResourceAperture (
**/
VOID
GetResourceFromDevice (
IN PCI_IO_DEVICE *PciDev,
IN OUT PCI_RESOURCE_NODE *IoNode,
IN OUT PCI_RESOURCE_NODE *Mem32Node,
IN OUT PCI_RESOURCE_NODE *PMem32Node,
IN OUT PCI_RESOURCE_NODE *Mem64Node,
IN OUT PCI_RESOURCE_NODE *PMem64Node
IN PCI_IO_DEVICE *PciDev,
IN OUT PCI_RESOURCE_NODE *IoNode,
IN OUT PCI_RESOURCE_NODE *Mem32Node,
IN OUT PCI_RESOURCE_NODE *PMem32Node,
IN OUT PCI_RESOURCE_NODE *Mem64Node,
IN OUT PCI_RESOURCE_NODE *PMem64Node
);
/**
@@ -160,12 +160,12 @@ GetResourceFromDevice (
**/
PCI_RESOURCE_NODE *
CreateResourceNode (
IN PCI_IO_DEVICE *PciDev,
IN UINT64 Length,
IN UINT64 Alignment,
IN UINT8 Bar,
IN PCI_BAR_TYPE ResType,
IN PCI_RESOURCE_USAGE ResUsage
IN PCI_IO_DEVICE *PciDev,
IN UINT64 Length,
IN UINT64 Alignment,
IN UINT8 Bar,
IN PCI_BAR_TYPE ResType,
IN PCI_RESOURCE_USAGE ResUsage
);
/**
@@ -184,12 +184,12 @@ CreateResourceNode (
**/
PCI_RESOURCE_NODE *
CreateVfResourceNode (
IN PCI_IO_DEVICE *PciDev,
IN UINT64 Length,
IN UINT64 Alignment,
IN UINT8 Bar,
IN PCI_BAR_TYPE ResType,
IN PCI_RESOURCE_USAGE ResUsage
IN PCI_IO_DEVICE *PciDev,
IN UINT64 Length,
IN UINT64 Alignment,
IN UINT8 Bar,
IN PCI_BAR_TYPE ResType,
IN PCI_RESOURCE_USAGE ResUsage
);
/**
@@ -206,12 +206,12 @@ CreateVfResourceNode (
**/
VOID
CreateResourceMap (
IN PCI_IO_DEVICE *Bridge,
IN OUT PCI_RESOURCE_NODE *IoNode,
IN OUT PCI_RESOURCE_NODE *Mem32Node,
IN OUT PCI_RESOURCE_NODE *PMem32Node,
IN OUT PCI_RESOURCE_NODE *Mem64Node,
IN OUT PCI_RESOURCE_NODE *PMem64Node
IN PCI_IO_DEVICE *Bridge,
IN OUT PCI_RESOURCE_NODE *IoNode,
IN OUT PCI_RESOURCE_NODE *Mem32Node,
IN OUT PCI_RESOURCE_NODE *PMem32Node,
IN OUT PCI_RESOURCE_NODE *Mem64Node,
IN OUT PCI_RESOURCE_NODE *PMem64Node
);
/**
@@ -227,12 +227,12 @@ CreateResourceMap (
**/
VOID
ResourcePaddingPolicy (
IN PCI_IO_DEVICE *PciDev,
IN PCI_RESOURCE_NODE *IoNode,
IN PCI_RESOURCE_NODE *Mem32Node,
IN PCI_RESOURCE_NODE *PMem32Node,
IN PCI_RESOURCE_NODE *Mem64Node,
IN PCI_RESOURCE_NODE *PMem64Node
IN PCI_IO_DEVICE *PciDev,
IN PCI_RESOURCE_NODE *IoNode,
IN PCI_RESOURCE_NODE *Mem32Node,
IN PCI_RESOURCE_NODE *PMem32Node,
IN PCI_RESOURCE_NODE *Mem64Node,
IN PCI_RESOURCE_NODE *PMem64Node
);
/**
@@ -251,11 +251,11 @@ ResourcePaddingPolicy (
**/
VOID
DegradeResource (
IN PCI_IO_DEVICE *Bridge,
IN PCI_RESOURCE_NODE *Mem32Node,
IN PCI_RESOURCE_NODE *PMem32Node,
IN PCI_RESOURCE_NODE *Mem64Node,
IN PCI_RESOURCE_NODE *PMem64Node
IN PCI_IO_DEVICE *Bridge,
IN PCI_RESOURCE_NODE *Mem32Node,
IN PCI_RESOURCE_NODE *PMem32Node,
IN PCI_RESOURCE_NODE *Mem64Node,
IN PCI_RESOURCE_NODE *PMem64Node
);
/**
@@ -270,8 +270,8 @@ DegradeResource (
**/
BOOLEAN
BridgeSupportResourceDecode (
IN PCI_IO_DEVICE *Bridge,
IN UINT32 Decode
IN PCI_IO_DEVICE *Bridge,
IN UINT32 Decode
);
/**
@@ -288,8 +288,8 @@ BridgeSupportResourceDecode (
**/
EFI_STATUS
ProgramResource (
IN UINT64 Base,
IN PCI_RESOURCE_NODE *Bridge
IN UINT64 Base,
IN PCI_RESOURCE_NODE *Bridge
);
/**
@@ -301,8 +301,8 @@ ProgramResource (
**/
VOID
ProgramBar (
IN UINT64 Base,
IN PCI_RESOURCE_NODE *Node
IN UINT64 Base,
IN PCI_RESOURCE_NODE *Node
);
/**
@@ -314,8 +314,8 @@ ProgramBar (
**/
EFI_STATUS
ProgramVfBar (
IN UINT64 Base,
IN PCI_RESOURCE_NODE *Node
IN UINT64 Base,
IN PCI_RESOURCE_NODE *Node
);
/**
@@ -327,8 +327,8 @@ ProgramVfBar (
**/
VOID
ProgramPpbApperture (
IN UINT64 Base,
IN PCI_RESOURCE_NODE *Node
IN UINT64 Base,
IN PCI_RESOURCE_NODE *Node
);
/**
@@ -341,9 +341,9 @@ ProgramPpbApperture (
**/
VOID
ProgramUpstreamBridgeForRom (
IN PCI_IO_DEVICE *PciDevice,
IN UINT32 OptionRomBase,
IN BOOLEAN Enable
IN PCI_IO_DEVICE *PciDevice,
IN UINT32 OptionRomBase,
IN BOOLEAN Enable
);
/**
@@ -357,7 +357,7 @@ ProgramUpstreamBridgeForRom (
**/
BOOLEAN
ResourceRequestExisted (
IN PCI_RESOURCE_NODE *Bridge
IN PCI_RESOURCE_NODE *Bridge
);
/**
@@ -370,8 +370,8 @@ ResourceRequestExisted (
**/
VOID
InitializeResourcePool (
IN OUT PCI_RESOURCE_NODE *ResourcePool,
IN PCI_BAR_TYPE ResourceType
IN OUT PCI_RESOURCE_NODE *ResourcePool,
IN PCI_BAR_TYPE ResourceType
);
/**
@@ -382,7 +382,7 @@ InitializeResourcePool (
**/
VOID
DestroyResourceTree (
IN PCI_RESOURCE_NODE *Bridge
IN PCI_RESOURCE_NODE *Bridge
);
/**
@@ -398,12 +398,12 @@ DestroyResourceTree (
**/
VOID
ResourcePaddingForCardBusBridge (
IN PCI_IO_DEVICE *PciDev,
IN PCI_RESOURCE_NODE *IoNode,
IN PCI_RESOURCE_NODE *Mem32Node,
IN PCI_RESOURCE_NODE *PMem32Node,
IN PCI_RESOURCE_NODE *Mem64Node,
IN PCI_RESOURCE_NODE *PMem64Node
IN PCI_IO_DEVICE *PciDev,
IN PCI_RESOURCE_NODE *IoNode,
IN PCI_RESOURCE_NODE *Mem32Node,
IN PCI_RESOURCE_NODE *PMem32Node,
IN PCI_RESOURCE_NODE *Mem64Node,
IN PCI_RESOURCE_NODE *PMem64Node
);
/**
@@ -415,8 +415,8 @@ ResourcePaddingForCardBusBridge (
**/
VOID
ProgramP2C (
IN UINT64 Base,
IN PCI_RESOURCE_NODE *Node
IN UINT64 Base,
IN PCI_RESOURCE_NODE *Node
);
/**
@@ -432,12 +432,12 @@ ProgramP2C (
**/
VOID
ApplyResourcePadding (
IN PCI_IO_DEVICE *PciDev,
IN PCI_RESOURCE_NODE *IoNode,
IN PCI_RESOURCE_NODE *Mem32Node,
IN PCI_RESOURCE_NODE *PMem32Node,
IN PCI_RESOURCE_NODE *Mem64Node,
IN PCI_RESOURCE_NODE *PMem64Node
IN PCI_IO_DEVICE *PciDev,
IN PCI_RESOURCE_NODE *IoNode,
IN PCI_RESOURCE_NODE *Mem32Node,
IN PCI_RESOURCE_NODE *PMem32Node,
IN PCI_RESOURCE_NODE *Mem64Node,
IN PCI_RESOURCE_NODE *PMem64Node
);
/**
@@ -450,7 +450,7 @@ ApplyResourcePadding (
**/
VOID
GetResourcePaddingPpb (
IN PCI_IO_DEVICE *PciIoDevice
IN PCI_IO_DEVICE *PciIoDevice
);
#endif

55
MdeModulePkg/Bus/Pci/PciBusDxe/PciRomTable.c
View File

@@ -12,18 +12,18 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
// PCI ROM image information
//
typedef struct {
EFI_HANDLE ImageHandle;
UINTN Seg;
UINT8 Bus;
UINT8 Dev;
UINT8 Func;
VOID *RomImage;
UINT64 RomSize;
EFI_HANDLE ImageHandle;
UINTN Seg;
UINT8 Bus;
UINT8 Dev;
UINT8 Func;
VOID *RomImage;
UINT64 RomSize;
} PCI_ROM_IMAGE;
UINTN mNumberOfPciRomImages = 0;
UINTN mMaxNumberOfPciRomImages = 0;
PCI_ROM_IMAGE *mRomImageTable = NULL;
UINTN mNumberOfPciRomImages = 0;
UINTN mMaxNumberOfPciRomImages = 0;
PCI_ROM_IMAGE *mRomImageTable = NULL;
/**
Add the Rom Image to internal database for later PCI light enumeration.
@@ -47,20 +47,21 @@ PciRomAddImageMapping (
IN UINT64 RomSize
)
{
UINTN Index;
PCI_ROM_IMAGE *NewTable;
UINTN Index;
PCI_ROM_IMAGE *NewTable;
for (Index = 0; Index < mNumberOfPciRomImages; Index++) {
if (mRomImageTable[Index].Seg == Seg &&
mRomImageTable[Index].Bus == Bus &&
mRomImageTable[Index].Dev == Dev &&
mRomImageTable[Index].Func == Func) {
if ((mRomImageTable[Index].Seg == Seg) &&
(mRomImageTable[Index].Bus == Bus) &&
(mRomImageTable[Index].Dev == Dev) &&
(mRomImageTable[Index].Func == Func))
{
//
// Expect once RomImage and RomSize are recorded, they will be passed in
// later when updating ImageHandle
//
ASSERT ((mRomImageTable[Index].RomImage == NULL) || (RomImage == mRomImageTable[Index].RomImage));
ASSERT ((mRomImageTable[Index].RomSize == 0 ) || (RomSize == mRomImageTable[Index].RomSize ));
ASSERT ((mRomImageTable[Index].RomSize == 0) || (RomSize == mRomImageTable[Index].RomSize));
break;
}
}
@@ -76,12 +77,13 @@ PciRomAddImageMapping (
mRomImageTable
);
if (NewTable == NULL) {
return ;
return;
}
mRomImageTable = NewTable;
mMaxNumberOfPciRomImages += 0x20;
}
//
// Record the new PCI device
//
@@ -108,23 +110,24 @@ PciRomAddImageMapping (
**/
BOOLEAN
PciRomGetImageMapping (
IN PCI_IO_DEVICE *PciIoDevice
IN PCI_IO_DEVICE *PciIoDevice
)
{
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
UINTN Index;
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
UINTN Index;
PciRootBridgeIo = PciIoDevice->PciRootBridgeIo;
for (Index = 0; Index < mNumberOfPciRomImages; Index++) {
if (mRomImageTable[Index].Seg == PciRootBridgeIo->SegmentNumber &&
mRomImageTable[Index].Bus == PciIoDevice->BusNumber &&
mRomImageTable[Index].Dev == PciIoDevice->DeviceNumber &&
mRomImageTable[Index].Func == PciIoDevice->FunctionNumber ) {
if ((mRomImageTable[Index].Seg == PciRootBridgeIo->SegmentNumber) &&
(mRomImageTable[Index].Bus == PciIoDevice->BusNumber) &&
(mRomImageTable[Index].Dev == PciIoDevice->DeviceNumber) &&
(mRomImageTable[Index].Func == PciIoDevice->FunctionNumber))
{
if (mRomImageTable[Index].ImageHandle != NULL) {
AddDriver (PciIoDevice, mRomImageTable[Index].ImageHandle, NULL);
}
PciIoDevice->PciIo.RomImage = mRomImageTable[Index].RomImage;
PciIoDevice->PciIo.RomSize = mRomImageTable[Index].RomSize;
return TRUE;

2
MdeModulePkg/Bus/Pci/PciBusDxe/PciRomTable.h
View File

@@ -42,7 +42,7 @@ PciRomAddImageMapping (
**/
BOOLEAN
PciRomGetImageMapping (
IN PCI_IO_DEVICE *PciIoDevice
IN PCI_IO_DEVICE *PciIoDevice
);
#endif

1386
MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c
View File

File diff suppressed because it is too large Load Diff

81
MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.h
View File

@@ -10,7 +10,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#ifndef _PCI_HOST_BRIDGE_H_
#define _PCI_HOST_BRIDGE_H_
#include <PiDxe.h>
#include <IndustryStandard/Acpi.h>
#include <Library/UefiDriverEntryPoint.h>
@@ -21,27 +20,28 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include "PciRootBridge.h"
#define PCI_HOST_BRIDGE_SIGNATURE SIGNATURE_32 ('p', 'h', 'b', 'g')
#define PCI_HOST_BRIDGE_SIGNATURE SIGNATURE_32 ('p', 'h', 'b', 'g')
typedef struct {
UINTN Signature;
EFI_HANDLE Handle;
LIST_ENTRY RootBridges;
BOOLEAN CanRestarted;
EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL ResAlloc;
UINTN Signature;
EFI_HANDLE Handle;
LIST_ENTRY RootBridges;
BOOLEAN CanRestarted;
EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL ResAlloc;
} PCI_HOST_BRIDGE_INSTANCE;
#define PCI_HOST_BRIDGE_FROM_THIS(a) CR (a, PCI_HOST_BRIDGE_INSTANCE, ResAlloc, PCI_HOST_BRIDGE_SIGNATURE)
#define PCI_HOST_BRIDGE_FROM_THIS(a) CR (a, PCI_HOST_BRIDGE_INSTANCE, ResAlloc, PCI_HOST_BRIDGE_SIGNATURE)
//
// Macros to translate device address to host address and vice versa. According
// to UEFI 2.7, device address = host address + translation offset.
//
#define TO_HOST_ADDRESS(DeviceAddress,TranslationOffset) ((DeviceAddress) - (TranslationOffset))
#define TO_DEVICE_ADDRESS(HostAddress,TranslationOffset) ((HostAddress) + (TranslationOffset))
#define TO_HOST_ADDRESS(DeviceAddress, TranslationOffset) ((DeviceAddress) - (TranslationOffset))
#define TO_DEVICE_ADDRESS(HostAddress, TranslationOffset) ((HostAddress) + (TranslationOffset))
//
// Driver Entry Point
//
/**
Entry point of this driver.
@@ -56,13 +56,14 @@ typedef struct {
EFI_STATUS
EFIAPI
InitializePciHostBridge (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
);
//
// HostBridge Resource Allocation interface
//
/**
Enter a certain phase of the PCI enumeration process.
@@ -78,8 +79,8 @@ InitializePciHostBridge (
EFI_STATUS
EFIAPI
NotifyPhase (
IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase
IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase
);
/**
@@ -101,8 +102,8 @@ NotifyPhase (
EFI_STATUS
EFIAPI
GetNextRootBridge (
IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
IN OUT EFI_HANDLE *RootBridgeHandle
IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
IN OUT EFI_HANDLE *RootBridgeHandle
);
/**
@@ -124,9 +125,9 @@ GetNextRootBridge (
EFI_STATUS
EFIAPI
GetAttributes (
IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
IN EFI_HANDLE RootBridgeHandle,
OUT UINT64 *Attributes
IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
IN EFI_HANDLE RootBridgeHandle,
OUT UINT64 *Attributes
);
/**
@@ -146,9 +147,9 @@ GetAttributes (
EFI_STATUS
EFIAPI
StartBusEnumeration (
IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
IN EFI_HANDLE RootBridgeHandle,
OUT VOID **Configuration
IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
IN EFI_HANDLE RootBridgeHandle,
OUT VOID **Configuration
);
/**
@@ -167,9 +168,9 @@ StartBusEnumeration (
EFI_STATUS
EFIAPI
SetBusNumbers (
IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
IN EFI_HANDLE RootBridgeHandle,
IN VOID *Configuration
IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
IN EFI_HANDLE RootBridgeHandle,
IN VOID *Configuration
);
/**
@@ -188,9 +189,9 @@ SetBusNumbers (
EFI_STATUS
EFIAPI
SubmitResources (
IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
IN EFI_HANDLE RootBridgeHandle,
IN VOID *Configuration
IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
IN EFI_HANDLE RootBridgeHandle,
IN VOID *Configuration
);
/**
@@ -211,9 +212,9 @@ SubmitResources (
EFI_STATUS
EFIAPI
GetProposedResources (
IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
IN EFI_HANDLE RootBridgeHandle,
OUT VOID **Configuration
IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
IN EFI_HANDLE RootBridgeHandle,
OUT VOID **Configuration
);
/**
@@ -233,10 +234,10 @@ GetProposedResources (
EFI_STATUS
EFIAPI
PreprocessController (
IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
IN EFI_HANDLE RootBridgeHandle,
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,
IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase
IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
IN EFI_HANDLE RootBridgeHandle,
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,
IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase
);
/**
@@ -246,7 +247,7 @@ PreprocessController (
**/
VOID
ResourceConflict (
IN PCI_HOST_BRIDGE_INSTANCE *HostBridge
IN PCI_HOST_BRIDGE_INSTANCE *HostBridge
);
/**
@@ -259,11 +260,11 @@ ResourceConflict (
**/
UINT64
GetTranslationByResourceType (
IN PCI_ROOT_BRIDGE_INSTANCE *RootBridge,
IN PCI_RESOURCE_TYPE ResourceType
IN PCI_ROOT_BRIDGE_INSTANCE *RootBridge,
IN PCI_RESOURCE_TYPE ResourceType
);
extern EFI_CPU_IO2_PROTOCOL *mCpuIo;
extern EDKII_IOMMU_PROTOCOL *mIoMmu;
extern EFI_CPU_IO2_PROTOCOL *mCpuIo;
extern EDKII_IOMMU_PROTOCOL *mIoMmu;
#endif

15
MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostResource.h
View File

@@ -6,15 +6,16 @@ Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _PCI_HOST_RESOURCE_H_
#define _PCI_HOST_RESOURCE_H_
#include <PiDxe.h>
#define PCI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFEULL
#define PCI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFEULL
typedef enum {
TypeIo = 0,
TypeIo = 0,
TypeMem32,
TypePMem32,
TypeMem64,
@@ -31,14 +32,14 @@ typedef enum {
} RES_STATUS;
typedef struct {
PCI_RESOURCE_TYPE Type;
PCI_RESOURCE_TYPE Type;
//
// Base is a host address
//
UINT64 Base;
UINT64 Length;
UINT64 Alignment;
RES_STATUS Status;
UINT64 Base;
UINT64 Length;
UINT64 Alignment;
RES_STATUS Status;
} PCI_RES_NODE;
#endif

80
MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridge.h
View File

@@ -31,7 +31,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/TimerLib.h>
#include "PciHostResource.h"
typedef enum {
IoOperation,
MemOperation,
@@ -40,46 +39,46 @@ typedef enum {
#define MAP_INFO_SIGNATURE SIGNATURE_32 ('_', 'm', 'a', 'p')
typedef struct {
UINT32 Signature;
LIST_ENTRY Link;
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation;
UINTN NumberOfBytes;
UINTN NumberOfPages;
EFI_PHYSICAL_ADDRESS HostAddress;
EFI_PHYSICAL_ADDRESS MappedHostAddress;
UINT32 Signature;
LIST_ENTRY Link;
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation;
UINTN NumberOfBytes;
UINTN NumberOfPages;
EFI_PHYSICAL_ADDRESS HostAddress;
EFI_PHYSICAL_ADDRESS MappedHostAddress;
} MAP_INFO;
#define MAP_INFO_FROM_LINK(a) CR (a, MAP_INFO, Link, MAP_INFO_SIGNATURE)
#define MAP_INFO_FROM_LINK(a) CR (a, MAP_INFO, Link, MAP_INFO_SIGNATURE)
#define PCI_ROOT_BRIDGE_SIGNATURE SIGNATURE_32 ('_', 'p', 'r', 'b')
#define PCI_ROOT_BRIDGE_SIGNATURE SIGNATURE_32 ('_', 'p', 'r', 'b')
typedef struct {
UINT32 Signature;
LIST_ENTRY Link;
EFI_HANDLE Handle;
UINT64 AllocationAttributes;
UINT64 Attributes;
UINT64 Supports;
PCI_RES_NODE ResAllocNode[TypeMax];
PCI_ROOT_BRIDGE_APERTURE Bus;
PCI_ROOT_BRIDGE_APERTURE Io;
PCI_ROOT_BRIDGE_APERTURE Mem;
PCI_ROOT_BRIDGE_APERTURE PMem;
PCI_ROOT_BRIDGE_APERTURE MemAbove4G;
PCI_ROOT_BRIDGE_APERTURE PMemAbove4G;
BOOLEAN DmaAbove4G;
BOOLEAN NoExtendedConfigSpace;
VOID *ConfigBuffer;
EFI_DEVICE_PATH_PROTOCOL *DevicePath;
CHAR16 *DevicePathStr;
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL RootBridgeIo;
UINT32 Signature;
LIST_ENTRY Link;
EFI_HANDLE Handle;
UINT64 AllocationAttributes;
UINT64 Attributes;
UINT64 Supports;
PCI_RES_NODE ResAllocNode[TypeMax];
PCI_ROOT_BRIDGE_APERTURE Bus;
PCI_ROOT_BRIDGE_APERTURE Io;
PCI_ROOT_BRIDGE_APERTURE Mem;
PCI_ROOT_BRIDGE_APERTURE PMem;
PCI_ROOT_BRIDGE_APERTURE MemAbove4G;
PCI_ROOT_BRIDGE_APERTURE PMemAbove4G;
BOOLEAN DmaAbove4G;
BOOLEAN NoExtendedConfigSpace;
VOID *ConfigBuffer;
EFI_DEVICE_PATH_PROTOCOL *DevicePath;
CHAR16 *DevicePathStr;
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL RootBridgeIo;
BOOLEAN ResourceSubmitted;
LIST_ENTRY Maps;
BOOLEAN ResourceSubmitted;
LIST_ENTRY Maps;
} PCI_ROOT_BRIDGE_INSTANCE;
#define ROOT_BRIDGE_FROM_THIS(a) CR (a, PCI_ROOT_BRIDGE_INSTANCE, RootBridgeIo, PCI_ROOT_BRIDGE_SIGNATURE)
#define ROOT_BRIDGE_FROM_THIS(a) CR (a, PCI_ROOT_BRIDGE_INSTANCE, RootBridgeIo, PCI_ROOT_BRIDGE_SIGNATURE)
#define ROOT_BRIDGE_FROM_LINK(a) CR (a, PCI_ROOT_BRIDGE_INSTANCE, Link, PCI_ROOT_BRIDGE_SIGNATURE)
#define ROOT_BRIDGE_FROM_LINK(a) CR (a, PCI_ROOT_BRIDGE_INSTANCE, Link, PCI_ROOT_BRIDGE_SIGNATURE)
/**
Construct the Pci Root Bridge instance.
@@ -91,12 +90,13 @@ typedef struct {
**/
PCI_ROOT_BRIDGE_INSTANCE *
CreateRootBridge (
IN PCI_ROOT_BRIDGE *Bridge
IN PCI_ROOT_BRIDGE *Bridge
);
//
// Protocol Member Function Prototypes
//
/**
Poll an address in memory mapped space until an exit condition is met
@@ -286,11 +286,11 @@ RootBridgeIoIoWrite (
EFI_STATUS
EFIAPI
RootBridgeIoCopyMem (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 DestAddress,
IN UINT64 SrcAddress,
IN UINTN Count
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 DestAddress,
IN UINT64 SrcAddress,
IN UINTN Count
)
;
@@ -567,5 +567,5 @@ RootBridgeIoConfiguration (
)
;
extern EFI_CPU_IO2_PROTOCOL *mCpuIo;
extern EFI_CPU_IO2_PROTOCOL *mCpuIo;
#endif

586
MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
View File

File diff suppressed because it is too large Load Diff

51
MdeModulePkg/Bus/Pci/PciSioSerialDxe/ComponentName.c
View File

@@ -20,14 +20,13 @@ GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME_PROTOCOL gPciSioSerialComponen
//
// EFI Component Name 2 Protocol
//
GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gPciSioSerialComponentName2 = {
(EFI_COMPONENT_NAME2_GET_DRIVER_NAME) SerialComponentNameGetDriverName,
(EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME) SerialComponentNameGetControllerName,
GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gPciSioSerialComponentName2 = {
(EFI_COMPONENT_NAME2_GET_DRIVER_NAME)SerialComponentNameGetDriverName,
(EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME)SerialComponentNameGetControllerName,
"en"
};
GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mSerialDriverNameTable[] = {
GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mSerialDriverNameTable[] = {
{
"eng;en",
L"PCI SIO Serial Driver"
@@ -165,11 +164,11 @@ SerialComponentNameGetDriverName (
EFI_STATUS
EFIAPI
SerialComponentNameGetControllerName (
IN EFI_COMPONENT_NAME_PROTOCOL *This,
IN EFI_HANDLE ControllerHandle,
IN EFI_HANDLE ChildHandle OPTIONAL,
IN CHAR8 *Language,
OUT CHAR16 **ControllerName
IN EFI_COMPONENT_NAME_PROTOCOL *This,
IN EFI_HANDLE ControllerHandle,
IN EFI_HANDLE ChildHandle OPTIONAL,
IN CHAR8 *Language,
OUT CHAR16 **ControllerName
)
{
EFI_STATUS Status;
@@ -182,18 +181,18 @@ SerialComponentNameGetControllerName (
// Make sure this driver is currently managing ControllerHandle
//
IoProtocolGuid = &gEfiSioProtocolGuid;
Status = EfiTestManagedDevice (
ControllerHandle,
gSerialControllerDriver.DriverBindingHandle,
IoProtocolGuid
);
Status = EfiTestManagedDevice (
ControllerHandle,
gSerialControllerDriver.DriverBindingHandle,
IoProtocolGuid
);
if (EFI_ERROR (Status)) {
IoProtocolGuid = &gEfiPciIoProtocolGuid;
Status = EfiTestManagedDevice (
ControllerHandle,
gSerialControllerDriver.DriverBindingHandle,
IoProtocolGuid
);
Status = EfiTestManagedDevice (
ControllerHandle,
gSerialControllerDriver.DriverBindingHandle,
IoProtocolGuid
);
}
if (EFI_ERROR (Status)) {
@@ -217,7 +216,7 @@ SerialComponentNameGetControllerName (
Status = gBS->OpenProtocol (
ChildHandle,
&gEfiSerialIoProtocolGuid,
(VOID **) &SerialIo,
(VOID **)&SerialIo,
gSerialControllerDriver.DriverBindingHandle,
ChildHandle,
EFI_OPEN_PROTOCOL_GET_PROTOCOL
@@ -229,7 +228,7 @@ SerialComponentNameGetControllerName (
//
// Get the Serial Controller's Device structure
//
SerialDevice = SERIAL_DEV_FROM_THIS (SerialIo);
SerialDevice = SERIAL_DEV_FROM_THIS (SerialIo);
ControllerNameTable = SerialDevice->ControllerNameTable;
}
@@ -250,11 +249,12 @@ SerialComponentNameGetControllerName (
**/
VOID
AddName (
IN SERIAL_DEV *SerialDevice,
IN UINT32 Instance
IN SERIAL_DEV *SerialDevice,
IN UINT32 Instance
)
{
CHAR16 SerialPortName[SERIAL_PORT_NAME_LEN];
CHAR16 SerialPortName[SERIAL_PORT_NAME_LEN];
UnicodeSPrint (
SerialPortName,
sizeof (SerialPortName),
@@ -275,5 +275,4 @@ AddName (
SerialPortName,
FALSE
);
}

671
MdeModulePkg/Bus/Pci/PciSioSerialDxe/Serial.c
View File

File diff suppressed because it is too large Load Diff

386
MdeModulePkg/Bus/Pci/PciSioSerialDxe/Serial.h
View File

@@ -9,7 +9,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#ifndef _SERIAL_H_
#define _SERIAL_H_
#include <Uefi.h>
#include <IndustryStandard/Pci.h>
@@ -34,13 +33,13 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
//
// Driver Binding Externs
//
extern EFI_DRIVER_BINDING_PROTOCOL gSerialControllerDriver;
extern EFI_COMPONENT_NAME_PROTOCOL gPciSioSerialComponentName;
extern EFI_COMPONENT_NAME2_PROTOCOL gPciSioSerialComponentName2;
extern EFI_DRIVER_BINDING_PROTOCOL gSerialControllerDriver;
extern EFI_COMPONENT_NAME_PROTOCOL gPciSioSerialComponentName;
extern EFI_COMPONENT_NAME2_PROTOCOL gPciSioSerialComponentName2;
#define SIO_SERIAL_PORT_NAME L"SIO Serial Port #%d"
#define PCI_SERIAL_PORT_NAME L"PCI Serial Port #%d"
#define SERIAL_PORT_NAME_LEN (sizeof (SIO_SERIAL_PORT_NAME) / sizeof (CHAR16) + MAXIMUM_VALUE_CHARACTERS)
#define SIO_SERIAL_PORT_NAME L"SIO Serial Port #%d"
#define PCI_SERIAL_PORT_NAME L"PCI Serial Port #%d"
#define SERIAL_PORT_NAME_LEN (sizeof (SIO_SERIAL_PORT_NAME) / sizeof (CHAR16) + MAXIMUM_VALUE_CHARACTERS)
//
// Internal Data Structures
@@ -61,73 +60,73 @@ extern EFI_COMPONENT_NAME2_PROTOCOL gPciSioSerialComponentName2;
/// RegisterStride equals to 4.
///
typedef struct {
UINT16 VendorId; ///< Vendor ID to match the PCI device. The value 0xFFFF terminates the list of entries.
UINT16 DeviceId; ///< Device ID to match the PCI device
UINT32 ClockRate; ///< UART clock rate. Set to 0 for default clock rate of 1843200 Hz
UINT64 Offset; ///< The byte offset into to the BAR
UINT8 BarIndex; ///< Which BAR to get the UART base address
UINT8 RegisterStride; ///< UART register stride in bytes. Set to 0 for default register stride of 1 byte.
UINT16 ReceiveFifoDepth; ///< UART receive FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.
UINT16 TransmitFifoDepth; ///< UART transmit FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.
UINT8 Reserved[2];
UINT16 VendorId; ///< Vendor ID to match the PCI device. The value 0xFFFF terminates the list of entries.
UINT16 DeviceId; ///< Device ID to match the PCI device
UINT32 ClockRate; ///< UART clock rate. Set to 0 for default clock rate of 1843200 Hz
UINT64 Offset; ///< The byte offset into to the BAR
UINT8 BarIndex; ///< Which BAR to get the UART base address
UINT8 RegisterStride; ///< UART register stride in bytes. Set to 0 for default register stride of 1 byte.
UINT16 ReceiveFifoDepth; ///< UART receive FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.
UINT16 TransmitFifoDepth; ///< UART transmit FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.
UINT8 Reserved[2];
} PCI_SERIAL_PARAMETER;
#pragma pack()
#define SERIAL_MAX_FIFO_SIZE 17 ///< Actual FIFO size is 16. FIFO based on circular wastes one unit.
#define SERIAL_MAX_FIFO_SIZE 17 ///< Actual FIFO size is 16. FIFO based on circular wastes one unit.
typedef struct {
UINT16 Head; ///< Head pointer of the FIFO. Empty when (Head == Tail).
UINT16 Tail; ///< Tail pointer of the FIFO. Full when ((Tail + 1) % SERIAL_MAX_FIFO_SIZE == Head).
UINT8 Data[SERIAL_MAX_FIFO_SIZE]; ///< Store the FIFO data.
UINT16 Head; ///< Head pointer of the FIFO. Empty when (Head == Tail).
UINT16 Tail; ///< Tail pointer of the FIFO. Full when ((Tail + 1) % SERIAL_MAX_FIFO_SIZE == Head).
UINT8 Data[SERIAL_MAX_FIFO_SIZE]; ///< Store the FIFO data.
} SERIAL_DEV_FIFO;
typedef union {
EFI_PCI_IO_PROTOCOL *PciIo;
EFI_SIO_PROTOCOL *Sio;
EFI_PCI_IO_PROTOCOL *PciIo;
EFI_SIO_PROTOCOL *Sio;
} PARENT_IO_PROTOCOL_PTR;
typedef struct {
EFI_PCI_IO_PROTOCOL *PciIo; // Pointer to parent PciIo instance.
UINTN ChildCount; // Count of child SerialIo instance.
UINT64 PciAttributes; // Original PCI attributes.
EFI_PCI_IO_PROTOCOL *PciIo; // Pointer to parent PciIo instance.
UINTN ChildCount; // Count of child SerialIo instance.
UINT64 PciAttributes; // Original PCI attributes.
} PCI_DEVICE_INFO;
typedef struct {
UINT32 Signature;
EFI_HANDLE Handle;
EFI_SERIAL_IO_PROTOCOL SerialIo;
EFI_SERIAL_IO_MODE SerialMode;
EFI_DEVICE_PATH_PROTOCOL *DevicePath;
UINT32 Signature;
EFI_HANDLE Handle;
EFI_SERIAL_IO_PROTOCOL SerialIo;
EFI_SERIAL_IO_MODE SerialMode;
EFI_DEVICE_PATH_PROTOCOL *DevicePath;
EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath;
UART_DEVICE_PATH UartDevicePath;
EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath;
UART_DEVICE_PATH UartDevicePath;
EFI_PHYSICAL_ADDRESS BaseAddress; ///< UART base address
BOOLEAN MmioAccess; ///< TRUE for MMIO, FALSE for IO
UINT8 RegisterStride; ///< UART Register Stride
UINT32 ClockRate; ///< UART clock rate
EFI_PHYSICAL_ADDRESS BaseAddress; ///< UART base address
BOOLEAN MmioAccess; ///< TRUE for MMIO, FALSE for IO
UINT8 RegisterStride; ///< UART Register Stride
UINT32 ClockRate; ///< UART clock rate
UINT16 ReceiveFifoDepth; ///< UART receive FIFO depth in bytes.
SERIAL_DEV_FIFO Receive; ///< The FIFO used to store received data
UINT16 ReceiveFifoDepth; ///< UART receive FIFO depth in bytes.
SERIAL_DEV_FIFO Receive; ///< The FIFO used to store received data
UINT16 TransmitFifoDepth; ///< UART transmit FIFO depth in bytes.
SERIAL_DEV_FIFO Transmit; ///< The FIFO used to store to-transmit data
UINT16 TransmitFifoDepth; ///< UART transmit FIFO depth in bytes.
SERIAL_DEV_FIFO Transmit; ///< The FIFO used to store to-transmit data
BOOLEAN SoftwareLoopbackEnable;
BOOLEAN HardwareFlowControl;
EFI_UNICODE_STRING_TABLE *ControllerNameTable;
BOOLEAN ContainsControllerNode; ///< TRUE if the device produced contains Controller node
UINT32 Instance;
PCI_DEVICE_INFO *PciDeviceInfo;
BOOLEAN SoftwareLoopbackEnable;
BOOLEAN HardwareFlowControl;
EFI_UNICODE_STRING_TABLE *ControllerNameTable;
BOOLEAN ContainsControllerNode; ///< TRUE if the device produced contains Controller node
UINT32 Instance;
PCI_DEVICE_INFO *PciDeviceInfo;
} SERIAL_DEV;
#define SERIAL_DEV_SIGNATURE SIGNATURE_32 ('s', 'e', 'r', 'd')
#define SERIAL_DEV_FROM_THIS(a) CR (a, SERIAL_DEV, SerialIo, SERIAL_DEV_SIGNATURE)
#define SERIAL_DEV_SIGNATURE SIGNATURE_32 ('s', 'e', 'r', 'd')
#define SERIAL_DEV_FROM_THIS(a) CR (a, SERIAL_DEV, SerialIo, SERIAL_DEV_SIGNATURE)
//
// Serial Driver Defaults
//
#define SERIAL_PORT_DEFAULT_TIMEOUT 1000000
#define SERIAL_PORT_SUPPORT_CONTROL_MASK (EFI_SERIAL_CLEAR_TO_SEND | \
#define SERIAL_PORT_DEFAULT_TIMEOUT 1000000
#define SERIAL_PORT_SUPPORT_CONTROL_MASK (EFI_SERIAL_CLEAR_TO_SEND | \
EFI_SERIAL_DATA_SET_READY | \
EFI_SERIAL_RING_INDICATE | \
EFI_SERIAL_CARRIER_DETECT | \
@@ -139,23 +138,23 @@ typedef struct {
EFI_SERIAL_OUTPUT_BUFFER_EMPTY | \
EFI_SERIAL_INPUT_BUFFER_EMPTY)
#define SERIAL_PORT_MIN_TIMEOUT 1 // 1 uS
#define SERIAL_PORT_MAX_TIMEOUT 100000000 // 100 seconds
#define SERIAL_PORT_MIN_TIMEOUT 1 // 1 uS
#define SERIAL_PORT_MAX_TIMEOUT 100000000 // 100 seconds
//
// UART Registers
//
#define SERIAL_REGISTER_THR 0 ///< WO Transmit Holding Register
#define SERIAL_REGISTER_RBR 0 ///< RO Receive Buffer Register
#define SERIAL_REGISTER_DLL 0 ///< R/W Divisor Latch LSB
#define SERIAL_REGISTER_DLM 1 ///< R/W Divisor Latch MSB
#define SERIAL_REGISTER_IER 1 ///< R/W Interrupt Enable Register
#define SERIAL_REGISTER_IIR 2 ///< RO Interrupt Identification Register
#define SERIAL_REGISTER_FCR 2 ///< WO FIFO Cotrol Register
#define SERIAL_REGISTER_LCR 3 ///< R/W Line Control Register
#define SERIAL_REGISTER_MCR 4 ///< R/W Modem Control Register
#define SERIAL_REGISTER_LSR 5 ///< R/W Line Status Register
#define SERIAL_REGISTER_MSR 6 ///< R/W Modem Status Register
#define SERIAL_REGISTER_SCR 7 ///< R/W Scratch Pad Register
#define SERIAL_REGISTER_THR 0 ///< WO Transmit Holding Register
#define SERIAL_REGISTER_RBR 0 ///< RO Receive Buffer Register
#define SERIAL_REGISTER_DLL 0 ///< R/W Divisor Latch LSB
#define SERIAL_REGISTER_DLM 1 ///< R/W Divisor Latch MSB
#define SERIAL_REGISTER_IER 1 ///< R/W Interrupt Enable Register
#define SERIAL_REGISTER_IIR 2 ///< RO Interrupt Identification Register
#define SERIAL_REGISTER_FCR 2 ///< WO FIFO Cotrol Register
#define SERIAL_REGISTER_LCR 3 ///< R/W Line Control Register
#define SERIAL_REGISTER_MCR 4 ///< R/W Modem Control Register
#define SERIAL_REGISTER_LSR 5 ///< R/W Line Status Register
#define SERIAL_REGISTER_MSR 6 ///< R/W Modem Status Register
#define SERIAL_REGISTER_SCR 7 ///< R/W Scratch Pad Register
#pragma pack(1)
///
@@ -163,13 +162,13 @@ typedef struct {
///
typedef union {
struct {
UINT8 Ravie : 1; ///< Receiver Data Available Interrupt Enable
UINT8 Theie : 1; ///< Transmistter Holding Register Empty Interrupt Enable
UINT8 Rie : 1; ///< Receiver Interrupt Enable
UINT8 Mie : 1; ///< Modem Interrupt Enable
UINT8 Reserved : 4;
UINT8 Ravie : 1; ///< Receiver Data Available Interrupt Enable
UINT8 Theie : 1; ///< Transmistter Holding Register Empty Interrupt Enable
UINT8 Rie : 1; ///< Receiver Interrupt Enable
UINT8 Mie : 1; ///< Modem Interrupt Enable
UINT8 Reserved : 4;
} Bits;
UINT8 Data;
UINT8 Data;
} SERIAL_PORT_IER;
///
@@ -177,15 +176,15 @@ typedef union {
///
typedef union {
struct {
UINT8 TrFIFOE : 1; ///< Transmit and Receive FIFO Enable
UINT8 ResetRF : 1; ///< Reset Reciever FIFO
UINT8 ResetTF : 1; ///< Reset Transmistter FIFO
UINT8 Dms : 1; ///< DMA Mode Select
UINT8 Reserved : 1;
UINT8 TrFIFO64 : 1; ///< Enable 64 byte FIFO
UINT8 Rtb : 2; ///< Receive Trigger Bits
UINT8 TrFIFOE : 1; ///< Transmit and Receive FIFO Enable
UINT8 ResetRF : 1; ///< Reset Reciever FIFO
UINT8 ResetTF : 1; ///< Reset Transmistter FIFO
UINT8 Dms : 1; ///< DMA Mode Select
UINT8 Reserved : 1;
UINT8 TrFIFO64 : 1; ///< Enable 64 byte FIFO
UINT8 Rtb : 2; ///< Receive Trigger Bits
} Bits;
UINT8 Data;
UINT8 Data;
} SERIAL_PORT_FCR;
///
@@ -193,15 +192,15 @@ typedef union {
///
typedef union {
struct {
UINT8 SerialDB : 2; ///< Number of Serial Data Bits
UINT8 StopB : 1; ///< Number of Stop Bits
UINT8 ParEn : 1; ///< Parity Enable
UINT8 EvenPar : 1; ///< Even Parity Select
UINT8 SticPar : 1; ///< Sticky Parity
UINT8 BrCon : 1; ///< Break Control
UINT8 DLab : 1; ///< Divisor Latch Access Bit
UINT8 SerialDB : 2; ///< Number of Serial Data Bits
UINT8 StopB : 1; ///< Number of Stop Bits
UINT8 ParEn : 1; ///< Parity Enable
UINT8 EvenPar : 1; ///< Even Parity Select
UINT8 SticPar : 1; ///< Sticky Parity
UINT8 BrCon : 1; ///< Break Control
UINT8 DLab : 1; ///< Divisor Latch Access Bit
} Bits;
UINT8 Data;
UINT8 Data;
} SERIAL_PORT_LCR;
///
@@ -209,14 +208,14 @@ typedef union {
///
typedef union {
struct {
UINT8 DtrC : 1; ///< Data Terminal Ready Control
UINT8 Rts : 1; ///< Request To Send Control
UINT8 Out1 : 1; ///< Output1
UINT8 Out2 : 1; ///< Output2, used to disable interrupt
UINT8 Lme : 1; ///< Loopback Mode Enable
UINT8 Reserved : 3;
UINT8 DtrC : 1; ///< Data Terminal Ready Control
UINT8 Rts : 1; ///< Request To Send Control
UINT8 Out1 : 1; ///< Output1
UINT8 Out2 : 1; ///< Output2, used to disable interrupt
UINT8 Lme : 1; ///< Loopback Mode Enable
UINT8 Reserved : 3;
} Bits;
UINT8 Data;
UINT8 Data;
} SERIAL_PORT_MCR;
///
@@ -224,16 +223,16 @@ typedef union {
///
typedef union {
struct {
UINT8 Dr : 1; ///< Receiver Data Ready Status
UINT8 Oe : 1; ///< Overrun Error Status
UINT8 Pe : 1; ///< Parity Error Status
UINT8 Fe : 1; ///< Framing Error Status
UINT8 Bi : 1; ///< Break Interrupt Status
UINT8 Thre : 1; ///< Transmistter Holding Register Status
UINT8 Temt : 1; ///< Transmitter Empty Status
UINT8 FIFOe : 1; ///< FIFO Error Status
UINT8 Dr : 1; ///< Receiver Data Ready Status
UINT8 Oe : 1; ///< Overrun Error Status
UINT8 Pe : 1; ///< Parity Error Status
UINT8 Fe : 1; ///< Framing Error Status
UINT8 Bi : 1; ///< Break Interrupt Status
UINT8 Thre : 1; ///< Transmistter Holding Register Status
UINT8 Temt : 1; ///< Transmitter Empty Status
UINT8 FIFOe : 1; ///< FIFO Error Status
} Bits;
UINT8 Data;
UINT8 Data;
} SERIAL_PORT_LSR;
///
@@ -241,48 +240,49 @@ typedef union {
///
typedef union {
struct {
UINT8 DeltaCTS : 1; ///< Delta Clear To Send Status
UINT8 DeltaDSR : 1; ///< Delta Data Set Ready Status
UINT8 TrailingEdgeRI : 1; ///< Trailing Edge of Ring Indicator Status
UINT8 DeltaDCD : 1; ///< Delta Data Carrier Detect Status
UINT8 Cts : 1; ///< Clear To Send Status
UINT8 Dsr : 1; ///< Data Set Ready Status
UINT8 Ri : 1; ///< Ring Indicator Status
UINT8 Dcd : 1; ///< Data Carrier Detect Status
UINT8 DeltaCTS : 1; ///< Delta Clear To Send Status
UINT8 DeltaDSR : 1; ///< Delta Data Set Ready Status
UINT8 TrailingEdgeRI : 1; ///< Trailing Edge of Ring Indicator Status
UINT8 DeltaDCD : 1; ///< Delta Data Carrier Detect Status
UINT8 Cts : 1; ///< Clear To Send Status
UINT8 Dsr : 1; ///< Data Set Ready Status
UINT8 Ri : 1; ///< Ring Indicator Status
UINT8 Dcd : 1; ///< Data Carrier Detect Status
} Bits;
UINT8 Data;
UINT8 Data;
} SERIAL_PORT_MSR;
#pragma pack()
//
// Define serial register I/O macros
//
#define READ_RBR(S) SerialReadRegister (S, SERIAL_REGISTER_RBR)
#define READ_DLL(S) SerialReadRegister (S, SERIAL_REGISTER_DLL)
#define READ_DLM(S) SerialReadRegister (S, SERIAL_REGISTER_DLM)
#define READ_IER(S) SerialReadRegister (S, SERIAL_REGISTER_IER)
#define READ_IIR(S) SerialReadRegister (S, SERIAL_REGISTER_IIR)
#define READ_LCR(S) SerialReadRegister (S, SERIAL_REGISTER_LCR)
#define READ_MCR(S) SerialReadRegister (S, SERIAL_REGISTER_MCR)
#define READ_LSR(S) SerialReadRegister (S, SERIAL_REGISTER_LSR)
#define READ_MSR(S) SerialReadRegister (S, SERIAL_REGISTER_MSR)
#define READ_SCR(S) SerialReadRegister (S, SERIAL_REGISTER_SCR)
#define READ_RBR(S) SerialReadRegister (S, SERIAL_REGISTER_RBR)
#define READ_DLL(S) SerialReadRegister (S, SERIAL_REGISTER_DLL)
#define READ_DLM(S) SerialReadRegister (S, SERIAL_REGISTER_DLM)
#define READ_IER(S) SerialReadRegister (S, SERIAL_REGISTER_IER)
#define READ_IIR(S) SerialReadRegister (S, SERIAL_REGISTER_IIR)
#define READ_LCR(S) SerialReadRegister (S, SERIAL_REGISTER_LCR)
#define READ_MCR(S) SerialReadRegister (S, SERIAL_REGISTER_MCR)
#define READ_LSR(S) SerialReadRegister (S, SERIAL_REGISTER_LSR)
#define READ_MSR(S) SerialReadRegister (S, SERIAL_REGISTER_MSR)
#define READ_SCR(S) SerialReadRegister (S, SERIAL_REGISTER_SCR)
#define WRITE_THR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_THR, D)
#define WRITE_DLL(S, D) SerialWriteRegister (S, SERIAL_REGISTER_DLL, D)
#define WRITE_DLM(S, D) SerialWriteRegister (S, SERIAL_REGISTER_DLM, D)
#define WRITE_IER(S, D) SerialWriteRegister (S, SERIAL_REGISTER_IER, D)
#define WRITE_FCR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_FCR, D)
#define WRITE_LCR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_LCR, D)
#define WRITE_MCR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_MCR, D)
#define WRITE_LSR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_LSR, D)
#define WRITE_MSR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_MSR, D)
#define WRITE_SCR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_SCR, D)
#define WRITE_THR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_THR, D)
#define WRITE_DLL(S, D) SerialWriteRegister (S, SERIAL_REGISTER_DLL, D)
#define WRITE_DLM(S, D) SerialWriteRegister (S, SERIAL_REGISTER_DLM, D)
#define WRITE_IER(S, D) SerialWriteRegister (S, SERIAL_REGISTER_IER, D)
#define WRITE_FCR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_FCR, D)
#define WRITE_LCR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_LCR, D)
#define WRITE_MCR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_MCR, D)
#define WRITE_LSR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_LSR, D)
#define WRITE_MSR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_MSR, D)
#define WRITE_SCR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_SCR, D)
//
// Prototypes
// Driver model protocol interface
//
/**
Check to see if this driver supports the given controller
@@ -296,9 +296,9 @@ typedef union {
EFI_STATUS
EFIAPI
SerialControllerDriverSupported (
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
);
/**
@@ -313,9 +313,9 @@ SerialControllerDriverSupported (
EFI_STATUS
EFIAPI
SerialControllerDriverStart (
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
);
/**
@@ -333,15 +333,16 @@ SerialControllerDriverStart (
EFI_STATUS
EFIAPI
SerialControllerDriverStop (
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN UINTN NumberOfChildren,
IN EFI_HANDLE *ChildHandleBuffer
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN UINTN NumberOfChildren,
IN EFI_HANDLE *ChildHandleBuffer
);
//
// Serial I/O Protocol Interface
//
/**
Reset serial device.
@@ -354,7 +355,7 @@ SerialControllerDriverStop (
EFI_STATUS
EFIAPI
SerialReset (
IN EFI_SERIAL_IO_PROTOCOL *This
IN EFI_SERIAL_IO_PROTOCOL *This
);
/**
@@ -377,13 +378,13 @@ SerialReset (
EFI_STATUS
EFIAPI
SerialSetAttributes (
IN EFI_SERIAL_IO_PROTOCOL *This,
IN UINT64 BaudRate,
IN UINT32 ReceiveFifoDepth,
IN UINT32 Timeout,
IN EFI_PARITY_TYPE Parity,
IN UINT8 DataBits,
IN EFI_STOP_BITS_TYPE StopBits
IN EFI_SERIAL_IO_PROTOCOL *This,
IN UINT64 BaudRate,
IN UINT32 ReceiveFifoDepth,
IN UINT32 Timeout,
IN EFI_PARITY_TYPE Parity,
IN UINT8 DataBits,
IN EFI_STOP_BITS_TYPE StopBits
);
/**
@@ -399,8 +400,8 @@ SerialSetAttributes (
EFI_STATUS
EFIAPI
SerialSetControl (
IN EFI_SERIAL_IO_PROTOCOL *This,
IN UINT32 Control
IN EFI_SERIAL_IO_PROTOCOL *This,
IN UINT32 Control
);
/**
@@ -415,8 +416,8 @@ SerialSetControl (
EFI_STATUS
EFIAPI
SerialGetControl (
IN EFI_SERIAL_IO_PROTOCOL *This,
OUT UINT32 *Control
IN EFI_SERIAL_IO_PROTOCOL *This,
OUT UINT32 *Control
);
/**
@@ -435,9 +436,9 @@ SerialGetControl (
EFI_STATUS
EFIAPI
SerialWrite (
IN EFI_SERIAL_IO_PROTOCOL *This,
IN OUT UINTN *BufferSize,
IN VOID *Buffer
IN EFI_SERIAL_IO_PROTOCOL *This,
IN OUT UINTN *BufferSize,
IN VOID *Buffer
);
/**
@@ -456,14 +457,15 @@ SerialWrite (
EFI_STATUS
EFIAPI
SerialRead (
IN EFI_SERIAL_IO_PROTOCOL *This,
IN OUT UINTN *BufferSize,
OUT VOID *Buffer
IN EFI_SERIAL_IO_PROTOCOL *This,
IN OUT UINTN *BufferSize,
OUT VOID *Buffer
);
//
// Internal Functions
//
/**
Use scratchpad register to test if this serial port is present.
@@ -473,7 +475,7 @@ SerialRead (
**/
BOOLEAN
SerialPresent (
IN SERIAL_DEV *SerialDevice
IN SERIAL_DEV *SerialDevice
);
/**
@@ -486,7 +488,7 @@ SerialPresent (
**/
BOOLEAN
SerialFifoFull (
IN SERIAL_DEV_FIFO *Fifo
IN SERIAL_DEV_FIFO *Fifo
);
/**
@@ -499,7 +501,7 @@ SerialFifoFull (
**/
BOOLEAN
SerialFifoEmpty (
IN SERIAL_DEV_FIFO *Fifo
IN SERIAL_DEV_FIFO *Fifo
);
/**
@@ -514,8 +516,8 @@ SerialFifoEmpty (
**/
EFI_STATUS
SerialFifoAdd (
IN SERIAL_DEV_FIFO *Fifo,
IN UINT8 Data
IN SERIAL_DEV_FIFO *Fifo,
IN UINT8 Data
);
/**
@@ -530,8 +532,8 @@ SerialFifoAdd (
**/
EFI_STATUS
SerialFifoRemove (
IN SERIAL_DEV_FIFO *Fifo,
OUT UINT8 *Data
IN SERIAL_DEV_FIFO *Fifo,
OUT UINT8 *Data
);
/**
@@ -546,7 +548,7 @@ SerialFifoRemove (
**/
EFI_STATUS
SerialReceiveTransmit (
IN SERIAL_DEV *SerialDevice
IN SERIAL_DEV *SerialDevice
);
/**
@@ -559,8 +561,8 @@ SerialReceiveTransmit (
**/
UINT8
SerialReadRegister (
IN SERIAL_DEV *SerialDev,
IN UINT32 Offset
IN SERIAL_DEV *SerialDev,
IN UINT32 Offset
);
/**
@@ -572,15 +574,15 @@ SerialReadRegister (
**/
VOID
SerialWriteRegister (
IN SERIAL_DEV *SerialDev,
IN UINT32 Offset,
IN UINT8 Data
IN SERIAL_DEV *SerialDev,
IN UINT32 Offset,
IN UINT8 Data
);
//
// EFI Component Name Functions
//
/**
Retrieves a Unicode string that is the user readable name of the driver.
@@ -628,7 +630,6 @@ SerialComponentNameGetDriverName (
OUT CHAR16 **DriverName
);
/**
Retrieves a Unicode string that is the user readable name of the controller
that is being managed by a driver.
@@ -700,11 +701,11 @@ SerialComponentNameGetDriverName (
EFI_STATUS
EFIAPI
SerialComponentNameGetControllerName (
IN EFI_COMPONENT_NAME_PROTOCOL *This,
IN EFI_HANDLE ControllerHandle,
IN EFI_HANDLE ChildHandle OPTIONAL,
IN CHAR8 *Language,
OUT CHAR16 **ControllerName
IN EFI_COMPONENT_NAME_PROTOCOL *This,
IN EFI_HANDLE ControllerHandle,
IN EFI_HANDLE ChildHandle OPTIONAL,
IN CHAR8 *Language,
OUT CHAR16 **ControllerName
);
/**
@@ -715,8 +716,8 @@ SerialComponentNameGetControllerName (
**/
VOID
AddName (
IN SERIAL_DEV *SerialDevice,
IN UINT32 Uid
IN SERIAL_DEV *SerialDevice,
IN UINT32 Uid
);
/**
@@ -741,13 +742,13 @@ AddName (
**/
BOOLEAN
VerifyUartParameters (
IN UINT32 ClockRate,
IN UINT64 BaudRate,
IN UINT8 DataBits,
IN EFI_PARITY_TYPE Parity,
IN EFI_STOP_BITS_TYPE StopBits,
OUT UINT64 *Divisor,
OUT UINT64 *ActualBaudRate
IN UINT32 ClockRate,
IN UINT64 BaudRate,
IN UINT8 DataBits,
IN EFI_PARITY_TYPE Parity,
IN EFI_STOP_BITS_TYPE StopBits,
OUT UINT64 *Divisor,
OUT UINT64 *ActualBaudRate
);
/**
@@ -762,9 +763,9 @@ VerifyUartParameters (
**/
UART_DEVICE_PATH *
SkipControllerDevicePathNode (
EFI_DEVICE_PATH_PROTOCOL *DevicePath,
BOOLEAN *ContainsControllerNode,
UINT32 *ControllerNumber
EFI_DEVICE_PATH_PROTOCOL *DevicePath,
BOOLEAN *ContainsControllerNode,
UINT32 *ControllerNumber
);
/**
@@ -778,6 +779,7 @@ SkipControllerDevicePathNode (
**/
BOOLEAN
IsUartFlowControlDevicePathNode (
IN UART_FLOW_CONTROL_DEVICE_PATH *FlowControl
IN UART_FLOW_CONTROL_DEVICE_PATH *FlowControl
);
#endif

462
MdeModulePkg/Bus/Pci/PciSioSerialDxe/SerialIo.c
View File

@@ -20,27 +20,31 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
UART_DEVICE_PATH *
SkipControllerDevicePathNode (
EFI_DEVICE_PATH_PROTOCOL *DevicePath,
BOOLEAN *ContainsControllerNode,
UINT32 *ControllerNumber
EFI_DEVICE_PATH_PROTOCOL *DevicePath,
BOOLEAN *ContainsControllerNode,
UINT32 *ControllerNumber
)
{
if ((DevicePathType (DevicePath) == HARDWARE_DEVICE_PATH) &&
(DevicePathSubType (DevicePath) == HW_CONTROLLER_DP)
) {
)
{
if (ContainsControllerNode != NULL) {
*ContainsControllerNode = TRUE;
}
if (ControllerNumber != NULL) {
*ControllerNumber = ((CONTROLLER_DEVICE_PATH *) DevicePath)->ControllerNumber;
*ControllerNumber = ((CONTROLLER_DEVICE_PATH *)DevicePath)->ControllerNumber;
}
DevicePath = NextDevicePathNode (DevicePath);
} else {
if (ContainsControllerNode != NULL) {
*ContainsControllerNode = FALSE;
}
}
return (UART_DEVICE_PATH *) DevicePath;
return (UART_DEVICE_PATH *)DevicePath;
}
/**
@@ -65,26 +69,27 @@ SkipControllerDevicePathNode (
**/
BOOLEAN
VerifyUartParameters (
IN UINT32 ClockRate,
IN UINT64 BaudRate,
IN UINT8 DataBits,
IN EFI_PARITY_TYPE Parity,
IN EFI_STOP_BITS_TYPE StopBits,
OUT UINT64 *Divisor,
OUT UINT64 *ActualBaudRate
IN UINT32 ClockRate,
IN UINT64 BaudRate,
IN UINT8 DataBits,
IN EFI_PARITY_TYPE Parity,
IN EFI_STOP_BITS_TYPE StopBits,
OUT UINT64 *Divisor,
OUT UINT64 *ActualBaudRate
)
{
UINT64 Remainder;
UINT32 ComputedBaudRate;
UINT64 ComputedDivisor;
UINT64 Percent;
UINT64 Remainder;
UINT32 ComputedBaudRate;
UINT64 ComputedDivisor;
UINT64 Percent;
if ((DataBits < 5) || (DataBits > 8) ||
(Parity < NoParity) || (Parity > SpaceParity) ||
(StopBits < OneStopBit) || (StopBits > TwoStopBits) ||
((DataBits == 5) && (StopBits == TwoStopBits)) ||
((DataBits >= 6) && (DataBits <= 8) && (StopBits == OneFiveStopBits))
) {
)
{
return FALSE;
}
@@ -108,6 +113,7 @@ VerifyUartParameters (
if (Remainder >= LShiftU64 (BaudRate, 3)) {
ComputedDivisor++;
}
//
// If the computed divisor is larger than the maximum value that can be programmed
// into the UART, then the requested baud rate can not be supported.
@@ -128,13 +134,13 @@ VerifyUartParameters (
// Actual baud rate that the serial port will be programmed for
// should be with in 4% of requested one.
//
ComputedBaudRate = ClockRate / ((UINT16) ComputedDivisor << 4);
ComputedBaudRate = ClockRate / ((UINT16)ComputedDivisor << 4);
if (ComputedBaudRate == 0) {
return FALSE;
}
Percent = DivU64x32 (MultU64x32 (BaudRate, 100), ComputedBaudRate);
DEBUG ((DEBUG_INFO, "ClockRate = %d\n", ClockRate));
DEBUG ((DEBUG_INFO, "ClockRate = %d\n", ClockRate));
DEBUG ((DEBUG_INFO, "Divisor = %ld\n", ComputedDivisor));
DEBUG ((DEBUG_INFO, "BaudRate/Actual (%ld/%d) = %d%%\n", BaudRate, ComputedBaudRate, Percent));
@@ -147,18 +153,23 @@ VerifyUartParameters (
if (ActualBaudRate != NULL) {
*ActualBaudRate = BaudRate;
}
if (Divisor != NULL) {
*Divisor = ComputedDivisor;
}
return TRUE;
}
if (ComputedBaudRate < BaudRate) {
if (ActualBaudRate != NULL) {
*ActualBaudRate = ComputedBaudRate;
}
if (Divisor != NULL) {
*Divisor = ComputedDivisor;
}
return TRUE;
}
@@ -170,22 +181,25 @@ VerifyUartParameters (
if (ComputedDivisor == MAX_UINT16) {
return FALSE;
}
ComputedDivisor++;
ComputedBaudRate = ClockRate / ((UINT16) ComputedDivisor << 4);
ComputedBaudRate = ClockRate / ((UINT16)ComputedDivisor << 4);
if (ComputedBaudRate == 0) {
return FALSE;
}
DEBUG ((DEBUG_INFO, "ClockRate = %d\n", ClockRate));
DEBUG ((DEBUG_INFO, "ClockRate = %d\n", ClockRate));
DEBUG ((DEBUG_INFO, "Divisor = %ld\n", ComputedDivisor));
DEBUG ((DEBUG_INFO, "BaudRate/Actual (%ld/%d) = %d%%\n", BaudRate, ComputedBaudRate, Percent));
if (ActualBaudRate != NULL) {
*ActualBaudRate = ComputedBaudRate;
}
if (Divisor != NULL) {
*Divisor = ComputedDivisor;
}
return TRUE;
}
@@ -198,10 +212,10 @@ VerifyUartParameters (
**/
BOOLEAN
SerialFifoFull (
IN SERIAL_DEV_FIFO *Fifo
IN SERIAL_DEV_FIFO *Fifo
)
{
return (BOOLEAN) (((Fifo->Tail + 1) % SERIAL_MAX_FIFO_SIZE) == Fifo->Head);
return (BOOLEAN)(((Fifo->Tail + 1) % SERIAL_MAX_FIFO_SIZE) == Fifo->Head);
}
/**
@@ -213,11 +227,11 @@ SerialFifoFull (
**/
BOOLEAN
SerialFifoEmpty (
IN SERIAL_DEV_FIFO *Fifo
IN SERIAL_DEV_FIFO *Fifo
)
{
return (BOOLEAN) (Fifo->Head == Fifo->Tail);
return (BOOLEAN)(Fifo->Head == Fifo->Tail);
}
/**
@@ -231,8 +245,8 @@ SerialFifoEmpty (
**/
EFI_STATUS
SerialFifoAdd (
IN OUT SERIAL_DEV_FIFO *Fifo,
IN UINT8 Data
IN OUT SERIAL_DEV_FIFO *Fifo,
IN UINT8 Data
)
{
//
@@ -241,11 +255,12 @@ SerialFifoAdd (
if (SerialFifoFull (Fifo)) {
return EFI_OUT_OF_RESOURCES;
}
//
// FIFO is not full can add data
//
Fifo->Data[Fifo->Tail] = Data;
Fifo->Tail = (Fifo->Tail + 1) % SERIAL_MAX_FIFO_SIZE;
Fifo->Tail = (Fifo->Tail + 1) % SERIAL_MAX_FIFO_SIZE;
return EFI_SUCCESS;
}
@@ -261,8 +276,8 @@ SerialFifoAdd (
**/
EFI_STATUS
SerialFifoRemove (
IN OUT SERIAL_DEV_FIFO *Fifo,
OUT UINT8 *Data
IN OUT SERIAL_DEV_FIFO *Fifo,
OUT UINT8 *Data
)
{
//
@@ -271,10 +286,11 @@ SerialFifoRemove (
if (SerialFifoEmpty (Fifo)) {
return EFI_OUT_OF_RESOURCES;
}
//
// FIFO is not empty, can remove data
//
*Data = Fifo->Data[Fifo->Head];
*Data = Fifo->Data[Fifo->Head];
Fifo->Head = (Fifo->Head + 1) % SERIAL_MAX_FIFO_SIZE;
return EFI_SUCCESS;
}
@@ -291,16 +307,16 @@ SerialFifoRemove (
**/
EFI_STATUS
SerialReceiveTransmit (
IN SERIAL_DEV *SerialDevice
IN SERIAL_DEV *SerialDevice
)
{
SERIAL_PORT_LSR Lsr;
UINT8 Data;
BOOLEAN ReceiveFifoFull;
SERIAL_PORT_MSR Msr;
SERIAL_PORT_MCR Mcr;
UINTN TimeOut;
SERIAL_PORT_LSR Lsr;
UINT8 Data;
BOOLEAN ReceiveFifoFull;
SERIAL_PORT_MSR Msr;
SERIAL_PORT_MCR Mcr;
UINTN TimeOut;
Data = 0;
@@ -326,13 +342,15 @@ SerialReceiveTransmit (
// if receive buffer is available.
//
if (SerialDevice->HardwareFlowControl &&
!FeaturePcdGet(PcdSerialUseHalfHandshake)&&
!FeaturePcdGet (PcdSerialUseHalfHandshake) &&
!ReceiveFifoFull
) {
)
{
Mcr.Data = READ_MCR (SerialDevice);
Mcr.Bits.Rts = 1;
WRITE_MCR (SerialDevice, Mcr.Data);
}
do {
Lsr.Data = READ_LSR (SerialDevice);
@@ -342,13 +360,13 @@ SerialReceiveTransmit (
if ((Lsr.Bits.Dr == 1) && !ReceiveFifoFull) {
ReceiveFifoFull = SerialFifoFull (&SerialDevice->Receive);
if (!ReceiveFifoFull) {
if (Lsr.Bits.FIFOe == 1 || Lsr.Bits.Oe == 1 || Lsr.Bits.Pe == 1 || Lsr.Bits.Fe == 1 || Lsr.Bits.Bi == 1) {
if ((Lsr.Bits.FIFOe == 1) || (Lsr.Bits.Oe == 1) || (Lsr.Bits.Pe == 1) || (Lsr.Bits.Fe == 1) || (Lsr.Bits.Bi == 1)) {
REPORT_STATUS_CODE_WITH_DEVICE_PATH (
EFI_ERROR_CODE,
EFI_P_EC_INPUT_ERROR | EFI_PERIPHERAL_SERIAL_PORT,
SerialDevice->DevicePath
);
if (Lsr.Bits.FIFOe == 1 || Lsr.Bits.Pe == 1|| Lsr.Bits.Fe == 1 || Lsr.Bits.Bi == 1) {
if ((Lsr.Bits.FIFOe == 1) || (Lsr.Bits.Pe == 1) || (Lsr.Bits.Fe == 1) || (Lsr.Bits.Bi == 1)) {
Data = READ_RBR (SerialDevice);
continue;
}
@@ -363,15 +381,15 @@ SerialReceiveTransmit (
// tell the peer to stop sending data.
//
if (SerialDevice->HardwareFlowControl &&
!FeaturePcdGet(PcdSerialUseHalfHandshake) &&
!FeaturePcdGet (PcdSerialUseHalfHandshake) &&
SerialFifoFull (&SerialDevice->Receive)
) {
)
{
Mcr.Data = READ_MCR (SerialDevice);
Mcr.Bits.Rts = 0;
WRITE_MCR (SerialDevice, Mcr.Data);
}
continue;
} else {
REPORT_STATUS_CODE_WITH_DEVICE_PATH (
@@ -381,10 +399,11 @@ SerialReceiveTransmit (
);
}
}
//
// Do the write
//
if (Lsr.Bits.Thre == 1 && !SerialFifoEmpty (&SerialDevice->Transmit)) {
if ((Lsr.Bits.Thre == 1) && !SerialFifoEmpty (&SerialDevice->Transmit)) {
//
// Make sure the transmit data will not be missed
//
@@ -392,17 +411,18 @@ SerialReceiveTransmit (
//
// For half handshake flow control assert RTS before sending.
//
if (FeaturePcdGet(PcdSerialUseHalfHandshake)) {
if (FeaturePcdGet (PcdSerialUseHalfHandshake)) {
Mcr.Data = READ_MCR (SerialDevice);
Mcr.Bits.Rts= 0;
Mcr.Bits.Rts = 0;
WRITE_MCR (SerialDevice, Mcr.Data);
}
//
// Wait for CTS
//
TimeOut = 0;
Msr.Data = READ_MSR (SerialDevice);
while ((Msr.Bits.Dcd == 1) && ((Msr.Bits.Cts == 0) ^ FeaturePcdGet(PcdSerialUseHalfHandshake))) {
TimeOut = 0;
Msr.Data = READ_MSR (SerialDevice);
while ((Msr.Bits.Dcd == 1) && ((Msr.Bits.Cts == 0) ^ FeaturePcdGet (PcdSerialUseHalfHandshake))) {
gBS->Stall (TIMEOUT_STALL_INTERVAL);
TimeOut++;
if (TimeOut > 5) {
@@ -412,7 +432,7 @@ SerialReceiveTransmit (
Msr.Data = READ_MSR (SerialDevice);
}
if ((Msr.Bits.Dcd == 0) || ((Msr.Bits.Cts == 1) ^ FeaturePcdGet(PcdSerialUseHalfHandshake))) {
if ((Msr.Bits.Dcd == 0) || ((Msr.Bits.Cts == 1) ^ FeaturePcdGet (PcdSerialUseHalfHandshake))) {
SerialFifoRemove (&SerialDevice->Transmit, &Data);
WRITE_THR (SerialDevice, Data);
}
@@ -420,8 +440,8 @@ SerialReceiveTransmit (
//
// For half handshake flow control, tell DCE we are done.
//
if (FeaturePcdGet(PcdSerialUseHalfHandshake)) {
Mcr.Data = READ_MCR (SerialDevice);
if (FeaturePcdGet (PcdSerialUseHalfHandshake)) {
Mcr.Data = READ_MCR (SerialDevice);
Mcr.Bits.Rts = 1;
WRITE_MCR (SerialDevice, Mcr.Data);
}
@@ -484,12 +504,13 @@ SerialFlushTransmitFifo (
// in the rest of this function that may send additional characters to this
// UART device invalidating the flush operation.
//
Elapsed = 0;
Elapsed = 0;
Lsr.Data = READ_LSR (SerialDevice);
while (Lsr.Bits.Temt == 0 || Lsr.Bits.Thre == 0) {
if (Elapsed >= Timeout) {
return EFI_TIMEOUT;
}
gBS->Stall (TIMEOUT_STALL_INTERVAL);
Elapsed += TIMEOUT_STALL_INTERVAL;
Lsr.Data = READ_LSR (SerialDevice);
@@ -501,6 +522,7 @@ SerialFlushTransmitFifo (
//
// Interface Functions
//
/**
Reset serial device.
@@ -516,14 +538,14 @@ SerialReset (
IN EFI_SERIAL_IO_PROTOCOL *This
)
{
EFI_STATUS Status;
SERIAL_DEV *SerialDevice;
SERIAL_PORT_LCR Lcr;
SERIAL_PORT_IER Ier;
SERIAL_PORT_MCR Mcr;
SERIAL_PORT_FCR Fcr;
EFI_TPL Tpl;
UINT32 Control;
EFI_STATUS Status;
SERIAL_DEV *SerialDevice;
SERIAL_PORT_LCR Lcr;
SERIAL_PORT_IER Ier;
SERIAL_PORT_MCR Mcr;
SERIAL_PORT_FCR Fcr;
EFI_TPL Tpl;
UINT32 Control;
SerialDevice = SERIAL_DEV_FROM_THIS (This);
@@ -557,17 +579,17 @@ SerialReset (
//
// Turn off all interrupts
//
Ier.Data = READ_IER (SerialDevice);
Ier.Bits.Ravie = 0;
Ier.Bits.Theie = 0;
Ier.Bits.Rie = 0;
Ier.Bits.Mie = 0;
Ier.Data = READ_IER (SerialDevice);
Ier.Bits.Ravie = 0;
Ier.Bits.Theie = 0;
Ier.Bits.Rie = 0;
Ier.Bits.Mie = 0;
WRITE_IER (SerialDevice, Ier.Data);
//
// Reset the FIFO
//
Fcr.Data = 0;
Fcr.Data = 0;
Fcr.Bits.TrFIFOE = 0;
WRITE_FCR (SerialDevice, Fcr.Data);
@@ -588,12 +610,13 @@ SerialReset (
//
// Enable FIFO
//
Fcr.Bits.TrFIFOE = 1;
Fcr.Bits.TrFIFOE = 1;
if (SerialDevice->ReceiveFifoDepth > 16) {
Fcr.Bits.TrFIFO64 = 1;
}
Fcr.Bits.ResetRF = 1;
Fcr.Bits.ResetTF = 1;
Fcr.Bits.ResetRF = 1;
Fcr.Bits.ResetTF = 1;
WRITE_FCR (SerialDevice, Fcr.Data);
//
@@ -604,15 +627,16 @@ SerialReset (
This->Mode->BaudRate,
This->Mode->ReceiveFifoDepth,
This->Mode->Timeout,
(EFI_PARITY_TYPE) This->Mode->Parity,
(UINT8) This->Mode->DataBits,
(EFI_STOP_BITS_TYPE) This->Mode->StopBits
(EFI_PARITY_TYPE)This->Mode->Parity,
(UINT8)This->Mode->DataBits,
(EFI_STOP_BITS_TYPE)This->Mode->StopBits
);
if (EFI_ERROR (Status)) {
gBS->RestoreTPL (Tpl);
return EFI_DEVICE_ERROR;
}
//
// Go set the current control bits
//
@@ -620,9 +644,11 @@ SerialReset (
if (SerialDevice->HardwareFlowControl) {
Control |= EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE;
}
if (SerialDevice->SoftwareLoopbackEnable) {
Control |= EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE;
}
Status = This->SetControl (
This,
Control
@@ -636,7 +662,7 @@ SerialReset (
//
// Reset the software FIFO
//
SerialDevice->Receive.Head = SerialDevice->Receive.Tail = 0;
SerialDevice->Receive.Head = SerialDevice->Receive.Tail = 0;
SerialDevice->Transmit.Head = SerialDevice->Transmit.Tail = 0;
gBS->RestoreTPL (Tpl);
@@ -675,12 +701,12 @@ SerialSetAttributes (
IN EFI_STOP_BITS_TYPE StopBits
)
{
EFI_STATUS Status;
SERIAL_DEV *SerialDevice;
UINT64 Divisor;
SERIAL_PORT_LCR Lcr;
UART_DEVICE_PATH *Uart;
EFI_TPL Tpl;
EFI_STATUS Status;
SERIAL_DEV *SerialDevice;
UINT64 Divisor;
SERIAL_PORT_LCR Lcr;
UART_DEVICE_PATH *Uart;
EFI_TPL Tpl;
SerialDevice = SERIAL_DEV_FROM_THIS (This);
@@ -700,7 +726,7 @@ SerialSetAttributes (
}
if (Parity == DefaultParity) {
Parity = (EFI_PARITY_TYPE) PcdGet8 (PcdUartDefaultParity);
Parity = (EFI_PARITY_TYPE)PcdGet8 (PcdUartDefaultParity);
}
if (DataBits == 0) {
@@ -708,7 +734,7 @@ SerialSetAttributes (
}
if (StopBits == DefaultStopBits) {
StopBits = (EFI_STOP_BITS_TYPE) PcdGet8 (PcdUartDefaultStopBits);
StopBits = (EFI_STOP_BITS_TYPE)PcdGet8 (PcdUartDefaultStopBits);
}
if (!VerifyUartParameters (SerialDevice->ClockRate, BaudRate, DataBits, Parity, StopBits, &Divisor, &BaudRate)) {
@@ -744,8 +770,8 @@ SerialSetAttributes (
//
// Write the divisor to the serial port
//
WRITE_DLL (SerialDevice, (UINT8) Divisor);
WRITE_DLM (SerialDevice, (UINT8) ((UINT16) Divisor >> 8));
WRITE_DLL (SerialDevice, (UINT8)Divisor);
WRITE_DLM (SerialDevice, (UINT8)((UINT16)Divisor >> 8));
//
// Put serial port back in normal mode and set remaining attributes.
@@ -753,98 +779,100 @@ SerialSetAttributes (
Lcr.Bits.DLab = 0;
switch (Parity) {
case NoParity:
Lcr.Bits.ParEn = 0;
Lcr.Bits.EvenPar = 0;
Lcr.Bits.SticPar = 0;
break;
case NoParity:
Lcr.Bits.ParEn = 0;
Lcr.Bits.EvenPar = 0;
Lcr.Bits.SticPar = 0;
break;
case EvenParity:
Lcr.Bits.ParEn = 1;
Lcr.Bits.EvenPar = 1;
Lcr.Bits.SticPar = 0;
break;
case EvenParity:
Lcr.Bits.ParEn = 1;
Lcr.Bits.EvenPar = 1;
Lcr.Bits.SticPar = 0;
break;
case OddParity:
Lcr.Bits.ParEn = 1;
Lcr.Bits.EvenPar = 0;
Lcr.Bits.SticPar = 0;
break;
case OddParity:
Lcr.Bits.ParEn = 1;
Lcr.Bits.EvenPar = 0;
Lcr.Bits.SticPar = 0;
break;
case SpaceParity:
Lcr.Bits.ParEn = 1;
Lcr.Bits.EvenPar = 1;
Lcr.Bits.SticPar = 1;
break;
case SpaceParity:
Lcr.Bits.ParEn = 1;
Lcr.Bits.EvenPar = 1;
Lcr.Bits.SticPar = 1;
break;
case MarkParity:
Lcr.Bits.ParEn = 1;
Lcr.Bits.EvenPar = 0;
Lcr.Bits.SticPar = 1;
break;
case MarkParity:
Lcr.Bits.ParEn = 1;
Lcr.Bits.EvenPar = 0;
Lcr.Bits.SticPar = 1;
break;
default:
break;
default:
break;
}
switch (StopBits) {
case OneStopBit:
Lcr.Bits.StopB = 0;
break;
case OneStopBit:
Lcr.Bits.StopB = 0;
break;
case OneFiveStopBits:
case TwoStopBits:
Lcr.Bits.StopB = 1;
break;
case OneFiveStopBits:
case TwoStopBits:
Lcr.Bits.StopB = 1;
break;
default:
break;
default:
break;
}
//
// DataBits
//
Lcr.Bits.SerialDB = (UINT8) ((DataBits - 5) & 0x03);
Lcr.Bits.SerialDB = (UINT8)((DataBits - 5) & 0x03);
WRITE_LCR (SerialDevice, Lcr.Data);
//
// Set the Serial I/O mode
//
This->Mode->BaudRate = BaudRate;
This->Mode->ReceiveFifoDepth = ReceiveFifoDepth;
This->Mode->Timeout = Timeout;
This->Mode->Parity = Parity;
This->Mode->DataBits = DataBits;
This->Mode->StopBits = StopBits;
This->Mode->BaudRate = BaudRate;
This->Mode->ReceiveFifoDepth = ReceiveFifoDepth;
This->Mode->Timeout = Timeout;
This->Mode->Parity = Parity;
This->Mode->DataBits = DataBits;
This->Mode->StopBits = StopBits;
//
// See if Device Path Node has actually changed
//
if (SerialDevice->UartDevicePath.BaudRate == BaudRate &&
SerialDevice->UartDevicePath.DataBits == DataBits &&
SerialDevice->UartDevicePath.Parity == Parity &&
SerialDevice->UartDevicePath.StopBits == StopBits
) {
if ((SerialDevice->UartDevicePath.BaudRate == BaudRate) &&
(SerialDevice->UartDevicePath.DataBits == DataBits) &&
(SerialDevice->UartDevicePath.Parity == Parity) &&
(SerialDevice->UartDevicePath.StopBits == StopBits)
)
{
gBS->RestoreTPL (Tpl);
return EFI_SUCCESS;
}
//
// Update the device path
//
SerialDevice->UartDevicePath.BaudRate = BaudRate;
SerialDevice->UartDevicePath.DataBits = DataBits;
SerialDevice->UartDevicePath.Parity = (UINT8) Parity;
SerialDevice->UartDevicePath.StopBits = (UINT8) StopBits;
SerialDevice->UartDevicePath.Parity = (UINT8)Parity;
SerialDevice->UartDevicePath.StopBits = (UINT8)StopBits;
Status = EFI_SUCCESS;
if (SerialDevice->Handle != NULL) {
//
// Skip the optional Controller device path node
//
Uart = SkipControllerDevicePathNode (
(EFI_DEVICE_PATH_PROTOCOL *) (
(UINT8 *) SerialDevice->DevicePath + GetDevicePathSize (SerialDevice->ParentDevicePath) - END_DEVICE_PATH_LENGTH
),
(EFI_DEVICE_PATH_PROTOCOL *)(
(UINT8 *)SerialDevice->DevicePath + GetDevicePathSize (SerialDevice->ParentDevicePath) - END_DEVICE_PATH_LENGTH
),
NULL,
NULL
);
@@ -879,11 +907,11 @@ SerialSetControl (
IN UINT32 Control
)
{
SERIAL_DEV *SerialDevice;
SERIAL_PORT_MCR Mcr;
EFI_TPL Tpl;
UART_FLOW_CONTROL_DEVICE_PATH *FlowControl;
EFI_STATUS Status;
SERIAL_DEV *SerialDevice;
SERIAL_PORT_MCR Mcr;
EFI_TPL Tpl;
UART_FLOW_CONTROL_DEVICE_PATH *FlowControl;
EFI_STATUS Status;
//
// The control bits that can be set are :
@@ -900,7 +928,8 @@ SerialSetControl (
//
if ((Control & (~(EFI_SERIAL_REQUEST_TO_SEND | EFI_SERIAL_DATA_TERMINAL_READY |
EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE | EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE |
EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE))) != 0) {
EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE))) != 0)
{
return EFI_UNSUPPORTED;
}
@@ -915,12 +944,12 @@ SerialSetControl (
//
SerialFlushTransmitFifo (SerialDevice);
Mcr.Data = READ_MCR (SerialDevice);
Mcr.Bits.DtrC = 0;
Mcr.Bits.Rts = 0;
Mcr.Bits.Lme = 0;
Mcr.Data = READ_MCR (SerialDevice);
Mcr.Bits.DtrC = 0;
Mcr.Bits.Rts = 0;
Mcr.Bits.Lme = 0;
SerialDevice->SoftwareLoopbackEnable = FALSE;
SerialDevice->HardwareFlowControl = FALSE;
SerialDevice->HardwareFlowControl = FALSE;
if ((Control & EFI_SERIAL_DATA_TERMINAL_READY) == EFI_SERIAL_DATA_TERMINAL_READY) {
Mcr.Bits.DtrC = 1;
@@ -946,14 +975,15 @@ SerialSetControl (
Status = EFI_SUCCESS;
if (SerialDevice->Handle != NULL) {
FlowControl = (UART_FLOW_CONTROL_DEVICE_PATH *) (
(UINTN) SerialDevice->DevicePath
+ GetDevicePathSize (SerialDevice->ParentDevicePath)
- END_DEVICE_PATH_LENGTH
+ sizeof (UART_DEVICE_PATH)
);
FlowControl = (UART_FLOW_CONTROL_DEVICE_PATH *)(
(UINTN)SerialDevice->DevicePath
+ GetDevicePathSize (SerialDevice->ParentDevicePath)
- END_DEVICE_PATH_LENGTH
+ sizeof (UART_DEVICE_PATH)
);
if (IsUartFlowControlDevicePathNode (FlowControl) &&
((BOOLEAN) (ReadUnaligned32 (&FlowControl->FlowControlMap) == UART_FLOW_CONTROL_HARDWARE) != SerialDevice->HardwareFlowControl)) {
((BOOLEAN)(ReadUnaligned32 (&FlowControl->FlowControlMap) == UART_FLOW_CONTROL_HARDWARE) != SerialDevice->HardwareFlowControl))
{
//
// Flow Control setting is changed, need to reinstall device path protocol
//
@@ -988,16 +1018,16 @@ SerialGetControl (
OUT UINT32 *Control
)
{
SERIAL_DEV *SerialDevice;
SERIAL_PORT_MSR Msr;
SERIAL_PORT_MCR Mcr;
EFI_TPL Tpl;
SERIAL_DEV *SerialDevice;
SERIAL_PORT_MSR Msr;
SERIAL_PORT_MCR Mcr;
EFI_TPL Tpl;
Tpl = gBS->RaiseTPL (TPL_NOTIFY);
Tpl = gBS->RaiseTPL (TPL_NOTIFY);
SerialDevice = SERIAL_DEV_FROM_THIS (This);
SerialDevice = SERIAL_DEV_FROM_THIS (This);
*Control = 0;
*Control = 0;
//
// Read the Modem Status Register
@@ -1019,6 +1049,7 @@ SerialGetControl (
if (Msr.Bits.Dcd == 1) {
*Control |= EFI_SERIAL_CARRIER_DETECT;
}
//
// Read the Modem Control Register
//
@@ -1039,6 +1070,7 @@ SerialGetControl (
if (SerialDevice->HardwareFlowControl) {
*Control |= EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE;
}
//
// Update FIFO status
//
@@ -1097,9 +1129,9 @@ SerialWrite (
UINTN Timeout;
UINTN BitsPerCharacter;
SerialDevice = SERIAL_DEV_FROM_THIS (This);
Elapsed = 0;
ActualWrite = 0;
SerialDevice = SERIAL_DEV_FROM_THIS (This);
Elapsed = 0;
ActualWrite = 0;
if (*BufferSize == 0) {
return EFI_SUCCESS;
@@ -1115,9 +1147,9 @@ SerialWrite (
return EFI_DEVICE_ERROR;
}
Tpl = gBS->RaiseTPL (TPL_NOTIFY);
Tpl = gBS->RaiseTPL (TPL_NOTIFY);
CharBuffer = (UINT8 *) Buffer;
CharBuffer = (UINT8 *)Buffer;
//
// Compute the number of bits in a single character. This is a start bit,
@@ -1143,10 +1175,10 @@ SerialWrite (
Timeout = MAX (
This->Mode->Timeout,
(UINTN)DivU64x64Remainder (
BitsPerCharacter * (SerialDevice->TransmitFifoDepth + 1) * 1000000,
This->Mode->BaudRate,
NULL
)
BitsPerCharacter * (SerialDevice->TransmitFifoDepth + 1) * 1000000,
This->Mode->BaudRate,
NULL
)
);
for (Index = 0; Index < *BufferSize; Index++) {
@@ -1208,8 +1240,8 @@ SerialRead (
EFI_STATUS Status;
EFI_TPL Tpl;
SerialDevice = SERIAL_DEV_FROM_THIS (This);
Elapsed = 0;
SerialDevice = SERIAL_DEV_FROM_THIS (This);
Elapsed = 0;
if (*BufferSize == 0) {
return EFI_SUCCESS;
@@ -1219,9 +1251,9 @@ SerialRead (
return EFI_DEVICE_ERROR;
}
Tpl = gBS->RaiseTPL (TPL_NOTIFY);
Tpl = gBS->RaiseTPL (TPL_NOTIFY);
Status = SerialReceiveTransmit (SerialDevice);
Status = SerialReceiveTransmit (SerialDevice);
if (EFI_ERROR (Status)) {
*BufferSize = 0;
@@ -1237,7 +1269,7 @@ SerialRead (
return EFI_DEVICE_ERROR;
}
CharBuffer = (UINT8 *) Buffer;
CharBuffer = (UINT8 *)Buffer;
for (Index = 0; Index < *BufferSize; Index++) {
while (SerialFifoRemove (&SerialDevice->Receive, &(CharBuffer[Index])) != EFI_SUCCESS) {
//
@@ -1261,6 +1293,7 @@ SerialRead (
return EFI_DEVICE_ERROR;
}
}
//
// Successful read so reset timeout
//
@@ -1283,12 +1316,12 @@ SerialRead (
**/
BOOLEAN
SerialPresent (
IN SERIAL_DEV *SerialDevice
IN SERIAL_DEV *SerialDevice
)
{
UINT8 Temp;
BOOLEAN Status;
UINT8 Temp;
BOOLEAN Status;
Status = TRUE;
@@ -1307,6 +1340,7 @@ SerialPresent (
if (READ_SCR (SerialDevice) != 0x55) {
Status = FALSE;
}
//
// Restore SCR
//
@@ -1325,23 +1359,36 @@ SerialPresent (
**/
UINT8
SerialReadRegister (
IN SERIAL_DEV *SerialDev,
IN UINT32 Offset
IN SERIAL_DEV *SerialDev,
IN UINT32 Offset
)
{
UINT8 Data;
EFI_STATUS Status;
UINT8 Data;
EFI_STATUS Status;
if (SerialDev->PciDeviceInfo == NULL) {
return IoRead8 ((UINTN) SerialDev->BaseAddress + Offset * SerialDev->RegisterStride);
return IoRead8 ((UINTN)SerialDev->BaseAddress + Offset * SerialDev->RegisterStride);
} else {
if (SerialDev->MmioAccess) {
Status = SerialDev->PciDeviceInfo->PciIo->Mem.Read (SerialDev->PciDeviceInfo->PciIo, EfiPciIoWidthUint8, EFI_PCI_IO_PASS_THROUGH_BAR,
SerialDev->BaseAddress + Offset * SerialDev->RegisterStride, 1, &Data);
Status = SerialDev->PciDeviceInfo->PciIo->Mem.Read (
SerialDev->PciDeviceInfo->PciIo,
EfiPciIoWidthUint8,
EFI_PCI_IO_PASS_THROUGH_BAR,
SerialDev->BaseAddress + Offset * SerialDev->RegisterStride,
1,
&Data
);
} else {
Status = SerialDev->PciDeviceInfo->PciIo->Io.Read (SerialDev->PciDeviceInfo->PciIo, EfiPciIoWidthUint8, EFI_PCI_IO_PASS_THROUGH_BAR,
SerialDev->BaseAddress + Offset * SerialDev->RegisterStride, 1, &Data);
Status = SerialDev->PciDeviceInfo->PciIo->Io.Read (
SerialDev->PciDeviceInfo->PciIo,
EfiPciIoWidthUint8,
EFI_PCI_IO_PASS_THROUGH_BAR,
SerialDev->BaseAddress + Offset * SerialDev->RegisterStride,
1,
&Data
);
}
ASSERT_EFI_ERROR (Status);
return Data;
}
@@ -1356,23 +1403,36 @@ SerialReadRegister (
**/
VOID
SerialWriteRegister (
IN SERIAL_DEV *SerialDev,
IN UINT32 Offset,
IN UINT8 Data
IN SERIAL_DEV *SerialDev,
IN UINT32 Offset,
IN UINT8 Data
)
{
EFI_STATUS Status;
EFI_STATUS Status;
if (SerialDev->PciDeviceInfo == NULL) {
IoWrite8 ((UINTN) SerialDev->BaseAddress + Offset * SerialDev->RegisterStride, Data);
IoWrite8 ((UINTN)SerialDev->BaseAddress + Offset * SerialDev->RegisterStride, Data);
} else {
if (SerialDev->MmioAccess) {
Status = SerialDev->PciDeviceInfo->PciIo->Mem.Write (SerialDev->PciDeviceInfo->PciIo, EfiPciIoWidthUint8, EFI_PCI_IO_PASS_THROUGH_BAR,
SerialDev->BaseAddress + Offset * SerialDev->RegisterStride, 1, &Data);
Status = SerialDev->PciDeviceInfo->PciIo->Mem.Write (
SerialDev->PciDeviceInfo->PciIo,
EfiPciIoWidthUint8,
EFI_PCI_IO_PASS_THROUGH_BAR,
SerialDev->BaseAddress + Offset * SerialDev->RegisterStride,
1,
&Data
);
} else {
Status = SerialDev->PciDeviceInfo->PciIo->Io.Write (SerialDev->PciDeviceInfo->PciIo, EfiPciIoWidthUint8, EFI_PCI_IO_PASS_THROUGH_BAR,
SerialDev->BaseAddress + Offset * SerialDev->RegisterStride, 1, &Data);
Status = SerialDev->PciDeviceInfo->PciIo->Io.Write (
SerialDev->PciDeviceInfo->PciIo,
EfiPciIoWidthUint8,
EFI_PCI_IO_PASS_THROUGH_BAR,
SerialDev->BaseAddress + Offset * SerialDev->RegisterStride,
1,
&Data
);
}
ASSERT_EFI_ERROR (Status);
}
}

41
MdeModulePkg/Bus/Pci/SataControllerDxe/ComponentName.c
View File

@@ -20,16 +20,16 @@ GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME_PROTOCOL gSataControllerCompon
//
/// EFI Component Name 2 Protocol
///
GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gSataControllerComponentName2 = {
(EFI_COMPONENT_NAME2_GET_DRIVER_NAME) SataControllerComponentNameGetDriverName,
(EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME) SataControllerComponentNameGetControllerName,
GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gSataControllerComponentName2 = {
(EFI_COMPONENT_NAME2_GET_DRIVER_NAME)SataControllerComponentNameGetDriverName,
(EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME)SataControllerComponentNameGetControllerName,
"en"
};
//
/// Driver Name Strings
///
GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mSataControllerDriverNameTable[] = {
GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mSataControllerDriverNameTable[] = {
{
"eng;en",
(CHAR16 *)L"Sata Controller Init Driver"
@@ -43,7 +43,7 @@ GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mSataControllerDriverName
///
/// Controller Name Strings
///
GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mSataControllerControllerNameTable[] = {
GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mSataControllerControllerNameTable[] = {
{
"eng;en",
(CHAR16 *)L"Sata Controller"
@@ -78,9 +78,9 @@ GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mSataControllerController
EFI_STATUS
EFIAPI
SataControllerComponentNameGetDriverName (
IN EFI_COMPONENT_NAME_PROTOCOL *This,
IN CHAR8 *Language,
OUT CHAR16 **DriverName
IN EFI_COMPONENT_NAME_PROTOCOL *This,
IN CHAR8 *Language,
OUT CHAR16 **DriverName
)
{
return LookupUnicodeString2 (
@@ -135,14 +135,14 @@ SataControllerComponentNameGetDriverName (
EFI_STATUS
EFIAPI
SataControllerComponentNameGetControllerName (
IN EFI_COMPONENT_NAME_PROTOCOL *This,
IN EFI_HANDLE ControllerHandle,
IN EFI_HANDLE ChildHandle OPTIONAL,
IN CHAR8 *Language,
OUT CHAR16 **ControllerName
IN EFI_COMPONENT_NAME_PROTOCOL *This,
IN EFI_HANDLE ControllerHandle,
IN EFI_HANDLE ChildHandle OPTIONAL,
IN CHAR8 *Language,
OUT CHAR16 **ControllerName
)
{
EFI_STATUS Status;
EFI_STATUS Status;
//
// Make sure this driver is currently managing ControllHandle
@@ -161,11 +161,10 @@ SataControllerComponentNameGetControllerName (
}
return LookupUnicodeString2 (
Language,
This->SupportedLanguages,
mSataControllerControllerNameTable,
ControllerName,
(BOOLEAN)(This == &gSataControllerComponentName)
);
Language,
This->SupportedLanguages,
mSataControllerControllerNameTable,
ControllerName,
(BOOLEAN)(This == &gSataControllerComponentName)
);
}

203
MdeModulePkg/Bus/Pci/SataControllerDxe/SataController.c
View File

@@ -12,7 +12,7 @@
///
/// EFI_DRIVER_BINDING_PROTOCOL instance
///
EFI_DRIVER_BINDING_PROTOCOL gSataControllerDriverBinding = {
EFI_DRIVER_BINDING_PROTOCOL gSataControllerDriverBinding = {
SataControllerSupported,
SataControllerStart,
SataControllerStop,
@@ -33,11 +33,11 @@ EFI_DRIVER_BINDING_PROTOCOL gSataControllerDriverBinding = {
UINT32
EFIAPI
AhciReadReg (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT32 Offset
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT32 Offset
)
{
UINT32 Data;
UINT32 Data;
ASSERT (PciIo != NULL);
@@ -47,7 +47,7 @@ AhciReadReg (
PciIo,
EfiPciIoWidthUint32,
AHCI_BAR_INDEX,
(UINT64) Offset,
(UINT64)Offset,
1,
&Data
);
@@ -73,21 +73,20 @@ CalculateBestPioMode (
OUT UINT16 *SelectedMode
)
{
UINT16 PioMode;
UINT16 AdvancedPioMode;
UINT16 Temp;
UINT16 Index;
UINT16 MinimumPioCycleTime;
UINT16 PioMode;
UINT16 AdvancedPioMode;
UINT16 Temp;
UINT16 Index;
UINT16 MinimumPioCycleTime;
Temp = 0xff;
PioMode = (UINT8) (((ATA5_IDENTIFY_DATA *) (&(IdentifyData->AtaData)))->pio_cycle_timing >> 8);
PioMode = (UINT8)(((ATA5_IDENTIFY_DATA *)(&(IdentifyData->AtaData)))->pio_cycle_timing >> 8);
//
// See whether Identify Data word 64 - 70 are valid
//
if ((IdentifyData->AtaData.field_validity & 0x02) == 0x02) {
AdvancedPioMode = IdentifyData->AtaData.advanced_pio_modes;
DEBUG ((DEBUG_INFO, "CalculateBestPioMode: AdvancedPioMode = %x\n", AdvancedPioMode));
@@ -105,7 +104,7 @@ CalculateBestPioMode (
// the best PIO Mode is the value in pio_cycle_timing.
//
if (Temp != 0xff) {
AdvancedPioMode = (UINT16) (Temp + 3);
AdvancedPioMode = (UINT16)(Temp + 3);
} else {
AdvancedPioMode = PioMode;
}
@@ -113,16 +112,16 @@ CalculateBestPioMode (
//
// Limit the PIO mode to at most PIO4.
//
PioMode = (UINT16) MIN (AdvancedPioMode, 4);
PioMode = (UINT16)MIN (AdvancedPioMode, 4);
MinimumPioCycleTime = IdentifyData->AtaData.min_pio_cycle_time_with_flow_control;
if (MinimumPioCycleTime <= 120) {
PioMode = (UINT16) MIN (4, PioMode);
PioMode = (UINT16)MIN (4, PioMode);
} else if (MinimumPioCycleTime <= 180) {
PioMode = (UINT16) MIN (3, PioMode);
PioMode = (UINT16)MIN (3, PioMode);
} else if (MinimumPioCycleTime <= 240) {
PioMode = (UINT16) MIN (2, PioMode);
PioMode = (UINT16)MIN (2, PioMode);
} else {
PioMode = 0;
}
@@ -136,7 +135,7 @@ CalculateBestPioMode (
}
if (PioMode >= *DisPioMode) {
PioMode = (UINT16) (*DisPioMode - 1);
PioMode = (UINT16)(*DisPioMode - 1);
}
}
@@ -145,7 +144,6 @@ CalculateBestPioMode (
} else {
*SelectedMode = PioMode; // ATA_PIO_MODE_2 to ATA_PIO_MODE_4;
}
} else {
//
// Identify Data word 64 - 70 are not valid
@@ -166,7 +164,6 @@ CalculateBestPioMode (
} else {
*SelectedMode = 2; // ATA_PIO_MODE_2;
}
}
return EFI_SUCCESS;
@@ -190,8 +187,8 @@ CalculateBestUdmaMode (
OUT UINT16 *SelectedMode
)
{
UINT16 TempMode;
UINT16 DeviceUDmaMode;
UINT16 TempMode;
UINT16 DeviceUDmaMode;
DeviceUDmaMode = 0;
@@ -205,7 +202,7 @@ CalculateBestUdmaMode (
DeviceUDmaMode = IdentifyData->AtaData.ultra_dma_mode;
DEBUG ((DEBUG_INFO, "CalculateBestUdmaMode: DeviceUDmaMode = %x\n", DeviceUDmaMode));
DeviceUDmaMode &= 0x3f;
TempMode = 0; // initialize it to UDMA-0
TempMode = 0; // initialize it to UDMA-0
while ((DeviceUDmaMode >>= 1) != 0) {
TempMode++;
@@ -221,7 +218,7 @@ CalculateBestUdmaMode (
}
if (TempMode >= *DisUDmaMode) {
TempMode = (UINT16) (*DisUDmaMode - 1);
TempMode = (UINT16)(*DisUDmaMode - 1);
}
}
@@ -246,11 +243,11 @@ CalculateBestUdmaMode (
EFI_STATUS
EFIAPI
InitializeSataControllerDriver (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
EFI_STATUS Status;
//
// Install driver model protocol(s).
@@ -285,14 +282,14 @@ InitializeSataControllerDriver (
EFI_STATUS
EFIAPI
SataControllerSupported (
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
)
{
EFI_STATUS Status;
EFI_PCI_IO_PROTOCOL *PciIo;
PCI_TYPE00 PciData;
EFI_STATUS Status;
EFI_PCI_IO_PROTOCOL *PciIo;
PCI_TYPE00 PciData;
//
// Attempt to open PCI I/O Protocol
@@ -300,7 +297,7 @@ SataControllerSupported (
Status = gBS->OpenProtocol (
Controller,
&gEfiPciIoProtocolGuid,
(VOID **) &PciIo,
(VOID **)&PciIo,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_GET_PROTOCOL
@@ -348,9 +345,9 @@ SataControllerSupported (
EFI_STATUS
EFIAPI
SataControllerStart (
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
)
{
EFI_STATUS Status;
@@ -372,7 +369,7 @@ SataControllerStart (
Status = gBS->OpenProtocol (
Controller,
&gEfiPciIoProtocolGuid,
(VOID **) &PciIo,
(VOID **)&PciIo,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_BY_DRIVER
@@ -394,8 +391,8 @@ SataControllerStart (
//
// Initialize Sata Private Data
//
Private->Signature = SATA_CONTROLLER_SIGNATURE;
Private->PciIo = PciIo;
Private->Signature = SATA_CONTROLLER_SIGNATURE;
Private->PciIo = PciIo;
Private->IdeInit.GetChannelInfo = IdeInitGetChannelInfo;
Private->IdeInit.NotifyPhase = IdeInitNotifyPhase;
Private->IdeInit.SubmitData = IdeInitSubmitData;
@@ -415,7 +412,7 @@ SataControllerStart (
&Private->OriginalPciAttributes
);
if (EFI_ERROR (Status)) {
goto Done;
goto Done;
}
DEBUG ((
@@ -437,12 +434,12 @@ SataControllerStart (
DEBUG ((DEBUG_INFO, "Supported PCI Attributes = 0x%llx\n", Supports));
Supports &= (UINT64)EFI_PCI_DEVICE_ENABLE;
Status = PciIo->Attributes (
PciIo,
EfiPciIoAttributeOperationEnable,
Supports,
NULL
);
Status = PciIo->Attributes (
PciIo,
EfiPciIoAttributeOperationEnable,
Supports,
NULL
);
if (EFI_ERROR (Status)) {
goto Done;
}
@@ -475,13 +472,16 @@ SataControllerStart (
Status = EFI_UNSUPPORTED;
goto Done;
}
MaxPortNumber = 31;
while (MaxPortNumber > 0) {
if ((Data32 & ((UINT32)1 << MaxPortNumber)) != 0) {
break;
}
MaxPortNumber--;
}
//
// Make the ChannelCount equal to the max port number (0 based) plus 1.
//
@@ -492,13 +492,13 @@ SataControllerStart (
//
Data32 = AhciReadReg (PciIo, R_AHCI_CAP);
DEBUG ((DEBUG_INFO, "HBA Capabilities(CAP) = 0x%x\n", Data32));
Private->DeviceCount = AHCI_MAX_DEVICES;
Private->DeviceCount = AHCI_MAX_DEVICES;
if ((Data32 & B_AHCI_CAP_SPM) == B_AHCI_CAP_SPM) {
Private->DeviceCount = AHCI_MULTI_MAX_DEVICES;
}
}
TotalCount = (UINTN) (Private->IdeInit.ChannelCount) * (UINTN) (Private->DeviceCount);
TotalCount = (UINTN)(Private->IdeInit.ChannelCount) * (UINTN)(Private->DeviceCount);
Private->DisqualifiedModes = AllocateZeroPool ((sizeof (EFI_ATA_COLLECTIVE_MODE)) * TotalCount);
if (Private->DisqualifiedModes == NULL) {
Status = EFI_OUT_OF_RESOURCES;
@@ -529,23 +529,25 @@ SataControllerStart (
Done:
if (EFI_ERROR (Status)) {
gBS->CloseProtocol (
Controller,
&gEfiPciIoProtocolGuid,
This->DriverBindingHandle,
Controller
);
Controller,
&gEfiPciIoProtocolGuid,
This->DriverBindingHandle,
Controller
);
if (Private != NULL) {
if (Private->DisqualifiedModes != NULL) {
FreePool (Private->DisqualifiedModes);
}
if (Private->IdentifyData != NULL) {
FreePool (Private->IdentifyData);
}
if (Private->IdentifyValid != NULL) {
FreePool (Private->IdentifyValid);
}
if (Private->PciAttributesChanged) {
//
// Restore original PCI attributes
@@ -557,6 +559,7 @@ Done:
NULL
);
}
FreePool (Private);
}
}
@@ -581,10 +584,10 @@ Done:
EFI_STATUS
EFIAPI
SataControllerStop (
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN UINTN NumberOfChildren,
IN EFI_HANDLE *ChildHandleBuffer
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN UINTN NumberOfChildren,
IN EFI_HANDLE *ChildHandleBuffer
)
{
EFI_STATUS Status;
@@ -597,7 +600,7 @@ SataControllerStop (
Status = gBS->OpenProtocol (
Controller,
&gEfiIdeControllerInitProtocolGuid,
(VOID **) &IdeInit,
(VOID **)&IdeInit,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_GET_PROTOCOL
@@ -626,12 +629,15 @@ SataControllerStop (
if (Private->DisqualifiedModes != NULL) {
FreePool (Private->DisqualifiedModes);
}
if (Private->IdentifyData != NULL) {
FreePool (Private->IdentifyData);
}
if (Private->IdentifyValid != NULL) {
FreePool (Private->IdentifyValid);
}
if (Private->PciAttributesChanged) {
//
// Restore original PCI attributes
@@ -643,6 +649,7 @@ SataControllerStop (
NULL
);
}
FreePool (Private);
}
@@ -691,6 +698,7 @@ FlatDeviceIndex (
//
// Interface functions of IDE_CONTROLLER_INIT protocol
//
/**
Returns the information about the specified IDE channel.
@@ -730,18 +738,19 @@ FlatDeviceIndex (
EFI_STATUS
EFIAPI
IdeInitGetChannelInfo (
IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
IN UINT8 Channel,
OUT BOOLEAN *Enabled,
OUT UINT8 *MaxDevices
IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
IN UINT8 Channel,
OUT BOOLEAN *Enabled,
OUT UINT8 *MaxDevices
)
{
EFI_SATA_CONTROLLER_PRIVATE_DATA *Private;
Private = SATA_CONTROLLER_PRIVATE_DATA_FROM_THIS (This);
ASSERT (Private != NULL);
if (Channel < This->ChannelCount) {
*Enabled = TRUE;
*Enabled = TRUE;
*MaxDevices = Private->DeviceCount;
return EFI_SUCCESS;
}
@@ -778,9 +787,9 @@ IdeInitGetChannelInfo (
EFI_STATUS
EFIAPI
IdeInitNotifyPhase (
IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
IN EFI_IDE_CONTROLLER_ENUM_PHASE Phase,
IN UINT8 Channel
IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
IN EFI_IDE_CONTROLLER_ENUM_PHASE Phase,
IN UINT8 Channel
)
{
return EFI_SUCCESS;
@@ -828,10 +837,10 @@ IdeInitNotifyPhase (
EFI_STATUS
EFIAPI
IdeInitSubmitData (
IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
IN UINT8 Channel,
IN UINT8 Device,
IN EFI_IDENTIFY_DATA *IdentifyData
IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
IN UINT8 Channel,
IN UINT8 Device,
IN EFI_IDENTIFY_DATA *IdentifyData
)
{
EFI_SATA_CONTROLLER_PRIVATE_DATA *Private;
@@ -907,10 +916,10 @@ IdeInitSubmitData (
EFI_STATUS
EFIAPI
IdeInitDisqualifyMode (
IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
IN UINT8 Channel,
IN UINT8 Device,
IN EFI_ATA_COLLECTIVE_MODE *BadModes
IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
IN UINT8 Channel,
IN UINT8 Device,
IN EFI_ATA_COLLECTIVE_MODE *BadModes
)
{
EFI_SATA_CONTROLLER_PRIVATE_DATA *Private;
@@ -995,10 +1004,10 @@ IdeInitDisqualifyMode (
EFI_STATUS
EFIAPI
IdeInitCalculateMode (
IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
IN UINT8 Channel,
IN UINT8 Device,
OUT EFI_ATA_COLLECTIVE_MODE **SupportedModes
IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
IN UINT8 Channel,
IN UINT8 Device,
OUT EFI_ATA_COLLECTIVE_MODE **SupportedModes
)
{
EFI_SATA_CONTROLLER_PRIVATE_DATA *Private;
@@ -1024,8 +1033,8 @@ IdeInitCalculateMode (
DeviceIndex = FlatDeviceIndex (Private, Channel, Device);
IdentifyData = &(Private->IdentifyData[DeviceIndex]);
IdentifyValid = Private->IdentifyValid[DeviceIndex];
IdentifyData = &(Private->IdentifyData[DeviceIndex]);
IdentifyValid = Private->IdentifyValid[DeviceIndex];
DisqualifiedModes = &(Private->DisqualifiedModes[DeviceIndex]);
//
@@ -1037,32 +1046,32 @@ IdeInitCalculateMode (
}
Status = CalculateBestPioMode (
IdentifyData,
(DisqualifiedModes->PioMode.Valid ? ((UINT16 *) &(DisqualifiedModes->PioMode.Mode)) : NULL),
&SelectedMode
);
IdentifyData,
(DisqualifiedModes->PioMode.Valid ? ((UINT16 *)&(DisqualifiedModes->PioMode.Mode)) : NULL),
&SelectedMode
);
if (!EFI_ERROR (Status)) {
(*SupportedModes)->PioMode.Valid = TRUE;
(*SupportedModes)->PioMode.Mode = SelectedMode;
(*SupportedModes)->PioMode.Mode = SelectedMode;
} else {
(*SupportedModes)->PioMode.Valid = FALSE;
}
DEBUG ((DEBUG_INFO, "IdeInitCalculateMode: PioMode = %x\n", (*SupportedModes)->PioMode.Mode));
Status = CalculateBestUdmaMode (
IdentifyData,
(DisqualifiedModes->UdmaMode.Valid ? ((UINT16 *) &(DisqualifiedModes->UdmaMode.Mode)) : NULL),
&SelectedMode
);
IdentifyData,
(DisqualifiedModes->UdmaMode.Valid ? ((UINT16 *)&(DisqualifiedModes->UdmaMode.Mode)) : NULL),
&SelectedMode
);
if (!EFI_ERROR (Status)) {
(*SupportedModes)->UdmaMode.Valid = TRUE;
(*SupportedModes)->UdmaMode.Mode = SelectedMode;
} else {
(*SupportedModes)->UdmaMode.Valid = FALSE;
}
DEBUG ((DEBUG_INFO, "IdeInitCalculateMode: UdmaMode = %x\n", (*SupportedModes)->UdmaMode.Mode));
//
@@ -1097,10 +1106,10 @@ IdeInitCalculateMode (
EFI_STATUS
EFIAPI
IdeInitSetTiming (
IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
IN UINT8 Channel,
IN UINT8 Device,
IN EFI_ATA_COLLECTIVE_MODE *Modes
IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
IN UINT8 Channel,
IN UINT8 Device,
IN EFI_ATA_COLLECTIVE_MODE *Modes
)
{
return EFI_SUCCESS;

134
MdeModulePkg/Bus/Pci/SataControllerDxe/SataController.h
View File

@@ -30,94 +30,95 @@
//
// Global Variables definitions
//
extern EFI_DRIVER_BINDING_PROTOCOL gSataControllerDriverBinding;
extern EFI_COMPONENT_NAME_PROTOCOL gSataControllerComponentName;
extern EFI_COMPONENT_NAME2_PROTOCOL gSataControllerComponentName2;
extern EFI_DRIVER_BINDING_PROTOCOL gSataControllerDriverBinding;
extern EFI_COMPONENT_NAME_PROTOCOL gSataControllerComponentName;
extern EFI_COMPONENT_NAME2_PROTOCOL gSataControllerComponentName2;
#define AHCI_BAR_INDEX 0x05
#define R_AHCI_CAP 0x0
#define B_AHCI_CAP_NPS (BIT4 | BIT3 | BIT2 | BIT1 | BIT0) // Number of Ports
#define B_AHCI_CAP_SPM BIT17 // Supports Port Multiplier
#define R_AHCI_PI 0xC
#define AHCI_BAR_INDEX 0x05
#define R_AHCI_CAP 0x0
#define B_AHCI_CAP_NPS (BIT4 | BIT3 | BIT2 | BIT1 | BIT0) // Number of Ports
#define B_AHCI_CAP_SPM BIT17 // Supports Port Multiplier
#define R_AHCI_PI 0xC
///
/// AHCI each channel can have up to 1 device
///
#define AHCI_MAX_DEVICES 0x01
#define AHCI_MAX_DEVICES 0x01
///
/// AHCI each channel can have 15 devices in the presence of a multiplier
///
#define AHCI_MULTI_MAX_DEVICES 0x0F
#define AHCI_MULTI_MAX_DEVICES 0x0F
///
/// IDE supports 2 channel max
///
#define IDE_MAX_CHANNEL 0x02
#define IDE_MAX_CHANNEL 0x02
///
/// IDE supports 2 devices max
///
#define IDE_MAX_DEVICES 0x02
#define IDE_MAX_DEVICES 0x02
#define SATA_ENUMER_ALL FALSE
#define SATA_ENUMER_ALL FALSE
//
// Sata Controller driver private data structure
//
#define SATA_CONTROLLER_SIGNATURE SIGNATURE_32('S','A','T','A')
#define SATA_CONTROLLER_SIGNATURE SIGNATURE_32('S','A','T','A')
typedef struct _EFI_SATA_CONTROLLER_PRIVATE_DATA {
//
// Standard signature used to identify Sata Controller private data
//
UINT32 Signature;
UINT32 Signature;
//
// Protocol instance of IDE_CONTROLLER_INIT produced by this driver
//
EFI_IDE_CONTROLLER_INIT_PROTOCOL IdeInit;
EFI_IDE_CONTROLLER_INIT_PROTOCOL IdeInit;
//
// Copy of protocol pointers used by this driver
//
EFI_PCI_IO_PROTOCOL *PciIo;
EFI_PCI_IO_PROTOCOL *PciIo;
//
// The number of devices that are supported by this channel
//
UINT8 DeviceCount;
UINT8 DeviceCount;
//
// The highest disqulified mode for each attached device,
// From ATA/ATAPI spec, if a mode is not supported,
// the modes higher than it is also not supported
//
EFI_ATA_COLLECTIVE_MODE *DisqualifiedModes;
EFI_ATA_COLLECTIVE_MODE *DisqualifiedModes;
//
// A copy of EFI_IDENTIFY_DATA data for each attached SATA device and its flag
//
EFI_IDENTIFY_DATA *IdentifyData;
BOOLEAN *IdentifyValid;
EFI_IDENTIFY_DATA *IdentifyData;
BOOLEAN *IdentifyValid;
//
// Track the state so that the PCI attributes that were modified
// can be restored to the original value later.
//
BOOLEAN PciAttributesChanged;
BOOLEAN PciAttributesChanged;
//
// Copy of the original PCI Attributes
//
UINT64 OriginalPciAttributes;
UINT64 OriginalPciAttributes;
} EFI_SATA_CONTROLLER_PRIVATE_DATA;
#define SATA_CONTROLLER_PRIVATE_DATA_FROM_THIS(a) CR(a, EFI_SATA_CONTROLLER_PRIVATE_DATA, IdeInit, SATA_CONTROLLER_SIGNATURE)
#define SATA_CONTROLLER_PRIVATE_DATA_FROM_THIS(a) CR(a, EFI_SATA_CONTROLLER_PRIVATE_DATA, IdeInit, SATA_CONTROLLER_SIGNATURE)
//
// Driver binding functions declaration
//
/**
Supported function of Driver Binding protocol for this driver.
Test to see if this driver supports ControllerHandle.
@@ -135,9 +136,9 @@ typedef struct _EFI_SATA_CONTROLLER_PRIVATE_DATA {
EFI_STATUS
EFIAPI
SataControllerSupported (
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
);
/**
@@ -157,9 +158,9 @@ SataControllerSupported (
EFI_STATUS
EFIAPI
SataControllerStart (
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
);
/**
@@ -177,15 +178,16 @@ SataControllerStart (
EFI_STATUS
EFIAPI
SataControllerStop (
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN UINTN NumberOfChildren,
IN EFI_HANDLE *ChildHandleBuffer
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN UINTN NumberOfChildren,
IN EFI_HANDLE *ChildHandleBuffer
);
//
// IDE controller init functions declaration
//
/**
Returns the information about the specified IDE channel.
@@ -226,10 +228,10 @@ SataControllerStop (
EFI_STATUS
EFIAPI
IdeInitGetChannelInfo (
IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
IN UINT8 Channel,
OUT BOOLEAN *Enabled,
OUT UINT8 *MaxDevices
IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
IN UINT8 Channel,
OUT BOOLEAN *Enabled,
OUT UINT8 *MaxDevices
);
/**
@@ -260,9 +262,9 @@ IdeInitGetChannelInfo (
EFI_STATUS
EFIAPI
IdeInitNotifyPhase (
IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
IN EFI_IDE_CONTROLLER_ENUM_PHASE Phase,
IN UINT8 Channel
IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
IN EFI_IDE_CONTROLLER_ENUM_PHASE Phase,
IN UINT8 Channel
);
/**
@@ -307,10 +309,10 @@ IdeInitNotifyPhase (
EFI_STATUS
EFIAPI
IdeInitSubmitData (
IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
IN UINT8 Channel,
IN UINT8 Device,
IN EFI_IDENTIFY_DATA *IdentifyData
IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
IN UINT8 Channel,
IN UINT8 Device,
IN EFI_IDENTIFY_DATA *IdentifyData
);
/**
@@ -356,10 +358,10 @@ IdeInitSubmitData (
EFI_STATUS
EFIAPI
IdeInitDisqualifyMode (
IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
IN UINT8 Channel,
IN UINT8 Device,
IN EFI_ATA_COLLECTIVE_MODE *BadModes
IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
IN UINT8 Channel,
IN UINT8 Device,
IN EFI_ATA_COLLECTIVE_MODE *BadModes
);
/**
@@ -419,10 +421,10 @@ IdeInitDisqualifyMode (
EFI_STATUS
EFIAPI
IdeInitCalculateMode (
IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
IN UINT8 Channel,
IN UINT8 Device,
OUT EFI_ATA_COLLECTIVE_MODE **SupportedModes
IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
IN UINT8 Channel,
IN UINT8 Device,
OUT EFI_ATA_COLLECTIVE_MODE **SupportedModes
);
/**
@@ -451,15 +453,16 @@ IdeInitCalculateMode (
EFI_STATUS
EFIAPI
IdeInitSetTiming (
IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
IN UINT8 Channel,
IN UINT8 Device,
IN EFI_ATA_COLLECTIVE_MODE *Modes
IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
IN UINT8 Channel,
IN UINT8 Device,
IN EFI_ATA_COLLECTIVE_MODE *Modes
);
//
// Forward reference declaration
//
/**
Retrieves a Unicode string that is the user readable name of the UEFI Driver.
@@ -484,9 +487,9 @@ IdeInitSetTiming (
EFI_STATUS
EFIAPI
SataControllerComponentNameGetDriverName (
IN EFI_COMPONENT_NAME_PROTOCOL *This,
IN CHAR8 *Language,
OUT CHAR16 **DriverName
IN EFI_COMPONENT_NAME_PROTOCOL *This,
IN CHAR8 *Language,
OUT CHAR16 **DriverName
);
/**
@@ -532,12 +535,11 @@ SataControllerComponentNameGetDriverName (
EFI_STATUS
EFIAPI
SataControllerComponentNameGetControllerName (
IN EFI_COMPONENT_NAME_PROTOCOL *This,
IN EFI_HANDLE ControllerHandle,
IN EFI_HANDLE ChildHandle OPTIONAL,
IN CHAR8 *Language,
OUT CHAR16 **ControllerName
IN EFI_COMPONENT_NAME_PROTOCOL *This,
IN EFI_HANDLE ControllerHandle,
IN EFI_HANDLE ChildHandle OPTIONAL,
IN CHAR8 *Language,
OUT CHAR16 **ControllerName
);
#endif

36
MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/ComponentName.c
View File

@@ -11,7 +11,7 @@
//
// EFI Component Name Protocol
//
GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME_PROTOCOL gSdMmcPciHcComponentName = {
GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME_PROTOCOL gSdMmcPciHcComponentName = {
SdMmcPciHcComponentNameGetDriverName,
SdMmcPciHcComponentNameGetControllerName,
"eng"
@@ -20,20 +20,20 @@ GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME_PROTOCOL gSdMmcPciHcComponentNa
//
// EFI Component Name 2 Protocol
//
GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gSdMmcPciHcComponentName2 = {
(EFI_COMPONENT_NAME2_GET_DRIVER_NAME) SdMmcPciHcComponentNameGetDriverName,
(EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME) SdMmcPciHcComponentNameGetControllerName,
GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gSdMmcPciHcComponentName2 = {
(EFI_COMPONENT_NAME2_GET_DRIVER_NAME)SdMmcPciHcComponentNameGetDriverName,
(EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME)SdMmcPciHcComponentNameGetControllerName,
"en"
};
GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mSdMmcPciHcDriverNameTable[] = {
GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mSdMmcPciHcDriverNameTable[] = {
{ "eng;en", L"Edkii Sd/Mmc Host Controller Driver" },
{ NULL , NULL }
{ NULL, NULL }
};
GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mSdMmcPciHcControllerNameTable[] = {
GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mSdMmcPciHcControllerNameTable[] = {
{ "eng;en", L"Edkii Sd/Mmc Host Controller" },
{ NULL , NULL }
{ NULL, NULL }
};
/**
@@ -78,9 +78,9 @@ GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mSdMmcPciHcControllerName
EFI_STATUS
EFIAPI
SdMmcPciHcComponentNameGetDriverName (
IN EFI_COMPONENT_NAME_PROTOCOL *This,
IN CHAR8 *Language,
OUT CHAR16 **DriverName
IN EFI_COMPONENT_NAME_PROTOCOL *This,
IN CHAR8 *Language,
OUT CHAR16 **DriverName
)
{
return LookupUnicodeString2 (
@@ -163,16 +163,16 @@ SdMmcPciHcComponentNameGetDriverName (
EFI_STATUS
EFIAPI
SdMmcPciHcComponentNameGetControllerName (
IN EFI_COMPONENT_NAME_PROTOCOL *This,
IN EFI_HANDLE ControllerHandle,
IN EFI_HANDLE ChildHandle OPTIONAL,
IN CHAR8 *Language,
OUT CHAR16 **ControllerName
IN EFI_COMPONENT_NAME_PROTOCOL *This,
IN EFI_HANDLE ControllerHandle,
IN EFI_HANDLE ChildHandle OPTIONAL,
IN CHAR8 *Language,
OUT CHAR16 **ControllerName
)
{
EFI_STATUS Status;
EFI_STATUS Status;
if (Language == NULL || ControllerName == NULL) {
if ((Language == NULL) || (ControllerName == NULL)) {
return EFI_INVALID_PARAMETER;
}

435
MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
View File

@@ -24,14 +24,14 @@
**/
EFI_STATUS
EmmcReset (
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
IN UINT8 Slot
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
IN UINT8 Slot
)
{
EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
EFI_STATUS Status;
EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
EFI_STATUS Status;
ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
@@ -41,9 +41,9 @@ EmmcReset (
Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
Packet.Timeout = SD_MMC_HC_GENERIC_TIMEOUT;
SdMmcCmdBlk.CommandIndex = EMMC_GO_IDLE_STATE;
SdMmcCmdBlk.CommandType = SdMmcCommandTypeBc;
SdMmcCmdBlk.ResponseType = 0;
SdMmcCmdBlk.CommandIndex = EMMC_GO_IDLE_STATE;
SdMmcCmdBlk.CommandType = SdMmcCommandTypeBc;
SdMmcCmdBlk.ResponseType = 0;
SdMmcCmdBlk.CommandArgument = 0;
gBS->Stall (1000);
@@ -74,10 +74,10 @@ EmmcGetOcr (
IN OUT UINT32 *Argument
)
{
EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
EFI_STATUS Status;
EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
EFI_STATUS Status;
ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
@@ -87,9 +87,9 @@ EmmcGetOcr (
Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
Packet.Timeout = SD_MMC_HC_GENERIC_TIMEOUT;
SdMmcCmdBlk.CommandIndex = EMMC_SEND_OP_COND;
SdMmcCmdBlk.CommandType = SdMmcCommandTypeBcr;
SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR3;
SdMmcCmdBlk.CommandIndex = EMMC_SEND_OP_COND;
SdMmcCmdBlk.CommandType = SdMmcCommandTypeBcr;
SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR3;
SdMmcCmdBlk.CommandArgument = *Argument;
Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
@@ -118,14 +118,14 @@ EmmcGetOcr (
**/
EFI_STATUS
EmmcGetAllCid (
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
IN UINT8 Slot
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
IN UINT8 Slot
)
{
EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
EFI_STATUS Status;
EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
EFI_STATUS Status;
ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
@@ -135,9 +135,9 @@ EmmcGetAllCid (
Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
Packet.Timeout = SD_MMC_HC_GENERIC_TIMEOUT;
SdMmcCmdBlk.CommandIndex = EMMC_ALL_SEND_CID;
SdMmcCmdBlk.CommandType = SdMmcCommandTypeBcr;
SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR2;
SdMmcCmdBlk.CommandIndex = EMMC_ALL_SEND_CID;
SdMmcCmdBlk.CommandType = SdMmcCommandTypeBcr;
SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR2;
SdMmcCmdBlk.CommandArgument = 0;
Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
@@ -161,15 +161,15 @@ EmmcGetAllCid (
**/
EFI_STATUS
EmmcSetRca (
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
IN UINT8 Slot,
IN UINT16 Rca
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
IN UINT8 Slot,
IN UINT16 Rca
)
{
EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
EFI_STATUS Status;
EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
EFI_STATUS Status;
ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
@@ -179,9 +179,9 @@ EmmcSetRca (
Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
Packet.Timeout = SD_MMC_HC_GENERIC_TIMEOUT;
SdMmcCmdBlk.CommandIndex = EMMC_SET_RELATIVE_ADDR;
SdMmcCmdBlk.CommandType = SdMmcCommandTypeAc;
SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
SdMmcCmdBlk.CommandIndex = EMMC_SET_RELATIVE_ADDR;
SdMmcCmdBlk.CommandType = SdMmcCommandTypeAc;
SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
SdMmcCmdBlk.CommandArgument = (UINT32)Rca << 16;
Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
@@ -211,13 +211,13 @@ EmmcGetCsd (
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
IN UINT8 Slot,
IN UINT16 Rca,
OUT EMMC_CSD *Csd
OUT EMMC_CSD *Csd
)
{
EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
EFI_STATUS Status;
EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
EFI_STATUS Status;
ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
@@ -227,9 +227,9 @@ EmmcGetCsd (
Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
Packet.Timeout = SD_MMC_HC_GENERIC_TIMEOUT;
SdMmcCmdBlk.CommandIndex = EMMC_SEND_CSD;
SdMmcCmdBlk.CommandType = SdMmcCommandTypeAc;
SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR2;
SdMmcCmdBlk.CommandIndex = EMMC_SEND_CSD;
SdMmcCmdBlk.CommandType = SdMmcCommandTypeAc;
SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR2;
SdMmcCmdBlk.CommandArgument = (UINT32)Rca << 16;
Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
@@ -237,7 +237,7 @@ EmmcGetCsd (
//
// For details, refer to SD Host Controller Simplified Spec 3.0 Table 2-12.
//
CopyMem (((UINT8*)Csd) + 1, &SdMmcStatusBlk.Resp0, sizeof (EMMC_CSD) - 1);
CopyMem (((UINT8 *)Csd) + 1, &SdMmcStatusBlk.Resp0, sizeof (EMMC_CSD) - 1);
}
return Status;
@@ -258,15 +258,15 @@ EmmcGetCsd (
**/
EFI_STATUS
EmmcSelect (
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
IN UINT8 Slot,
IN UINT16 Rca
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
IN UINT8 Slot,
IN UINT16 Rca
)
{
EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
EFI_STATUS Status;
EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
EFI_STATUS Status;
ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
@@ -276,9 +276,9 @@ EmmcSelect (
Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
Packet.Timeout = SD_MMC_HC_GENERIC_TIMEOUT;
SdMmcCmdBlk.CommandIndex = EMMC_SELECT_DESELECT_CARD;
SdMmcCmdBlk.CommandType = SdMmcCommandTypeAc;
SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
SdMmcCmdBlk.CommandIndex = EMMC_SELECT_DESELECT_CARD;
SdMmcCmdBlk.CommandType = SdMmcCommandTypeAc;
SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
SdMmcCmdBlk.CommandArgument = (UINT32)Rca << 16;
Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
@@ -303,13 +303,13 @@ EFI_STATUS
EmmcGetExtCsd (
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
IN UINT8 Slot,
OUT EMMC_EXT_CSD *ExtCsd
OUT EMMC_EXT_CSD *ExtCsd
)
{
EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
EFI_STATUS Status;
EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
EFI_STATUS Status;
ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
@@ -319,9 +319,9 @@ EmmcGetExtCsd (
Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
Packet.Timeout = SD_MMC_HC_GENERIC_TIMEOUT;
SdMmcCmdBlk.CommandIndex = EMMC_SEND_EXT_CSD;
SdMmcCmdBlk.CommandType = SdMmcCommandTypeAdtc;
SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
SdMmcCmdBlk.CommandIndex = EMMC_SEND_EXT_CSD;
SdMmcCmdBlk.CommandType = SdMmcCommandTypeAdtc;
SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
SdMmcCmdBlk.CommandArgument = 0x00000000;
Packet.InDataBuffer = ExtCsd;
@@ -350,18 +350,18 @@ EmmcGetExtCsd (
**/
EFI_STATUS
EmmcSwitch (
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
IN UINT8 Slot,
IN UINT8 Access,
IN UINT8 Index,
IN UINT8 Value,
IN UINT8 CmdSet
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
IN UINT8 Slot,
IN UINT8 Access,
IN UINT8 Index,
IN UINT8 Value,
IN UINT8 CmdSet
)
{
EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
EFI_STATUS Status;
EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
EFI_STATUS Status;
ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
@@ -371,9 +371,9 @@ EmmcSwitch (
Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
Packet.Timeout = SD_MMC_HC_GENERIC_TIMEOUT;
SdMmcCmdBlk.CommandIndex = EMMC_SWITCH;
SdMmcCmdBlk.CommandType = SdMmcCommandTypeAc;
SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1b;
SdMmcCmdBlk.CommandIndex = EMMC_SWITCH;
SdMmcCmdBlk.CommandType = SdMmcCommandTypeAc;
SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1b;
SdMmcCmdBlk.CommandArgument = (Access << 24) | (Index << 16) | (Value << 8) | CmdSet;
Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
@@ -400,13 +400,13 @@ EmmcSendStatus (
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
IN UINT8 Slot,
IN UINT16 Rca,
OUT UINT32 *DevStatus
OUT UINT32 *DevStatus
)
{
EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
EFI_STATUS Status;
EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
EFI_STATUS Status;
ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
@@ -416,9 +416,9 @@ EmmcSendStatus (
Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
Packet.Timeout = SD_MMC_HC_GENERIC_TIMEOUT;
SdMmcCmdBlk.CommandIndex = EMMC_SEND_STATUS;
SdMmcCmdBlk.CommandType = SdMmcCommandTypeAc;
SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
SdMmcCmdBlk.CommandIndex = EMMC_SEND_STATUS;
SdMmcCmdBlk.CommandType = SdMmcCommandTypeAc;
SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
SdMmcCmdBlk.CommandArgument = (UINT32)Rca << 16;
Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
@@ -447,16 +447,16 @@ EmmcSendStatus (
**/
EFI_STATUS
EmmcSendTuningBlk (
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
IN UINT8 Slot,
IN UINT8 BusWidth
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
IN UINT8 Slot,
IN UINT8 BusWidth
)
{
EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
EFI_STATUS Status;
UINT8 TuningBlock[128];
EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
EFI_STATUS Status;
UINT8 TuningBlock[128];
ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
@@ -466,9 +466,9 @@ EmmcSendTuningBlk (
Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
Packet.Timeout = SD_MMC_HC_GENERIC_TIMEOUT;
SdMmcCmdBlk.CommandIndex = EMMC_SEND_TUNING_BLOCK;
SdMmcCmdBlk.CommandType = SdMmcCommandTypeAdtc;
SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
SdMmcCmdBlk.CommandIndex = EMMC_SEND_TUNING_BLOCK;
SdMmcCmdBlk.CommandType = SdMmcCommandTypeAdtc;
SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
SdMmcCmdBlk.CommandArgument = 0;
Packet.InDataBuffer = TuningBlock;
@@ -503,24 +503,25 @@ EmmcSendTuningBlk (
**/
EFI_STATUS
EmmcTuningClkForHs200 (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
IN UINT8 Slot,
IN UINT8 BusWidth
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
IN UINT8 Slot,
IN UINT8 BusWidth
)
{
EFI_STATUS Status;
UINT8 HostCtrl2;
UINT8 Retry;
EFI_STATUS Status;
UINT8 HostCtrl2;
UINT8 Retry;
//
// Notify the host that the sampling clock tuning procedure starts.
//
HostCtrl2 = BIT6;
Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
if (EFI_ERROR (Status)) {
return Status;
}
//
// Ask the device to send a sequence of tuning blocks till the tuning procedure is done.
//
@@ -550,11 +551,12 @@ EmmcTuningClkForHs200 (
//
// Abort the tuning procedure and reset the tuning circuit.
//
HostCtrl2 = (UINT8)~(BIT6 | BIT7);
Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
HostCtrl2 = (UINT8) ~(BIT6 | BIT7);
Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
if (EFI_ERROR (Status)) {
return Status;
}
return EFI_DEVICE_ERROR;
}
@@ -615,19 +617,19 @@ EmmcCheckSwitchStatus (
**/
EFI_STATUS
EmmcSwitchBusWidth (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
IN UINT8 Slot,
IN UINT16 Rca,
IN BOOLEAN IsDdr,
IN UINT8 BusWidth
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
IN UINT8 Slot,
IN UINT16 Rca,
IN BOOLEAN IsDdr,
IN UINT8 BusWidth
)
{
EFI_STATUS Status;
UINT8 Access;
UINT8 Index;
UINT8 Value;
UINT8 CmdSet;
EFI_STATUS Status;
UINT8 Access;
UINT8 Index;
UINT8 Value;
UINT8 CmdSet;
//
// Write Byte, the Value field is written into the byte pointed by Index.
@@ -683,23 +685,23 @@ EmmcSwitchBusWidth (
**/
EFI_STATUS
EmmcSwitchBusTiming (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
IN UINT8 Slot,
IN UINT16 Rca,
IN EDKII_SD_MMC_DRIVER_STRENGTH DriverStrength,
IN SD_MMC_BUS_MODE BusTiming,
IN UINT32 ClockFreq
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
IN UINT8 Slot,
IN UINT16 Rca,
IN EDKII_SD_MMC_DRIVER_STRENGTH DriverStrength,
IN SD_MMC_BUS_MODE BusTiming,
IN UINT32 ClockFreq
)
{
EFI_STATUS Status;
UINT8 Access;
UINT8 Index;
UINT8 Value;
UINT8 CmdSet;
SD_MMC_HC_PRIVATE_DATA *Private;
UINT8 HostCtrl1;
BOOLEAN DelaySendStatus;
EFI_STATUS Status;
UINT8 Access;
UINT8 Index;
UINT8 Value;
UINT8 CmdSet;
SD_MMC_HC_PRIVATE_DATA *Private;
UINT8 HostCtrl1;
BOOLEAN DelaySendStatus;
Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
//
@@ -733,15 +735,15 @@ EmmcSwitchBusTiming (
return Status;
}
if (BusTiming == SdMmcMmcHsSdr || BusTiming == SdMmcMmcHsDdr) {
if ((BusTiming == SdMmcMmcHsSdr) || (BusTiming == SdMmcMmcHsDdr)) {
HostCtrl1 = BIT2;
Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
if (EFI_ERROR (Status)) {
return Status;
}
} else {
HostCtrl1 = (UINT8)~BIT2;
Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
HostCtrl1 = (UINT8) ~BIT2;
Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
if (EFI_ERROR (Status)) {
return Status;
}
@@ -767,6 +769,7 @@ EmmcSwitchBusTiming (
if (EFI_ERROR (Status)) {
return Status;
}
DelaySendStatus = FALSE;
} else {
DelaySendStatus = TRUE;
@@ -808,18 +811,19 @@ EmmcSwitchBusTiming (
**/
EFI_STATUS
EmmcSwitchToHighSpeed (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
IN UINT8 Slot,
IN UINT16 Rca,
IN SD_MMC_BUS_SETTINGS *BusMode
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
IN UINT8 Slot,
IN UINT16 Rca,
IN SD_MMC_BUS_SETTINGS *BusMode
)
{
EFI_STATUS Status;
BOOLEAN IsDdr;
if ((BusMode->BusTiming != SdMmcMmcHsSdr && BusMode->BusTiming != SdMmcMmcHsDdr && BusMode->BusTiming != SdMmcMmcLegacy) ||
BusMode->ClockFreq > 52) {
if (((BusMode->BusTiming != SdMmcMmcHsSdr) && (BusMode->BusTiming != SdMmcMmcHsDdr) && (BusMode->BusTiming != SdMmcMmcLegacy)) ||
(BusMode->ClockFreq > 52))
{
return EFI_INVALID_PARAMETER;
}
@@ -855,17 +859,18 @@ EmmcSwitchToHighSpeed (
**/
EFI_STATUS
EmmcSwitchToHS200 (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
IN UINT8 Slot,
IN UINT16 Rca,
IN SD_MMC_BUS_SETTINGS *BusMode
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
IN UINT8 Slot,
IN UINT16 Rca,
IN SD_MMC_BUS_SETTINGS *BusMode
)
{
EFI_STATUS Status;
if (BusMode->BusTiming != SdMmcMmcHs200 ||
(BusMode->BusWidth != 4 && BusMode->BusWidth != 8)) {
if ((BusMode->BusTiming != SdMmcMmcHs200) ||
((BusMode->BusWidth != 4) && (BusMode->BusWidth != 8)))
{
return EFI_INVALID_PARAMETER;
}
@@ -902,25 +907,26 @@ EmmcSwitchToHS200 (
**/
EFI_STATUS
EmmcSwitchToHS400 (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
IN UINT8 Slot,
IN UINT16 Rca,
IN SD_MMC_BUS_SETTINGS *BusMode
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
IN UINT8 Slot,
IN UINT16 Rca,
IN SD_MMC_BUS_SETTINGS *BusMode
)
{
EFI_STATUS Status;
SD_MMC_BUS_SETTINGS Hs200BusMode;
UINT32 HsFreq;
if (BusMode->BusTiming != SdMmcMmcHs400 ||
BusMode->BusWidth != 8) {
if ((BusMode->BusTiming != SdMmcMmcHs400) ||
(BusMode->BusWidth != 8))
{
return EFI_INVALID_PARAMETER;
}
Hs200BusMode.BusTiming = SdMmcMmcHs200;
Hs200BusMode.BusWidth = BusMode->BusWidth;
Hs200BusMode.ClockFreq = BusMode->ClockFreq;
Hs200BusMode.BusTiming = SdMmcMmcHs200;
Hs200BusMode.BusWidth = BusMode->BusWidth;
Hs200BusMode.ClockFreq = BusMode->ClockFreq;
Hs200BusMode.DriverStrength = BusMode->DriverStrength;
Status = EmmcSwitchToHS200 (PciIo, PassThru, Slot, Rca, &Hs200BusMode);
@@ -973,29 +979,34 @@ EmmcIsBusTimingSupported (
Supported = FALSE;
switch (BusTiming) {
case SdMmcMmcHs400:
if ((((ExtCsd->DeviceType & (BIT6 | BIT7)) != 0) && (Capabilities->Hs400 != 0)) && Capabilities->BusWidth8 != 0) {
if ((((ExtCsd->DeviceType & (BIT6 | BIT7)) != 0) && (Capabilities->Hs400 != 0)) && (Capabilities->BusWidth8 != 0)) {
Supported = TRUE;
}
break;
case SdMmcMmcHs200:
if ((((ExtCsd->DeviceType & (BIT4 | BIT5)) != 0) && (Capabilities->Sdr104 != 0))) {
Supported = TRUE;
}
break;
case SdMmcMmcHsDdr:
if ((((ExtCsd->DeviceType & (BIT2 | BIT3)) != 0) && (Capabilities->Ddr50 != 0))) {
Supported = TRUE;
}
break;
case SdMmcMmcHsSdr:
if ((((ExtCsd->DeviceType & BIT1) != 0) && (Capabilities->HighSpeed != 0))) {
Supported = TRUE;
}
break;
case SdMmcMmcLegacy:
if ((ExtCsd->DeviceType & BIT0) != 0) {
Supported = TRUE;
}
break;
default:
ASSERT (FALSE);
@@ -1018,8 +1029,8 @@ EmmcIsBusTimingSupported (
SD_MMC_BUS_MODE
EmmcGetTargetBusTiming (
IN SD_MMC_HC_PRIVATE_DATA *Private,
IN UINT8 SlotIndex,
IN EMMC_EXT_CSD *ExtCsd
IN UINT8 SlotIndex,
IN EMMC_EXT_CSD *ExtCsd
)
{
SD_MMC_BUS_MODE BusTiming;
@@ -1033,6 +1044,7 @@ EmmcGetTargetBusTiming (
if (EmmcIsBusTimingSupported (Private, SlotIndex, ExtCsd, BusTiming)) {
break;
}
BusTiming--;
}
@@ -1052,17 +1064,17 @@ EmmcGetTargetBusTiming (
**/
BOOLEAN
EmmcIsBusWidthSupported (
IN SD_MMC_HC_PRIVATE_DATA *Private,
IN UINT8 SlotIndex,
IN SD_MMC_BUS_MODE BusTiming,
IN UINT16 BusWidth
IN SD_MMC_HC_PRIVATE_DATA *Private,
IN UINT8 SlotIndex,
IN SD_MMC_BUS_MODE BusTiming,
IN UINT16 BusWidth
)
{
if (BusWidth == 8 && Private->Capability[SlotIndex].BusWidth8 != 0) {
if ((BusWidth == 8) && (Private->Capability[SlotIndex].BusWidth8 != 0)) {
return TRUE;
} else if (BusWidth == 4 && BusTiming != SdMmcMmcHs400) {
} else if ((BusWidth == 4) && (BusTiming != SdMmcMmcHs400)) {
return TRUE;
} else if (BusWidth == 1 && (BusTiming == SdMmcMmcHsSdr || BusTiming == SdMmcMmcLegacy)) {
} else if ((BusWidth == 1) && ((BusTiming == SdMmcMmcHsSdr) || (BusTiming == SdMmcMmcLegacy))) {
return TRUE;
}
@@ -1081,10 +1093,10 @@ EmmcIsBusWidthSupported (
**/
UINT8
EmmcGetTargetBusWidth (
IN SD_MMC_HC_PRIVATE_DATA *Private,
IN UINT8 SlotIndex,
IN EMMC_EXT_CSD *ExtCsd,
IN SD_MMC_BUS_MODE BusTiming
IN SD_MMC_HC_PRIVATE_DATA *Private,
IN UINT8 SlotIndex,
IN EMMC_EXT_CSD *ExtCsd,
IN SD_MMC_BUS_MODE BusTiming
)
{
UINT8 BusWidth;
@@ -1092,8 +1104,9 @@ EmmcGetTargetBusWidth (
PreferredBusWidth = Private->Slot[SlotIndex].OperatingParameters.BusWidth;
if (PreferredBusWidth != EDKII_SD_MMC_BUS_WIDTH_IGNORE &&
EmmcIsBusWidthSupported (Private, SlotIndex, BusTiming, PreferredBusWidth)) {
if ((PreferredBusWidth != EDKII_SD_MMC_BUS_WIDTH_IGNORE) &&
EmmcIsBusWidthSupported (Private, SlotIndex, BusTiming, PreferredBusWidth))
{
BusWidth = PreferredBusWidth;
} else if (EmmcIsBusWidthSupported (Private, SlotIndex, BusTiming, 8)) {
BusWidth = 8;
@@ -1118,14 +1131,14 @@ EmmcGetTargetBusWidth (
**/
UINT32
EmmcGetTargetClockFreq (
IN SD_MMC_HC_PRIVATE_DATA *Private,
IN UINT8 SlotIndex,
IN EMMC_EXT_CSD *ExtCsd,
IN SD_MMC_BUS_MODE BusTiming
IN SD_MMC_HC_PRIVATE_DATA *Private,
IN UINT8 SlotIndex,
IN EMMC_EXT_CSD *ExtCsd,
IN SD_MMC_BUS_MODE BusTiming
)
{
UINT32 PreferredClockFreq;
UINT32 MaxClockFreq;
UINT32 PreferredClockFreq;
UINT32 MaxClockFreq;
PreferredClockFreq = Private->Slot[SlotIndex].OperatingParameters.ClockFreq;
@@ -1143,7 +1156,7 @@ EmmcGetTargetClockFreq (
break;
}
if (PreferredClockFreq != EDKII_SD_MMC_CLOCK_FREQ_IGNORE && PreferredClockFreq < MaxClockFreq) {
if ((PreferredClockFreq != EDKII_SD_MMC_CLOCK_FREQ_IGNORE) && (PreferredClockFreq < MaxClockFreq)) {
return PreferredClockFreq;
} else {
return MaxClockFreq;
@@ -1162,20 +1175,21 @@ EmmcGetTargetClockFreq (
**/
EDKII_SD_MMC_DRIVER_STRENGTH
EmmcGetTargetDriverStrength (
IN SD_MMC_HC_PRIVATE_DATA *Private,
IN UINT8 SlotIndex,
IN EMMC_EXT_CSD *ExtCsd,
IN SD_MMC_BUS_MODE BusTiming
IN SD_MMC_HC_PRIVATE_DATA *Private,
IN UINT8 SlotIndex,
IN EMMC_EXT_CSD *ExtCsd,
IN SD_MMC_BUS_MODE BusTiming
)
{
EDKII_SD_MMC_DRIVER_STRENGTH PreferredDriverStrength;
EDKII_SD_MMC_DRIVER_STRENGTH DriverStrength;
PreferredDriverStrength = Private->Slot[SlotIndex].OperatingParameters.DriverStrength;
DriverStrength.Emmc = EmmcDriverStrengthType0;
DriverStrength.Emmc = EmmcDriverStrengthType0;
if (PreferredDriverStrength.Emmc != EDKII_SD_MMC_DRIVER_STRENGTH_IGNORE &&
(ExtCsd->DriverStrength & (BIT0 << PreferredDriverStrength.Emmc))) {
if ((PreferredDriverStrength.Emmc != EDKII_SD_MMC_DRIVER_STRENGTH_IGNORE) &&
(ExtCsd->DriverStrength & (BIT0 << PreferredDriverStrength.Emmc)))
{
DriverStrength.Emmc = PreferredDriverStrength.Emmc;
}
@@ -1198,9 +1212,9 @@ EmmcGetTargetBusMode (
OUT SD_MMC_BUS_SETTINGS *BusMode
)
{
BusMode->BusTiming = EmmcGetTargetBusTiming (Private, SlotIndex, ExtCsd);
BusMode->BusWidth = EmmcGetTargetBusWidth (Private, SlotIndex, ExtCsd, BusMode->BusTiming);
BusMode->ClockFreq = EmmcGetTargetClockFreq (Private, SlotIndex, ExtCsd, BusMode->BusTiming);
BusMode->BusTiming = EmmcGetTargetBusTiming (Private, SlotIndex, ExtCsd);
BusMode->BusWidth = EmmcGetTargetBusWidth (Private, SlotIndex, ExtCsd, BusMode->BusTiming);
BusMode->ClockFreq = EmmcGetTargetClockFreq (Private, SlotIndex, ExtCsd, BusMode->BusTiming);
BusMode->DriverStrength = EmmcGetTargetDriverStrength (Private, SlotIndex, ExtCsd, BusMode->BusTiming);
}
@@ -1221,17 +1235,17 @@ EmmcGetTargetBusMode (
**/
EFI_STATUS
EmmcSetBusMode (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
IN UINT8 Slot,
IN UINT16 Rca
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
IN UINT8 Slot,
IN UINT16 Rca
)
{
EFI_STATUS Status;
EMMC_CSD Csd;
EMMC_EXT_CSD ExtCsd;
SD_MMC_BUS_SETTINGS BusMode;
SD_MMC_HC_PRIVATE_DATA *Private;
EFI_STATUS Status;
EMMC_CSD Csd;
EMMC_EXT_CSD ExtCsd;
SD_MMC_BUS_SETTINGS BusMode;
SD_MMC_HC_PRIVATE_DATA *Private;
Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
@@ -1260,8 +1274,14 @@ EmmcSetBusMode (
EmmcGetTargetBusMode (Private, Slot, &ExtCsd, &BusMode);
DEBUG ((DEBUG_INFO, "EmmcSetBusMode: Target bus mode: timing = %d, width = %d, clock freq = %d, driver strength = %d\n",
BusMode.BusTiming, BusMode.BusWidth, BusMode.ClockFreq, BusMode.DriverStrength.Emmc));
DEBUG ((
DEBUG_INFO,
"EmmcSetBusMode: Target bus mode: timing = %d, width = %d, clock freq = %d, driver strength = %d\n",
BusMode.BusTiming,
BusMode.BusWidth,
BusMode.ClockFreq,
BusMode.DriverStrength.Emmc
));
if (BusMode.BusTiming == SdMmcMmcHs400) {
Status = EmmcSwitchToHS400 (PciIo, PassThru, Slot, Rca, &BusMode);
@@ -1296,8 +1316,8 @@ EmmcSetBusMode (
**/
EFI_STATUS
EmmcIdentification (
IN SD_MMC_HC_PRIVATE_DATA *Private,
IN UINT8 Slot
IN SD_MMC_HC_PRIVATE_DATA *Private,
IN UINT8 Slot
)
{
EFI_STATUS Status;
@@ -1324,13 +1344,15 @@ EmmcIdentification (
DEBUG ((DEBUG_VERBOSE, "EmmcIdentification: Executing Cmd1 fails with %r\n", Status));
return Status;
}
Ocr |= BIT30;
if (Retry++ == 100) {
DEBUG ((DEBUG_VERBOSE, "EmmcIdentification: Executing Cmd1 fails too many times\n"));
return EFI_DEVICE_ERROR;
}
gBS->Stall(10 * 1000);
gBS->Stall (10 * 1000);
} while ((Ocr & BIT31) == 0);
Status = EmmcGetAllCid (PassThru, Slot);
@@ -1338,6 +1360,7 @@ EmmcIdentification (
DEBUG ((DEBUG_VERBOSE, "EmmcIdentification: Executing Cmd2 fails with %r\n", Status));
return Status;
}
//
// Slot starts from 0 and valid RCA starts from 1.
// Here we takes a simple formula to calculate the RCA.
@@ -1350,6 +1373,7 @@ EmmcIdentification (
DEBUG ((DEBUG_ERROR, "EmmcIdentification: Executing Cmd3 fails with %r\n", Status));
return Status;
}
//
// Enter Data Tranfer Mode.
//
@@ -1360,4 +1384,3 @@ EmmcIdentification (
return Status;
}

393
MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
View File

@@ -23,14 +23,14 @@
**/
EFI_STATUS
SdCardReset (
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
IN UINT8 Slot
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
IN UINT8 Slot
)
{
EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
EFI_STATUS Status;
EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
EFI_STATUS Status;
ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
@@ -65,16 +65,16 @@ SdCardReset (
**/
EFI_STATUS
SdCardVoltageCheck (
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
IN UINT8 Slot,
IN UINT8 SupplyVoltage,
IN UINT8 CheckPattern
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
IN UINT8 Slot,
IN UINT8 SupplyVoltage,
IN UINT8 CheckPattern
)
{
EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
EFI_STATUS Status;
EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
EFI_STATUS Status;
ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
@@ -84,9 +84,9 @@ SdCardVoltageCheck (
Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
Packet.Timeout = SD_MMC_HC_GENERIC_TIMEOUT;
SdMmcCmdBlk.CommandIndex = SD_SEND_IF_COND;
SdMmcCmdBlk.CommandType = SdMmcCommandTypeBcr;
SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR7;
SdMmcCmdBlk.CommandIndex = SD_SEND_IF_COND;
SdMmcCmdBlk.CommandType = SdMmcCommandTypeBcr;
SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR7;
SdMmcCmdBlk.CommandArgument = (SupplyVoltage << 8) | CheckPattern;
Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
@@ -116,17 +116,17 @@ SdCardVoltageCheck (
**/
EFI_STATUS
SdioSendOpCond (
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
IN UINT8 Slot,
IN UINT32 VoltageWindow,
IN BOOLEAN S18R
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
IN UINT8 Slot,
IN UINT32 VoltageWindow,
IN BOOLEAN S18R
)
{
EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
EFI_STATUS Status;
UINT32 Switch;
EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
EFI_STATUS Status;
UINT32 Switch;
ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
@@ -176,16 +176,16 @@ SdCardSendOpCond (
IN BOOLEAN S18R,
IN BOOLEAN Xpc,
IN BOOLEAN Hcs,
OUT UINT32 *Ocr
OUT UINT32 *Ocr
)
{
EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
EFI_STATUS Status;
UINT32 Switch;
UINT32 MaxPower;
UINT32 HostCapacity;
EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
EFI_STATUS Status;
UINT32 Switch;
UINT32 MaxPower;
UINT32 HostCapacity;
ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
@@ -195,9 +195,9 @@ SdCardSendOpCond (
Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
Packet.Timeout = SD_MMC_HC_GENERIC_TIMEOUT;
SdMmcCmdBlk.CommandIndex = SD_APP_CMD;
SdMmcCmdBlk.CommandType = SdMmcCommandTypeAc;
SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
SdMmcCmdBlk.CommandIndex = SD_APP_CMD;
SdMmcCmdBlk.CommandType = SdMmcCommandTypeAc;
SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
SdMmcCmdBlk.CommandArgument = (UINT32)Rca << 16;
Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
@@ -241,14 +241,14 @@ SdCardSendOpCond (
**/
EFI_STATUS
SdCardAllSendCid (
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
IN UINT8 Slot
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
IN UINT8 Slot
)
{
EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
EFI_STATUS Status;
EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
EFI_STATUS Status;
ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
@@ -285,13 +285,13 @@ EFI_STATUS
SdCardSetRca (
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
IN UINT8 Slot,
OUT UINT16 *Rca
OUT UINT16 *Rca
)
{
EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
EFI_STATUS Status;
EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
EFI_STATUS Status;
ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
@@ -328,15 +328,15 @@ SdCardSetRca (
**/
EFI_STATUS
SdCardSelect (
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
IN UINT8 Slot,
IN UINT16 Rca
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
IN UINT8 Slot,
IN UINT16 Rca
)
{
EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
EFI_STATUS Status;
EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
EFI_STATUS Status;
ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
@@ -351,6 +351,7 @@ SdCardSelect (
if (Rca != 0) {
SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1b;
}
SdMmcCmdBlk.CommandArgument = (UINT32)Rca << 16;
Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
@@ -372,14 +373,14 @@ SdCardSelect (
**/
EFI_STATUS
SdCardVoltageSwitch (
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
IN UINT8 Slot
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
IN UINT8 Slot
)
{
EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
EFI_STATUS Status;
EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
EFI_STATUS Status;
ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
@@ -389,9 +390,9 @@ SdCardVoltageSwitch (
Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
Packet.Timeout = SD_MMC_HC_GENERIC_TIMEOUT;
SdMmcCmdBlk.CommandIndex = SD_VOLTAGE_SWITCH;
SdMmcCmdBlk.CommandType = SdMmcCommandTypeAc;
SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
SdMmcCmdBlk.CommandIndex = SD_VOLTAGE_SWITCH;
SdMmcCmdBlk.CommandType = SdMmcCommandTypeAc;
SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
SdMmcCmdBlk.CommandArgument = 0;
Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
@@ -415,17 +416,17 @@ SdCardVoltageSwitch (
**/
EFI_STATUS
SdCardSetBusWidth (
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
IN UINT8 Slot,
IN UINT16 Rca,
IN UINT8 BusWidth
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
IN UINT8 Slot,
IN UINT16 Rca,
IN UINT8 BusWidth
)
{
EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
EFI_STATUS Status;
UINT8 Value;
EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
EFI_STATUS Status;
UINT8 Value;
ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
@@ -435,9 +436,9 @@ SdCardSetBusWidth (
Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
Packet.Timeout = SD_MMC_HC_GENERIC_TIMEOUT;
SdMmcCmdBlk.CommandIndex = SD_APP_CMD;
SdMmcCmdBlk.CommandType = SdMmcCommandTypeAc;
SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
SdMmcCmdBlk.CommandIndex = SD_APP_CMD;
SdMmcCmdBlk.CommandType = SdMmcCommandTypeAc;
SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
SdMmcCmdBlk.CommandArgument = (UINT32)Rca << 16;
Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
@@ -490,15 +491,15 @@ SdCardSwitch (
IN SD_DRIVER_STRENGTH_TYPE DriverStrength,
IN UINT8 PowerLimit,
IN BOOLEAN Mode,
OUT UINT8 *SwitchResp
OUT UINT8 *SwitchResp
)
{
EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
EFI_STATUS Status;
UINT32 ModeValue;
UINT8 AccessMode;
EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
EFI_STATUS Status;
UINT32 ModeValue;
UINT8 AccessMode;
ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
@@ -552,7 +553,8 @@ SdCardSwitch (
if ((((AccessMode & 0xF) != 0xF) && ((SwitchResp[16] & 0xF) != AccessMode)) ||
(((CommandSystem & 0xF) != 0xF) && (((SwitchResp[16] >> 4) & 0xF) != CommandSystem)) ||
(((DriverStrength & 0xF) != 0xF) && ((SwitchResp[15] & 0xF) != DriverStrength)) ||
(((PowerLimit & 0xF) != 0xF) && (((SwitchResp[15] >> 4) & 0xF) != PowerLimit))) {
(((PowerLimit & 0xF) != 0xF) && (((SwitchResp[15] >> 4) & 0xF) != PowerLimit)))
{
return EFI_DEVICE_ERROR;
}
}
@@ -579,13 +581,13 @@ SdCardSendStatus (
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
IN UINT8 Slot,
IN UINT16 Rca,
OUT UINT32 *DevStatus
OUT UINT32 *DevStatus
)
{
EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
EFI_STATUS Status;
EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
EFI_STATUS Status;
ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
@@ -595,9 +597,9 @@ SdCardSendStatus (
Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
Packet.Timeout = SD_MMC_HC_GENERIC_TIMEOUT;
SdMmcCmdBlk.CommandIndex = SD_SEND_STATUS;
SdMmcCmdBlk.CommandType = SdMmcCommandTypeAc;
SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
SdMmcCmdBlk.CommandIndex = SD_SEND_STATUS;
SdMmcCmdBlk.CommandType = SdMmcCommandTypeAc;
SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
SdMmcCmdBlk.CommandArgument = (UINT32)Rca << 16;
Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
@@ -625,15 +627,15 @@ SdCardSendStatus (
**/
EFI_STATUS
SdCardSendTuningBlk (
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
IN UINT8 Slot
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
IN UINT8 Slot
)
{
EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
EFI_STATUS Status;
UINT8 TuningBlock[64];
EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
EFI_STATUS Status;
UINT8 TuningBlock[64];
ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
@@ -643,9 +645,9 @@ SdCardSendTuningBlk (
Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
Packet.Timeout = SD_MMC_HC_GENERIC_TIMEOUT;
SdMmcCmdBlk.CommandIndex = SD_SEND_TUNING_BLOCK;
SdMmcCmdBlk.CommandType = SdMmcCommandTypeAdtc;
SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
SdMmcCmdBlk.CommandIndex = SD_SEND_TUNING_BLOCK;
SdMmcCmdBlk.CommandType = SdMmcCommandTypeAdtc;
SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
SdMmcCmdBlk.CommandArgument = 0;
Packet.InDataBuffer = TuningBlock;
@@ -675,23 +677,24 @@ SdCardSendTuningBlk (
**/
EFI_STATUS
SdCardTuningClock (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
IN UINT8 Slot
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
IN UINT8 Slot
)
{
EFI_STATUS Status;
UINT8 HostCtrl2;
UINT8 Retry;
EFI_STATUS Status;
UINT8 HostCtrl2;
UINT8 Retry;
//
// Notify the host that the sampling clock tuning procedure starts.
//
HostCtrl2 = BIT6;
Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
if (EFI_ERROR (Status)) {
return Status;
}
//
// Ask the device to send a sequence of tuning blocks till the tuning procedure is done.
//
@@ -711,6 +714,7 @@ SdCardTuningClock (
if ((HostCtrl2 & (BIT6 | BIT7)) == 0) {
break;
}
if ((HostCtrl2 & (BIT6 | BIT7)) == BIT7) {
return EFI_SUCCESS;
}
@@ -720,11 +724,12 @@ SdCardTuningClock (
//
// Abort the tuning procedure and reset the tuning circuit.
//
HostCtrl2 = (UINT8)~(BIT6 | BIT7);
Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
HostCtrl2 = (UINT8) ~(BIT6 | BIT7);
Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
if (EFI_ERROR (Status)) {
return Status;
}
return EFI_DEVICE_ERROR;
}
@@ -746,15 +751,15 @@ SdCardTuningClock (
**/
EFI_STATUS
SdCardSwitchBusWidth (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
IN UINT8 Slot,
IN UINT16 Rca,
IN UINT8 BusWidth
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
IN UINT8 Slot,
IN UINT16 Rca,
IN UINT8 BusWidth
)
{
EFI_STATUS Status;
UINT32 DevStatus;
EFI_STATUS Status;
UINT32 DevStatus;
Status = SdCardSetBusWidth (PassThru, Slot, Rca, BusWidth);
if (EFI_ERROR (Status)) {
@@ -767,6 +772,7 @@ SdCardSwitchBusWidth (
DEBUG ((DEBUG_ERROR, "SdCardSwitchBusWidth: Send status fails with %r\n", Status));
return Status;
}
//
// Check the switch operation is really successful or not.
//
@@ -793,14 +799,14 @@ SdCardSwitchBusWidth (
**/
BOOLEAN
SdIsBusTimingSupported (
IN SD_MMC_HC_PRIVATE_DATA *Private,
IN UINT8 SlotIndex,
IN UINT8 CardSupportedBusTimings,
IN BOOLEAN IsInUhsI,
IN SD_MMC_BUS_MODE BusTiming
IN SD_MMC_HC_PRIVATE_DATA *Private,
IN UINT8 SlotIndex,
IN UINT8 CardSupportedBusTimings,
IN BOOLEAN IsInUhsI,
IN SD_MMC_BUS_MODE BusTiming
)
{
SD_MMC_HC_SLOT_CAP *Capability;
SD_MMC_HC_SLOT_CAP *Capability;
Capability = &Private->Capability[SlotIndex];
@@ -810,26 +816,31 @@ SdIsBusTimingSupported (
if ((Capability->Sdr104 != 0) && ((CardSupportedBusTimings & BIT3) != 0)) {
return TRUE;
}
break;
case SdMmcUhsDdr50:
if ((Capability->Ddr50 != 0) && ((CardSupportedBusTimings & BIT4) != 0)) {
return TRUE;
}
break;
case SdMmcUhsSdr50:
if ((Capability->Sdr50 != 0) && ((CardSupportedBusTimings & BIT2) != 0)) {
return TRUE;
}
break;
case SdMmcUhsSdr25:
if ((CardSupportedBusTimings & BIT1) != 0) {
return TRUE;
}
break;
case SdMmcUhsSdr12:
if ((CardSupportedBusTimings & BIT0) != 0) {
return TRUE;
}
break;
default:
break;
@@ -837,14 +848,16 @@ SdIsBusTimingSupported (
} else {
switch (BusTiming) {
case SdMmcSdHs:
if ((Capability->HighSpeed != 0) && (CardSupportedBusTimings & BIT1) != 0) {
if ((Capability->HighSpeed != 0) && ((CardSupportedBusTimings & BIT1) != 0)) {
return TRUE;
}
break;
case SdMmcSdDs:
if ((CardSupportedBusTimings & BIT0) != 0) {
return TRUE;
}
break;
default:
break;
@@ -886,6 +899,7 @@ SdGetTargetBusTiming (
if (SdIsBusTimingSupported (Private, SlotIndex, CardSupportedBusTimings, IsInUhsI, BusTiming)) {
break;
}
BusTiming--;
}
@@ -903,9 +917,9 @@ SdGetTargetBusTiming (
**/
UINT8
SdGetTargetBusWidth (
IN SD_MMC_HC_PRIVATE_DATA *Private,
IN UINT8 SlotIndex,
IN SD_MMC_BUS_MODE BusTiming
IN SD_MMC_HC_PRIVATE_DATA *Private,
IN UINT8 SlotIndex,
IN SD_MMC_BUS_MODE BusTiming
)
{
UINT8 BusWidth;
@@ -913,9 +927,10 @@ SdGetTargetBusWidth (
PreferredBusWidth = Private->Slot[SlotIndex].OperatingParameters.BusWidth;
if (BusTiming == SdMmcSdDs || BusTiming == SdMmcSdHs) {
if (PreferredBusWidth != EDKII_SD_MMC_BUS_WIDTH_IGNORE &&
(PreferredBusWidth == 1 || PreferredBusWidth == 4)) {
if ((BusTiming == SdMmcSdDs) || (BusTiming == SdMmcSdHs)) {
if ((PreferredBusWidth != EDKII_SD_MMC_BUS_WIDTH_IGNORE) &&
((PreferredBusWidth == 1) || (PreferredBusWidth == 4)))
{
BusWidth = PreferredBusWidth;
} else {
BusWidth = 4;
@@ -943,13 +958,13 @@ SdGetTargetBusWidth (
**/
UINT32
SdGetTargetBusClockFreq (
IN SD_MMC_HC_PRIVATE_DATA *Private,
IN UINT8 SlotIndex,
IN SD_MMC_BUS_MODE BusTiming
IN SD_MMC_HC_PRIVATE_DATA *Private,
IN UINT8 SlotIndex,
IN SD_MMC_BUS_MODE BusTiming
)
{
UINT32 PreferredClockFreq;
UINT32 MaxClockFreq;
UINT32 PreferredClockFreq;
UINT32 MaxClockFreq;
PreferredClockFreq = Private->Slot[SlotIndex].OperatingParameters.ClockFreq;
@@ -971,7 +986,7 @@ SdGetTargetBusClockFreq (
MaxClockFreq = 25;
}
if (PreferredClockFreq != EDKII_SD_MMC_CLOCK_FREQ_IGNORE && PreferredClockFreq < MaxClockFreq) {
if ((PreferredClockFreq != EDKII_SD_MMC_CLOCK_FREQ_IGNORE) && (PreferredClockFreq < MaxClockFreq)) {
return PreferredClockFreq;
} else {
return MaxClockFreq;
@@ -990,32 +1005,33 @@ SdGetTargetBusClockFreq (
**/
EDKII_SD_MMC_DRIVER_STRENGTH
SdGetTargetDriverStrength (
IN SD_MMC_HC_PRIVATE_DATA *Private,
IN UINT8 SlotIndex,
IN UINT8 CardSupportedDriverStrengths,
IN SD_MMC_BUS_MODE BusTiming
IN SD_MMC_HC_PRIVATE_DATA *Private,
IN UINT8 SlotIndex,
IN UINT8 CardSupportedDriverStrengths,
IN SD_MMC_BUS_MODE BusTiming
)
{
EDKII_SD_MMC_DRIVER_STRENGTH PreferredDriverStrength;
EDKII_SD_MMC_DRIVER_STRENGTH DriverStrength;
if (BusTiming == SdMmcSdDs || BusTiming == SdMmcSdHs) {
if ((BusTiming == SdMmcSdDs) || (BusTiming == SdMmcSdHs)) {
DriverStrength.Sd = SdDriverStrengthIgnore;
return DriverStrength;
}
PreferredDriverStrength = Private->Slot[SlotIndex].OperatingParameters.DriverStrength;
DriverStrength.Sd = SdDriverStrengthTypeB;
DriverStrength.Sd = SdDriverStrengthTypeB;
if (PreferredDriverStrength.Sd != EDKII_SD_MMC_DRIVER_STRENGTH_IGNORE &&
(CardSupportedDriverStrengths & (BIT0 << PreferredDriverStrength.Sd))) {
if ((PreferredDriverStrength.Sd == SdDriverStrengthTypeA &&
(Private->Capability[SlotIndex].DriverTypeA != 0)) ||
(PreferredDriverStrength.Sd == SdDriverStrengthTypeC &&
(Private->Capability[SlotIndex].DriverTypeC != 0)) ||
(PreferredDriverStrength.Sd == SdDriverStrengthTypeD &&
(Private->Capability[SlotIndex].DriverTypeD != 0))) {
if ((PreferredDriverStrength.Sd != EDKII_SD_MMC_DRIVER_STRENGTH_IGNORE) &&
(CardSupportedDriverStrengths & (BIT0 << PreferredDriverStrength.Sd)))
{
if (((PreferredDriverStrength.Sd == SdDriverStrengthTypeA) &&
(Private->Capability[SlotIndex].DriverTypeA != 0)) ||
((PreferredDriverStrength.Sd == SdDriverStrengthTypeC) &&
(Private->Capability[SlotIndex].DriverTypeC != 0)) ||
((PreferredDriverStrength.Sd == SdDriverStrengthTypeD) &&
(Private->Capability[SlotIndex].DriverTypeD != 0)))
{
DriverStrength.Sd = PreferredDriverStrength.Sd;
}
}
@@ -1041,9 +1057,9 @@ SdGetTargetBusMode (
OUT SD_MMC_BUS_SETTINGS *BusMode
)
{
BusMode->BusTiming = SdGetTargetBusTiming (Private, SlotIndex, SwitchQueryResp[13], IsInUhsI);
BusMode->BusWidth = SdGetTargetBusWidth (Private, SlotIndex, BusMode->BusTiming);
BusMode->ClockFreq = SdGetTargetBusClockFreq (Private, SlotIndex, BusMode->BusTiming);
BusMode->BusTiming = SdGetTargetBusTiming (Private, SlotIndex, SwitchQueryResp[13], IsInUhsI);
BusMode->BusWidth = SdGetTargetBusWidth (Private, SlotIndex, BusMode->BusTiming);
BusMode->ClockFreq = SdGetTargetBusClockFreq (Private, SlotIndex, BusMode->BusTiming);
BusMode->DriverStrength = SdGetTargetDriverStrength (Private, SlotIndex, SwitchQueryResp[9], BusMode->BusTiming);
}
@@ -1065,19 +1081,19 @@ SdGetTargetBusMode (
**/
EFI_STATUS
SdCardSetBusMode (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
IN UINT8 Slot,
IN UINT16 Rca,
IN BOOLEAN S18A
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
IN UINT8 Slot,
IN UINT16 Rca,
IN BOOLEAN S18A
)
{
EFI_STATUS Status;
SD_MMC_HC_SLOT_CAP *Capability;
UINT8 HostCtrl1;
UINT8 SwitchResp[64];
SD_MMC_HC_PRIVATE_DATA *Private;
SD_MMC_BUS_SETTINGS BusMode;
EFI_STATUS Status;
SD_MMC_HC_SLOT_CAP *Capability;
UINT8 HostCtrl1;
UINT8 SwitchResp[64];
SD_MMC_HC_PRIVATE_DATA *Private;
SD_MMC_BUS_SETTINGS BusMode;
Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
@@ -1109,8 +1125,14 @@ SdCardSetBusMode (
SdGetTargetBusMode (Private, Slot, SwitchResp, S18A, &BusMode);
DEBUG ((DEBUG_INFO, "SdCardSetBusMode: Target bus mode: bus timing = %d, bus width = %d, clock freq[MHz] = %d, driver strength = %d\n",
BusMode.BusTiming, BusMode.BusWidth, BusMode.ClockFreq, BusMode.DriverStrength.Sd));
DEBUG ((
DEBUG_INFO,
"SdCardSetBusMode: Target bus mode: bus timing = %d, bus width = %d, clock freq[MHz] = %d, driver strength = %d\n",
BusMode.BusTiming,
BusMode.BusWidth,
BusMode.ClockFreq,
BusMode.DriverStrength.Sd
));
if (!S18A) {
Status = SdCardSwitchBusWidth (PciIo, PassThru, Slot, Rca, BusMode.BusWidth);
@@ -1134,7 +1156,7 @@ SdCardSetBusMode (
//
if (BusMode.BusTiming == SdMmcSdHs) {
HostCtrl1 = BIT2;
Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
if (EFI_ERROR (Status)) {
return Status;
}
@@ -1174,8 +1196,8 @@ SdCardSetBusMode (
**/
EFI_STATUS
SdCardIdentification (
IN SD_MMC_HC_PRIVATE_DATA *Private,
IN UINT8 Slot
IN SD_MMC_HC_PRIVATE_DATA *Private,
IN UINT8 Slot
)
{
EFI_STATUS Status;
@@ -1202,6 +1224,7 @@ SdCardIdentification (
DEBUG ((DEBUG_INFO, "SdCardIdentification: Executing Cmd0 fails with %r\n", Status));
return Status;
}
//
// 2. Send Cmd8 to the device
//
@@ -1210,6 +1233,7 @@ SdCardIdentification (
DEBUG ((DEBUG_INFO, "SdCardIdentification: Executing Cmd8 fails with %r\n", Status));
return Status;
}
//
// 3. Send SDIO Cmd5 to the device to the SDIO device OCR register.
//
@@ -1218,6 +1242,7 @@ SdCardIdentification (
DEBUG ((DEBUG_INFO, "SdCardIdentification: Found SDIO device, ignore it as we don't support\n"));
return EFI_DEVICE_ERROR;
}
//
// 4. Send Acmd41 with voltage window 0 to the device
//
@@ -1259,7 +1284,8 @@ SdCardIdentification (
}
if (((ControllerVer & 0xFF) >= SD_MMC_HC_CTRL_VER_300) &&
((ControllerVer & 0xFF) <= SD_MMC_HC_CTRL_VER_420)) {
((ControllerVer & 0xFF) <= SD_MMC_HC_CTRL_VER_420))
{
S18r = TRUE;
} else if (((ControllerVer & 0xFF) == SD_MMC_HC_CTRL_VER_100) || ((ControllerVer & 0xFF) == SD_MMC_HC_CTRL_VER_200)) {
S18r = FALSE;
@@ -1267,6 +1293,7 @@ SdCardIdentification (
ASSERT (FALSE);
return EFI_UNSUPPORTED;
}
//
// 5. Repeatly send Acmd41 with supply voltage window to the device.
// Note here we only support the cards complied with SD physical
@@ -1285,7 +1312,8 @@ SdCardIdentification (
DEBUG ((DEBUG_ERROR, "SdCardIdentification: SdCardSendOpCond fails too many times\n"));
return EFI_DEVICE_ERROR;
}
gBS->Stall(10 * 1000);
gBS->Stall (10 * 1000);
} while ((Ocr & BIT31) == 0);
//
@@ -1293,10 +1321,11 @@ SdCardIdentification (
// (One of support bits is set to 1: SDR50, SDR104 or DDR50 in the
// Capabilities register), switch its voltage to 1.8V.
//
if ((Private->Capability[Slot].Sdr50 != 0 ||
Private->Capability[Slot].Sdr104 != 0 ||
Private->Capability[Slot].Ddr50 != 0) &&
((Ocr & BIT24) != 0)) {
if (((Private->Capability[Slot].Sdr50 != 0) ||
(Private->Capability[Slot].Sdr104 != 0) ||
(Private->Capability[Slot].Ddr50 != 0)) &&
((Ocr & BIT24) != 0))
{
Status = SdCardVoltageSwitch (PassThru, Slot);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "SdCardIdentification: Executing SdCardVoltageSwitch fails with %r\n", Status));
@@ -1315,7 +1344,8 @@ SdCardIdentification (
Status = EFI_DEVICE_ERROR;
goto Error;
}
HostCtrl2 = BIT3;
HostCtrl2 = BIT3;
SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
gBS->Stall (5000);
@@ -1341,6 +1371,7 @@ SdCardIdentification (
goto Error;
}
}
DEBUG ((DEBUG_INFO, "SdCardIdentification: Switch to 1.8v signal voltage success\n"));
}
@@ -1355,6 +1386,7 @@ SdCardIdentification (
DEBUG ((DEBUG_ERROR, "SdCardIdentification: Executing SdCardSetRca fails with %r\n", Status));
return Status;
}
//
// Enter Data Tranfer Mode.
//
@@ -1369,8 +1401,7 @@ Error:
//
// Set SD Bus Power = 0
//
PowerCtrl = (UINT8)~BIT0;
Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_POWER_CTRL, sizeof (PowerCtrl), &PowerCtrl);
PowerCtrl = (UINT8) ~BIT0;
Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_POWER_CTRL, sizeof (PowerCtrl), &PowerCtrl);
return EFI_DEVICE_ERROR;
}

363
MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c
View File

@@ -14,12 +14,12 @@
#include "SdMmcPciHcDxe.h"
EDKII_SD_MMC_OVERRIDE *mOverride;
EDKII_SD_MMC_OVERRIDE *mOverride;
//
// Driver Global Variables
//
EFI_DRIVER_BINDING_PROTOCOL gSdMmcPciHcDriverBinding = {
EFI_DRIVER_BINDING_PROTOCOL gSdMmcPciHcDriverBinding = {
SdMmcPciHcDriverBindingSupported,
SdMmcPciHcDriverBindingStart,
SdMmcPciHcDriverBindingStop,
@@ -28,7 +28,7 @@ EFI_DRIVER_BINDING_PROTOCOL gSdMmcPciHcDriverBinding = {
NULL
};
#define SLOT_INIT_TEMPLATE {0, UnknownSlot, 0, 0, 0, 0, \
#define SLOT_INIT_TEMPLATE {0, UnknownSlot, 0, 0, 0, 0,\
{EDKII_SD_MMC_BUS_WIDTH_IGNORE,\
EDKII_SD_MMC_CLOCK_FREQ_IGNORE,\
{EDKII_SD_MMC_DRIVER_STRENGTH_IGNORE}}}
@@ -36,7 +36,7 @@ EFI_DRIVER_BINDING_PROTOCOL gSdMmcPciHcDriverBinding = {
//
// Template for SD/MMC host controller private data.
//
SD_MMC_HC_PRIVATE_DATA gSdMmcPciHcTemplate = {
SD_MMC_HC_PRIVATE_DATA gSdMmcPciHcTemplate = {
SD_MMC_HC_PRIVATE_SIGNATURE, // Signature
NULL, // ControllerHandle
NULL, // PciIo
@@ -63,7 +63,7 @@ SD_MMC_HC_PRIVATE_DATA gSdMmcPciHcTemplate = {
SLOT_INIT_TEMPLATE
},
{ // Capability
{0},
{ 0 },
},
{ // MaxCurrent
0,
@@ -73,25 +73,25 @@ SD_MMC_HC_PRIVATE_DATA gSdMmcPciHcTemplate = {
}
};
SD_DEVICE_PATH mSdDpTemplate = {
SD_DEVICE_PATH mSdDpTemplate = {
{
MESSAGING_DEVICE_PATH,
MSG_SD_DP,
{
(UINT8) (sizeof (SD_DEVICE_PATH)),
(UINT8) ((sizeof (SD_DEVICE_PATH)) >> 8)
(UINT8)(sizeof (SD_DEVICE_PATH)),
(UINT8)((sizeof (SD_DEVICE_PATH)) >> 8)
}
},
0
};
EMMC_DEVICE_PATH mEmmcDpTemplate = {
EMMC_DEVICE_PATH mEmmcDpTemplate = {
{
MESSAGING_DEVICE_PATH,
MSG_EMMC_DP,
{
(UINT8) (sizeof (EMMC_DEVICE_PATH)),
(UINT8) ((sizeof (EMMC_DEVICE_PATH)) >> 8)
(UINT8)(sizeof (EMMC_DEVICE_PATH)),
(UINT8)((sizeof (EMMC_DEVICE_PATH)) >> 8)
}
},
0
@@ -101,7 +101,7 @@ EMMC_DEVICE_PATH mEmmcDpTemplate = {
// Prioritized function list to detect card type.
// User could add other card detection logic here.
//
CARD_TYPE_DETECT_ROUTINE mCardTypeDetectRoutineTable[] = {
CARD_TYPE_DETECT_ROUTINE mCardTypeDetectRoutineTable[] = {
EmmcIdentification,
SdCardIdentification,
NULL
@@ -124,7 +124,7 @@ InitializeSdMmcPciHcDxe (
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
EFI_STATUS Status;
Status = EfiLibInstallDriverBindingComponentName2 (
ImageHandle,
@@ -150,19 +150,19 @@ InitializeSdMmcPciHcDxe (
VOID
EFIAPI
ProcessAsyncTaskList (
IN EFI_EVENT Event,
IN VOID* Context
IN EFI_EVENT Event,
IN VOID *Context
)
{
SD_MMC_HC_PRIVATE_DATA *Private;
LIST_ENTRY *Link;
SD_MMC_HC_TRB *Trb;
EFI_STATUS Status;
EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
BOOLEAN InfiniteWait;
EFI_EVENT TrbEvent;
SD_MMC_HC_PRIVATE_DATA *Private;
LIST_ENTRY *Link;
SD_MMC_HC_TRB *Trb;
EFI_STATUS Status;
EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
BOOLEAN InfiniteWait;
EFI_EVENT TrbEvent;
Private = (SD_MMC_HC_PRIVATE_DATA*)Context;
Private = (SD_MMC_HC_PRIVATE_DATA *)Context;
//
// Check if the first entry in the async I/O queue is done or not.
@@ -176,6 +176,7 @@ ProcessAsyncTaskList (
Status = EFI_NO_MEDIA;
goto Done;
}
if (!Trb->Started) {
//
// Check whether the cmd/data line is ready for transfer.
@@ -183,7 +184,7 @@ ProcessAsyncTaskList (
Status = SdMmcCheckTrbEnv (Private, Trb);
if (!EFI_ERROR (Status)) {
Trb->Started = TRUE;
Status = SdMmcExecTrb (Private, Trb);
Status = SdMmcExecTrb (Private, Trb);
if (EFI_ERROR (Status)) {
goto Done;
}
@@ -191,6 +192,7 @@ ProcessAsyncTaskList (
goto Done;
}
}
Status = SdMmcCheckTrbResult (Private, Trb);
}
@@ -202,10 +204,11 @@ Done:
} else {
InfiniteWait = FALSE;
}
if ((!InfiniteWait) && (Trb->Timeout-- == 0)) {
RemoveEntryList (Link);
Trb->Packet->TransactionStatus = EFI_TIMEOUT;
TrbEvent = Trb->Event;
TrbEvent = Trb->Event;
SdMmcFreeTrb (Trb);
DEBUG ((DEBUG_VERBOSE, "ProcessAsyncTaskList(): Signal Event %p EFI_TIMEOUT\n", TrbEvent));
gBS->SignalEvent (TrbEvent);
@@ -217,11 +220,12 @@ Done:
} else if ((Trb != NULL)) {
RemoveEntryList (Link);
Trb->Packet->TransactionStatus = Status;
TrbEvent = Trb->Event;
TrbEvent = Trb->Event;
SdMmcFreeTrb (Trb);
DEBUG ((DEBUG_VERBOSE, "ProcessAsyncTaskList(): Signal Event %p with %r\n", TrbEvent, Status));
gBS->SignalEvent (TrbEvent);
}
return;
}
@@ -236,23 +240,23 @@ Done:
VOID
EFIAPI
SdMmcPciHcEnumerateDevice (
IN EFI_EVENT Event,
IN VOID* Context
IN EFI_EVENT Event,
IN VOID *Context
)
{
SD_MMC_HC_PRIVATE_DATA *Private;
EFI_STATUS Status;
UINT8 Slot;
BOOLEAN MediaPresent;
UINT32 RoutineNum;
CARD_TYPE_DETECT_ROUTINE *Routine;
UINTN Index;
LIST_ENTRY *Link;
LIST_ENTRY *NextLink;
SD_MMC_HC_TRB *Trb;
EFI_TPL OldTpl;
SD_MMC_HC_PRIVATE_DATA *Private;
EFI_STATUS Status;
UINT8 Slot;
BOOLEAN MediaPresent;
UINT32 RoutineNum;
CARD_TYPE_DETECT_ROUTINE *Routine;
UINTN Index;
LIST_ENTRY *Link;
LIST_ENTRY *NextLink;
SD_MMC_HC_TRB *Trb;
EFI_TPL OldTpl;
Private = (SD_MMC_HC_PRIVATE_DATA*)Context;
Private = (SD_MMC_HC_PRIVATE_DATA *)Context;
for (Slot = 0; Slot < SD_MMC_HC_MAX_SLOT; Slot++) {
if ((Private->Slot[Slot].Enable) && (Private->Slot[Slot].SlotType == RemovableSlot)) {
@@ -267,9 +271,10 @@ SdMmcPciHcEnumerateDevice (
OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
for (Link = GetFirstNode (&Private->Queue);
!IsNull (&Private->Queue, Link);
Link = NextLink) {
Link = NextLink)
{
NextLink = GetNextNode (&Private->Queue, Link);
Trb = SD_MMC_HC_TRB_FROM_THIS (Link);
Trb = SD_MMC_HC_TRB_FROM_THIS (Link);
if (Trb->Slot == Slot) {
RemoveEntryList (Link);
Trb->Packet->TransactionStatus = EFI_NO_MEDIA;
@@ -277,17 +282,19 @@ SdMmcPciHcEnumerateDevice (
SdMmcFreeTrb (Trb);
}
}
gBS->RestoreTPL (OldTpl);
//
// Notify the upper layer the connect state change through ReinstallProtocolInterface.
//
gBS->ReinstallProtocolInterface (
Private->ControllerHandle,
&gEfiSdMmcPassThruProtocolGuid,
&Private->PassThru,
&Private->PassThru
);
Private->ControllerHandle,
&gEfiSdMmcPassThruProtocolGuid,
&Private->PassThru,
&Private->PassThru
);
}
if ((Status == EFI_MEDIA_CHANGED) && MediaPresent) {
DEBUG ((DEBUG_INFO, "SdMmcPciHcEnumerateDevice: device connected at slot %d of pci %p\n", Slot, Private->PciIo));
//
@@ -297,6 +304,7 @@ SdMmcPciHcEnumerateDevice (
if (EFI_ERROR (Status)) {
continue;
}
//
// Reinitialize slot and restart identification process for the new attached device
//
@@ -307,16 +315,17 @@ SdMmcPciHcEnumerateDevice (
Private->Slot[Slot].MediaPresent = TRUE;
Private->Slot[Slot].Initialized = TRUE;
RoutineNum = sizeof (mCardTypeDetectRoutineTable) / sizeof (CARD_TYPE_DETECT_ROUTINE);
RoutineNum = sizeof (mCardTypeDetectRoutineTable) / sizeof (CARD_TYPE_DETECT_ROUTINE);
for (Index = 0; Index < RoutineNum; Index++) {
Routine = &mCardTypeDetectRoutineTable[Index];
if (*Routine != NULL) {
Status = (*Routine) (Private, Slot);
Status = (*Routine)(Private, Slot);
if (!EFI_ERROR (Status)) {
break;
}
}
}
//
// This card doesn't get initialized correctly.
//
@@ -385,9 +394,9 @@ SdMmcPciHcEnumerateDevice (
EFI_STATUS
EFIAPI
SdMmcPciHcDriverBindingSupported (
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
)
{
EFI_STATUS Status;
@@ -405,7 +414,7 @@ SdMmcPciHcDriverBindingSupported (
Status = gBS->OpenProtocol (
Controller,
&gEfiDevicePathProtocolGuid,
(VOID *) &ParentDevicePath,
(VOID *)&ParentDevicePath,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_BY_DRIVER
@@ -416,15 +425,16 @@ SdMmcPciHcDriverBindingSupported (
//
return Status;
}
//
// Close the protocol because we don't use it here.
//
gBS->CloseProtocol (
Controller,
&gEfiDevicePathProtocolGuid,
This->DriverBindingHandle,
Controller
);
Controller,
&gEfiDevicePathProtocolGuid,
This->DriverBindingHandle,
Controller
);
//
// Now test the EfiPciIoProtocol.
@@ -432,7 +442,7 @@ SdMmcPciHcDriverBindingSupported (
Status = gBS->OpenProtocol (
Controller,
&gEfiPciIoProtocolGuid,
(VOID **) &PciIo,
(VOID **)&PciIo,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_BY_DRIVER
@@ -455,30 +465,32 @@ SdMmcPciHcDriverBindingSupported (
);
if (EFI_ERROR (Status)) {
gBS->CloseProtocol (
Controller,
&gEfiPciIoProtocolGuid,
This->DriverBindingHandle,
Controller
);
Controller,
&gEfiPciIoProtocolGuid,
This->DriverBindingHandle,
Controller
);
return EFI_UNSUPPORTED;
}
//
// Since we already got the PciData, we can close protocol to avoid to carry it
// on for multiple exit points.
//
gBS->CloseProtocol (
Controller,
&gEfiPciIoProtocolGuid,
This->DriverBindingHandle,
Controller
);
Controller,
&gEfiPciIoProtocolGuid,
This->DriverBindingHandle,
Controller
);
//
// Examine SD PCI Host Controller PCI Configuration table fields.
//
if ((PciData.Hdr.ClassCode[2] == PCI_CLASS_SYSTEM_PERIPHERAL) &&
(PciData.Hdr.ClassCode[1] == PCI_SUBCLASS_SD_HOST_CONTROLLER) &&
((PciData.Hdr.ClassCode[0] == 0x00) || (PciData.Hdr.ClassCode[0] == 0x01))) {
((PciData.Hdr.ClassCode[0] == 0x00) || (PciData.Hdr.ClassCode[0] == 0x01)))
{
return EFI_SUCCESS;
}
@@ -523,24 +535,24 @@ SdMmcPciHcDriverBindingSupported (
EFI_STATUS
EFIAPI
SdMmcPciHcDriverBindingStart (
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
)
{
EFI_STATUS Status;
SD_MMC_HC_PRIVATE_DATA *Private;
EFI_PCI_IO_PROTOCOL *PciIo;
UINT64 Supports;
UINT64 PciAttributes;
UINT8 SlotNum;
UINT8 FirstBar;
UINT8 Slot;
UINT8 Index;
CARD_TYPE_DETECT_ROUTINE *Routine;
UINT32 RoutineNum;
BOOLEAN MediaPresent;
BOOLEAN Support64BitDma;
EFI_STATUS Status;
SD_MMC_HC_PRIVATE_DATA *Private;
EFI_PCI_IO_PROTOCOL *PciIo;
UINT64 Supports;
UINT64 PciAttributes;
UINT8 SlotNum;
UINT8 FirstBar;
UINT8 Slot;
UINT8 Index;
CARD_TYPE_DETECT_ROUTINE *Routine;
UINT32 RoutineNum;
BOOLEAN MediaPresent;
BOOLEAN Support64BitDma;
DEBUG ((DEBUG_INFO, "SdMmcPciHcDriverBindingStart: Start\n"));
@@ -552,7 +564,7 @@ SdMmcPciHcDriverBindingStart (
Status = gBS->OpenProtocol (
Controller,
&gEfiPciIoProtocolGuid,
(VOID **) &PciIo,
(VOID **)&PciIo,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_BY_DRIVER
@@ -620,11 +632,17 @@ SdMmcPciHcDriverBindingStart (
// implementations.
//
if (mOverride == NULL) {
Status = gBS->LocateProtocol (&gEdkiiSdMmcOverrideProtocolGuid, NULL,
(VOID **)&mOverride);
Status = gBS->LocateProtocol (
&gEdkiiSdMmcOverrideProtocolGuid,
NULL,
(VOID **)&mOverride
);
if (!EFI_ERROR (Status)) {
DEBUG ((DEBUG_INFO, "%a: found SD/MMC override protocol\n",
__FUNCTION__));
DEBUG ((
DEBUG_INFO,
"%a: found SD/MMC override protocol\n",
__FUNCTION__
));
}
}
@@ -655,8 +673,12 @@ SdMmcPciHcDriverBindingStart (
&Private->BaseClkFreq[Slot]
);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_WARN, "%a: Failed to override capability - %r\n",
__FUNCTION__, Status));
DEBUG ((
DEBUG_WARN,
"%a: Failed to override capability - %r\n",
__FUNCTION__,
Status
));
continue;
}
}
@@ -666,7 +688,7 @@ SdMmcPciHcDriverBindingStart (
Controller,
Slot,
EdkiiSdMmcGetOperatingParam,
(VOID*)&Private->Slot[Slot].OperatingParameters
(VOID *)&Private->Slot[Slot].OperatingParameters
);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_WARN, "%a: Failed to get operating parameters, using defaults\n", __FUNCTION__));
@@ -686,12 +708,13 @@ SdMmcPciHcDriverBindingStart (
// If any of the slots does not support 64b system bus
// do not enable 64b DMA in the PCI layer.
//
if ((Private->ControllerVersion[Slot] == SD_MMC_HC_CTRL_VER_300 &&
Private->Capability[Slot].SysBus64V3 == 0) ||
(Private->ControllerVersion[Slot] == SD_MMC_HC_CTRL_VER_400 &&
Private->Capability[Slot].SysBus64V3 == 0) ||
(Private->ControllerVersion[Slot] >= SD_MMC_HC_CTRL_VER_410 &&
Private->Capability[Slot].SysBus64V4 == 0)) {
if (((Private->ControllerVersion[Slot] == SD_MMC_HC_CTRL_VER_300) &&
(Private->Capability[Slot].SysBus64V3 == 0)) ||
((Private->ControllerVersion[Slot] == SD_MMC_HC_CTRL_VER_400) &&
(Private->Capability[Slot].SysBus64V3 == 0)) ||
((Private->ControllerVersion[Slot] >= SD_MMC_HC_CTRL_VER_410) &&
(Private->Capability[Slot].SysBus64V4 == 0)))
{
Support64BitDma = FALSE;
}
@@ -713,6 +736,7 @@ SdMmcPciHcDriverBindingStart (
if (EFI_ERROR (Status)) {
continue;
}
//
// Check whether there is a SD/MMC card attached
//
@@ -737,16 +761,17 @@ SdMmcPciHcDriverBindingStart (
Private->Slot[Slot].MediaPresent = TRUE;
Private->Slot[Slot].Initialized = TRUE;
RoutineNum = sizeof (mCardTypeDetectRoutineTable) / sizeof (CARD_TYPE_DETECT_ROUTINE);
RoutineNum = sizeof (mCardTypeDetectRoutineTable) / sizeof (CARD_TYPE_DETECT_ROUTINE);
for (Index = 0; Index < RoutineNum; Index++) {
Routine = &mCardTypeDetectRoutineTable[Index];
if (*Routine != NULL) {
Status = (*Routine) (Private, Slot);
Status = (*Routine)(Private, Slot);
if (!EFI_ERROR (Status)) {
break;
}
}
}
//
// This card doesn't get initialized correctly.
//
@@ -831,12 +856,13 @@ Done:
NULL
);
}
gBS->CloseProtocol (
Controller,
&gEfiPciIoProtocolGuid,
This->DriverBindingHandle,
Controller
);
Controller,
&gEfiPciIoProtocolGuid,
This->DriverBindingHandle,
Controller
);
if ((Private != NULL) && (Private->TimerEvent != NULL)) {
gBS->CloseEvent (Private->TimerEvent);
@@ -883,26 +909,26 @@ Done:
EFI_STATUS
EFIAPI
SdMmcPciHcDriverBindingStop (
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN UINTN NumberOfChildren,
IN EFI_HANDLE *ChildHandleBuffer
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN UINTN NumberOfChildren,
IN EFI_HANDLE *ChildHandleBuffer
)
{
EFI_STATUS Status;
EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru;
SD_MMC_HC_PRIVATE_DATA *Private;
EFI_PCI_IO_PROTOCOL *PciIo;
LIST_ENTRY *Link;
LIST_ENTRY *NextLink;
SD_MMC_HC_TRB *Trb;
EFI_STATUS Status;
EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru;
SD_MMC_HC_PRIVATE_DATA *Private;
EFI_PCI_IO_PROTOCOL *PciIo;
LIST_ENTRY *Link;
LIST_ENTRY *NextLink;
SD_MMC_HC_TRB *Trb;
DEBUG ((DEBUG_INFO, "SdMmcPciHcDriverBindingStop: Start\n"));
Status = gBS->OpenProtocol (
Controller,
&gEfiSdMmcPassThruProtocolGuid,
(VOID**) &PassThru,
(VOID **)&PassThru,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_GET_PROTOCOL
@@ -919,20 +945,23 @@ SdMmcPciHcDriverBindingStop (
gBS->CloseEvent (Private->TimerEvent);
Private->TimerEvent = NULL;
}
if (Private->ConnectEvent != NULL) {
gBS->CloseEvent (Private->ConnectEvent);
Private->ConnectEvent = NULL;
}
//
// As the timer is closed, there is no needs to use TPL lock to
// protect the critical region "queue".
//
for (Link = GetFirstNode (&Private->Queue);
!IsNull (&Private->Queue, Link);
Link = NextLink) {
Link = NextLink)
{
NextLink = GetNextNode (&Private->Queue, Link);
RemoveEntryList (Link);
Trb = SD_MMC_HC_TRB_FROM_THIS (Link);
Trb = SD_MMC_HC_TRB_FROM_THIS (Link);
Trb->Packet->TransactionStatus = EFI_ABORTED;
gBS->SignalEvent (Trb->Event);
SdMmcFreeTrb (Trb);
@@ -1003,6 +1032,7 @@ SdMmcPassThruExecSyncTrb (
gBS->RestoreTPL (OldTpl);
break;
}
gBS->RestoreTPL (OldTpl);
}
@@ -1068,15 +1098,15 @@ SdMmcPassThruExecSyncTrb (
EFI_STATUS
EFIAPI
SdMmcPassThruPassThru (
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This,
IN UINT8 Slot,
IN OUT EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet,
IN EFI_EVENT Event OPTIONAL
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This,
IN UINT8 Slot,
IN OUT EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet,
IN EFI_EVENT Event OPTIONAL
)
{
EFI_STATUS Status;
SD_MMC_HC_PRIVATE_DATA *Private;
SD_MMC_HC_TRB *Trb;
EFI_STATUS Status;
SD_MMC_HC_PRIVATE_DATA *Private;
SD_MMC_HC_TRB *Trb;
if ((This == NULL) || (Packet == NULL)) {
return EFI_INVALID_PARAMETER;
@@ -1112,6 +1142,7 @@ SdMmcPassThruPassThru (
if (Trb == NULL) {
return EFI_OUT_OF_RESOURCES;
}
//
// Immediately return for async I/O.
//
@@ -1158,12 +1189,12 @@ SdMmcPassThruPassThru (
EFI_STATUS
EFIAPI
SdMmcPassThruGetNextSlot (
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This,
IN OUT UINT8 *Slot
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This,
IN OUT UINT8 *Slot
)
{
SD_MMC_HC_PRIVATE_DATA *Private;
UINT8 Index;
SD_MMC_HC_PRIVATE_DATA *Private;
UINT8 Index;
if ((This == NULL) || (Slot == NULL)) {
return EFI_INVALID_PARAMETER;
@@ -1174,20 +1205,22 @@ SdMmcPassThruGetNextSlot (
if (*Slot == 0xFF) {
for (Index = 0; Index < SD_MMC_HC_MAX_SLOT; Index++) {
if (Private->Slot[Index].Enable) {
*Slot = Index;
*Slot = Index;
Private->PreviousSlot = Index;
return EFI_SUCCESS;
}
}
return EFI_NOT_FOUND;
} else if (*Slot == Private->PreviousSlot) {
for (Index = *Slot + 1; Index < SD_MMC_HC_MAX_SLOT; Index++) {
if (Private->Slot[Index].Enable) {
*Slot = Index;
*Slot = Index;
Private->PreviousSlot = Index;
return EFI_SUCCESS;
}
}
return EFI_NOT_FOUND;
} else {
return EFI_INVALID_PARAMETER;
@@ -1231,14 +1264,14 @@ SdMmcPassThruGetNextSlot (
EFI_STATUS
EFIAPI
SdMmcPassThruBuildDevicePath (
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This,
IN UINT8 Slot,
IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This,
IN UINT8 Slot,
IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath
)
{
SD_MMC_HC_PRIVATE_DATA *Private;
SD_DEVICE_PATH *SdNode;
EMMC_DEVICE_PATH *EmmcNode;
SD_MMC_HC_PRIVATE_DATA *Private;
SD_DEVICE_PATH *SdNode;
EMMC_DEVICE_PATH *EmmcNode;
if ((This == NULL) || (DevicePath == NULL) || (Slot >= SD_MMC_HC_MAX_SLOT)) {
return EFI_INVALID_PARAMETER;
@@ -1255,17 +1288,19 @@ SdMmcPassThruBuildDevicePath (
if (SdNode == NULL) {
return EFI_OUT_OF_RESOURCES;
}
SdNode->SlotNumber = Slot;
*DevicePath = (EFI_DEVICE_PATH_PROTOCOL *) SdNode;
*DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)SdNode;
} else if (Private->Slot[Slot].CardType == EmmcCardType) {
EmmcNode = AllocateCopyPool (sizeof (EMMC_DEVICE_PATH), &mEmmcDpTemplate);
if (EmmcNode == NULL) {
return EFI_OUT_OF_RESOURCES;
}
EmmcNode->SlotNumber = Slot;
*DevicePath = (EFI_DEVICE_PATH_PROTOCOL *) EmmcNode;
*DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)EmmcNode;
} else {
//
// Currently we only support SD and EMMC two device nodes.
@@ -1300,15 +1335,15 @@ SdMmcPassThruBuildDevicePath (
EFI_STATUS
EFIAPI
SdMmcPassThruGetSlotNumber (
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This,
IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
OUT UINT8 *Slot
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This,
IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
OUT UINT8 *Slot
)
{
SD_MMC_HC_PRIVATE_DATA *Private;
SD_DEVICE_PATH *SdNode;
EMMC_DEVICE_PATH *EmmcNode;
UINT8 SlotNumber;
SD_MMC_HC_PRIVATE_DATA *Private;
SD_DEVICE_PATH *SdNode;
EMMC_DEVICE_PATH *EmmcNode;
UINT8 SlotNumber;
if ((This == NULL) || (DevicePath == NULL) || (Slot == NULL)) {
return EFI_INVALID_PARAMETER;
@@ -1322,16 +1357,17 @@ SdMmcPassThruGetSlotNumber (
if ((DevicePath->Type != MESSAGING_DEVICE_PATH) ||
((DevicePath->SubType != MSG_SD_DP) &&
(DevicePath->SubType != MSG_EMMC_DP)) ||
(DevicePathNodeLength(DevicePath) != sizeof(SD_DEVICE_PATH)) ||
(DevicePathNodeLength(DevicePath) != sizeof(EMMC_DEVICE_PATH))) {
(DevicePathNodeLength (DevicePath) != sizeof (SD_DEVICE_PATH)) ||
(DevicePathNodeLength (DevicePath) != sizeof (EMMC_DEVICE_PATH)))
{
return EFI_UNSUPPORTED;
}
if (DevicePath->SubType == MSG_SD_DP) {
SdNode = (SD_DEVICE_PATH *) DevicePath;
SdNode = (SD_DEVICE_PATH *)DevicePath;
SlotNumber = SdNode->SlotNumber;
} else {
EmmcNode = (EMMC_DEVICE_PATH *) DevicePath;
EmmcNode = (EMMC_DEVICE_PATH *)DevicePath;
SlotNumber = EmmcNode->SlotNumber;
}
@@ -1373,15 +1409,15 @@ SdMmcPassThruGetSlotNumber (
EFI_STATUS
EFIAPI
SdMmcPassThruResetDevice (
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This,
IN UINT8 Slot
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This,
IN UINT8 Slot
)
{
SD_MMC_HC_PRIVATE_DATA *Private;
LIST_ENTRY *Link;
LIST_ENTRY *NextLink;
SD_MMC_HC_TRB *Trb;
EFI_TPL OldTpl;
SD_MMC_HC_PRIVATE_DATA *Private;
LIST_ENTRY *Link;
LIST_ENTRY *NextLink;
SD_MMC_HC_TRB *Trb;
EFI_TPL OldTpl;
if (This == NULL) {
return EFI_INVALID_PARAMETER;
@@ -1400,6 +1436,7 @@ SdMmcPassThruResetDevice (
if (!Private->Slot[Slot].Initialized) {
return EFI_DEVICE_ERROR;
}
//
// Free all async I/O requests in the queue
//
@@ -1407,10 +1444,11 @@ SdMmcPassThruResetDevice (
for (Link = GetFirstNode (&Private->Queue);
!IsNull (&Private->Queue, Link);
Link = NextLink) {
Link = NextLink)
{
NextLink = GetNextNode (&Private->Queue, Link);
RemoveEntryList (Link);
Trb = SD_MMC_HC_TRB_FROM_THIS (Link);
Trb = SD_MMC_HC_TRB_FROM_THIS (Link);
Trb->Packet->TransactionStatus = EFI_ABORTED;
gBS->SignalEvent (Trb->Event);
SdMmcFreeTrb (Trb);
@@ -1420,4 +1458,3 @@ SdMmcPassThruResetDevice (
return EFI_SUCCESS;
}

257
MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
View File

@@ -35,11 +35,11 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include "SdMmcPciHci.h"
extern EFI_COMPONENT_NAME_PROTOCOL gSdMmcPciHcComponentName;
extern EFI_COMPONENT_NAME2_PROTOCOL gSdMmcPciHcComponentName2;
extern EFI_DRIVER_BINDING_PROTOCOL gSdMmcPciHcDriverBinding;
extern EFI_COMPONENT_NAME_PROTOCOL gSdMmcPciHcComponentName;
extern EFI_COMPONENT_NAME2_PROTOCOL gSdMmcPciHcComponentName2;
extern EFI_DRIVER_BINDING_PROTOCOL gSdMmcPciHcDriverBinding;
extern EDKII_SD_MMC_OVERRIDE *mOverride;
extern EDKII_SD_MMC_OVERRIDE *mOverride;
#define SD_MMC_HC_PRIVATE_SIGNATURE SIGNATURE_32 ('s', 'd', 't', 'f')
@@ -49,18 +49,18 @@ extern EDKII_SD_MMC_OVERRIDE *mOverride;
//
// Generic time out value, 1 microsecond as unit.
//
#define SD_MMC_HC_GENERIC_TIMEOUT 1 * 1000 * 1000
#define SD_MMC_HC_GENERIC_TIMEOUT 1 * 1000 * 1000
//
// SD/MMC async transfer timer interval, set by experience.
// The unit is 100us, takes 1ms as interval.
//
#define SD_MMC_HC_ASYNC_TIMER EFI_TIMER_PERIOD_MILLISECONDS(1)
#define SD_MMC_HC_ASYNC_TIMER EFI_TIMER_PERIOD_MILLISECONDS(1)
//
// SD/MMC removable device enumeration timer interval, set by experience.
// The unit is 100us, takes 100ms as interval.
//
#define SD_MMC_HC_ENUM_TIMER EFI_TIMER_PERIOD_MILLISECONDS(100)
#define SD_MMC_HC_ENUM_TIMER EFI_TIMER_PERIOD_MILLISECONDS(100)
typedef enum {
UnknownCardType,
@@ -78,97 +78,97 @@ typedef enum {
} EFI_SD_MMC_SLOT_TYPE;
typedef struct {
BOOLEAN Enable;
EFI_SD_MMC_SLOT_TYPE SlotType;
BOOLEAN MediaPresent;
BOOLEAN Initialized;
SD_MMC_CARD_TYPE CardType;
UINT64 CurrentFreq;
EDKII_SD_MMC_OPERATING_PARAMETERS OperatingParameters;
BOOLEAN Enable;
EFI_SD_MMC_SLOT_TYPE SlotType;
BOOLEAN MediaPresent;
BOOLEAN Initialized;
SD_MMC_CARD_TYPE CardType;
UINT64 CurrentFreq;
EDKII_SD_MMC_OPERATING_PARAMETERS OperatingParameters;
} SD_MMC_HC_SLOT;
typedef struct {
UINTN Signature;
UINTN Signature;
EFI_HANDLE ControllerHandle;
EFI_PCI_IO_PROTOCOL *PciIo;
EFI_HANDLE ControllerHandle;
EFI_PCI_IO_PROTOCOL *PciIo;
EFI_SD_MMC_PASS_THRU_PROTOCOL PassThru;
EFI_SD_MMC_PASS_THRU_PROTOCOL PassThru;
UINT64 PciAttributes;
UINT64 PciAttributes;
//
// The field is used to record the previous slot in GetNextSlot().
//
UINT8 PreviousSlot;
UINT8 PreviousSlot;
//
// For Non-blocking operation.
//
EFI_EVENT TimerEvent;
EFI_EVENT TimerEvent;
//
// For Sd removable device enumeration.
//
EFI_EVENT ConnectEvent;
LIST_ENTRY Queue;
EFI_EVENT ConnectEvent;
LIST_ENTRY Queue;
SD_MMC_HC_SLOT Slot[SD_MMC_HC_MAX_SLOT];
SD_MMC_HC_SLOT_CAP Capability[SD_MMC_HC_MAX_SLOT];
UINT64 MaxCurrent[SD_MMC_HC_MAX_SLOT];
UINT16 ControllerVersion[SD_MMC_HC_MAX_SLOT];
SD_MMC_HC_SLOT Slot[SD_MMC_HC_MAX_SLOT];
SD_MMC_HC_SLOT_CAP Capability[SD_MMC_HC_MAX_SLOT];
UINT64 MaxCurrent[SD_MMC_HC_MAX_SLOT];
UINT16 ControllerVersion[SD_MMC_HC_MAX_SLOT];
//
// Some controllers may require to override base clock frequency
// value stored in Capabilities Register 1.
//
UINT32 BaseClkFreq[SD_MMC_HC_MAX_SLOT];
UINT32 BaseClkFreq[SD_MMC_HC_MAX_SLOT];
} SD_MMC_HC_PRIVATE_DATA;
typedef struct {
SD_MMC_BUS_MODE BusTiming;
UINT8 BusWidth;
UINT32 ClockFreq;
EDKII_SD_MMC_DRIVER_STRENGTH DriverStrength;
SD_MMC_BUS_MODE BusTiming;
UINT8 BusWidth;
UINT32 ClockFreq;
EDKII_SD_MMC_DRIVER_STRENGTH DriverStrength;
} SD_MMC_BUS_SETTINGS;
#define SD_MMC_HC_TRB_SIG SIGNATURE_32 ('T', 'R', 'B', 'T')
#define SD_MMC_HC_TRB_SIG SIGNATURE_32 ('T', 'R', 'B', 'T')
#define SD_MMC_TRB_RETRIES 5
#define SD_MMC_TRB_RETRIES 5
//
// TRB (Transfer Request Block) contains information for the cmd request.
//
typedef struct {
UINT32 Signature;
LIST_ENTRY TrbList;
UINT32 Signature;
LIST_ENTRY TrbList;
UINT8 Slot;
UINT16 BlockSize;
UINT8 Slot;
UINT16 BlockSize;
EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
VOID *Data;
UINT32 DataLen;
BOOLEAN Read;
EFI_PHYSICAL_ADDRESS DataPhy;
VOID *DataMap;
SD_MMC_HC_TRANSFER_MODE Mode;
SD_MMC_HC_ADMA_LENGTH_MODE AdmaLengthMode;
EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
VOID *Data;
UINT32 DataLen;
BOOLEAN Read;
EFI_PHYSICAL_ADDRESS DataPhy;
VOID *DataMap;
SD_MMC_HC_TRANSFER_MODE Mode;
SD_MMC_HC_ADMA_LENGTH_MODE AdmaLengthMode;
EFI_EVENT Event;
BOOLEAN Started;
BOOLEAN CommandComplete;
UINT64 Timeout;
UINT32 Retries;
EFI_EVENT Event;
BOOLEAN Started;
BOOLEAN CommandComplete;
UINT64 Timeout;
UINT32 Retries;
BOOLEAN PioModeTransferCompleted;
UINT32 PioBlockIndex;
BOOLEAN PioModeTransferCompleted;
UINT32 PioBlockIndex;
SD_MMC_HC_ADMA_32_DESC_LINE *Adma32Desc;
SD_MMC_HC_ADMA_64_V3_DESC_LINE *Adma64V3Desc;
SD_MMC_HC_ADMA_64_V4_DESC_LINE *Adma64V4Desc;
EFI_PHYSICAL_ADDRESS AdmaDescPhy;
VOID *AdmaMap;
UINT32 AdmaPages;
SD_MMC_HC_ADMA_32_DESC_LINE *Adma32Desc;
SD_MMC_HC_ADMA_64_V3_DESC_LINE *Adma64V3Desc;
SD_MMC_HC_ADMA_64_V4_DESC_LINE *Adma64V4Desc;
EFI_PHYSICAL_ADDRESS AdmaDescPhy;
VOID *AdmaMap;
UINT32 AdmaPages;
SD_MMC_HC_PRIVATE_DATA *Private;
SD_MMC_HC_PRIVATE_DATA *Private;
} SD_MMC_HC_TRB;
#define SD_MMC_HC_TRB_FROM_THIS(a) \
@@ -178,22 +178,23 @@ typedef struct {
// Task for Non-blocking mode.
//
typedef struct {
UINT32 Signature;
LIST_ENTRY Link;
UINT32 Signature;
LIST_ENTRY Link;
UINT8 Slot;
EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
BOOLEAN IsStart;
EFI_EVENT Event;
UINT64 RetryTimes;
BOOLEAN InfiniteWait;
VOID *Map;
VOID *MapAddress;
UINT8 Slot;
EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
BOOLEAN IsStart;
EFI_EVENT Event;
UINT64 RetryTimes;
BOOLEAN InfiniteWait;
VOID *Map;
VOID *MapAddress;
} SD_MMC_HC_QUEUE;
//
// Prototypes
//
/**
Execute card identification procedure.
@@ -207,8 +208,8 @@ typedef struct {
typedef
EFI_STATUS
(*CARD_TYPE_DETECT_ROUTINE) (
IN SD_MMC_HC_PRIVATE_DATA *Private,
IN UINT8 Slot
IN SD_MMC_HC_PRIVATE_DATA *Private,
IN UINT8 Slot
);
/**
@@ -251,10 +252,10 @@ EFI_STATUS
EFI_STATUS
EFIAPI
SdMmcPassThruPassThru (
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This,
IN UINT8 Slot,
IN OUT EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet,
IN EFI_EVENT Event OPTIONAL
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This,
IN UINT8 Slot,
IN OUT EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet,
IN EFI_EVENT Event OPTIONAL
);
/**
@@ -289,8 +290,8 @@ SdMmcPassThruPassThru (
EFI_STATUS
EFIAPI
SdMmcPassThruGetNextSlot (
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This,
IN OUT UINT8 *Slot
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This,
IN OUT UINT8 *Slot
);
/**
@@ -330,9 +331,9 @@ SdMmcPassThruGetNextSlot (
EFI_STATUS
EFIAPI
SdMmcPassThruBuildDevicePath (
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This,
IN UINT8 Slot,
IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This,
IN UINT8 Slot,
IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath
);
/**
@@ -359,9 +360,9 @@ SdMmcPassThruBuildDevicePath (
EFI_STATUS
EFIAPI
SdMmcPassThruGetSlotNumber (
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This,
IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
OUT UINT8 *Slot
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This,
IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
OUT UINT8 *Slot
);
/**
@@ -390,13 +391,14 @@ SdMmcPassThruGetSlotNumber (
EFI_STATUS
EFIAPI
SdMmcPassThruResetDevice (
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This,
IN UINT8 Slot
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This,
IN UINT8 Slot
);
//
// Driver model protocol interfaces
//
/**
Tests to see if this driver supports a given controller. If a child device is provided,
it further tests to see if this driver supports creating a handle for the specified child device.
@@ -442,9 +444,9 @@ SdMmcPassThruResetDevice (
EFI_STATUS
EFIAPI
SdMmcPciHcDriverBindingSupported (
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
);
/**
@@ -485,9 +487,9 @@ SdMmcPciHcDriverBindingSupported (
EFI_STATUS
EFIAPI
SdMmcPciHcDriverBindingStart (
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
);
/**
@@ -519,15 +521,16 @@ SdMmcPciHcDriverBindingStart (
EFI_STATUS
EFIAPI
SdMmcPciHcDriverBindingStop (
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN UINTN NumberOfChildren,
IN EFI_HANDLE *ChildHandleBuffer
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN UINTN NumberOfChildren,
IN EFI_HANDLE *ChildHandleBuffer
);
//
// EFI Component Name Functions
//
/**
Retrieves a Unicode string that is the user readable name of the driver.
@@ -570,9 +573,9 @@ SdMmcPciHcDriverBindingStop (
EFI_STATUS
EFIAPI
SdMmcPciHcComponentNameGetDriverName (
IN EFI_COMPONENT_NAME_PROTOCOL *This,
IN CHAR8 *Language,
OUT CHAR16 **DriverName
IN EFI_COMPONENT_NAME_PROTOCOL *This,
IN CHAR8 *Language,
OUT CHAR16 **DriverName
);
/**
@@ -646,11 +649,11 @@ SdMmcPciHcComponentNameGetDriverName (
EFI_STATUS
EFIAPI
SdMmcPciHcComponentNameGetControllerName (
IN EFI_COMPONENT_NAME_PROTOCOL *This,
IN EFI_HANDLE ControllerHandle,
IN EFI_HANDLE ChildHandle OPTIONAL,
IN CHAR8 *Language,
OUT CHAR16 **ControllerName
IN EFI_COMPONENT_NAME_PROTOCOL *This,
IN EFI_HANDLE ControllerHandle,
IN EFI_HANDLE ChildHandle OPTIONAL,
IN CHAR8 *Language,
OUT CHAR16 **ControllerName
);
/**
@@ -668,10 +671,10 @@ SdMmcPciHcComponentNameGetControllerName (
**/
SD_MMC_HC_TRB *
SdMmcCreateTrb (
IN SD_MMC_HC_PRIVATE_DATA *Private,
IN UINT8 Slot,
IN EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet,
IN EFI_EVENT Event
IN SD_MMC_HC_PRIVATE_DATA *Private,
IN UINT8 Slot,
IN EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet,
IN EFI_EVENT Event
);
/**
@@ -682,7 +685,7 @@ SdMmcCreateTrb (
**/
VOID
SdMmcFreeTrb (
IN SD_MMC_HC_TRB *Trb
IN SD_MMC_HC_TRB *Trb
);
/**
@@ -698,8 +701,8 @@ SdMmcFreeTrb (
**/
EFI_STATUS
SdMmcCheckTrbEnv (
IN SD_MMC_HC_PRIVATE_DATA *Private,
IN SD_MMC_HC_TRB *Trb
IN SD_MMC_HC_PRIVATE_DATA *Private,
IN SD_MMC_HC_TRB *Trb
);
/**
@@ -715,8 +718,8 @@ SdMmcCheckTrbEnv (
**/
EFI_STATUS
SdMmcWaitTrbEnv (
IN SD_MMC_HC_PRIVATE_DATA *Private,
IN SD_MMC_HC_TRB *Trb
IN SD_MMC_HC_PRIVATE_DATA *Private,
IN SD_MMC_HC_TRB *Trb
);
/**
@@ -731,8 +734,8 @@ SdMmcWaitTrbEnv (
**/
EFI_STATUS
SdMmcExecTrb (
IN SD_MMC_HC_PRIVATE_DATA *Private,
IN SD_MMC_HC_TRB *Trb
IN SD_MMC_HC_PRIVATE_DATA *Private,
IN SD_MMC_HC_TRB *Trb
);
/**
@@ -748,8 +751,8 @@ SdMmcExecTrb (
**/
EFI_STATUS
SdMmcCheckTrbResult (
IN SD_MMC_HC_PRIVATE_DATA *Private,
IN SD_MMC_HC_TRB *Trb
IN SD_MMC_HC_PRIVATE_DATA *Private,
IN SD_MMC_HC_TRB *Trb
);
/**
@@ -764,8 +767,8 @@ SdMmcCheckTrbResult (
**/
EFI_STATUS
SdMmcWaitTrbResult (
IN SD_MMC_HC_PRIVATE_DATA *Private,
IN SD_MMC_HC_TRB *Trb
IN SD_MMC_HC_PRIVATE_DATA *Private,
IN SD_MMC_HC_TRB *Trb
);
/**
@@ -782,8 +785,8 @@ SdMmcWaitTrbResult (
**/
EFI_STATUS
EmmcIdentification (
IN SD_MMC_HC_PRIVATE_DATA *Private,
IN UINT8 Slot
IN SD_MMC_HC_PRIVATE_DATA *Private,
IN UINT8 Slot
);
/**
@@ -800,8 +803,8 @@ EmmcIdentification (
**/
EFI_STATUS
SdCardIdentification (
IN SD_MMC_HC_PRIVATE_DATA *Private,
IN UINT8 Slot
IN SD_MMC_HC_PRIVATE_DATA *Private,
IN UINT8 Slot
);
/**
@@ -840,8 +843,8 @@ SdMmcHcClockSupply (
**/
EFI_STATUS
SdMmcHcReset (
IN SD_MMC_HC_PRIVATE_DATA *Private,
IN UINT8 Slot
IN SD_MMC_HC_PRIVATE_DATA *Private,
IN UINT8 Slot
);
/**
@@ -857,8 +860,8 @@ SdMmcHcReset (
**/
EFI_STATUS
SdMmcHcInitHost (
IN SD_MMC_HC_PRIVATE_DATA *Private,
IN UINT8 Slot
IN SD_MMC_HC_PRIVATE_DATA *Private,
IN UINT8 Slot
);
#endif

843
MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
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