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MdeModulePkg: Apply uncrustify changes

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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737

Apply uncrustify changes to .c/.h files in the MdeModulePkg package

Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
This commit is contained in:
Michael Kubacki
2021-12-05 14:54:02 -08:00
committed by mergify[bot]
parent 7c7184e201
commit 1436aea4d5
994 changed files with 107608 additions and 101311 deletions
Download Patch File Download Diff File Expand all files Collapse all files

34
MdeModulePkg/Bus/Pci/EhciDxe/ComponentName.c
View File

@@ -9,7 +9,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include "Ehci.h"
//
// EFI Component Name Protocol
//
@@ -22,19 +21,17 @@ GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME_PROTOCOL gEhciComponentName =
//
// EFI Component Name 2 Protocol
//
GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gEhciComponentName2 = {
(EFI_COMPONENT_NAME2_GET_DRIVER_NAME) EhciComponentNameGetDriverName,
(EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME) EhciComponentNameGetControllerName,
GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gEhciComponentName2 = {
(EFI_COMPONENT_NAME2_GET_DRIVER_NAME)EhciComponentNameGetDriverName,
(EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME)EhciComponentNameGetControllerName,
"en"
};
GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mEhciDriverNameTable[] = {
GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mEhciDriverNameTable[] = {
{ "eng;en", L"Usb Ehci Driver" },
{ NULL , NULL }
{ NULL, NULL }
};
/**
Retrieves a Unicode string that is the user readable name of the driver.
@@ -162,16 +159,16 @@ EhciComponentNameGetDriverName (
EFI_STATUS
EFIAPI
EhciComponentNameGetControllerName (
IN EFI_COMPONENT_NAME_PROTOCOL *This,
IN EFI_HANDLE ControllerHandle,
IN EFI_HANDLE ChildHandle OPTIONAL,
IN CHAR8 *Language,
OUT CHAR16 **ControllerName
IN EFI_COMPONENT_NAME_PROTOCOL *This,
IN EFI_HANDLE ControllerHandle,
IN EFI_HANDLE ChildHandle OPTIONAL,
IN CHAR8 *Language,
OUT CHAR16 **ControllerName
)
{
EFI_STATUS Status;
USB2_HC_DEV *EhciDev;
EFI_USB2_HC_PROTOCOL *Usb2Hc;
EFI_STATUS Status;
USB2_HC_DEV *EhciDev;
EFI_USB2_HC_PROTOCOL *Usb2Hc;
//
// This is a device driver, so ChildHandle must be NULL.
@@ -179,6 +176,7 @@ EhciComponentNameGetControllerName (
if (ChildHandle != NULL) {
return EFI_UNSUPPORTED;
}
//
// Make sure this driver is currently managing ControllerHandle
//
@@ -190,13 +188,14 @@ EhciComponentNameGetControllerName (
if (EFI_ERROR (Status)) {
return Status;
}
//
// Get the device context
//
Status = gBS->OpenProtocol (
ControllerHandle,
&gEfiUsb2HcProtocolGuid,
(VOID **) &Usb2Hc,
(VOID **)&Usb2Hc,
gEhciDriverBinding.DriverBindingHandle,
ControllerHandle,
EFI_OPEN_PROTOCOL_GET_PROTOCOL
@@ -214,5 +213,4 @@ EhciComponentNameGetControllerName (
ControllerName,
(BOOLEAN)(This == &gEhciComponentName)
);
}

13
MdeModulePkg/Bus/Pci/EhciDxe/ComponentName.h
View File

@@ -10,7 +10,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#ifndef _COMPONENT_NAME_H_
#define _COMPONENT_NAME_H_
/**
Retrieves a Unicode string that is the user readable name of the driver.
@@ -58,7 +57,6 @@ EhciComponentNameGetDriverName (
OUT CHAR16 **DriverName
);
/**
Retrieves a Unicode string that is the user readable name of the controller
that is being managed by a driver.
@@ -130,12 +128,11 @@ EhciComponentNameGetDriverName (
EFI_STATUS
EFIAPI
EhciComponentNameGetControllerName (
IN EFI_COMPONENT_NAME_PROTOCOL *This,
IN EFI_HANDLE ControllerHandle,
IN EFI_HANDLE ChildHandle OPTIONAL,
IN CHAR8 *Language,
OUT CHAR16 **ControllerName
IN EFI_COMPONENT_NAME_PROTOCOL *This,
IN EFI_HANDLE ControllerHandle,
IN EFI_HANDLE ChildHandle OPTIONAL,
IN CHAR8 *Language,
OUT CHAR16 **ControllerName
);
#endif

941
MdeModulePkg/Bus/Pci/EhciDxe/Ehci.c
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File diff suppressed because it is too large Load Diff

114
MdeModulePkg/Bus/Pci/EhciDxe/Ehci.h
View File

@@ -11,7 +11,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#ifndef _EFI_EHCI_H_
#define _EFI_EHCI_H_
#include <Uefi.h>
#include <Protocol/Usb2HostController.h>
@@ -31,7 +30,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <IndustryStandard/Pci.h>
typedef struct _USB2_HC_DEV USB2_HC_DEV;
typedef struct _USB2_HC_DEV USB2_HC_DEV;
#include "UsbHcMem.h"
#include "EhciReg.h"
@@ -44,64 +43,63 @@ typedef struct _USB2_HC_DEV USB2_HC_DEV;
// EHC timeout experience values
//
#define EHC_1_MICROSECOND 1
#define EHC_1_MILLISECOND (1000 * EHC_1_MICROSECOND)
#define EHC_1_SECOND (1000 * EHC_1_MILLISECOND)
#define EHC_1_MICROSECOND 1
#define EHC_1_MILLISECOND (1000 * EHC_1_MICROSECOND)
#define EHC_1_SECOND (1000 * EHC_1_MILLISECOND)
//
// EHCI register operation timeout, set by experience
//
#define EHC_RESET_TIMEOUT (1 * EHC_1_SECOND)
#define EHC_GENERIC_TIMEOUT (10 * EHC_1_MILLISECOND)
#define EHC_RESET_TIMEOUT (1 * EHC_1_SECOND)
#define EHC_GENERIC_TIMEOUT (10 * EHC_1_MILLISECOND)
//
// Wait for roothub port power stable, refers to Spec[EHCI1.0-2.3.9]
//
#define EHC_ROOT_PORT_RECOVERY_STALL (20 * EHC_1_MILLISECOND)
#define EHC_ROOT_PORT_RECOVERY_STALL (20 * EHC_1_MILLISECOND)
//
// Sync and Async transfer polling interval, set by experience,
// and the unit of Async is 100us, means 1ms as interval.
//
#define EHC_SYNC_POLL_INTERVAL (1 * EHC_1_MILLISECOND)
#define EHC_ASYNC_POLL_INTERVAL EFI_TIMER_PERIOD_MILLISECONDS(1)
#define EHC_SYNC_POLL_INTERVAL (1 * EHC_1_MILLISECOND)
#define EHC_ASYNC_POLL_INTERVAL EFI_TIMER_PERIOD_MILLISECONDS(1)
//
// EHCI debug port control status register bit definition
//
#define USB_DEBUG_PORT_IN_USE BIT10
#define USB_DEBUG_PORT_ENABLE BIT28
#define USB_DEBUG_PORT_OWNER BIT30
#define USB_DEBUG_PORT_IN_USE_MASK (USB_DEBUG_PORT_IN_USE | \
#define USB_DEBUG_PORT_IN_USE BIT10
#define USB_DEBUG_PORT_ENABLE BIT28
#define USB_DEBUG_PORT_OWNER BIT30
#define USB_DEBUG_PORT_IN_USE_MASK (USB_DEBUG_PORT_IN_USE | \
USB_DEBUG_PORT_OWNER)
//
// EHC raises TPL to TPL_NOTIFY to serialize all its operations
// to protect shared data structures.
//
#define EHC_TPL TPL_NOTIFY
#define EHC_TPL TPL_NOTIFY
#define EFI_LIST_CONTAINER(Entry, Type, Field) BASE_CR(Entry, Type, Field)
#define EFI_LIST_CONTAINER(Entry, Type, Field) BASE_CR(Entry, Type, Field)
#define EHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0XFFFFFFFF))
#define EHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINTN)(Addr64), 32) & 0XFFFFFFFF))
#define EHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))
#define EHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0XFFFFFFFF))
#define EHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINTN)(Addr64), 32) & 0XFFFFFFFF))
#define EHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))
#define EHC_REG_BIT_IS_SET(Ehc, Offset, Bit) \
(EHC_BIT_IS_SET(EhcReadOpReg ((Ehc), (Offset)), (Bit)))
#define USB2_HC_DEV_SIGNATURE SIGNATURE_32 ('e', 'h', 'c', 'i')
#define EHC_FROM_THIS(a) CR(a, USB2_HC_DEV, Usb2Hc, USB2_HC_DEV_SIGNATURE)
#define EHC_FROM_THIS(a) CR(a, USB2_HC_DEV, Usb2Hc, USB2_HC_DEV_SIGNATURE)
struct _USB2_HC_DEV {
UINTN Signature;
EFI_USB2_HC_PROTOCOL Usb2Hc;
UINTN Signature;
EFI_USB2_HC_PROTOCOL Usb2Hc;
EFI_PCI_IO_PROTOCOL *PciIo;
EFI_DEVICE_PATH_PROTOCOL *DevicePath;
UINT64 OriginalPciAttributes;
USBHC_MEM_POOL *MemPool;
EFI_PCI_IO_PROTOCOL *PciIo;
EFI_DEVICE_PATH_PROTOCOL *DevicePath;
UINT64 OriginalPciAttributes;
USBHC_MEM_POOL *MemPool;
//
// Schedule data shared between asynchronous and periodic
@@ -112,58 +110,57 @@ struct _USB2_HC_DEV {
// For control transfer, even the short read happens, try the
// status stage.
//
EHC_QTD *ShortReadStop;
EFI_EVENT PollTimer;
EHC_QTD *ShortReadStop;
EFI_EVENT PollTimer;
//
// ExitBootServicesEvent is used to stop the EHC DMA operation
// after exit boot service.
//
EFI_EVENT ExitBootServiceEvent;
EFI_EVENT ExitBootServiceEvent;
//
// Asynchronous(bulk and control) transfer schedule data:
// ReclaimHead is used as the head of the asynchronous transfer
// list. It acts as the reclamation header.
//
EHC_QH *ReclaimHead;
EHC_QH *ReclaimHead;
//
// Periodic (interrupt) transfer schedule data:
//
VOID *PeriodFrame; // the buffer pointed by this pointer is used to store pci bus address of the QH descriptor.
VOID *PeriodFrameHost; // the buffer pointed by this pointer is used to store host memory address of the QH descriptor.
VOID *PeriodFrameMap;
VOID *PeriodFrame; // the buffer pointed by this pointer is used to store pci bus address of the QH descriptor.
VOID *PeriodFrameHost; // the buffer pointed by this pointer is used to store host memory address of the QH descriptor.
VOID *PeriodFrameMap;
EHC_QH *PeriodOne;
LIST_ENTRY AsyncIntTransfers;
EHC_QH *PeriodOne;
LIST_ENTRY AsyncIntTransfers;
//
// EHCI configuration data
//
UINT32 HcStructParams; // Cache of HC structure parameter, EHC_HCSPARAMS_OFFSET
UINT32 HcCapParams; // Cache of HC capability parameter, HCCPARAMS
UINT32 CapLen; // Capability length
UINT32 HcStructParams; // Cache of HC structure parameter, EHC_HCSPARAMS_OFFSET
UINT32 HcCapParams; // Cache of HC capability parameter, HCCPARAMS
UINT32 CapLen; // Capability length
//
// Misc
//
EFI_UNICODE_STRING_TABLE *ControllerNameTable;
EFI_UNICODE_STRING_TABLE *ControllerNameTable;
//
// EHCI debug port info
//
UINT16 DebugPortOffset; // The offset of debug port mmio register
UINT8 DebugPortBarNum; // The bar number of debug port mmio register
UINT8 DebugPortNum; // The port number of usb debug port
UINT16 DebugPortOffset; // The offset of debug port mmio register
UINT8 DebugPortBarNum; // The bar number of debug port mmio register
UINT8 DebugPortNum; // The port number of usb debug port
BOOLEAN Support64BitDma; // Whether 64 bit DMA may be used with this device
BOOLEAN Support64BitDma; // Whether 64 bit DMA may be used with this device
};
extern EFI_DRIVER_BINDING_PROTOCOL gEhciDriverBinding;
extern EFI_COMPONENT_NAME_PROTOCOL gEhciComponentName;
extern EFI_COMPONENT_NAME2_PROTOCOL gEhciComponentName2;
extern EFI_DRIVER_BINDING_PROTOCOL gEhciDriverBinding;
extern EFI_COMPONENT_NAME_PROTOCOL gEhciComponentName;
extern EFI_COMPONENT_NAME2_PROTOCOL gEhciComponentName2;
/**
Test to see if this driver supports ControllerHandle. Any
@@ -181,9 +178,9 @@ extern EFI_COMPONENT_NAME2_PROTOCOL gEhciComponentName2;
EFI_STATUS
EFIAPI
EhcDriverBindingSupported (
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
);
/**
@@ -202,9 +199,9 @@ EhcDriverBindingSupported (
EFI_STATUS
EFIAPI
EhcDriverBindingStart (
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
);
/**
@@ -223,11 +220,10 @@ EhcDriverBindingStart (
EFI_STATUS
EFIAPI
EhcDriverBindingStop (
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN UINTN NumberOfChildren,
IN EFI_HANDLE *ChildHandleBuffer
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN UINTN NumberOfChildren,
IN EFI_HANDLE *ChildHandleBuffer
);
#endif

50
MdeModulePkg/Bus/Pci/EhciDxe/EhciDebug.c
View File

@@ -8,7 +8,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include "Ehci.h"
/**
@@ -19,7 +18,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
VOID
EhcDumpStatus (
IN UINT32 State
IN UINT32 State
)
{
if (EHC_BIT_IS_SET (State, QTD_STAT_DO_PING)) {
@@ -57,7 +56,6 @@ EhcDumpStatus (
DEBUG ((DEBUG_VERBOSE, "\n"));
}
/**
Dump the fields of a QTD.
@@ -67,12 +65,12 @@ EhcDumpStatus (
**/
VOID
EhcDumpQtd (
IN EHC_QTD *Qtd,
IN CHAR8 *Msg
IN EHC_QTD *Qtd,
IN CHAR8 *Msg
)
{
QTD_HW *QtdHw;
UINTN Index;
QTD_HW *QtdHw;
UINTN Index;
if (Msg != NULL) {
DEBUG ((DEBUG_VERBOSE, Msg));
@@ -89,13 +87,10 @@ EhcDumpQtd (
if (QtdHw->Pid == QTD_PID_SETUP) {
DEBUG ((DEBUG_VERBOSE, "PID : Setup\n"));
} else if (QtdHw->Pid == QTD_PID_INPUT) {
DEBUG ((DEBUG_VERBOSE, "PID : IN\n"));
} else if (QtdHw->Pid == QTD_PID_OUTPUT) {
DEBUG ((DEBUG_VERBOSE, "PID : OUT\n"));
}
DEBUG ((DEBUG_VERBOSE, "Error Count : %d\n", QtdHw->ErrCnt));
@@ -109,7 +104,6 @@ EhcDumpQtd (
}
}
/**
Dump the queue head.
@@ -120,22 +114,27 @@ EhcDumpQtd (
**/
VOID
EhcDumpQh (
IN EHC_QH *Qh,
IN CHAR8 *Msg,
IN BOOLEAN DumpBuf
IN EHC_QH *Qh,
IN CHAR8 *Msg,
IN BOOLEAN DumpBuf
)
{
EHC_QTD *Qtd;
QH_HW *QhHw;
LIST_ENTRY *Entry;
UINTN Index;
EHC_QTD *Qtd;
QH_HW *QhHw;
LIST_ENTRY *Entry;
UINTN Index;
if (Msg != NULL) {
DEBUG ((DEBUG_VERBOSE, Msg));
}
DEBUG ((DEBUG_VERBOSE, "Queue head @ 0x%p, interval %ld, next qh %p\n",
Qh, (UINT64)Qh->Interval, Qh->NextQh));
DEBUG ((
DEBUG_VERBOSE,
"Queue head @ 0x%p, interval %ld, next qh %p\n",
Qh,
(UINT64)Qh->Interval,
Qh->NextQh
));
QhHw = &Qh->QhHw;
@@ -166,10 +165,8 @@ EhcDumpQh (
if (QhHw->Pid == QTD_PID_SETUP) {
DEBUG ((DEBUG_VERBOSE, "PID : Setup\n"));
} else if (QhHw->Pid == QTD_PID_INPUT) {
DEBUG ((DEBUG_VERBOSE, "PID : IN\n"));
} else if (QhHw->Pid == QTD_PID_OUTPUT) {
DEBUG ((DEBUG_VERBOSE, "PID : OUT\n"));
}
@@ -196,7 +193,6 @@ EhcDumpQh (
}
}
/**
Dump the buffer in the form of hex.
@@ -206,15 +202,15 @@ EhcDumpQh (
**/
VOID
EhcDumpBuf (
IN UINT8 *Buf,
IN UINTN Len
IN UINT8 *Buf,
IN UINTN Len
)
{
UINTN Index;
UINTN Index;
for (Index = 0; Index < Len; Index++) {
if (Index % 16 == 0) {
DEBUG ((DEBUG_VERBOSE,"\n"));
DEBUG ((DEBUG_VERBOSE, "\n"));
}
DEBUG ((DEBUG_VERBOSE, "%02x ", Buf[Index]));

18
MdeModulePkg/Bus/Pci/EhciDxe/EhciDebug.h
View File

@@ -10,7 +10,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#ifndef _EFI_EHCI_DEBUG_H_
#define _EFI_EHCI_DEBUG_H_
/**
Dump the fields of a QTD.
@@ -20,11 +19,10 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
VOID
EhcDumpQtd (
IN EHC_QTD *Qtd,
IN CHAR8 *Msg
IN EHC_QTD *Qtd,
IN CHAR8 *Msg
);
/**
Dump the queue head.
@@ -35,12 +33,11 @@ EhcDumpQtd (
**/
VOID
EhcDumpQh (
IN EHC_QH *Qh,
IN CHAR8 *Msg,
IN BOOLEAN DumpBuf
IN EHC_QH *Qh,
IN CHAR8 *Msg,
IN BOOLEAN DumpBuf
);
/**
Dump the buffer in the form of hex.
@@ -50,9 +47,8 @@ EhcDumpQh (
**/
VOID
EhcDumpBuf (
IN UINT8 *Buf,
IN UINTN Len
IN UINT8 *Buf,
IN UINTN Len
);
#endif

169
MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.c
View File

@@ -7,10 +7,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include "Ehci.h"
/**
Read EHCI capability register.
@@ -23,18 +21,18 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
UINT32
EhcReadCapRegister (
IN USB2_HC_DEV *Ehc,
IN UINT32 Offset
IN USB2_HC_DEV *Ehc,
IN UINT32 Offset
)
{
UINT32 Data;
EFI_STATUS Status;
UINT32 Data;
EFI_STATUS Status;
Status = Ehc->PciIo->Mem.Read (
Ehc->PciIo,
EfiPciIoWidthUint32,
EHC_BAR_INDEX,
(UINT64) Offset,
(UINT64)Offset,
1,
&Data
);
@@ -59,12 +57,12 @@ EhcReadCapRegister (
**/
UINT32
EhcReadDbgRegister (
IN CONST USB2_HC_DEV *Ehc,
IN UINT32 Offset
IN CONST USB2_HC_DEV *Ehc,
IN UINT32 Offset
)
{
UINT32 Data;
EFI_STATUS Status;
UINT32 Data;
EFI_STATUS Status;
Status = Ehc->PciIo->Mem.Read (
Ehc->PciIo,
@@ -83,7 +81,6 @@ EhcReadDbgRegister (
return Data;
}
/**
Check whether the host controller has an in-use debug port.
@@ -105,11 +102,11 @@ EhcReadDbgRegister (
**/
BOOLEAN
EhcIsDebugPortInUse (
IN CONST USB2_HC_DEV *Ehc,
IN CONST UINT8 *PortNumber OPTIONAL
IN CONST USB2_HC_DEV *Ehc,
IN CONST UINT8 *PortNumber OPTIONAL
)
{
UINT32 State;
UINT32 State;
if (Ehc->DebugPortNum == 0) {
//
@@ -121,7 +118,7 @@ EhcIsDebugPortInUse (
//
// The Debug Port Number field in HCSPARAMS is one-based.
//
if (PortNumber != NULL && *PortNumber != Ehc->DebugPortNum - 1) {
if ((PortNumber != NULL) && (*PortNumber != Ehc->DebugPortNum - 1)) {
//
// The caller specified a port, but it's not the debug port of the host
// controller.
@@ -132,11 +129,10 @@ EhcIsDebugPortInUse (
//
// Deduce usage from the Control Register.
//
State = EhcReadDbgRegister(Ehc, 0);
State = EhcReadDbgRegister (Ehc, 0);
return (State & USB_DEBUG_PORT_IN_USE_MASK) == USB_DEBUG_PORT_IN_USE_MASK;
}
/**
Read EHCI Operation register.
@@ -149,12 +145,12 @@ EhcIsDebugPortInUse (
**/
UINT32
EhcReadOpReg (
IN USB2_HC_DEV *Ehc,
IN UINT32 Offset
IN USB2_HC_DEV *Ehc,
IN UINT32 Offset
)
{
UINT32 Data;
EFI_STATUS Status;
UINT32 Data;
EFI_STATUS Status;
ASSERT (Ehc->CapLen != 0);
@@ -175,7 +171,6 @@ EhcReadOpReg (
return Data;
}
/**
Write the data to the EHCI operation register.
@@ -186,12 +181,12 @@ EhcReadOpReg (
**/
VOID
EhcWriteOpReg (
IN USB2_HC_DEV *Ehc,
IN UINT32 Offset,
IN UINT32 Data
IN USB2_HC_DEV *Ehc,
IN UINT32 Offset,
IN UINT32 Data
)
{
EFI_STATUS Status;
EFI_STATUS Status;
ASSERT (Ehc->CapLen != 0);
@@ -209,7 +204,6 @@ EhcWriteOpReg (
}
}
/**
Set one bit of the operational register while keeping other bits.
@@ -220,19 +214,18 @@ EhcWriteOpReg (
**/
VOID
EhcSetOpRegBit (
IN USB2_HC_DEV *Ehc,
IN UINT32 Offset,
IN UINT32 Bit
IN USB2_HC_DEV *Ehc,
IN UINT32 Offset,
IN UINT32 Bit
)
{
UINT32 Data;
UINT32 Data;
Data = EhcReadOpReg (Ehc, Offset);
Data |= Bit;
EhcWriteOpReg (Ehc, Offset, Data);
}
/**
Clear one bit of the operational register while keeping other bits.
@@ -243,19 +236,18 @@ EhcSetOpRegBit (
**/
VOID
EhcClearOpRegBit (
IN USB2_HC_DEV *Ehc,
IN UINT32 Offset,
IN UINT32 Bit
IN USB2_HC_DEV *Ehc,
IN UINT32 Offset,
IN UINT32 Bit
)
{
UINT32 Data;
UINT32 Data;
Data = EhcReadOpReg (Ehc, Offset);
Data &= ~Bit;
EhcWriteOpReg (Ehc, Offset, Data);
}
/**
Wait the operation register's bit as specified by Bit
to become set (or clear).
@@ -272,14 +264,14 @@ EhcClearOpRegBit (
**/
EFI_STATUS
EhcWaitOpRegBit (
IN USB2_HC_DEV *Ehc,
IN UINT32 Offset,
IN UINT32 Bit,
IN BOOLEAN WaitToSet,
IN UINT32 Timeout
IN USB2_HC_DEV *Ehc,
IN UINT32 Offset,
IN UINT32 Bit,
IN BOOLEAN WaitToSet,
IN UINT32 Timeout
)
{
UINT32 Index;
UINT32 Index;
for (Index = 0; Index < Timeout / EHC_SYNC_POLL_INTERVAL + 1; Index++) {
if (EHC_REG_BIT_IS_SET (Ehc, Offset, Bit) == WaitToSet) {
@@ -292,7 +284,6 @@ EhcWaitOpRegBit (
return EFI_TIMEOUT;
}
/**
Add support for UEFI Over Legacy (UoL) feature, stop
the legacy USB SMI support.
@@ -302,13 +293,13 @@ EhcWaitOpRegBit (
**/
VOID
EhcClearLegacySupport (
IN USB2_HC_DEV *Ehc
IN USB2_HC_DEV *Ehc
)
{
UINT32 ExtendCap;
EFI_PCI_IO_PROTOCOL *PciIo;
UINT32 Value;
UINT32 TimeOut;
UINT32 ExtendCap;
EFI_PCI_IO_PROTOCOL *PciIo;
UINT32 Value;
UINT32 TimeOut;
DEBUG ((DEBUG_INFO, "EhcClearLegacySupport: called to clear legacy support\n"));
@@ -337,8 +328,6 @@ EhcClearLegacySupport (
PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, ExtendCap + 0x4, 1, &Value);
}
/**
Set door bell and wait it to be ACKed by host controller.
This function is used to synchronize with the hardware.
@@ -352,12 +341,12 @@ EhcClearLegacySupport (
**/
EFI_STATUS
EhcSetAndWaitDoorBell (
IN USB2_HC_DEV *Ehc,
IN UINT32 Timeout
IN USB2_HC_DEV *Ehc,
IN UINT32 Timeout
)
{
EFI_STATUS Status;
UINT32 Data;
EFI_STATUS Status;
UINT32 Data;
EhcSetOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_IAAD);
@@ -376,7 +365,6 @@ EhcSetAndWaitDoorBell (
return Status;
}
/**
Clear all the interrutp status bits, these bits
are Write-Clean.
@@ -386,13 +374,12 @@ EhcSetAndWaitDoorBell (
**/
VOID
EhcAckAllInterrupt (
IN USB2_HC_DEV *Ehc
IN USB2_HC_DEV *Ehc
)
{
EhcWriteOpReg (Ehc, EHC_USBSTS_OFFSET, USBSTS_INTACK_MASK);
}
/**
Enable the periodic schedule then wait EHC to
actually enable it.
@@ -406,11 +393,11 @@ EhcAckAllInterrupt (
**/
EFI_STATUS
EhcEnablePeriodSchd (
IN USB2_HC_DEV *Ehc,
IN UINT32 Timeout
IN USB2_HC_DEV *Ehc,
IN UINT32 Timeout
)
{
EFI_STATUS Status;
EFI_STATUS Status;
EhcSetOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_ENABLE_PERIOD);
@@ -418,11 +405,6 @@ EhcEnablePeriodSchd (
return Status;
}
/**
Enable asynchrounous schedule.
@@ -435,11 +417,11 @@ EhcEnablePeriodSchd (
**/
EFI_STATUS
EhcEnableAsyncSchd (
IN USB2_HC_DEV *Ehc,
IN UINT32 Timeout
IN USB2_HC_DEV *Ehc,
IN UINT32 Timeout
)
{
EFI_STATUS Status;
EFI_STATUS Status;
EhcSetOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_ENABLE_ASYNC);
@@ -447,12 +429,6 @@ EhcEnableAsyncSchd (
return Status;
}
/**
Whether Ehc is halted.
@@ -464,13 +440,12 @@ EhcEnableAsyncSchd (
**/
BOOLEAN
EhcIsHalt (
IN USB2_HC_DEV *Ehc
IN USB2_HC_DEV *Ehc
)
{
return EHC_REG_BIT_IS_SET (Ehc, EHC_USBSTS_OFFSET, USBSTS_HALT);
}
/**
Whether system error occurred.
@@ -482,13 +457,12 @@ EhcIsHalt (
**/
BOOLEAN
EhcIsSysError (
IN USB2_HC_DEV *Ehc
IN USB2_HC_DEV *Ehc
)
{
return EHC_REG_BIT_IS_SET (Ehc, EHC_USBSTS_OFFSET, USBSTS_SYS_ERROR);
}
/**
Reset the host controller.
@@ -501,11 +475,11 @@ EhcIsSysError (
**/
EFI_STATUS
EhcResetHC (
IN USB2_HC_DEV *Ehc,
IN UINT32 Timeout
IN USB2_HC_DEV *Ehc,
IN UINT32 Timeout
)
{
EFI_STATUS Status;
EFI_STATUS Status;
//
// Host can only be reset when it is halt. If not so, halt it
@@ -523,7 +497,6 @@ EhcResetHC (
return Status;
}
/**
Halt the host controller.
@@ -536,18 +509,17 @@ EhcResetHC (
**/
EFI_STATUS
EhcHaltHC (
IN USB2_HC_DEV *Ehc,
IN UINT32 Timeout
IN USB2_HC_DEV *Ehc,
IN UINT32 Timeout
)
{
EFI_STATUS Status;
EFI_STATUS Status;
EhcClearOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_RUN);
Status = EhcWaitOpRegBit (Ehc, EHC_USBSTS_OFFSET, USBSTS_HALT, TRUE, Timeout);
return Status;
}
/**
Set the EHCI to run.
@@ -560,18 +532,17 @@ EhcHaltHC (
**/
EFI_STATUS
EhcRunHC (
IN USB2_HC_DEV *Ehc,
IN UINT32 Timeout
IN USB2_HC_DEV *Ehc,
IN UINT32 Timeout
)
{
EFI_STATUS Status;
EFI_STATUS Status;
EhcSetOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_RUN);
Status = EhcWaitOpRegBit (Ehc, EHC_USBSTS_OFFSET, USBSTS_HALT, FALSE, Timeout);
return Status;
}
/**
Initialize the HC hardware.
EHCI spec lists the five things to do to initialize the hardware:
@@ -589,12 +560,12 @@ EhcRunHC (
**/
EFI_STATUS
EhcInitHC (
IN USB2_HC_DEV *Ehc
IN USB2_HC_DEV *Ehc
)
{
EFI_STATUS Status;
UINT32 Index;
UINT32 RegVal;
EFI_STATUS Status;
UINT32 Index;
UINT32 RegVal;
// This ASSERT crashes the BeagleBoard. There is some issue in the USB stack.
// This ASSERT needs to be removed so the BeagleBoard will boot. When we fix
@@ -629,15 +600,15 @@ EhcInitHC (
// 3. Power up all ports if EHCI has Port Power Control (PPC) support
//
if (Ehc->HcStructParams & HCSP_PPC) {
for (Index = 0; Index < (UINT8) (Ehc->HcStructParams & HCSP_NPORTS); Index++) {
for (Index = 0; Index < (UINT8)(Ehc->HcStructParams & HCSP_NPORTS); Index++) {
//
// Do not clear port status bits on initialization. Otherwise devices will
// not enumerate properly at startup.
//
RegVal = EhcReadOpReg(Ehc, (UINT32)(EHC_PORT_STAT_OFFSET + (4 * Index)));
RegVal = EhcReadOpReg (Ehc, (UINT32)(EHC_PORT_STAT_OFFSET + (4 * Index)));
RegVal &= ~PORTSC_CHANGE_MASK;
RegVal |= PORTSC_POWER;
EhcWriteOpReg (Ehc, (UINT32) (EHC_PORT_STAT_OFFSET + (4 * Index)), RegVal);
EhcWriteOpReg (Ehc, (UINT32)(EHC_PORT_STAT_OFFSET + (4 * Index)), RegVal);
}
}

153
MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.h
View File

@@ -14,20 +14,19 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
// EHCI register offset
//
//
// Capability register offset
//
#define EHC_CAPLENGTH_OFFSET 0 // Capability register length offset
#define EHC_HCSPARAMS_OFFSET 0x04 // Structural Parameters 04-07h
#define EHC_HCCPARAMS_OFFSET 0x08 // Capability parameters offset
#define EHC_CAPLENGTH_OFFSET 0 // Capability register length offset
#define EHC_HCSPARAMS_OFFSET 0x04 // Structural Parameters 04-07h
#define EHC_HCCPARAMS_OFFSET 0x08 // Capability parameters offset
//
// Capability register bit definition
//
#define HCSP_NPORTS 0x0F // Number of root hub port
#define HCSP_PPC 0x10 // Port Power Control
#define HCCP_64BIT 0x01 // 64-bit addressing capability
#define HCSP_NPORTS 0x0F // Number of root hub port
#define HCSP_PPC 0x10 // Port Power Control
#define HCCP_64BIT 0x01 // 64-bit addressing capability
//
// Operational register offset
@@ -42,66 +41,66 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#define EHC_CONFIG_FLAG_OFFSET 0x40 // Configure flag register offset
#define EHC_PORT_STAT_OFFSET 0x44 // Port status/control offset
#define EHC_FRAME_LEN 1024
#define EHC_FRAME_LEN 1024
//
// Register bit definition
//
#define CONFIGFLAG_ROUTE_EHC 0x01 // Route port to EHC
#define CONFIGFLAG_ROUTE_EHC 0x01 // Route port to EHC
#define USBCMD_RUN 0x01 // Run/stop
#define USBCMD_RESET 0x02 // Start the host controller reset
#define USBCMD_ENABLE_PERIOD 0x10 // Enable periodic schedule
#define USBCMD_ENABLE_ASYNC 0x20 // Enable asynchronous schedule
#define USBCMD_IAAD 0x40 // Interrupt on async advance doorbell
#define USBCMD_RUN 0x01 // Run/stop
#define USBCMD_RESET 0x02 // Start the host controller reset
#define USBCMD_ENABLE_PERIOD 0x10 // Enable periodic schedule
#define USBCMD_ENABLE_ASYNC 0x20 // Enable asynchronous schedule
#define USBCMD_IAAD 0x40 // Interrupt on async advance doorbell
#define USBSTS_IAA 0x20 // Interrupt on async advance
#define USBSTS_PERIOD_ENABLED 0x4000 // Periodic schedule status
#define USBSTS_ASYNC_ENABLED 0x8000 // Asynchronous schedule status
#define USBSTS_HALT 0x1000 // Host controller halted
#define USBSTS_SYS_ERROR 0x10 // Host system error
#define USBSTS_INTACK_MASK 0x003F // Mask for the interrupt ACK, the WC
#define USBSTS_IAA 0x20 // Interrupt on async advance
#define USBSTS_PERIOD_ENABLED 0x4000 // Periodic schedule status
#define USBSTS_ASYNC_ENABLED 0x8000 // Asynchronous schedule status
#define USBSTS_HALT 0x1000 // Host controller halted
#define USBSTS_SYS_ERROR 0x10 // Host system error
#define USBSTS_INTACK_MASK 0x003F // Mask for the interrupt ACK, the WC
// (write clean) bits in USBSTS register
#define PORTSC_CONN 0x01 // Current Connect Status
#define PORTSC_CONN_CHANGE 0x02 // Connect Status Change
#define PORTSC_ENABLED 0x04 // Port Enable / Disable
#define PORTSC_ENABLE_CHANGE 0x08 // Port Enable / Disable Change
#define PORTSC_OVERCUR 0x10 // Over current Active
#define PORTSC_OVERCUR_CHANGE 0x20 // Over current Change
#define PORSTSC_RESUME 0x40 // Force Port Resume
#define PORTSC_SUSPEND 0x80 // Port Suspend State
#define PORTSC_RESET 0x100 // Port Reset
#define PORTSC_LINESTATE_K 0x400 // Line Status K-state
#define PORTSC_LINESTATE_J 0x800 // Line Status J-state
#define PORTSC_POWER 0x1000 // Port Power
#define PORTSC_OWNER 0x2000 // Port Owner
#define PORTSC_CHANGE_MASK 0x2A // Mask of the port change bits,
#define PORTSC_CONN 0x01 // Current Connect Status
#define PORTSC_CONN_CHANGE 0x02 // Connect Status Change
#define PORTSC_ENABLED 0x04 // Port Enable / Disable
#define PORTSC_ENABLE_CHANGE 0x08 // Port Enable / Disable Change
#define PORTSC_OVERCUR 0x10 // Over current Active
#define PORTSC_OVERCUR_CHANGE 0x20 // Over current Change
#define PORSTSC_RESUME 0x40 // Force Port Resume
#define PORTSC_SUSPEND 0x80 // Port Suspend State
#define PORTSC_RESET 0x100 // Port Reset
#define PORTSC_LINESTATE_K 0x400 // Line Status K-state
#define PORTSC_LINESTATE_J 0x800 // Line Status J-state
#define PORTSC_POWER 0x1000 // Port Power
#define PORTSC_OWNER 0x2000 // Port Owner
#define PORTSC_CHANGE_MASK 0x2A // Mask of the port change bits,
// they are WC (write clean)
//
// PCI Configuration Registers
//
#define EHC_BAR_INDEX 0 // how many bytes away from USB_BASE to 0x10
#define EHC_BAR_INDEX 0 // how many bytes away from USB_BASE to 0x10
//
// Debug port capability id
//
#define EHC_DEBUG_PORT_CAP_ID 0x0A
#define EHC_DEBUG_PORT_CAP_ID 0x0A
#define EHC_LINK_TERMINATED(Link) (((Link) & 0x01) != 0)
#define EHC_LINK_TERMINATED(Link) (((Link) & 0x01) != 0)
#define EHC_ADDR(High, QhHw32) \
((VOID *) (UINTN) (LShiftU64 ((High), 32) | ((QhHw32) & 0xFFFFFFF0)))
#define EHCI_IS_DATAIN(EndpointAddr) EHC_BIT_IS_SET((EndpointAddr), 0x80)
#define EHCI_IS_DATAIN(EndpointAddr) EHC_BIT_IS_SET((EndpointAddr), 0x80)
//
// Structure to map the hardware port states to the
// UEFI's port states.
//
typedef struct {
UINT16 HwState;
UINT16 UefiState;
UINT16 HwState;
UINT16 UefiState;
} USB_PORT_STATE_MAP;
//
@@ -109,9 +108,9 @@ typedef struct {
//
#pragma pack(1)
typedef struct {
UINT8 ProgInterface;
UINT8 SubClassCode;
UINT8 BaseCode;
UINT8 ProgInterface;
UINT8 SubClassCode;
UINT8 BaseCode;
} USB_CLASSC;
#pragma pack()
@@ -126,8 +125,8 @@ typedef struct {
**/
UINT32
EhcReadCapRegister (
IN USB2_HC_DEV *Ehc,
IN UINT32 Offset
IN USB2_HC_DEV *Ehc,
IN UINT32 Offset
);
/**
@@ -151,8 +150,8 @@ EhcReadCapRegister (
**/
BOOLEAN
EhcIsDebugPortInUse (
IN CONST USB2_HC_DEV *Ehc,
IN CONST UINT8 *PortNumber OPTIONAL
IN CONST USB2_HC_DEV *Ehc,
IN CONST UINT8 *PortNumber OPTIONAL
);
/**
@@ -166,11 +165,10 @@ EhcIsDebugPortInUse (
**/
UINT32
EhcReadOpReg (
IN USB2_HC_DEV *Ehc,
IN UINT32 Offset
IN USB2_HC_DEV *Ehc,
IN UINT32 Offset
);
/**
Write the data to the EHCI operation register.
@@ -181,9 +179,9 @@ EhcReadOpReg (
**/
VOID
EhcWriteOpReg (
IN USB2_HC_DEV *Ehc,
IN UINT32 Offset,
IN UINT32 Data
IN USB2_HC_DEV *Ehc,
IN UINT32 Offset,
IN UINT32 Data
);
/**
@@ -196,9 +194,9 @@ EhcWriteOpReg (
**/
VOID
EhcSetOpRegBit (
IN USB2_HC_DEV *Ehc,
IN UINT32 Offset,
IN UINT32 Bit
IN USB2_HC_DEV *Ehc,
IN UINT32 Offset,
IN UINT32 Bit
);
/**
@@ -211,9 +209,9 @@ EhcSetOpRegBit (
**/
VOID
EhcClearOpRegBit (
IN USB2_HC_DEV *Ehc,
IN UINT32 Offset,
IN UINT32 Bit
IN USB2_HC_DEV *Ehc,
IN UINT32 Offset,
IN UINT32 Bit
);
/**
@@ -225,11 +223,9 @@ EhcClearOpRegBit (
**/
VOID
EhcClearLegacySupport (
IN USB2_HC_DEV *Ehc
IN USB2_HC_DEV *Ehc
);
/**
Set door bell and wait it to be ACKed by host controller.
This function is used to synchronize with the hardware.
@@ -243,11 +239,10 @@ EhcClearLegacySupport (
**/
EFI_STATUS
EhcSetAndWaitDoorBell (
IN USB2_HC_DEV *Ehc,
IN UINT32 Timeout
IN USB2_HC_DEV *Ehc,
IN UINT32 Timeout
);
/**
Clear all the interrutp status bits, these bits are Write-Clean.
@@ -256,11 +251,9 @@ EhcSetAndWaitDoorBell (
**/
VOID
EhcAckAllInterrupt (
IN USB2_HC_DEV *Ehc
IN USB2_HC_DEV *Ehc
);
/**
Whether Ehc is halted.
@@ -272,10 +265,9 @@ EhcAckAllInterrupt (
**/
BOOLEAN
EhcIsHalt (
IN USB2_HC_DEV *Ehc
IN USB2_HC_DEV *Ehc
);
/**
Whether system error occurred.
@@ -287,10 +279,9 @@ EhcIsHalt (
**/
BOOLEAN
EhcIsSysError (
IN USB2_HC_DEV *Ehc
IN USB2_HC_DEV *Ehc
);
/**
Reset the host controller.
@@ -303,11 +294,10 @@ EhcIsSysError (
**/
EFI_STATUS
EhcResetHC (
IN USB2_HC_DEV *Ehc,
IN UINT32 Timeout
IN USB2_HC_DEV *Ehc,
IN UINT32 Timeout
);
/**
Halt the host controller.
@@ -320,11 +310,10 @@ EhcResetHC (
**/
EFI_STATUS
EhcHaltHC (
IN USB2_HC_DEV *Ehc,
IN UINT32 Timeout
IN USB2_HC_DEV *Ehc,
IN UINT32 Timeout
);
/**
Set the EHCI to run.
@@ -337,12 +326,10 @@ EhcHaltHC (
**/
EFI_STATUS
EhcRunHC (
IN USB2_HC_DEV *Ehc,
IN UINT32 Timeout
IN USB2_HC_DEV *Ehc,
IN UINT32 Timeout
);
/**
Initialize the HC hardware.
EHCI spec lists the five things to do to initialize the hardware:
@@ -360,7 +347,7 @@ EhcRunHC (
**/
EFI_STATUS
EhcInitHC (
IN USB2_HC_DEV *Ehc
IN USB2_HC_DEV *Ehc
);
#endif

377
MdeModulePkg/Bus/Pci/EhciDxe/EhciSched.c
View File

@@ -10,7 +10,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include "Ehci.h"
/**
Create helper QTD/QH for the EHCI device.
@@ -22,14 +21,14 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
EFI_STATUS
EhcCreateHelpQ (
IN USB2_HC_DEV *Ehc
IN USB2_HC_DEV *Ehc
)
{
USB_ENDPOINT Ep;
EHC_QH *Qh;
QH_HW *QhHw;
EHC_QTD *Qtd;
EFI_PHYSICAL_ADDRESS PciAddr;
USB_ENDPOINT Ep;
EHC_QH *Qh;
QH_HW *QhHw;
EHC_QTD *Qtd;
EFI_PHYSICAL_ADDRESS PciAddr;
//
// Create an inactive Qtd to terminate the short packet read.
@@ -40,25 +39,25 @@ EhcCreateHelpQ (
return EFI_OUT_OF_RESOURCES;
}
Qtd->QtdHw.Status = QTD_STAT_HALTED;
Ehc->ShortReadStop = Qtd;
Qtd->QtdHw.Status = QTD_STAT_HALTED;
Ehc->ShortReadStop = Qtd;
//
// Create a QH to act as the EHC reclamation header.
// Set the header to loopback to itself.
//
Ep.DevAddr = 0;
Ep.EpAddr = 1;
Ep.Direction = EfiUsbDataIn;
Ep.DevSpeed = EFI_USB_SPEED_HIGH;
Ep.MaxPacket = 64;
Ep.HubAddr = 0;
Ep.HubPort = 0;
Ep.Toggle = 0;
Ep.Type = EHC_BULK_TRANSFER;
Ep.PollRate = 1;
Ep.DevAddr = 0;
Ep.EpAddr = 1;
Ep.Direction = EfiUsbDataIn;
Ep.DevSpeed = EFI_USB_SPEED_HIGH;
Ep.MaxPacket = 64;
Ep.HubAddr = 0;
Ep.HubPort = 0;
Ep.Toggle = 0;
Ep.Type = EHC_BULK_TRANSFER;
Ep.PollRate = 1;
Qh = EhcCreateQh (Ehc, &Ep);
Qh = EhcCreateQh (Ehc, &Ep);
if (Qh == NULL) {
return EFI_OUT_OF_RESOURCES;
@@ -66,7 +65,7 @@ EhcCreateHelpQ (
PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Qh, sizeof (EHC_QH));
QhHw = &Qh->QhHw;
QhHw->HorizonLink = QH_LINK (PciAddr + OFFSET_OF(EHC_QH, QhHw), EHC_TYPE_QH, FALSE);
QhHw->HorizonLink = QH_LINK (PciAddr + OFFSET_OF (EHC_QH, QhHw), EHC_TYPE_QH, FALSE);
QhHw->Status = QTD_STAT_HALTED;
QhHw->ReclaimHead = 1;
Qh->NextQh = Qh;
@@ -75,10 +74,10 @@ EhcCreateHelpQ (
//
// Create a dummy QH to act as the terminator for periodical schedule
//
Ep.EpAddr = 2;
Ep.Type = EHC_INT_TRANSFER_SYNC;
Ep.EpAddr = 2;
Ep.Type = EHC_INT_TRANSFER_SYNC;
Qh = EhcCreateQh (Ehc, &Ep);
Qh = EhcCreateQh (Ehc, &Ep);
if (Qh == NULL) {
return EFI_OUT_OF_RESOURCES;
@@ -90,7 +89,6 @@ EhcCreateHelpQ (
return EFI_SUCCESS;
}
/**
Initialize the schedule data structure such as frame list.
@@ -102,7 +100,7 @@ EhcCreateHelpQ (
**/
EFI_STATUS
EhcInitSched (
IN USB2_HC_DEV *Ehc
IN USB2_HC_DEV *Ehc
)
{
EFI_PCI_IO_PROTOCOL *PciIo;
@@ -154,8 +152,8 @@ EhcInitSched (
return EFI_OUT_OF_RESOURCES;
}
Ehc->PeriodFrame = Buf;
Ehc->PeriodFrameMap = Map;
Ehc->PeriodFrame = Buf;
Ehc->PeriodFrameMap = Map;
//
// Program the FRAMELISTBASE register with the low 32 bit addr
@@ -191,13 +189,13 @@ EhcInitSched (
//
// Initialize the frame list entries then set the registers
//
Ehc->PeriodFrameHost = AllocateZeroPool (EHC_FRAME_LEN * sizeof (UINTN));
Ehc->PeriodFrameHost = AllocateZeroPool (EHC_FRAME_LEN * sizeof (UINTN));
if (Ehc->PeriodFrameHost == NULL) {
Status = EFI_OUT_OF_RESOURCES;
goto ErrorExit;
}
PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Ehc->PeriodOne, sizeof (EHC_QH));
PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Ehc->PeriodOne, sizeof (EHC_QH));
for (Index = 0; Index < EHC_FRAME_LEN; Index++) {
//
@@ -242,7 +240,6 @@ ErrorExit1:
return Status;
}
/**
Free the schedule data. It may be partially initialized.
@@ -251,10 +248,10 @@ ErrorExit1:
**/
VOID
EhcFreeSched (
IN USB2_HC_DEV *Ehc
IN USB2_HC_DEV *Ehc
)
{
EFI_PCI_IO_PROTOCOL *PciIo;
EFI_PCI_IO_PROTOCOL *PciIo;
EhcWriteOpReg (Ehc, EHC_FRAME_BASE_OFFSET, 0);
EhcWriteOpReg (Ehc, EHC_ASYNC_HEAD_OFFSET, 0);
@@ -300,7 +297,6 @@ EhcFreeSched (
}
}
/**
Link the queue head to the asynchronous schedule list.
UEFI only supports one CTRL/BULK transfer at a time
@@ -314,30 +310,29 @@ EhcFreeSched (
**/
VOID
EhcLinkQhToAsync (
IN USB2_HC_DEV *Ehc,
IN EHC_QH *Qh
IN USB2_HC_DEV *Ehc,
IN EHC_QH *Qh
)
{
EHC_QH *Head;
EFI_PHYSICAL_ADDRESS PciAddr;
EHC_QH *Head;
EFI_PHYSICAL_ADDRESS PciAddr;
//
// Append the queue head after the reclaim header, then
// fix the hardware visiable parts (EHCI R1.0 page 72).
// ReclaimHead is always linked to the EHCI's AsynListAddr.
//
Head = Ehc->ReclaimHead;
Head = Ehc->ReclaimHead;
Qh->NextQh = Head->NextQh;
Head->NextQh = Qh;
Qh->NextQh = Head->NextQh;
Head->NextQh = Qh;
PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Qh->NextQh, sizeof (EHC_QH));
Qh->QhHw.HorizonLink = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);
PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Head->NextQh, sizeof (EHC_QH));
Head->QhHw.HorizonLink = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);
PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Qh->NextQh, sizeof (EHC_QH));
Qh->QhHw.HorizonLink = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);
PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Head->NextQh, sizeof (EHC_QH));
Head->QhHw.HorizonLink = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);
}
/**
Unlink a queue head from the asynchronous schedule list.
Need to synchronize with hardware.
@@ -348,13 +343,13 @@ EhcLinkQhToAsync (
**/
VOID
EhcUnlinkQhFromAsync (
IN USB2_HC_DEV *Ehc,
IN EHC_QH *Qh
IN USB2_HC_DEV *Ehc,
IN EHC_QH *Qh
)
{
EHC_QH *Head;
EFI_STATUS Status;
EFI_PHYSICAL_ADDRESS PciAddr;
EHC_QH *Head;
EFI_STATUS Status;
EFI_PHYSICAL_ADDRESS PciAddr;
ASSERT (Ehc->ReclaimHead->NextQh == Qh);
@@ -363,13 +358,13 @@ EhcUnlinkQhFromAsync (
// visiable part: Only need to loopback the ReclaimHead. The Qh
// is pointing to ReclaimHead (which is staill in the list).
//
Head = Ehc->ReclaimHead;
Head = Ehc->ReclaimHead;
Head->NextQh = Qh->NextQh;
Qh->NextQh = NULL;
Head->NextQh = Qh->NextQh;
Qh->NextQh = NULL;
PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Head->NextQh, sizeof (EHC_QH));
Head->QhHw.HorizonLink = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);
PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Head->NextQh, sizeof (EHC_QH));
Head->QhHw.HorizonLink = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);
//
// Set and wait the door bell to synchronize with the hardware
@@ -381,7 +376,6 @@ EhcUnlinkQhFromAsync (
}
}
/**
Link a queue head for interrupt transfer to the periodic
schedule frame list. This code is very much the same as
@@ -393,23 +387,23 @@ EhcUnlinkQhFromAsync (
**/
VOID
EhcLinkQhToPeriod (
IN USB2_HC_DEV *Ehc,
IN EHC_QH *Qh
IN USB2_HC_DEV *Ehc,
IN EHC_QH *Qh
)
{
UINTN Index;
EHC_QH *Prev;
EHC_QH *Next;
EFI_PHYSICAL_ADDRESS PciAddr;
UINTN Index;
EHC_QH *Prev;
EHC_QH *Next;
EFI_PHYSICAL_ADDRESS PciAddr;
for (Index = 0; Index < EHC_FRAME_LEN; Index += Qh->Interval) {
//
// First QH can't be NULL because we always keep PeriodOne
// heads on the frame list
//
ASSERT (!EHC_LINK_TERMINATED (((UINT32*)Ehc->PeriodFrame)[Index]));
Next = (EHC_QH*)((UINTN*)Ehc->PeriodFrameHost)[Index];
Prev = NULL;
ASSERT (!EHC_LINK_TERMINATED (((UINT32 *)Ehc->PeriodFrame)[Index]));
Next = (EHC_QH *)((UINTN *)Ehc->PeriodFrameHost)[Index];
Prev = NULL;
//
// Now, insert the queue head (Qh) into this frame:
@@ -422,8 +416,8 @@ EhcLinkQhToPeriod (
// Then, insert the Qh between then
//
while (Next->Interval > Qh->Interval) {
Prev = Next;
Next = Next->NextQh;
Prev = Next;
Next = Next->NextQh;
}
ASSERT (Next != NULL);
@@ -449,15 +443,15 @@ EhcLinkQhToPeriod (
//
ASSERT ((Index == 0) && (Qh->NextQh == NULL));
Prev = Next;
Next = Next->NextQh;
Prev = Next;
Next = Next->NextQh;
Qh->NextQh = Next;
Prev->NextQh = Qh;
Qh->NextQh = Next;
Prev->NextQh = Qh;
Qh->QhHw.HorizonLink = Prev->QhHw.HorizonLink;
PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Qh, sizeof (EHC_QH));
Prev->QhHw.HorizonLink = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);
Qh->QhHw.HorizonLink = Prev->QhHw.HorizonLink;
PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Qh, sizeof (EHC_QH));
Prev->QhHw.HorizonLink = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);
break;
}
@@ -467,24 +461,23 @@ EhcLinkQhToPeriod (
// guarranted by 2^n polling interval.
//
if (Qh->NextQh == NULL) {
Qh->NextQh = Next;
PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Next, sizeof (EHC_QH));
Qh->QhHw.HorizonLink = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);
Qh->NextQh = Next;
PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Next, sizeof (EHC_QH));
Qh->QhHw.HorizonLink = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);
}
PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Qh, sizeof (EHC_QH));
if (Prev == NULL) {
((UINT32*)Ehc->PeriodFrame)[Index] = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);
((UINTN*)Ehc->PeriodFrameHost)[Index] = (UINTN)Qh;
((UINT32 *)Ehc->PeriodFrame)[Index] = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);
((UINTN *)Ehc->PeriodFrameHost)[Index] = (UINTN)Qh;
} else {
Prev->NextQh = Qh;
Prev->QhHw.HorizonLink = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);
Prev->NextQh = Qh;
Prev->QhHw.HorizonLink = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);
}
}
}
/**
Unlink an interrupt queue head from the periodic
schedule frame list.
@@ -495,30 +488,30 @@ EhcLinkQhToPeriod (
**/
VOID
EhcUnlinkQhFromPeriod (
IN USB2_HC_DEV *Ehc,
IN EHC_QH *Qh
IN USB2_HC_DEV *Ehc,
IN EHC_QH *Qh
)
{
UINTN Index;
EHC_QH *Prev;
EHC_QH *This;
UINTN Index;
EHC_QH *Prev;
EHC_QH *This;
for (Index = 0; Index < EHC_FRAME_LEN; Index += Qh->Interval) {
//
// Frame link can't be NULL because we always keep PeroidOne
// on the frame list
//
ASSERT (!EHC_LINK_TERMINATED (((UINT32*)Ehc->PeriodFrame)[Index]));
This = (EHC_QH*)((UINTN*)Ehc->PeriodFrameHost)[Index];
Prev = NULL;
ASSERT (!EHC_LINK_TERMINATED (((UINT32 *)Ehc->PeriodFrame)[Index]));
This = (EHC_QH *)((UINTN *)Ehc->PeriodFrameHost)[Index];
Prev = NULL;
//
// Walk through the frame's QH list to find the
// queue head to remove
//
while ((This != NULL) && (This != Qh)) {
Prev = This;
This = This->NextQh;
Prev = This;
This = This->NextQh;
}
//
@@ -533,16 +526,15 @@ EhcUnlinkQhFromPeriod (
//
// Qh is the first entry in the frame
//
((UINT32*)Ehc->PeriodFrame)[Index] = Qh->QhHw.HorizonLink;
((UINTN*)Ehc->PeriodFrameHost)[Index] = (UINTN)Qh->NextQh;
((UINT32 *)Ehc->PeriodFrame)[Index] = Qh->QhHw.HorizonLink;
((UINTN *)Ehc->PeriodFrameHost)[Index] = (UINTN)Qh->NextQh;
} else {
Prev->NextQh = Qh->NextQh;
Prev->QhHw.HorizonLink = Qh->QhHw.HorizonLink;
Prev->NextQh = Qh->NextQh;
Prev->QhHw.HorizonLink = Qh->QhHw.HorizonLink;
}
}
}
/**
Check the URB's execution result and update the URB's
result accordingly.
@@ -555,23 +547,23 @@ EhcUnlinkQhFromPeriod (
**/
BOOLEAN
EhcCheckUrbResult (
IN USB2_HC_DEV *Ehc,
IN URB *Urb
IN USB2_HC_DEV *Ehc,
IN URB *Urb
)
{
LIST_ENTRY *Entry;
EHC_QTD *Qtd;
QTD_HW *QtdHw;
UINT8 State;
BOOLEAN Finished;
EFI_PHYSICAL_ADDRESS PciAddr;
LIST_ENTRY *Entry;
EHC_QTD *Qtd;
QTD_HW *QtdHw;
UINT8 State;
BOOLEAN Finished;
EFI_PHYSICAL_ADDRESS PciAddr;
ASSERT ((Ehc != NULL) && (Urb != NULL) && (Urb->Qh != NULL));
Finished = TRUE;
Urb->Completed = 0;
Finished = TRUE;
Urb->Completed = 0;
Urb->Result = EFI_USB_NOERROR;
Urb->Result = EFI_USB_NOERROR;
if (EhcIsHalt (Ehc) || EhcIsSysError (Ehc)) {
Urb->Result |= EFI_USB_ERR_SYSTEM;
@@ -581,7 +573,7 @@ EhcCheckUrbResult (
BASE_LIST_FOR_EACH (Entry, &Urb->Qh->Qtds) {
Qtd = EFI_LIST_CONTAINER (Entry, EHC_QTD, QtdList);
QtdHw = &Qtd->QtdHw;
State = (UINT8) QtdHw->Status;
State = (UINT8)QtdHw->Status;
if (EHC_BIT_IS_SET (State, QTD_STAT_HALTED)) {
//
@@ -606,7 +598,6 @@ EhcCheckUrbResult (
Finished = TRUE;
goto ON_EXIT;
} else if (EHC_BIT_IS_SET (State, QTD_STAT_ACTIVE)) {
//
// The QTD is still active, no need to check furthur.
@@ -615,7 +606,6 @@ EhcCheckUrbResult (
Finished = FALSE;
goto ON_EXIT;
} else {
//
// This QTD is finished OK or met short packet read. Update the
@@ -657,12 +647,11 @@ ON_EXIT:
// NOTICE: don't move DT update before the loop, otherwise there is
// a race condition that DT is wrong.
//
Urb->DataToggle = (UINT8) Urb->Qh->QhHw.DataToggle;
Urb->DataToggle = (UINT8)Urb->Qh->QhHw.DataToggle;
return Finished;
}
/**
Execute the transfer by polling the URB. This is a synchronous operation.
@@ -677,16 +666,16 @@ ON_EXIT:
**/
EFI_STATUS
EhcExecTransfer (
IN USB2_HC_DEV *Ehc,
IN URB *Urb,
IN UINTN TimeOut
IN USB2_HC_DEV *Ehc,
IN URB *Urb,
IN UINTN TimeOut
)
{
EFI_STATUS Status;
UINTN Index;
UINTN Loop;
BOOLEAN Finished;
BOOLEAN InfiniteLoop;
EFI_STATUS Status;
UINTN Index;
UINTN Loop;
BOOLEAN Finished;
BOOLEAN InfiniteLoop;
Status = EFI_SUCCESS;
Loop = TimeOut * EHC_1_MILLISECOND;
@@ -717,7 +706,6 @@ EhcExecTransfer (
EhcDumpQh (Urb->Qh, NULL, FALSE);
Status = EFI_TIMEOUT;
} else if (Urb->Result != EFI_USB_NOERROR) {
DEBUG ((DEBUG_ERROR, "EhcExecTransfer: transfer failed with %x\n", Urb->Result));
EhcDumpQh (Urb->Qh, NULL, FALSE);
@@ -728,7 +716,6 @@ EhcExecTransfer (
return Status;
}
/**
Delete a single asynchronous interrupt transfer for
the device and endpoint.
@@ -744,10 +731,10 @@ EhcExecTransfer (
**/
EFI_STATUS
EhciDelAsyncIntTransfer (
IN USB2_HC_DEV *Ehc,
IN UINT8 DevAddr,
IN UINT8 EpNum,
OUT UINT8 *DataToggle
IN USB2_HC_DEV *Ehc,
IN UINT8 DevAddr,
IN UINT8 EpNum,
OUT UINT8 *DataToggle
)
{
LIST_ENTRY *Entry;
@@ -762,7 +749,8 @@ EhciDelAsyncIntTransfer (
Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);
if ((Urb->Ep.DevAddr == DevAddr) && (Urb->Ep.EpAddr == EpNum) &&
(Urb->Ep.Direction == Direction)) {
(Urb->Ep.Direction == Direction))
{
//
// Check the URB status to retrieve the next data toggle
// from the associated queue head.
@@ -782,7 +770,6 @@ EhciDelAsyncIntTransfer (
return EFI_NOT_FOUND;
}
/**
Remove all the asynchronous interrutp transfers.
@@ -791,12 +778,12 @@ EhciDelAsyncIntTransfer (
**/
VOID
EhciDelAllAsyncIntTransfers (
IN USB2_HC_DEV *Ehc
IN USB2_HC_DEV *Ehc
)
{
LIST_ENTRY *Entry;
LIST_ENTRY *Next;
URB *Urb;
LIST_ENTRY *Entry;
LIST_ENTRY *Next;
URB *Urb;
BASE_LIST_FOR_EACH_SAFE (Entry, Next, &Ehc->AsyncIntTransfers) {
Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);
@@ -830,21 +817,21 @@ EhciDelAllAsyncIntTransfers (
**/
URB *
EhciInsertAsyncIntTransfer (
IN USB2_HC_DEV *Ehc,
IN UINT8 DevAddr,
IN UINT8 EpAddr,
IN UINT8 DevSpeed,
IN UINT8 Toggle,
IN UINTN MaxPacket,
IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Hub,
IN UINTN DataLen,
IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
IN VOID *Context,
IN UINTN Interval
IN USB2_HC_DEV *Ehc,
IN UINT8 DevAddr,
IN UINT8 EpAddr,
IN UINT8 DevSpeed,
IN UINT8 Toggle,
IN UINTN MaxPacket,
IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Hub,
IN UINTN DataLen,
IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
IN VOID *Context,
IN UINTN Interval
)
{
VOID *Data;
URB *Urb;
VOID *Data;
URB *Urb;
Data = AllocatePool (DataLen);
@@ -899,16 +886,16 @@ EhciInsertAsyncIntTransfer (
**/
EFI_STATUS
EhcFlushAsyncIntMap (
IN USB2_HC_DEV *Ehc,
IN URB *Urb
IN USB2_HC_DEV *Ehc,
IN URB *Urb
)
{
EFI_STATUS Status;
EFI_PHYSICAL_ADDRESS PhyAddr;
EFI_PCI_IO_PROTOCOL_OPERATION MapOp;
EFI_PCI_IO_PROTOCOL *PciIo;
UINTN Len;
VOID *Map;
EFI_STATUS Status;
EFI_PHYSICAL_ADDRESS PhyAddr;
EFI_PCI_IO_PROTOCOL_OPERATION MapOp;
EFI_PCI_IO_PROTOCOL *PciIo;
UINTN Len;
VOID *Map;
PciIo = Ehc->PciIo;
Len = Urb->DataLen;
@@ -931,15 +918,14 @@ EhcFlushAsyncIntMap (
goto ON_ERROR;
}
Urb->DataPhy = (VOID *) ((UINTN) PhyAddr);
Urb->DataMap = Map;
Urb->DataPhy = (VOID *)((UINTN)PhyAddr);
Urb->DataMap = Map;
return EFI_SUCCESS;
ON_ERROR:
return EFI_DEVICE_ERROR;
}
/**
Update the queue head for next round of asynchronous transfer.
@@ -949,17 +935,17 @@ ON_ERROR:
**/
VOID
EhcUpdateAsyncRequest (
IN USB2_HC_DEV *Ehc,
IN URB *Urb
IN USB2_HC_DEV *Ehc,
IN URB *Urb
)
{
LIST_ENTRY *Entry;
EHC_QTD *FirstQtd;
QH_HW *QhHw;
EHC_QTD *Qtd;
QTD_HW *QtdHw;
UINTN Index;
EFI_PHYSICAL_ADDRESS PciAddr;
LIST_ENTRY *Entry;
EHC_QTD *FirstQtd;
QH_HW *QhHw;
EHC_QTD *Qtd;
QTD_HW *QtdHw;
UINTN Index;
EFI_PHYSICAL_ADDRESS PciAddr;
Qtd = NULL;
@@ -985,13 +971,13 @@ EhcUpdateAsyncRequest (
QtdHw->Status = QTD_STAT_ACTIVE;
QtdHw->ErrCnt = QTD_MAX_ERR;
QtdHw->CurPage = 0;
QtdHw->TotalBytes = (UINT32) Qtd->DataLen;
QtdHw->TotalBytes = (UINT32)Qtd->DataLen;
//
// calculate physical address by offset.
//
PciAddr = (UINTN)Urb->DataPhy + ((UINTN)Qtd->Data - (UINTN)Urb->Data);
QtdHw->Page[0] = EHC_LOW_32BIT (PciAddr);
QtdHw->PageHigh[0]= EHC_HIGH_32BIT (PciAddr);
PciAddr = (UINTN)Urb->DataPhy + ((UINTN)Qtd->Data - (UINTN)Urb->Data);
QtdHw->Page[0] = EHC_LOW_32BIT (PciAddr);
QtdHw->PageHigh[0] = EHC_HIGH_32BIT (PciAddr);
}
//
@@ -1000,30 +986,29 @@ EhcUpdateAsyncRequest (
// zero out the overlay area and set NextQtd to the first
// QTD. DateToggle bit is left untouched.
//
QhHw = &Urb->Qh->QhHw;
QhHw->CurQtd = QTD_LINK (0, TRUE);
QhHw->AltQtd = 0;
QhHw = &Urb->Qh->QhHw;
QhHw->CurQtd = QTD_LINK (0, TRUE);
QhHw->AltQtd = 0;
QhHw->Status = 0;
QhHw->Pid = 0;
QhHw->ErrCnt = 0;
QhHw->CurPage = 0;
QhHw->Ioc = 0;
QhHw->TotalBytes = 0;
QhHw->Status = 0;
QhHw->Pid = 0;
QhHw->ErrCnt = 0;
QhHw->CurPage = 0;
QhHw->Ioc = 0;
QhHw->TotalBytes = 0;
for (Index = 0; Index < 5; Index++) {
QhHw->Page[Index] = 0;
QhHw->PageHigh[Index] = 0;
}
PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, FirstQtd, sizeof (EHC_QTD));
PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, FirstQtd, sizeof (EHC_QTD));
QhHw->NextQtd = QTD_LINK (PciAddr, FALSE);
}
return ;
return;
}
/**
Interrupt transfer periodic check handler.
@@ -1034,21 +1019,21 @@ EhcUpdateAsyncRequest (
VOID
EFIAPI
EhcMonitorAsyncRequests (
IN EFI_EVENT Event,
IN VOID *Context
IN EFI_EVENT Event,
IN VOID *Context
)
{
USB2_HC_DEV *Ehc;
EFI_TPL OldTpl;
LIST_ENTRY *Entry;
LIST_ENTRY *Next;
BOOLEAN Finished;
UINT8 *ProcBuf;
URB *Urb;
EFI_STATUS Status;
USB2_HC_DEV *Ehc;
EFI_TPL OldTpl;
LIST_ENTRY *Entry;
LIST_ENTRY *Next;
BOOLEAN Finished;
UINT8 *ProcBuf;
URB *Urb;
EFI_STATUS Status;
OldTpl = gBS->RaiseTPL (EHC_TPL);
Ehc = (USB2_HC_DEV *) Context;
OldTpl = gBS->RaiseTPL (EHC_TPL);
Ehc = (USB2_HC_DEV *)Context;
BASE_LIST_FOR_EACH_SAFE (Entry, Next, &Ehc->AsyncIntTransfers) {
Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);
@@ -1113,7 +1098,7 @@ EhcMonitorAsyncRequests (
// his callback. Some drivers may has a lower TPL restriction.
//
gBS->RestoreTPL (OldTpl);
(Urb->Callback) (ProcBuf, Urb->Completed, Urb->Context, Urb->Result);
(Urb->Callback)(ProcBuf, Urb->Completed, Urb->Context, Urb->Result);
OldTpl = gBS->RaiseTPL (EHC_TPL);
}

72
MdeModulePkg/Bus/Pci/EhciDxe/EhciSched.h
View File

@@ -10,7 +10,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#ifndef _EFI_EHCI_SCHED_H_
#define _EFI_EHCI_SCHED_H_
/**
Initialize the schedule data structure such as frame list.
@@ -22,10 +21,9 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
EFI_STATUS
EhcInitSched (
IN USB2_HC_DEV *Ehc
IN USB2_HC_DEV *Ehc
);
/**
Free the schedule data. It may be partially initialized.
@@ -34,10 +32,9 @@ EhcInitSched (
**/
VOID
EhcFreeSched (
IN USB2_HC_DEV *Ehc
IN USB2_HC_DEV *Ehc
);
/**
Link the queue head to the asynchronous schedule list.
UEFI only supports one CTRL/BULK transfer at a time
@@ -51,11 +48,10 @@ EhcFreeSched (
**/
VOID
EhcLinkQhToAsync (
IN USB2_HC_DEV *Ehc,
IN EHC_QH *Qh
IN USB2_HC_DEV *Ehc,
IN EHC_QH *Qh
);
/**
Unlink a queue head from the asynchronous schedule list.
Need to synchronize with hardware.
@@ -66,11 +62,10 @@ EhcLinkQhToAsync (
**/
VOID
EhcUnlinkQhFromAsync (
IN USB2_HC_DEV *Ehc,
IN EHC_QH *Qh
IN USB2_HC_DEV *Ehc,
IN EHC_QH *Qh
);
/**
Link a queue head for interrupt transfer to the periodic
schedule frame list. This code is very much the same as
@@ -82,11 +77,10 @@ EhcUnlinkQhFromAsync (
**/
VOID
EhcLinkQhToPeriod (
IN USB2_HC_DEV *Ehc,
IN EHC_QH *Qh
IN USB2_HC_DEV *Ehc,
IN EHC_QH *Qh
);
/**
Unlink an interrupt queue head from the periodic
schedule frame list.
@@ -97,12 +91,10 @@ EhcLinkQhToPeriod (
**/
VOID
EhcUnlinkQhFromPeriod (
IN USB2_HC_DEV *Ehc,
IN EHC_QH *Qh
IN USB2_HC_DEV *Ehc,
IN EHC_QH *Qh
);
/**
Execute the transfer by polling the URB. This is a synchronous operation.
@@ -117,12 +109,11 @@ EhcUnlinkQhFromPeriod (
**/
EFI_STATUS
EhcExecTransfer (
IN USB2_HC_DEV *Ehc,
IN URB *Urb,
IN UINTN TimeOut
IN USB2_HC_DEV *Ehc,
IN URB *Urb,
IN UINTN TimeOut
);
/**
Delete a single asynchronous interrupt transfer for
the device and endpoint.
@@ -138,13 +129,12 @@ EhcExecTransfer (
**/
EFI_STATUS
EhciDelAsyncIntTransfer (
IN USB2_HC_DEV *Ehc,
IN UINT8 DevAddr,
IN UINT8 EpNum,
OUT UINT8 *DataToggle
IN USB2_HC_DEV *Ehc,
IN UINT8 DevAddr,
IN UINT8 EpNum,
OUT UINT8 *DataToggle
);
/**
Remove all the asynchronous interrutp transfers.
@@ -153,7 +143,7 @@ EhciDelAsyncIntTransfer (
**/
VOID
EhciDelAllAsyncIntTransfers (
IN USB2_HC_DEV *Ehc
IN USB2_HC_DEV *Ehc
);
/**
@@ -177,17 +167,17 @@ EhciDelAllAsyncIntTransfers (
**/
URB *
EhciInsertAsyncIntTransfer (
IN USB2_HC_DEV *Ehc,
IN UINT8 DevAddr,
IN UINT8 EpAddr,
IN UINT8 DevSpeed,
IN UINT8 Toggle,
IN UINTN MaxPacket,
IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Hub,
IN UINTN DataLen,
IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
IN VOID *Context,
IN UINTN Interval
IN USB2_HC_DEV *Ehc,
IN UINT8 DevAddr,
IN UINT8 EpAddr,
IN UINT8 DevSpeed,
IN UINT8 Toggle,
IN UINTN MaxPacket,
IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Hub,
IN UINTN DataLen,
IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
IN VOID *Context,
IN UINTN Interval
);
/**
@@ -200,8 +190,8 @@ EhciInsertAsyncIntTransfer (
VOID
EFIAPI
EhcMonitorAsyncRequests (
IN EFI_EVENT Event,
IN VOID *Context
IN EFI_EVENT Event,
IN VOID *Context
);
#endif

321
MdeModulePkg/Bus/Pci/EhciDxe/EhciUrb.c
View File

@@ -11,7 +11,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include "Ehci.h"
/**
Create a single QTD to hold the data.
@@ -28,20 +27,20 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
EHC_QTD *
EhcCreateQtd (
IN USB2_HC_DEV *Ehc,
IN UINT8 *Data,
IN UINT8 *DataPhy,
IN UINTN DataLen,
IN UINT8 PktId,
IN UINT8 Toggle,
IN UINTN MaxPacket
IN USB2_HC_DEV *Ehc,
IN UINT8 *Data,
IN UINT8 *DataPhy,
IN UINTN DataLen,
IN UINT8 PktId,
IN UINT8 Toggle,
IN UINTN MaxPacket
)
{
EHC_QTD *Qtd;
QTD_HW *QtdHw;
UINTN Index;
UINTN Len;
UINTN ThisBufLen;
EHC_QTD *Qtd;
QTD_HW *QtdHw;
UINTN Index;
UINTN Len;
UINTN ThisBufLen;
ASSERT (Ehc != NULL);
@@ -51,9 +50,9 @@ EhcCreateQtd (
return NULL;
}
Qtd->Signature = EHC_QTD_SIG;
Qtd->Data = Data;
Qtd->DataLen = 0;
Qtd->Signature = EHC_QTD_SIG;
Qtd->Data = Data;
Qtd->DataLen = 0;
InitializeListHead (&Qtd->QtdList);
@@ -79,18 +78,18 @@ EhcCreateQtd (
// compute the offset and clear Reserved fields. This is already
// done in the data point.
//
QtdHw->Page[Index] = EHC_LOW_32BIT (DataPhy);
QtdHw->PageHigh[Index] = EHC_HIGH_32BIT (DataPhy);
QtdHw->Page[Index] = EHC_LOW_32BIT (DataPhy);
QtdHw->PageHigh[Index] = EHC_HIGH_32BIT (DataPhy);
ThisBufLen = QTD_BUF_LEN - (EHC_LOW_32BIT (DataPhy) & QTD_BUF_MASK);
ThisBufLen = QTD_BUF_LEN - (EHC_LOW_32BIT (DataPhy) & QTD_BUF_MASK);
if (Len + ThisBufLen >= DataLen) {
Len = DataLen;
break;
}
Len += ThisBufLen;
Data += ThisBufLen;
Len += ThisBufLen;
Data += ThisBufLen;
DataPhy += ThisBufLen;
}
@@ -104,15 +103,13 @@ EhcCreateQtd (
Len = Len - Len % MaxPacket;
}
QtdHw->TotalBytes = (UINT32) Len;
QtdHw->TotalBytes = (UINT32)Len;
Qtd->DataLen = Len;
}
return Qtd;
}
/**
Initialize the queue head for interrupt transfer,
that is, initialize the following three fields:
@@ -126,8 +123,8 @@ EhcCreateQtd (
**/
VOID
EhcInitIntQh (
IN USB_ENDPOINT *Ep,
IN QH_HW *QhHw
IN USB_ENDPOINT *Ep,
IN QH_HW *QhHw
)
{
//
@@ -139,7 +136,7 @@ EhcInitIntQh (
//
if (Ep->DevSpeed == EFI_USB_SPEED_HIGH) {
QhHw->SMask = QH_MICROFRAME_0;
return ;
return;
}
//
@@ -157,8 +154,6 @@ EhcInitIntQh (
QhHw->CMask = QH_MICROFRAME_3 | QH_MICROFRAME_4 | QH_MICROFRAME_5;
}
/**
Allocate and initialize a EHCI queue head.
@@ -170,12 +165,12 @@ EhcInitIntQh (
**/
EHC_QH *
EhcCreateQh (
IN USB2_HC_DEV *Ehci,
IN USB_ENDPOINT *Ep
IN USB2_HC_DEV *Ehci,
IN USB_ENDPOINT *Ep
)
{
EHC_QH *Qh;
QH_HW *QhHw;
EHC_QH *Qh;
QH_HW *QhHw;
Qh = UsbHcAllocateMem (Ehci->MemPool, sizeof (EHC_QH));
@@ -183,68 +178,68 @@ EhcCreateQh (
return NULL;
}
Qh->Signature = EHC_QH_SIG;
Qh->NextQh = NULL;
Qh->Interval = Ep->PollRate;
Qh->Signature = EHC_QH_SIG;
Qh->NextQh = NULL;
Qh->Interval = Ep->PollRate;
InitializeListHead (&Qh->Qtds);
QhHw = &Qh->QhHw;
QhHw->HorizonLink = QH_LINK (NULL, 0, TRUE);
QhHw->DeviceAddr = Ep->DevAddr;
QhHw->Inactive = 0;
QhHw->EpNum = Ep->EpAddr;
QhHw->EpSpeed = Ep->DevSpeed;
QhHw->DtCtrl = 0;
QhHw->ReclaimHead = 0;
QhHw->MaxPacketLen = (UINT32) Ep->MaxPacket;
QhHw->CtrlEp = 0;
QhHw->NakReload = QH_NAK_RELOAD;
QhHw->HubAddr = Ep->HubAddr;
QhHw->PortNum = Ep->HubPort;
QhHw->Multiplier = 1;
QhHw->DataToggle = Ep->Toggle;
QhHw = &Qh->QhHw;
QhHw->HorizonLink = QH_LINK (NULL, 0, TRUE);
QhHw->DeviceAddr = Ep->DevAddr;
QhHw->Inactive = 0;
QhHw->EpNum = Ep->EpAddr;
QhHw->EpSpeed = Ep->DevSpeed;
QhHw->DtCtrl = 0;
QhHw->ReclaimHead = 0;
QhHw->MaxPacketLen = (UINT32)Ep->MaxPacket;
QhHw->CtrlEp = 0;
QhHw->NakReload = QH_NAK_RELOAD;
QhHw->HubAddr = Ep->HubAddr;
QhHw->PortNum = Ep->HubPort;
QhHw->Multiplier = 1;
QhHw->DataToggle = Ep->Toggle;
if (Ep->DevSpeed != EFI_USB_SPEED_HIGH) {
QhHw->Status |= QTD_STAT_DO_SS;
}
switch (Ep->Type) {
case EHC_CTRL_TRANSFER:
//
// Special initialization for the control transfer:
// 1. Control transfer initialize data toggle from each QTD
// 2. Set the Control Endpoint Flag (C) for low/full speed endpoint.
//
QhHw->DtCtrl = 1;
case EHC_CTRL_TRANSFER:
//
// Special initialization for the control transfer:
// 1. Control transfer initialize data toggle from each QTD
// 2. Set the Control Endpoint Flag (C) for low/full speed endpoint.
//
QhHw->DtCtrl = 1;
if (Ep->DevSpeed != EFI_USB_SPEED_HIGH) {
QhHw->CtrlEp = 1;
}
break;
if (Ep->DevSpeed != EFI_USB_SPEED_HIGH) {
QhHw->CtrlEp = 1;
}
case EHC_INT_TRANSFER_ASYNC:
case EHC_INT_TRANSFER_SYNC:
//
// Special initialization for the interrupt transfer
// to set the S-Mask and C-Mask
//
QhHw->NakReload = 0;
EhcInitIntQh (Ep, QhHw);
break;
break;
case EHC_BULK_TRANSFER:
if ((Ep->DevSpeed == EFI_USB_SPEED_HIGH) && (Ep->Direction == EfiUsbDataOut)) {
QhHw->Status |= QTD_STAT_DO_PING;
}
case EHC_INT_TRANSFER_ASYNC:
case EHC_INT_TRANSFER_SYNC:
//
// Special initialization for the interrupt transfer
// to set the S-Mask and C-Mask
//
QhHw->NakReload = 0;
EhcInitIntQh (Ep, QhHw);
break;
break;
case EHC_BULK_TRANSFER:
if ((Ep->DevSpeed == EFI_USB_SPEED_HIGH) && (Ep->Direction == EfiUsbDataOut)) {
QhHw->Status |= QTD_STAT_DO_PING;
}
break;
}
return Qh;
}
/**
Convert the poll interval from application to that
be used by EHCI interface data structure. Only need
@@ -260,10 +255,10 @@ EhcCreateQh (
**/
UINTN
EhcConvertPollRate (
IN UINTN Interval
IN UINTN Interval
)
{
UINTN BitCount;
UINTN BitCount;
if (Interval == 0) {
return 1;
@@ -282,7 +277,6 @@ EhcConvertPollRate (
return (UINTN)1 << (BitCount - 1);
}
/**
Free a list of QTDs.
@@ -292,13 +286,13 @@ EhcConvertPollRate (
**/
VOID
EhcFreeQtds (
IN USB2_HC_DEV *Ehc,
IN LIST_ENTRY *Qtds
IN USB2_HC_DEV *Ehc,
IN LIST_ENTRY *Qtds
)
{
LIST_ENTRY *Entry;
LIST_ENTRY *Next;
EHC_QTD *Qtd;
LIST_ENTRY *Entry;
LIST_ENTRY *Next;
EHC_QTD *Qtd;
BASE_LIST_FOR_EACH_SAFE (Entry, Next, Qtds) {
Qtd = EFI_LIST_CONTAINER (Entry, EHC_QTD, QtdList);
@@ -308,7 +302,6 @@ EhcFreeQtds (
}
}
/**
Free an allocated URB. It is possible for it to be partially inited.
@@ -318,11 +311,11 @@ EhcFreeQtds (
**/
VOID
EhcFreeUrb (
IN USB2_HC_DEV *Ehc,
IN URB *Urb
IN USB2_HC_DEV *Ehc,
IN URB *Urb
)
{
EFI_PCI_IO_PROTOCOL *PciIo;
EFI_PCI_IO_PROTOCOL *PciIo;
PciIo = Ehc->PciIo;
@@ -346,7 +339,6 @@ EhcFreeUrb (
gBS->FreePool (Urb);
}
/**
Create a list of QTDs for the URB.
@@ -359,21 +351,21 @@ EhcFreeUrb (
**/
EFI_STATUS
EhcCreateQtds (
IN USB2_HC_DEV *Ehc,
IN URB *Urb
IN USB2_HC_DEV *Ehc,
IN URB *Urb
)
{
USB_ENDPOINT *Ep;
EHC_QH *Qh;
EHC_QTD *Qtd;
EHC_QTD *StatusQtd;
EHC_QTD *NextQtd;
LIST_ENTRY *Entry;
UINT32 AlterNext;
UINT8 Toggle;
UINTN Len;
UINT8 Pid;
EFI_PHYSICAL_ADDRESS PhyAddr;
USB_ENDPOINT *Ep;
EHC_QH *Qh;
EHC_QTD *Qtd;
EHC_QTD *StatusQtd;
EHC_QTD *NextQtd;
LIST_ENTRY *Entry;
UINT32 AlterNext;
UINT8 Toggle;
UINTN Len;
UINT8 Pid;
EFI_PHYSICAL_ADDRESS PhyAddr;
ASSERT ((Urb != NULL) && (Urb->Qh != NULL));
@@ -389,7 +381,7 @@ EhcCreateQtds (
StatusQtd = NULL;
AlterNext = QTD_LINK (NULL, TRUE);
PhyAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Ehc->ShortReadStop, sizeof (EHC_QTD));
PhyAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Ehc->ShortReadStop, sizeof (EHC_QTD));
if (Ep->Direction == EfiUsbDataIn) {
AlterNext = QTD_LINK (PhyAddr, FALSE);
}
@@ -448,8 +440,8 @@ EhcCreateQtds (
while (Len < Urb->DataLen) {
Qtd = EhcCreateQtd (
Ehc,
(UINT8 *) Urb->Data + Len,
(UINT8 *) Urb->DataPhy + Len,
(UINT8 *)Urb->Data + Len,
(UINT8 *)Urb->DataPhy + Len,
Urb->DataLen - Len,
Pid,
Toggle,
@@ -467,7 +459,7 @@ EhcCreateQtds (
// Switch the Toggle bit if odd number of packets are included in the QTD.
//
if (((Qtd->DataLen + Ep->MaxPacket - 1) / Ep->MaxPacket) % 2) {
Toggle = (UINT8) (1 - Toggle);
Toggle = (UINT8)(1 - Toggle);
}
Len += Qtd->DataLen;
@@ -493,17 +485,17 @@ EhcCreateQtds (
break;
}
NextQtd = EFI_LIST_CONTAINER (Entry->ForwardLink, EHC_QTD, QtdList);
PhyAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, NextQtd, sizeof (EHC_QTD));
Qtd->QtdHw.NextQtd = QTD_LINK (PhyAddr, FALSE);
NextQtd = EFI_LIST_CONTAINER (Entry->ForwardLink, EHC_QTD, QtdList);
PhyAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, NextQtd, sizeof (EHC_QTD));
Qtd->QtdHw.NextQtd = QTD_LINK (PhyAddr, FALSE);
}
//
// Link the QTDs to the queue head
//
NextQtd = EFI_LIST_CONTAINER (Qh->Qtds.ForwardLink, EHC_QTD, QtdList);
PhyAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, NextQtd, sizeof (EHC_QTD));
Qh->QhHw.NextQtd = QTD_LINK (PhyAddr, FALSE);
NextQtd = EFI_LIST_CONTAINER (Qh->Qtds.ForwardLink, EHC_QTD, QtdList);
PhyAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, NextQtd, sizeof (EHC_QTD));
Qh->QhHw.NextQtd = QTD_LINK (PhyAddr, FALSE);
return EFI_SUCCESS;
ON_ERROR:
@@ -511,7 +503,6 @@ ON_ERROR:
return EFI_OUT_OF_RESOURCES;
}
/**
Create a new URB and its associated QTD.
@@ -535,30 +526,30 @@ ON_ERROR:
**/
URB *
EhcCreateUrb (
IN USB2_HC_DEV *Ehc,
IN UINT8 DevAddr,
IN UINT8 EpAddr,
IN UINT8 DevSpeed,
IN UINT8 Toggle,
IN UINTN MaxPacket,
IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Hub,
IN UINTN Type,
IN EFI_USB_DEVICE_REQUEST *Request,
IN VOID *Data,
IN UINTN DataLen,
IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
IN VOID *Context,
IN UINTN Interval
IN USB2_HC_DEV *Ehc,
IN UINT8 DevAddr,
IN UINT8 EpAddr,
IN UINT8 DevSpeed,
IN UINT8 Toggle,
IN UINTN MaxPacket,
IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Hub,
IN UINTN Type,
IN EFI_USB_DEVICE_REQUEST *Request,
IN VOID *Data,
IN UINTN DataLen,
IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
IN VOID *Context,
IN UINTN Interval
)
{
USB_ENDPOINT *Ep;
EFI_PHYSICAL_ADDRESS PhyAddr;
EFI_PCI_IO_PROTOCOL_OPERATION MapOp;
EFI_PCI_IO_PROTOCOL *PciIo;
EFI_STATUS Status;
UINTN Len;
URB *Urb;
VOID *Map;
USB_ENDPOINT *Ep;
EFI_PHYSICAL_ADDRESS PhyAddr;
EFI_PCI_IO_PROTOCOL_OPERATION MapOp;
EFI_PCI_IO_PROTOCOL *PciIo;
EFI_STATUS Status;
UINTN Len;
URB *Urb;
VOID *Map;
Urb = AllocateZeroPool (sizeof (URB));
@@ -566,38 +557,38 @@ EhcCreateUrb (
return NULL;
}
Urb->Signature = EHC_URB_SIG;
Urb->Signature = EHC_URB_SIG;
InitializeListHead (&Urb->UrbList);
Ep = &Urb->Ep;
Ep->DevAddr = DevAddr;
Ep->EpAddr = (UINT8) (EpAddr & 0x0F);
Ep->Direction = (((EpAddr & 0x80) != 0) ? EfiUsbDataIn : EfiUsbDataOut);
Ep->DevSpeed = DevSpeed;
Ep->MaxPacket = MaxPacket;
Ep = &Urb->Ep;
Ep->DevAddr = DevAddr;
Ep->EpAddr = (UINT8)(EpAddr & 0x0F);
Ep->Direction = (((EpAddr & 0x80) != 0) ? EfiUsbDataIn : EfiUsbDataOut);
Ep->DevSpeed = DevSpeed;
Ep->MaxPacket = MaxPacket;
Ep->HubAddr = 0;
Ep->HubPort = 0;
Ep->HubAddr = 0;
Ep->HubPort = 0;
if (DevSpeed != EFI_USB_SPEED_HIGH) {
ASSERT (Hub != NULL);
Ep->HubAddr = Hub->TranslatorHubAddress;
Ep->HubPort = Hub->TranslatorPortNumber;
Ep->HubAddr = Hub->TranslatorHubAddress;
Ep->HubPort = Hub->TranslatorPortNumber;
}
Ep->Toggle = Toggle;
Ep->Type = Type;
Ep->PollRate = EhcConvertPollRate (Interval);
Ep->Toggle = Toggle;
Ep->Type = Type;
Ep->PollRate = EhcConvertPollRate (Interval);
Urb->Request = Request;
Urb->Data = Data;
Urb->DataLen = DataLen;
Urb->Callback = Callback;
Urb->Context = Context;
Urb->Request = Request;
Urb->Data = Data;
Urb->DataLen = DataLen;
Urb->Callback = Callback;
Urb->Context = Context;
PciIo = Ehc->PciIo;
Urb->Qh = EhcCreateQh (Ehc, &Urb->Ep);
PciIo = Ehc->PciIo;
Urb->Qh = EhcCreateQh (Ehc, &Urb->Ep);
if (Urb->Qh == NULL) {
goto ON_ERROR;
@@ -607,20 +598,20 @@ EhcCreateUrb (
// Map the request and user data
//
if (Request != NULL) {
Len = sizeof (EFI_USB_DEVICE_REQUEST);
MapOp = EfiPciIoOperationBusMasterRead;
Status = PciIo->Map (PciIo, MapOp, Request, &Len, &PhyAddr, &Map);
Len = sizeof (EFI_USB_DEVICE_REQUEST);
MapOp = EfiPciIoOperationBusMasterRead;
Status = PciIo->Map (PciIo, MapOp, Request, &Len, &PhyAddr, &Map);
if (EFI_ERROR (Status) || (Len != sizeof (EFI_USB_DEVICE_REQUEST))) {
goto ON_ERROR;
}
Urb->RequestPhy = (VOID *) ((UINTN) PhyAddr);
Urb->RequestPhy = (VOID *)((UINTN)PhyAddr);
Urb->RequestMap = Map;
}
if (Data != NULL) {
Len = DataLen;
Len = DataLen;
if (Ep->Direction == EfiUsbDataIn) {
MapOp = EfiPciIoOperationBusMasterWrite;
@@ -628,14 +619,14 @@ EhcCreateUrb (
MapOp = EfiPciIoOperationBusMasterRead;
}
Status = PciIo->Map (PciIo, MapOp, Data, &Len, &PhyAddr, &Map);
Status = PciIo->Map (PciIo, MapOp, Data, &Len, &PhyAddr, &Map);
if (EFI_ERROR (Status) || (Len != DataLen)) {
goto ON_ERROR;
}
Urb->DataPhy = (VOID *) ((UINTN) PhyAddr);
Urb->DataMap = Map;
Urb->DataPhy = (VOID *)((UINTN)PhyAddr);
Urb->DataMap = Map;
}
Status = EhcCreateQtds (Ehc, Urb);

279
MdeModulePkg/Bus/Pci/EhciDxe/EhciUrb.h
View File

@@ -11,7 +11,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#ifndef _EFI_EHCI_URB_H_
#define _EFI_EHCI_URB_H_
typedef struct _EHC_QTD EHC_QTD;
typedef struct _EHC_QH EHC_QH;
typedef struct _URB URB;
@@ -24,51 +23,51 @@ typedef struct _URB URB;
#define EHC_INT_TRANSFER_SYNC 0x04
#define EHC_INT_TRANSFER_ASYNC 0x08
#define EHC_QTD_SIG SIGNATURE_32 ('U', 'S', 'B', 'T')
#define EHC_QH_SIG SIGNATURE_32 ('U', 'S', 'B', 'H')
#define EHC_URB_SIG SIGNATURE_32 ('U', 'S', 'B', 'R')
#define EHC_QTD_SIG SIGNATURE_32 ('U', 'S', 'B', 'T')
#define EHC_QH_SIG SIGNATURE_32 ('U', 'S', 'B', 'H')
#define EHC_URB_SIG SIGNATURE_32 ('U', 'S', 'B', 'R')
//
// Hardware related bit definitions
//
#define EHC_TYPE_ITD 0x00
#define EHC_TYPE_QH 0x02
#define EHC_TYPE_SITD 0x04
#define EHC_TYPE_FSTN 0x06
#define EHC_TYPE_ITD 0x00
#define EHC_TYPE_QH 0x02
#define EHC_TYPE_SITD 0x04
#define EHC_TYPE_FSTN 0x06
#define QH_NAK_RELOAD 3
#define QH_HSHBW_MULTI 1
#define QH_NAK_RELOAD 3
#define QH_HSHBW_MULTI 1
#define QTD_MAX_ERR 3
#define QTD_PID_OUTPUT 0x00
#define QTD_PID_INPUT 0x01
#define QTD_PID_SETUP 0x02
#define QTD_MAX_ERR 3
#define QTD_PID_OUTPUT 0x00
#define QTD_PID_INPUT 0x01
#define QTD_PID_SETUP 0x02
#define QTD_STAT_DO_OUT 0
#define QTD_STAT_DO_SS 0
#define QTD_STAT_DO_PING 0x01
#define QTD_STAT_DO_CS 0x02
#define QTD_STAT_TRANS_ERR 0x08
#define QTD_STAT_BABBLE_ERR 0x10
#define QTD_STAT_BUFF_ERR 0x20
#define QTD_STAT_HALTED 0x40
#define QTD_STAT_ACTIVE 0x80
#define QTD_STAT_ERR_MASK (QTD_STAT_TRANS_ERR | QTD_STAT_BABBLE_ERR | QTD_STAT_BUFF_ERR)
#define QTD_STAT_DO_OUT 0
#define QTD_STAT_DO_SS 0
#define QTD_STAT_DO_PING 0x01
#define QTD_STAT_DO_CS 0x02
#define QTD_STAT_TRANS_ERR 0x08
#define QTD_STAT_BABBLE_ERR 0x10
#define QTD_STAT_BUFF_ERR 0x20
#define QTD_STAT_HALTED 0x40
#define QTD_STAT_ACTIVE 0x80
#define QTD_STAT_ERR_MASK (QTD_STAT_TRANS_ERR | QTD_STAT_BABBLE_ERR | QTD_STAT_BUFF_ERR)
#define QTD_MAX_BUFFER 4
#define QTD_BUF_LEN 4096
#define QTD_BUF_MASK 0x0FFF
#define QTD_MAX_BUFFER 4
#define QTD_BUF_LEN 4096
#define QTD_BUF_MASK 0x0FFF
#define QH_MICROFRAME_0 0x01
#define QH_MICROFRAME_1 0x02
#define QH_MICROFRAME_2 0x04
#define QH_MICROFRAME_3 0x08
#define QH_MICROFRAME_4 0x10
#define QH_MICROFRAME_5 0x20
#define QH_MICROFRAME_6 0x40
#define QH_MICROFRAME_7 0x80
#define QH_MICROFRAME_0 0x01
#define QH_MICROFRAME_1 0x02
#define QH_MICROFRAME_2 0x04
#define QH_MICROFRAME_3 0x08
#define QH_MICROFRAME_4 0x10
#define QH_MICROFRAME_5 0x20
#define QH_MICROFRAME_6 0x40
#define QH_MICROFRAME_7 0x80
#define USB_ERR_SHORT_PACKET 0x200
#define USB_ERR_SHORT_PACKET 0x200
//
// Fill in the hardware link point: pass in a EHC_QH/QH_HW
@@ -77,7 +76,7 @@ typedef struct _URB URB;
#define QH_LINK(Addr, Type, Term) \
((UINT32) ((EHC_LOW_32BIT (Addr) & 0xFFFFFFE0) | (Type) | ((Term) ? 1 : 0)))
#define QTD_LINK(Addr, Term) QH_LINK((Addr), 0, (Term))
#define QTD_LINK(Addr, Term) QH_LINK((Addr), 0, (Term))
//
// The defination of EHCI hardware used data structure for
@@ -87,77 +86,76 @@ typedef struct _URB URB;
//
#pragma pack(1)
typedef struct {
UINT32 NextQtd;
UINT32 AltNext;
UINT32 NextQtd;
UINT32 AltNext;
UINT32 Status : 8;
UINT32 Pid : 2;
UINT32 ErrCnt : 2;
UINT32 CurPage : 3;
UINT32 Ioc : 1;
UINT32 TotalBytes : 15;
UINT32 DataToggle : 1;
UINT32 Status : 8;
UINT32 Pid : 2;
UINT32 ErrCnt : 2;
UINT32 CurPage : 3;
UINT32 Ioc : 1;
UINT32 TotalBytes : 15;
UINT32 DataToggle : 1;
UINT32 Page[5];
UINT32 PageHigh[5];
UINT32 Page[5];
UINT32 PageHigh[5];
} QTD_HW;
typedef struct {
UINT32 HorizonLink;
UINT32 HorizonLink;
//
// Endpoint capabilities/Characteristics DWord 1 and DWord 2
//
UINT32 DeviceAddr : 7;
UINT32 Inactive : 1;
UINT32 EpNum : 4;
UINT32 EpSpeed : 2;
UINT32 DtCtrl : 1;
UINT32 ReclaimHead : 1;
UINT32 MaxPacketLen : 11;
UINT32 CtrlEp : 1;
UINT32 NakReload : 4;
UINT32 DeviceAddr : 7;
UINT32 Inactive : 1;
UINT32 EpNum : 4;
UINT32 EpSpeed : 2;
UINT32 DtCtrl : 1;
UINT32 ReclaimHead : 1;
UINT32 MaxPacketLen : 11;
UINT32 CtrlEp : 1;
UINT32 NakReload : 4;
UINT32 SMask : 8;
UINT32 CMask : 8;
UINT32 HubAddr : 7;
UINT32 PortNum : 7;
UINT32 Multiplier : 2;
UINT32 SMask : 8;
UINT32 CMask : 8;
UINT32 HubAddr : 7;
UINT32 PortNum : 7;
UINT32 Multiplier : 2;
//
// Transaction execution overlay area
//
UINT32 CurQtd;
UINT32 NextQtd;
UINT32 AltQtd;
UINT32 CurQtd;
UINT32 NextQtd;
UINT32 AltQtd;
UINT32 Status : 8;
UINT32 Pid : 2;
UINT32 ErrCnt : 2;
UINT32 CurPage : 3;
UINT32 Ioc : 1;
UINT32 TotalBytes : 15;
UINT32 DataToggle : 1;
UINT32 Status : 8;
UINT32 Pid : 2;
UINT32 ErrCnt : 2;
UINT32 CurPage : 3;
UINT32 Ioc : 1;
UINT32 TotalBytes : 15;
UINT32 DataToggle : 1;
UINT32 Page[5];
UINT32 PageHigh[5];
UINT32 Page[5];
UINT32 PageHigh[5];
} QH_HW;
#pragma pack()
//
// Endpoint address and its capabilities
//
typedef struct _USB_ENDPOINT {
UINT8 DevAddr;
UINT8 EpAddr; // Endpoint address, no direction encoded in
EFI_USB_DATA_DIRECTION Direction;
UINT8 DevSpeed;
UINTN MaxPacket;
UINT8 HubAddr;
UINT8 HubPort;
UINT8 Toggle; // Data toggle, not used for control transfer
UINTN Type;
UINTN PollRate; // Polling interval used by EHCI
UINT8 DevAddr;
UINT8 EpAddr; // Endpoint address, no direction encoded in
EFI_USB_DATA_DIRECTION Direction;
UINT8 DevSpeed;
UINTN MaxPacket;
UINT8 HubAddr;
UINT8 HubPort;
UINT8 Toggle; // Data toggle, not used for control transfer
UINTN Type;
UINTN PollRate; // Polling interval used by EHCI
} USB_ENDPOINT;
//
@@ -165,11 +163,11 @@ typedef struct _USB_ENDPOINT {
// QTD generated from a URB. Don't add fields before QtdHw.
//
struct _EHC_QTD {
QTD_HW QtdHw;
UINT32 Signature;
LIST_ENTRY QtdList; // The list of QTDs to one end point
UINT8 *Data; // Buffer of the original data
UINTN DataLen; // Original amount of data in this QTD
QTD_HW QtdHw;
UINT32 Signature;
LIST_ENTRY QtdList; // The list of QTDs to one end point
UINT8 *Data; // Buffer of the original data
UINTN DataLen; // Original amount of data in this QTD
};
//
@@ -188,11 +186,11 @@ struct _EHC_QTD {
// as the reclamation header. New transfer is inserted after this QH.
//
struct _EHC_QH {
QH_HW QhHw;
UINT32 Signature;
EHC_QH *NextQh; // The queue head pointed to by horizontal link
LIST_ENTRY Qtds; // The list of QTDs to this queue head
UINTN Interval;
QH_HW QhHw;
UINT32 Signature;
EHC_QH *NextQh; // The queue head pointed to by horizontal link
LIST_ENTRY Qtds; // The list of QTDs to this queue head
UINTN Interval;
};
//
@@ -200,38 +198,36 @@ struct _EHC_QH {
// usb requests.
//
struct _URB {
UINT32 Signature;
LIST_ENTRY UrbList;
UINT32 Signature;
LIST_ENTRY UrbList;
//
// Transaction information
//
USB_ENDPOINT Ep;
EFI_USB_DEVICE_REQUEST *Request; // Control transfer only
VOID *RequestPhy; // Address of the mapped request
VOID *RequestMap;
VOID *Data;
UINTN DataLen;
VOID *DataPhy; // Address of the mapped user data
VOID *DataMap;
EFI_ASYNC_USB_TRANSFER_CALLBACK Callback;
VOID *Context;
USB_ENDPOINT Ep;
EFI_USB_DEVICE_REQUEST *Request; // Control transfer only
VOID *RequestPhy; // Address of the mapped request
VOID *RequestMap;
VOID *Data;
UINTN DataLen;
VOID *DataPhy; // Address of the mapped user data
VOID *DataMap;
EFI_ASYNC_USB_TRANSFER_CALLBACK Callback;
VOID *Context;
//
// Schedule data
//
EHC_QH *Qh;
EHC_QH *Qh;
//
// Transaction result
//
UINT32 Result;
UINTN Completed; // completed data length
UINT8 DataToggle;
UINT32 Result;
UINTN Completed; // completed data length
UINT8 DataToggle;
};
/**
Create a single QTD to hold the data.
@@ -248,17 +244,15 @@ struct _URB {
**/
EHC_QTD *
EhcCreateQtd (
IN USB2_HC_DEV *Ehc,
IN UINT8 *Data,
IN UINT8 *DataPhy,
IN UINTN DataLen,
IN UINT8 PktId,
IN UINT8 Toggle,
IN UINTN MaxPacket
IN USB2_HC_DEV *Ehc,
IN UINT8 *Data,
IN UINT8 *DataPhy,
IN UINTN DataLen,
IN UINT8 PktId,
IN UINT8 Toggle,
IN UINTN MaxPacket
);
/**
Allocate and initialize a EHCI queue head.
@@ -270,11 +264,10 @@ EhcCreateQtd (
**/
EHC_QH *
EhcCreateQh (
IN USB2_HC_DEV *Ehci,
IN USB_ENDPOINT *Ep
IN USB2_HC_DEV *Ehci,
IN USB_ENDPOINT *Ep
);
/**
Free an allocated URB. It is possible for it to be partially inited.
@@ -284,11 +277,10 @@ EhcCreateQh (
**/
VOID
EhcFreeUrb (
IN USB2_HC_DEV *Ehc,
IN URB *Urb
IN USB2_HC_DEV *Ehc,
IN URB *Urb
);
/**
Create a new URB and its associated QTD.
@@ -312,19 +304,20 @@ EhcFreeUrb (
**/
URB *
EhcCreateUrb (
IN USB2_HC_DEV *Ehc,
IN UINT8 DevAddr,
IN UINT8 EpAddr,
IN UINT8 DevSpeed,
IN UINT8 Toggle,
IN UINTN MaxPacket,
IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Hub,
IN UINTN Type,
IN EFI_USB_DEVICE_REQUEST *Request,
IN VOID *Data,
IN UINTN DataLen,
IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
IN VOID *Context,
IN UINTN Interval
IN USB2_HC_DEV *Ehc,
IN UINT8 DevAddr,
IN UINT8 EpAddr,
IN UINT8 DevSpeed,
IN UINT8 Toggle,
IN UINTN MaxPacket,
IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Hub,
IN UINTN Type,
IN EFI_USB_DEVICE_REQUEST *Request,
IN VOID *Data,
IN UINTN DataLen,
IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
IN VOID *Context,
IN UINTN Interval
);
#endif

172
MdeModulePkg/Bus/Pci/EhciDxe/UsbHcMem.c
View File

@@ -7,10 +7,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include "Ehci.h"
/**
Allocate a block of memory to be used by the buffer pool.
@@ -22,17 +20,17 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
USBHC_MEM_BLOCK *
UsbHcAllocMemBlock (
IN USBHC_MEM_POOL *Pool,
IN UINTN Pages
IN USBHC_MEM_POOL *Pool,
IN UINTN Pages
)
{
USBHC_MEM_BLOCK *Block;
EFI_PCI_IO_PROTOCOL *PciIo;
VOID *BufHost;
VOID *Mapping;
EFI_PHYSICAL_ADDRESS MappedAddr;
UINTN Bytes;
EFI_STATUS Status;
USBHC_MEM_BLOCK *Block;
EFI_PCI_IO_PROTOCOL *PciIo;
VOID *BufHost;
VOID *Mapping;
EFI_PHYSICAL_ADDRESS MappedAddr;
UINTN Bytes;
EFI_STATUS Status;
PciIo = Pool->PciIo;
@@ -47,9 +45,9 @@ UsbHcAllocMemBlock (
//
ASSERT (USBHC_MEM_UNIT * 8 <= EFI_PAGE_SIZE);
Block->BufLen = EFI_PAGES_TO_SIZE (Pages);
Block->BitsLen = Block->BufLen / (USBHC_MEM_UNIT * 8);
Block->Bits = AllocateZeroPool (Block->BitsLen);
Block->BufLen = EFI_PAGES_TO_SIZE (Pages);
Block->BitsLen = Block->BufLen / (USBHC_MEM_UNIT * 8);
Block->Bits = AllocateZeroPool (Block->BitsLen);
if (Block->Bits == NULL) {
gBS->FreePool (Block);
@@ -73,7 +71,7 @@ UsbHcAllocMemBlock (
goto FREE_BITARRAY;
}
Bytes = EFI_PAGES_TO_SIZE (Pages);
Bytes = EFI_PAGES_TO_SIZE (Pages);
Status = PciIo->Map (
PciIo,
EfiPciIoOperationBusMasterCommonBuffer,
@@ -96,9 +94,9 @@ UsbHcAllocMemBlock (
goto FREE_BUFFER;
}
Block->BufHost = BufHost;
Block->Buf = (UINT8 *) ((UINTN) MappedAddr);
Block->Mapping = Mapping;
Block->BufHost = BufHost;
Block->Buf = (UINT8 *)((UINTN)MappedAddr);
Block->Mapping = Mapping;
return Block;
@@ -111,7 +109,6 @@ FREE_BITARRAY:
return NULL;
}
/**
Free the memory block from the memory pool.
@@ -121,11 +118,11 @@ FREE_BITARRAY:
**/
VOID
UsbHcFreeMemBlock (
IN USBHC_MEM_POOL *Pool,
IN USBHC_MEM_BLOCK *Block
IN USBHC_MEM_POOL *Pool,
IN USBHC_MEM_BLOCK *Block
)
{
EFI_PCI_IO_PROTOCOL *PciIo;
EFI_PCI_IO_PROTOCOL *PciIo;
ASSERT ((Pool != NULL) && (Block != NULL));
@@ -141,7 +138,6 @@ UsbHcFreeMemBlock (
gBS->FreePool (Block);
}
/**
Alloc some memory from the block.
@@ -154,22 +150,22 @@ UsbHcFreeMemBlock (
**/
VOID *
UsbHcAllocMemFromBlock (
IN USBHC_MEM_BLOCK *Block,
IN UINTN Units
IN USBHC_MEM_BLOCK *Block,
IN UINTN Units
)
{
UINTN Byte;
UINT8 Bit;
UINTN StartByte;
UINT8 StartBit;
UINTN Available;
UINTN Count;
UINTN Byte;
UINT8 Bit;
UINTN StartByte;
UINT8 StartBit;
UINTN Available;
UINTN Count;
ASSERT ((Block != 0) && (Units != 0));
StartByte = 0;
StartBit = 0;
Available = 0;
StartByte = 0;
StartBit = 0;
Available = 0;
for (Byte = 0, Bit = 0; Byte < Block->BitsLen;) {
//
@@ -185,13 +181,12 @@ UsbHcAllocMemFromBlock (
}
NEXT_BIT (Byte, Bit);
} else {
NEXT_BIT (Byte, Bit);
Available = 0;
StartByte = Byte;
StartBit = Bit;
Available = 0;
StartByte = Byte;
StartBit = Bit;
}
}
@@ -202,13 +197,13 @@ UsbHcAllocMemFromBlock (
//
// Mark the memory as allocated
//
Byte = StartByte;
Bit = StartBit;
Byte = StartByte;
Bit = StartBit;
for (Count = 0; Count < Units; Count++) {
ASSERT (!USB_HC_BIT_IS_SET (Block->Bits[Byte], Bit));
Block->Bits[Byte] = (UINT8) (Block->Bits[Byte] | USB_HC_BIT (Bit));
Block->Bits[Byte] = (UINT8)(Block->Bits[Byte] | USB_HC_BIT (Bit));
NEXT_BIT (Byte, Bit);
}
@@ -226,16 +221,16 @@ UsbHcAllocMemFromBlock (
**/
EFI_PHYSICAL_ADDRESS
UsbHcGetPciAddressForHostMem (
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
)
{
USBHC_MEM_BLOCK *Head;
USBHC_MEM_BLOCK *Block;
UINTN AllocSize;
EFI_PHYSICAL_ADDRESS PhyAddr;
UINTN Offset;
USBHC_MEM_BLOCK *Head;
USBHC_MEM_BLOCK *Block;
UINTN AllocSize;
EFI_PHYSICAL_ADDRESS PhyAddr;
UINTN Offset;
Head = Pool->Head;
AllocSize = USBHC_MEM_ROUND (Size);
@@ -249,7 +244,7 @@ UsbHcGetPciAddressForHostMem (
// scan the memory block list for the memory block that
// completely contains the allocated memory.
//
if ((Block->BufHost <= (UINT8 *) Mem) && (((UINT8 *) Mem + AllocSize) <= (Block->BufHost + Block->BufLen))) {
if ((Block->BufHost <= (UINT8 *)Mem) && (((UINT8 *)Mem + AllocSize) <= (Block->BufHost + Block->BufLen))) {
break;
}
}
@@ -258,12 +253,11 @@ UsbHcGetPciAddressForHostMem (
//
// calculate the pci memory address for host memory address.
//
Offset = (UINT8 *)Mem - Block->BufHost;
PhyAddr = (EFI_PHYSICAL_ADDRESS)(UINTN) (Block->Buf + Offset);
Offset = (UINT8 *)Mem - Block->BufHost;
PhyAddr = (EFI_PHYSICAL_ADDRESS)(UINTN)(Block->Buf + Offset);
return PhyAddr;
}
/**
Insert the memory block to the pool's list of the blocks.
@@ -273,8 +267,8 @@ UsbHcGetPciAddressForHostMem (
**/
VOID
UsbHcInsertMemBlockToPool (
IN USBHC_MEM_BLOCK *Head,
IN USBHC_MEM_BLOCK *Block
IN USBHC_MEM_BLOCK *Head,
IN USBHC_MEM_BLOCK *Block
)
{
ASSERT ((Head != NULL) && (Block != NULL));
@@ -282,7 +276,6 @@ UsbHcInsertMemBlockToPool (
Head->Next = Block;
}
/**
Is the memory block empty?
@@ -294,10 +287,10 @@ UsbHcInsertMemBlockToPool (
**/
BOOLEAN
UsbHcIsMemBlockEmpty (
IN USBHC_MEM_BLOCK *Block
IN USBHC_MEM_BLOCK *Block
)
{
UINTN Index;
UINTN Index;
for (Index = 0; Index < Block->BitsLen; Index++) {
if (Block->Bits[Index] != 0) {
@@ -308,7 +301,6 @@ UsbHcIsMemBlockEmpty (
return TRUE;
}
/**
Unlink the memory block from the pool's list.
@@ -318,11 +310,11 @@ UsbHcIsMemBlockEmpty (
**/
VOID
UsbHcUnlinkMemBlock (
IN USBHC_MEM_BLOCK *Head,
IN USBHC_MEM_BLOCK *BlockToUnlink
IN USBHC_MEM_BLOCK *Head,
IN USBHC_MEM_BLOCK *BlockToUnlink
)
{
USBHC_MEM_BLOCK *Block;
USBHC_MEM_BLOCK *Block;
ASSERT ((Head != NULL) && (BlockToUnlink != NULL));
@@ -335,7 +327,6 @@ UsbHcUnlinkMemBlock (
}
}
/**
Initialize the memory management pool for the host controller.
@@ -355,7 +346,7 @@ UsbHcInitMemPool (
IN UINT32 Which4G
)
{
USBHC_MEM_POOL *Pool;
USBHC_MEM_POOL *Pool;
Pool = AllocatePool (sizeof (USBHC_MEM_POOL));
@@ -376,7 +367,6 @@ UsbHcInitMemPool (
return Pool;
}
/**
Release the memory management pool.
@@ -388,10 +378,10 @@ UsbHcInitMemPool (
**/
EFI_STATUS
UsbHcFreeMemPool (
IN USBHC_MEM_POOL *Pool
IN USBHC_MEM_POOL *Pool
)
{
USBHC_MEM_BLOCK *Block;
USBHC_MEM_BLOCK *Block;
ASSERT (Pool->Head != NULL);
@@ -410,7 +400,6 @@ UsbHcFreeMemPool (
return EFI_SUCCESS;
}
/**
Allocate some memory from the host controller's memory pool
which can be used to communicate with host controller.
@@ -423,16 +412,16 @@ UsbHcFreeMemPool (
**/
VOID *
UsbHcAllocateMem (
IN USBHC_MEM_POOL *Pool,
IN UINTN Size
IN USBHC_MEM_POOL *Pool,
IN UINTN Size
)
{
USBHC_MEM_BLOCK *Head;
USBHC_MEM_BLOCK *Block;
USBHC_MEM_BLOCK *NewBlock;
VOID *Mem;
UINTN AllocSize;
UINTN Pages;
USBHC_MEM_BLOCK *Head;
USBHC_MEM_BLOCK *Block;
USBHC_MEM_BLOCK *NewBlock;
VOID *Mem;
UINTN AllocSize;
UINTN Pages;
Mem = NULL;
AllocSize = USBHC_MEM_ROUND (Size);
@@ -487,7 +476,6 @@ UsbHcAllocateMem (
return Mem;
}
/**
Free the allocated memory back to the memory pool.
@@ -498,22 +486,22 @@ UsbHcAllocateMem (
**/
VOID
UsbHcFreeMem (
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
)
{
USBHC_MEM_BLOCK *Head;
USBHC_MEM_BLOCK *Block;
UINT8 *ToFree;
UINTN AllocSize;
UINTN Byte;
UINTN Bit;
UINTN Count;
USBHC_MEM_BLOCK *Head;
USBHC_MEM_BLOCK *Block;
UINT8 *ToFree;
UINTN AllocSize;
UINTN Byte;
UINTN Bit;
UINTN Count;
Head = Pool->Head;
AllocSize = USBHC_MEM_ROUND (Size);
ToFree = (UINT8 *) Mem;
ToFree = (UINT8 *)Mem;
for (Block = Head; Block != NULL; Block = Block->Next) {
//
@@ -524,8 +512,8 @@ UsbHcFreeMem (
//
// compute the start byte and bit in the bit array
//
Byte = ((ToFree - Block->BufHost) / USBHC_MEM_UNIT) / 8;
Bit = ((ToFree - Block->BufHost) / USBHC_MEM_UNIT) % 8;
Byte = ((ToFree - Block->BufHost) / USBHC_MEM_UNIT) / 8;
Bit = ((ToFree - Block->BufHost) / USBHC_MEM_UNIT) % 8;
//
// reset associated bits in bit array
@@ -533,7 +521,7 @@ UsbHcFreeMem (
for (Count = 0; Count < (AllocSize / USBHC_MEM_UNIT); Count++) {
ASSERT (USB_HC_BIT_IS_SET (Block->Bits[Byte], Bit));
Block->Bits[Byte] = (UINT8) (Block->Bits[Byte] ^ USB_HC_BIT (Bit));
Block->Bits[Byte] = (UINT8)(Block->Bits[Byte] ^ USB_HC_BIT (Bit));
NEXT_BIT (Byte, Bit);
}
@@ -556,5 +544,5 @@ UsbHcFreeMem (
UsbHcFreeMemBlock (Pool, Block);
}
return ;
return;
}

49
MdeModulePkg/Bus/Pci/EhciDxe/UsbHcMem.h
View File

@@ -10,7 +10,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#ifndef _EFI_EHCI_MEM_H_
#define _EFI_EHCI_MEM_H_
#define USB_HC_BIT(a) ((UINTN)(1 << (a)))
#define USB_HC_BIT(a) ((UINTN)(1 << (a)))
#define USB_HC_BIT_IS_SET(Data, Bit) \
((BOOLEAN)(((Data) & USB_HC_BIT(Bit)) == USB_HC_BIT(Bit)))
@@ -20,13 +20,13 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
typedef struct _USBHC_MEM_BLOCK USBHC_MEM_BLOCK;
struct _USBHC_MEM_BLOCK {
UINT8 *Bits; // Bit array to record which unit is allocated
UINTN BitsLen;
UINT8 *Buf;
UINT8 *BufHost;
UINTN BufLen; // Memory size in bytes
VOID *Mapping;
USBHC_MEM_BLOCK *Next;
UINT8 *Bits; // Bit array to record which unit is allocated
UINTN BitsLen;
UINT8 *Buf;
UINT8 *BufHost;
UINTN BufLen; // Memory size in bytes
VOID *Mapping;
USBHC_MEM_BLOCK *Next;
};
//
@@ -35,16 +35,16 @@ struct _USBHC_MEM_BLOCK {
// data to be on the same 4G memory.
//
typedef struct _USBHC_MEM_POOL {
EFI_PCI_IO_PROTOCOL *PciIo;
BOOLEAN Check4G;
UINT32 Which4G;
USBHC_MEM_BLOCK *Head;
EFI_PCI_IO_PROTOCOL *PciIo;
BOOLEAN Check4G;
UINT32 Which4G;
USBHC_MEM_BLOCK *Head;
} USBHC_MEM_POOL;
//
// Memory allocation unit, must be 2^n, n>4
//
#define USBHC_MEM_UNIT 64
#define USBHC_MEM_UNIT 64
#define USBHC_MEM_UNIT_MASK (USBHC_MEM_UNIT - 1)
#define USBHC_MEM_DEFAULT_PAGES 16
@@ -63,8 +63,6 @@ typedef struct _USBHC_MEM_POOL {
} \
} while (0)
/**
Initialize the memory management pool for the host controller.
@@ -84,7 +82,6 @@ UsbHcInitMemPool (
IN UINT32 Which4G
);
/**
Release the memory management pool.
@@ -96,10 +93,9 @@ UsbHcInitMemPool (
**/
EFI_STATUS
UsbHcFreeMemPool (
IN USBHC_MEM_POOL *Pool
IN USBHC_MEM_POOL *Pool
);
/**
Allocate some memory from the host controller's memory pool
which can be used to communicate with host controller.
@@ -112,11 +108,10 @@ UsbHcFreeMemPool (
**/
VOID *
UsbHcAllocateMem (
IN USBHC_MEM_POOL *Pool,
IN UINTN Size
IN USBHC_MEM_POOL *Pool,
IN UINTN Size
);
/**
Free the allocated memory back to the memory pool.
@@ -127,9 +122,9 @@ UsbHcAllocateMem (
**/
VOID
UsbHcFreeMem (
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
);
/**
@@ -143,9 +138,9 @@ UsbHcFreeMem (
**/
EFI_PHYSICAL_ADDRESS
UsbHcGetPciAddressForHostMem (
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
);
#endif