sravan/system76-edk2
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

MdeModulePkg: Apply uncrustify changes

Browse Source 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737

Apply uncrustify changes to .c/.h files in the MdeModulePkg package

Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
This commit is contained in:
Michael Kubacki
2021-12-05 14:54:02 -08:00
committed by mergify[bot]
parent 7c7184e201
commit 1436aea4d5
994 changed files with 107608 additions and 101311 deletions
Download Patch File Download Diff File Expand all files Collapse all files

153
MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.h
View File

@@ -14,20 +14,19 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
// EHCI register offset
//
//
// Capability register offset
//
#define EHC_CAPLENGTH_OFFSET 0 // Capability register length offset
#define EHC_HCSPARAMS_OFFSET 0x04 // Structural Parameters 04-07h
#define EHC_HCCPARAMS_OFFSET 0x08 // Capability parameters offset
#define EHC_CAPLENGTH_OFFSET 0 // Capability register length offset
#define EHC_HCSPARAMS_OFFSET 0x04 // Structural Parameters 04-07h
#define EHC_HCCPARAMS_OFFSET 0x08 // Capability parameters offset
//
// Capability register bit definition
//
#define HCSP_NPORTS 0x0F // Number of root hub port
#define HCSP_PPC 0x10 // Port Power Control
#define HCCP_64BIT 0x01 // 64-bit addressing capability
#define HCSP_NPORTS 0x0F // Number of root hub port
#define HCSP_PPC 0x10 // Port Power Control
#define HCCP_64BIT 0x01 // 64-bit addressing capability
//
// Operational register offset
@@ -42,66 +41,66 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#define EHC_CONFIG_FLAG_OFFSET 0x40 // Configure flag register offset
#define EHC_PORT_STAT_OFFSET 0x44 // Port status/control offset
#define EHC_FRAME_LEN 1024
#define EHC_FRAME_LEN 1024
//
// Register bit definition
//
#define CONFIGFLAG_ROUTE_EHC 0x01 // Route port to EHC
#define CONFIGFLAG_ROUTE_EHC 0x01 // Route port to EHC
#define USBCMD_RUN 0x01 // Run/stop
#define USBCMD_RESET 0x02 // Start the host controller reset
#define USBCMD_ENABLE_PERIOD 0x10 // Enable periodic schedule
#define USBCMD_ENABLE_ASYNC 0x20 // Enable asynchronous schedule
#define USBCMD_IAAD 0x40 // Interrupt on async advance doorbell
#define USBCMD_RUN 0x01 // Run/stop
#define USBCMD_RESET 0x02 // Start the host controller reset
#define USBCMD_ENABLE_PERIOD 0x10 // Enable periodic schedule
#define USBCMD_ENABLE_ASYNC 0x20 // Enable asynchronous schedule
#define USBCMD_IAAD 0x40 // Interrupt on async advance doorbell
#define USBSTS_IAA 0x20 // Interrupt on async advance
#define USBSTS_PERIOD_ENABLED 0x4000 // Periodic schedule status
#define USBSTS_ASYNC_ENABLED 0x8000 // Asynchronous schedule status
#define USBSTS_HALT 0x1000 // Host controller halted
#define USBSTS_SYS_ERROR 0x10 // Host system error
#define USBSTS_INTACK_MASK 0x003F // Mask for the interrupt ACK, the WC
#define USBSTS_IAA 0x20 // Interrupt on async advance
#define USBSTS_PERIOD_ENABLED 0x4000 // Periodic schedule status
#define USBSTS_ASYNC_ENABLED 0x8000 // Asynchronous schedule status
#define USBSTS_HALT 0x1000 // Host controller halted
#define USBSTS_SYS_ERROR 0x10 // Host system error
#define USBSTS_INTACK_MASK 0x003F // Mask for the interrupt ACK, the WC
// (write clean) bits in USBSTS register
#define PORTSC_CONN 0x01 // Current Connect Status
#define PORTSC_CONN_CHANGE 0x02 // Connect Status Change
#define PORTSC_ENABLED 0x04 // Port Enable / Disable
#define PORTSC_ENABLE_CHANGE 0x08 // Port Enable / Disable Change
#define PORTSC_OVERCUR 0x10 // Over current Active
#define PORTSC_OVERCUR_CHANGE 0x20 // Over current Change
#define PORSTSC_RESUME 0x40 // Force Port Resume
#define PORTSC_SUSPEND 0x80 // Port Suspend State
#define PORTSC_RESET 0x100 // Port Reset
#define PORTSC_LINESTATE_K 0x400 // Line Status K-state
#define PORTSC_LINESTATE_J 0x800 // Line Status J-state
#define PORTSC_POWER 0x1000 // Port Power
#define PORTSC_OWNER 0x2000 // Port Owner
#define PORTSC_CHANGE_MASK 0x2A // Mask of the port change bits,
#define PORTSC_CONN 0x01 // Current Connect Status
#define PORTSC_CONN_CHANGE 0x02 // Connect Status Change
#define PORTSC_ENABLED 0x04 // Port Enable / Disable
#define PORTSC_ENABLE_CHANGE 0x08 // Port Enable / Disable Change
#define PORTSC_OVERCUR 0x10 // Over current Active
#define PORTSC_OVERCUR_CHANGE 0x20 // Over current Change
#define PORSTSC_RESUME 0x40 // Force Port Resume
#define PORTSC_SUSPEND 0x80 // Port Suspend State
#define PORTSC_RESET 0x100 // Port Reset
#define PORTSC_LINESTATE_K 0x400 // Line Status K-state
#define PORTSC_LINESTATE_J 0x800 // Line Status J-state
#define PORTSC_POWER 0x1000 // Port Power
#define PORTSC_OWNER 0x2000 // Port Owner
#define PORTSC_CHANGE_MASK 0x2A // Mask of the port change bits,
// they are WC (write clean)
//
// PCI Configuration Registers
//
#define EHC_BAR_INDEX 0 // how many bytes away from USB_BASE to 0x10
#define EHC_BAR_INDEX 0 // how many bytes away from USB_BASE to 0x10
//
// Debug port capability id
//
#define EHC_DEBUG_PORT_CAP_ID 0x0A
#define EHC_DEBUG_PORT_CAP_ID 0x0A
#define EHC_LINK_TERMINATED(Link) (((Link) & 0x01) != 0)
#define EHC_LINK_TERMINATED(Link) (((Link) & 0x01) != 0)
#define EHC_ADDR(High, QhHw32) \
((VOID *) (UINTN) (LShiftU64 ((High), 32) | ((QhHw32) & 0xFFFFFFF0)))
#define EHCI_IS_DATAIN(EndpointAddr) EHC_BIT_IS_SET((EndpointAddr), 0x80)
#define EHCI_IS_DATAIN(EndpointAddr) EHC_BIT_IS_SET((EndpointAddr), 0x80)
//
// Structure to map the hardware port states to the
// UEFI's port states.
//
typedef struct {
UINT16 HwState;
UINT16 UefiState;
UINT16 HwState;
UINT16 UefiState;
} USB_PORT_STATE_MAP;
//
@@ -109,9 +108,9 @@ typedef struct {
//
#pragma pack(1)
typedef struct {
UINT8 ProgInterface;
UINT8 SubClassCode;
UINT8 BaseCode;
UINT8 ProgInterface;
UINT8 SubClassCode;
UINT8 BaseCode;
} USB_CLASSC;
#pragma pack()
@@ -126,8 +125,8 @@ typedef struct {
**/
UINT32
EhcReadCapRegister (
IN USB2_HC_DEV *Ehc,
IN UINT32 Offset
IN USB2_HC_DEV *Ehc,
IN UINT32 Offset
);
/**
@@ -151,8 +150,8 @@ EhcReadCapRegister (
**/
BOOLEAN
EhcIsDebugPortInUse (
IN CONST USB2_HC_DEV *Ehc,
IN CONST UINT8 *PortNumber OPTIONAL
IN CONST USB2_HC_DEV *Ehc,
IN CONST UINT8 *PortNumber OPTIONAL
);
/**
@@ -166,11 +165,10 @@ EhcIsDebugPortInUse (
**/
UINT32
EhcReadOpReg (
IN USB2_HC_DEV *Ehc,
IN UINT32 Offset
IN USB2_HC_DEV *Ehc,
IN UINT32 Offset
);
/**
Write the data to the EHCI operation register.
@@ -181,9 +179,9 @@ EhcReadOpReg (
**/
VOID
EhcWriteOpReg (
IN USB2_HC_DEV *Ehc,
IN UINT32 Offset,
IN UINT32 Data
IN USB2_HC_DEV *Ehc,
IN UINT32 Offset,
IN UINT32 Data
);
/**
@@ -196,9 +194,9 @@ EhcWriteOpReg (
**/
VOID
EhcSetOpRegBit (
IN USB2_HC_DEV *Ehc,
IN UINT32 Offset,
IN UINT32 Bit
IN USB2_HC_DEV *Ehc,
IN UINT32 Offset,
IN UINT32 Bit
);
/**
@@ -211,9 +209,9 @@ EhcSetOpRegBit (
**/
VOID
EhcClearOpRegBit (
IN USB2_HC_DEV *Ehc,
IN UINT32 Offset,
IN UINT32 Bit
IN USB2_HC_DEV *Ehc,
IN UINT32 Offset,
IN UINT32 Bit
);
/**
@@ -225,11 +223,9 @@ EhcClearOpRegBit (
**/
VOID
EhcClearLegacySupport (
IN USB2_HC_DEV *Ehc
IN USB2_HC_DEV *Ehc
);
/**
Set door bell and wait it to be ACKed by host controller.
This function is used to synchronize with the hardware.
@@ -243,11 +239,10 @@ EhcClearLegacySupport (
**/
EFI_STATUS
EhcSetAndWaitDoorBell (
IN USB2_HC_DEV *Ehc,
IN UINT32 Timeout
IN USB2_HC_DEV *Ehc,
IN UINT32 Timeout
);
/**
Clear all the interrutp status bits, these bits are Write-Clean.
@@ -256,11 +251,9 @@ EhcSetAndWaitDoorBell (
**/
VOID
EhcAckAllInterrupt (
IN USB2_HC_DEV *Ehc
IN USB2_HC_DEV *Ehc
);
/**
Whether Ehc is halted.
@@ -272,10 +265,9 @@ EhcAckAllInterrupt (
**/
BOOLEAN
EhcIsHalt (
IN USB2_HC_DEV *Ehc
IN USB2_HC_DEV *Ehc
);
/**
Whether system error occurred.
@@ -287,10 +279,9 @@ EhcIsHalt (
**/
BOOLEAN
EhcIsSysError (
IN USB2_HC_DEV *Ehc
IN USB2_HC_DEV *Ehc
);
/**
Reset the host controller.
@@ -303,11 +294,10 @@ EhcIsSysError (
**/
EFI_STATUS
EhcResetHC (
IN USB2_HC_DEV *Ehc,
IN UINT32 Timeout
IN USB2_HC_DEV *Ehc,
IN UINT32 Timeout
);
/**
Halt the host controller.
@@ -320,11 +310,10 @@ EhcResetHC (
**/
EFI_STATUS
EhcHaltHC (
IN USB2_HC_DEV *Ehc,
IN UINT32 Timeout
IN USB2_HC_DEV *Ehc,
IN UINT32 Timeout
);
/**
Set the EHCI to run.
@@ -337,12 +326,10 @@ EhcHaltHC (
**/
EFI_STATUS
EhcRunHC (
IN USB2_HC_DEV *Ehc,
IN UINT32 Timeout
IN USB2_HC_DEV *Ehc,
IN UINT32 Timeout
);
/**
Initialize the HC hardware.
EHCI spec lists the five things to do to initialize the hardware:
@@ -360,7 +347,7 @@ EhcRunHC (
**/
EFI_STATUS
EhcInitHC (
IN USB2_HC_DEV *Ehc
IN USB2_HC_DEV *Ehc
);
#endif