MdeModulePkg: Apply uncrustify changes
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737 Apply uncrustify changes to .c/.h files in the MdeModulePkg package Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
This commit is contained in:
Michael Kubacki
committed by
mergify[bot]
mergify[bot]
parent
7c7184e201
commit
1436aea4d5
@@ -9,13 +9,13 @@
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#include "NvmExpress.h"
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#define NVME_SHUTDOWN_PROCESS_TIMEOUT 45
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#define NVME_SHUTDOWN_PROCESS_TIMEOUT 45
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//
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// The number of NVME controllers managed by this driver, used by
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// NvmeRegisterShutdownNotification() and NvmeUnregisterShutdownNotification().
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//
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UINTN mNvmeControllerNumber = 0;
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UINTN mNvmeControllerNumber = 0;
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/**
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Read Nvm Express controller capability register.
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@@ -29,13 +29,13 @@ UINTN mNvmeControllerNumber = 0;
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**/
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EFI_STATUS
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ReadNvmeControllerCapabilities (
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IN NVME_CONTROLLER_PRIVATE_DATA *Private,
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IN NVME_CAP *Cap
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IN NVME_CONTROLLER_PRIVATE_DATA *Private,
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IN NVME_CAP *Cap
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)
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{
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EFI_PCI_IO_PROTOCOL *PciIo;
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EFI_STATUS Status;
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UINT64 Data;
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EFI_PCI_IO_PROTOCOL *PciIo;
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EFI_STATUS Status;
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UINT64 Data;
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PciIo = Private->PciIo;
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Status = PciIo->Mem.Read (
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@@ -47,11 +47,11 @@ ReadNvmeControllerCapabilities (
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&Data
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);
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if (EFI_ERROR(Status)) {
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if (EFI_ERROR (Status)) {
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return Status;
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}
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WriteUnaligned64 ((UINT64*)Cap, Data);
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WriteUnaligned64 ((UINT64 *)Cap, Data);
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return EFI_SUCCESS;
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}
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@@ -67,13 +67,13 @@ ReadNvmeControllerCapabilities (
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**/
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EFI_STATUS
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ReadNvmeControllerConfiguration (
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IN NVME_CONTROLLER_PRIVATE_DATA *Private,
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IN NVME_CC *Cc
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IN NVME_CONTROLLER_PRIVATE_DATA *Private,
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IN NVME_CC *Cc
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)
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{
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EFI_PCI_IO_PROTOCOL *PciIo;
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EFI_STATUS Status;
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UINT32 Data;
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EFI_PCI_IO_PROTOCOL *PciIo;
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EFI_STATUS Status;
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UINT32 Data;
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PciIo = Private->PciIo;
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Status = PciIo->Mem.Read (
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@@ -85,11 +85,11 @@ ReadNvmeControllerConfiguration (
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&Data
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);
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if (EFI_ERROR(Status)) {
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if (EFI_ERROR (Status)) {
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return Status;
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}
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WriteUnaligned32 ((UINT32*)Cc, Data);
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WriteUnaligned32 ((UINT32 *)Cc, Data);
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return EFI_SUCCESS;
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}
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@@ -105,16 +105,16 @@ ReadNvmeControllerConfiguration (
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**/
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EFI_STATUS
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WriteNvmeControllerConfiguration (
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IN NVME_CONTROLLER_PRIVATE_DATA *Private,
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IN NVME_CC *Cc
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IN NVME_CONTROLLER_PRIVATE_DATA *Private,
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IN NVME_CC *Cc
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)
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{
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EFI_PCI_IO_PROTOCOL *PciIo;
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EFI_STATUS Status;
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UINT32 Data;
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EFI_PCI_IO_PROTOCOL *PciIo;
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EFI_STATUS Status;
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UINT32 Data;
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PciIo = Private->PciIo;
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Data = ReadUnaligned32 ((UINT32*)Cc);
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Data = ReadUnaligned32 ((UINT32 *)Cc);
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Status = PciIo->Mem.Write (
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PciIo,
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EfiPciIoWidthUint32,
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@@ -124,7 +124,7 @@ WriteNvmeControllerConfiguration (
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&Data
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);
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if (EFI_ERROR(Status)) {
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if (EFI_ERROR (Status)) {
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return Status;
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}
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@@ -151,13 +151,13 @@ WriteNvmeControllerConfiguration (
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**/
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EFI_STATUS
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ReadNvmeControllerStatus (
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IN NVME_CONTROLLER_PRIVATE_DATA *Private,
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IN NVME_CSTS *Csts
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IN NVME_CONTROLLER_PRIVATE_DATA *Private,
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IN NVME_CSTS *Csts
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)
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{
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EFI_PCI_IO_PROTOCOL *PciIo;
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EFI_STATUS Status;
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UINT32 Data;
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EFI_PCI_IO_PROTOCOL *PciIo;
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EFI_STATUS Status;
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UINT32 Data;
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PciIo = Private->PciIo;
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Status = PciIo->Mem.Read (
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@@ -169,16 +169,14 @@ ReadNvmeControllerStatus (
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&Data
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);
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if (EFI_ERROR(Status)) {
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if (EFI_ERROR (Status)) {
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return Status;
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}
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WriteUnaligned32 ((UINT32*)Csts, Data);
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WriteUnaligned32 ((UINT32 *)Csts, Data);
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return EFI_SUCCESS;
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}
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/**
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Write Nvm Express admin queue attributes register.
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@@ -191,16 +189,16 @@ ReadNvmeControllerStatus (
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**/
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EFI_STATUS
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WriteNvmeAdminQueueAttributes (
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IN NVME_CONTROLLER_PRIVATE_DATA *Private,
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IN NVME_AQA *Aqa
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IN NVME_CONTROLLER_PRIVATE_DATA *Private,
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IN NVME_AQA *Aqa
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)
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{
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EFI_PCI_IO_PROTOCOL *PciIo;
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EFI_STATUS Status;
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UINT32 Data;
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EFI_PCI_IO_PROTOCOL *PciIo;
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EFI_STATUS Status;
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UINT32 Data;
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PciIo = Private->PciIo;
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Data = ReadUnaligned32 ((UINT32*)Aqa);
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Data = ReadUnaligned32 ((UINT32 *)Aqa);
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Status = PciIo->Mem.Write (
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PciIo,
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EfiPciIoWidthUint32,
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@@ -210,7 +208,7 @@ WriteNvmeAdminQueueAttributes (
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&Data
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);
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if (EFI_ERROR(Status)) {
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if (EFI_ERROR (Status)) {
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return Status;
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}
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@@ -220,7 +218,6 @@ WriteNvmeAdminQueueAttributes (
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return EFI_SUCCESS;
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}
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/**
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Write Nvm Express admin submission queue base address register.
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@@ -233,16 +230,16 @@ WriteNvmeAdminQueueAttributes (
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**/
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EFI_STATUS
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WriteNvmeAdminSubmissionQueueBaseAddress (
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IN NVME_CONTROLLER_PRIVATE_DATA *Private,
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IN NVME_ASQ *Asq
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IN NVME_CONTROLLER_PRIVATE_DATA *Private,
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IN NVME_ASQ *Asq
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)
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{
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EFI_PCI_IO_PROTOCOL *PciIo;
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EFI_STATUS Status;
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UINT64 Data;
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EFI_PCI_IO_PROTOCOL *PciIo;
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EFI_STATUS Status;
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UINT64 Data;
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PciIo = Private->PciIo;
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Data = ReadUnaligned64 ((UINT64*)Asq);
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PciIo = Private->PciIo;
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Data = ReadUnaligned64 ((UINT64 *)Asq);
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Status = PciIo->Mem.Write (
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PciIo,
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@@ -253,7 +250,7 @@ WriteNvmeAdminSubmissionQueueBaseAddress (
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&Data
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);
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if (EFI_ERROR(Status)) {
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if (EFI_ERROR (Status)) {
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return Status;
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}
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@@ -262,8 +259,6 @@ WriteNvmeAdminSubmissionQueueBaseAddress (
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return EFI_SUCCESS;
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}
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/**
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Write Nvm Express admin completion queue base address register.
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@@ -276,16 +271,16 @@ WriteNvmeAdminSubmissionQueueBaseAddress (
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**/
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EFI_STATUS
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WriteNvmeAdminCompletionQueueBaseAddress (
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IN NVME_CONTROLLER_PRIVATE_DATA *Private,
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IN NVME_ACQ *Acq
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IN NVME_CONTROLLER_PRIVATE_DATA *Private,
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IN NVME_ACQ *Acq
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)
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{
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EFI_PCI_IO_PROTOCOL *PciIo;
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EFI_STATUS Status;
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UINT64 Data;
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EFI_PCI_IO_PROTOCOL *PciIo;
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EFI_STATUS Status;
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UINT64 Data;
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PciIo = Private->PciIo;
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Data = ReadUnaligned64 ((UINT64*)Acq);
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PciIo = Private->PciIo;
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Data = ReadUnaligned64 ((UINT64 *)Acq);
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Status = PciIo->Mem.Write (
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PciIo,
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@@ -296,7 +291,7 @@ WriteNvmeAdminCompletionQueueBaseAddress (
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&Data
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);
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if (EFI_ERROR(Status)) {
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if (EFI_ERROR (Status)) {
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return Status;
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}
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@@ -316,20 +311,20 @@ WriteNvmeAdminCompletionQueueBaseAddress (
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**/
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EFI_STATUS
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NvmeDisableController (
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IN NVME_CONTROLLER_PRIVATE_DATA *Private
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IN NVME_CONTROLLER_PRIVATE_DATA *Private
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)
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{
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NVME_CC Cc;
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NVME_CSTS Csts;
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EFI_STATUS Status;
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UINT32 Index;
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UINT8 Timeout;
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NVME_CC Cc;
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NVME_CSTS Csts;
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EFI_STATUS Status;
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UINT32 Index;
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UINT8 Timeout;
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//
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// Read Controller Configuration Register.
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//
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Status = ReadNvmeControllerConfiguration (Private, &Cc);
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if (EFI_ERROR(Status)) {
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if (EFI_ERROR (Status)) {
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return Status;
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}
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@@ -340,7 +335,7 @@ NvmeDisableController (
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//
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Status = WriteNvmeControllerConfiguration (Private, &Cc);
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if (EFI_ERROR(Status)) {
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if (EFI_ERROR (Status)) {
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return Status;
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}
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@@ -354,15 +349,15 @@ NvmeDisableController (
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Timeout = Private->Cap.To;
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}
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for(Index = (Timeout * 500); Index != 0; --Index) {
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gBS->Stall(1000);
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for (Index = (Timeout * 500); Index != 0; --Index) {
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gBS->Stall (1000);
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//
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// Check if the controller is initialized
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//
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Status = ReadNvmeControllerStatus (Private, &Csts);
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if (EFI_ERROR(Status)) {
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if (EFI_ERROR (Status)) {
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return Status;
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}
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@@ -395,14 +390,14 @@ NvmeDisableController (
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**/
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EFI_STATUS
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NvmeEnableController (
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IN NVME_CONTROLLER_PRIVATE_DATA *Private
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IN NVME_CONTROLLER_PRIVATE_DATA *Private
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)
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{
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NVME_CC Cc;
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NVME_CSTS Csts;
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EFI_STATUS Status;
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UINT32 Index;
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UINT8 Timeout;
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NVME_CC Cc;
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NVME_CSTS Csts;
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EFI_STATUS Status;
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UINT32 Index;
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UINT8 Timeout;
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//
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// Enable the controller.
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@@ -414,7 +409,7 @@ NvmeEnableController (
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Cc.Iocqes = 4;
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Status = WriteNvmeControllerConfiguration (Private, &Cc);
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if (EFI_ERROR(Status)) {
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if (EFI_ERROR (Status)) {
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return Status;
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}
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@@ -428,15 +423,15 @@ NvmeEnableController (
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Timeout = Private->Cap.To;
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}
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for(Index = (Timeout * 500); Index != 0; --Index) {
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gBS->Stall(1000);
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for (Index = (Timeout * 500); Index != 0; --Index) {
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gBS->Stall (1000);
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//
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// Check if the controller is initialized
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//
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Status = ReadNvmeControllerStatus (Private, &Csts);
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if (EFI_ERROR(Status)) {
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if (EFI_ERROR (Status)) {
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return Status;
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}
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@@ -469,25 +464,25 @@ NvmeEnableController (
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**/
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EFI_STATUS
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NvmeIdentifyController (
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IN NVME_CONTROLLER_PRIVATE_DATA *Private,
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IN VOID *Buffer
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IN NVME_CONTROLLER_PRIVATE_DATA *Private,
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IN VOID *Buffer
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)
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{
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EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
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EFI_NVM_EXPRESS_COMMAND Command;
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EFI_NVM_EXPRESS_COMPLETION Completion;
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EFI_STATUS Status;
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EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
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EFI_NVM_EXPRESS_COMMAND Command;
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EFI_NVM_EXPRESS_COMPLETION Completion;
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EFI_STATUS Status;
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ZeroMem (&CommandPacket, sizeof(EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
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ZeroMem (&Command, sizeof(EFI_NVM_EXPRESS_COMMAND));
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ZeroMem (&Completion, sizeof(EFI_NVM_EXPRESS_COMPLETION));
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ZeroMem (&CommandPacket, sizeof (EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
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ZeroMem (&Command, sizeof (EFI_NVM_EXPRESS_COMMAND));
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ZeroMem (&Completion, sizeof (EFI_NVM_EXPRESS_COMPLETION));
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Command.Cdw0.Opcode = NVME_ADMIN_IDENTIFY_CMD;
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//
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// According to Nvm Express 1.1 spec Figure 38, When not used, the field shall be cleared to 0h.
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// For the Identify command, the Namespace Identifier is only used for the Namespace data structure.
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//
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Command.Nsid = 0;
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Command.Nsid = 0;
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CommandPacket.NvmeCmd = &Command;
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CommandPacket.NvmeCompletion = &Completion;
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@@ -498,8 +493,8 @@ NvmeIdentifyController (
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//
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// Set bit 0 (Cns bit) to 1 to identify a controller
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//
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Command.Cdw10 = 1;
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Command.Flags = CDW10_VALID;
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Command.Cdw10 = 1;
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Command.Flags = CDW10_VALID;
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Status = Private->Passthru.PassThru (
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&Private->Passthru,
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@@ -524,25 +519,25 @@ NvmeIdentifyController (
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**/
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EFI_STATUS
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NvmeIdentifyNamespace (
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IN NVME_CONTROLLER_PRIVATE_DATA *Private,
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IN UINT32 NamespaceId,
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IN VOID *Buffer
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IN NVME_CONTROLLER_PRIVATE_DATA *Private,
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IN UINT32 NamespaceId,
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IN VOID *Buffer
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)
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{
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EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
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EFI_NVM_EXPRESS_COMMAND Command;
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EFI_NVM_EXPRESS_COMPLETION Completion;
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EFI_STATUS Status;
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EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
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EFI_NVM_EXPRESS_COMMAND Command;
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EFI_NVM_EXPRESS_COMPLETION Completion;
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EFI_STATUS Status;
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ZeroMem (&CommandPacket, sizeof(EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
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ZeroMem (&Command, sizeof(EFI_NVM_EXPRESS_COMMAND));
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ZeroMem (&Completion, sizeof(EFI_NVM_EXPRESS_COMPLETION));
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ZeroMem (&CommandPacket, sizeof (EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
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ZeroMem (&Command, sizeof (EFI_NVM_EXPRESS_COMMAND));
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ZeroMem (&Completion, sizeof (EFI_NVM_EXPRESS_COMPLETION));
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CommandPacket.NvmeCmd = &Command;
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CommandPacket.NvmeCompletion = &Completion;
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Command.Cdw0.Opcode = NVME_ADMIN_IDENTIFY_CMD;
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Command.Nsid = NamespaceId;
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Command.Cdw0.Opcode = NVME_ADMIN_IDENTIFY_CMD;
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Command.Nsid = NamespaceId;
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CommandPacket.TransferBuffer = Buffer;
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CommandPacket.TransferLength = sizeof (NVME_ADMIN_NAMESPACE_DATA);
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CommandPacket.CommandTimeout = NVME_GENERIC_TIMEOUT;
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@@ -574,30 +569,30 @@ NvmeIdentifyNamespace (
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**/
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EFI_STATUS
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NvmeCreateIoCompletionQueue (
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IN NVME_CONTROLLER_PRIVATE_DATA *Private
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IN NVME_CONTROLLER_PRIVATE_DATA *Private
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)
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{
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EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
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EFI_NVM_EXPRESS_COMMAND Command;
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EFI_NVM_EXPRESS_COMPLETION Completion;
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EFI_STATUS Status;
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NVME_ADMIN_CRIOCQ CrIoCq;
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UINT32 Index;
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UINT16 QueueSize;
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EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
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EFI_NVM_EXPRESS_COMMAND Command;
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EFI_NVM_EXPRESS_COMPLETION Completion;
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EFI_STATUS Status;
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NVME_ADMIN_CRIOCQ CrIoCq;
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UINT32 Index;
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UINT16 QueueSize;
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Status = EFI_SUCCESS;
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Status = EFI_SUCCESS;
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Private->CreateIoQueue = TRUE;
|
||||
|
||||
for (Index = 1; Index < NVME_MAX_QUEUES; Index++) {
|
||||
ZeroMem (&CommandPacket, sizeof(EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
|
||||
ZeroMem (&Command, sizeof(EFI_NVM_EXPRESS_COMMAND));
|
||||
ZeroMem (&Completion, sizeof(EFI_NVM_EXPRESS_COMPLETION));
|
||||
ZeroMem (&CrIoCq, sizeof(NVME_ADMIN_CRIOCQ));
|
||||
ZeroMem (&CommandPacket, sizeof (EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
|
||||
ZeroMem (&Command, sizeof (EFI_NVM_EXPRESS_COMMAND));
|
||||
ZeroMem (&Completion, sizeof (EFI_NVM_EXPRESS_COMPLETION));
|
||||
ZeroMem (&CrIoCq, sizeof (NVME_ADMIN_CRIOCQ));
|
||||
|
||||
CommandPacket.NvmeCmd = &Command;
|
||||
CommandPacket.NvmeCompletion = &Completion;
|
||||
|
||||
Command.Cdw0.Opcode = NVME_ADMIN_CRIOCQ_CMD;
|
||||
Command.Cdw0.Opcode = NVME_ADMIN_CRIOCQ_CMD;
|
||||
CommandPacket.TransferBuffer = Private->CqBufferPciAddr[Index];
|
||||
CommandPacket.TransferLength = EFI_PAGE_SIZE;
|
||||
CommandPacket.CommandTimeout = NVME_GENERIC_TIMEOUT;
|
||||
@@ -646,30 +641,30 @@ NvmeCreateIoCompletionQueue (
|
||||
**/
|
||||
EFI_STATUS
|
||||
NvmeCreateIoSubmissionQueue (
|
||||
IN NVME_CONTROLLER_PRIVATE_DATA *Private
|
||||
IN NVME_CONTROLLER_PRIVATE_DATA *Private
|
||||
)
|
||||
{
|
||||
EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
|
||||
EFI_NVM_EXPRESS_COMMAND Command;
|
||||
EFI_NVM_EXPRESS_COMPLETION Completion;
|
||||
EFI_STATUS Status;
|
||||
NVME_ADMIN_CRIOSQ CrIoSq;
|
||||
UINT32 Index;
|
||||
UINT16 QueueSize;
|
||||
EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
|
||||
EFI_NVM_EXPRESS_COMMAND Command;
|
||||
EFI_NVM_EXPRESS_COMPLETION Completion;
|
||||
EFI_STATUS Status;
|
||||
NVME_ADMIN_CRIOSQ CrIoSq;
|
||||
UINT32 Index;
|
||||
UINT16 QueueSize;
|
||||
|
||||
Status = EFI_SUCCESS;
|
||||
Status = EFI_SUCCESS;
|
||||
Private->CreateIoQueue = TRUE;
|
||||
|
||||
for (Index = 1; Index < NVME_MAX_QUEUES; Index++) {
|
||||
ZeroMem (&CommandPacket, sizeof(EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
|
||||
ZeroMem (&Command, sizeof(EFI_NVM_EXPRESS_COMMAND));
|
||||
ZeroMem (&Completion, sizeof(EFI_NVM_EXPRESS_COMPLETION));
|
||||
ZeroMem (&CrIoSq, sizeof(NVME_ADMIN_CRIOSQ));
|
||||
ZeroMem (&CommandPacket, sizeof (EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
|
||||
ZeroMem (&Command, sizeof (EFI_NVM_EXPRESS_COMMAND));
|
||||
ZeroMem (&Completion, sizeof (EFI_NVM_EXPRESS_COMPLETION));
|
||||
ZeroMem (&CrIoSq, sizeof (NVME_ADMIN_CRIOSQ));
|
||||
|
||||
CommandPacket.NvmeCmd = &Command;
|
||||
CommandPacket.NvmeCompletion = &Completion;
|
||||
|
||||
Command.Cdw0.Opcode = NVME_ADMIN_CRIOSQ_CMD;
|
||||
Command.Cdw0.Opcode = NVME_ADMIN_CRIOSQ_CMD;
|
||||
CommandPacket.TransferBuffer = Private->SqBufferPciAddr[Index];
|
||||
CommandPacket.TransferLength = EFI_PAGE_SIZE;
|
||||
CommandPacket.CommandTimeout = NVME_GENERIC_TIMEOUT;
|
||||
@@ -720,17 +715,18 @@ NvmeCreateIoSubmissionQueue (
|
||||
**/
|
||||
EFI_STATUS
|
||||
NvmeControllerInit (
|
||||
IN NVME_CONTROLLER_PRIVATE_DATA *Private
|
||||
IN NVME_CONTROLLER_PRIVATE_DATA *Private
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
EFI_PCI_IO_PROTOCOL *PciIo;
|
||||
UINT64 Supports;
|
||||
NVME_AQA Aqa;
|
||||
NVME_ASQ Asq;
|
||||
NVME_ACQ Acq;
|
||||
UINT8 Sn[21];
|
||||
UINT8 Mn[41];
|
||||
EFI_STATUS Status;
|
||||
EFI_PCI_IO_PROTOCOL *PciIo;
|
||||
UINT64 Supports;
|
||||
NVME_AQA Aqa;
|
||||
NVME_ASQ Asq;
|
||||
NVME_ACQ Acq;
|
||||
UINT8 Sn[21];
|
||||
UINT8 Mn[41];
|
||||
|
||||
//
|
||||
// Save original PCI attributes and enable this controller.
|
||||
//
|
||||
@@ -799,12 +795,12 @@ NvmeControllerInit (
|
||||
//
|
||||
ASSERT ((Private->Cap.Mpsmin + 12) <= EFI_PAGE_SHIFT);
|
||||
|
||||
Private->Cid[0] = 0;
|
||||
Private->Cid[1] = 0;
|
||||
Private->Cid[2] = 0;
|
||||
Private->Pt[0] = 0;
|
||||
Private->Pt[1] = 0;
|
||||
Private->Pt[2] = 0;
|
||||
Private->Cid[0] = 0;
|
||||
Private->Cid[1] = 0;
|
||||
Private->Cid[2] = 0;
|
||||
Private->Pt[0] = 0;
|
||||
Private->Pt[1] = 0;
|
||||
Private->Pt[2] = 0;
|
||||
Private->SqTdbl[0].Sqt = 0;
|
||||
Private->SqTdbl[1].Sqt = 0;
|
||||
Private->SqTdbl[2].Sqt = 0;
|
||||
@@ -815,7 +811,7 @@ NvmeControllerInit (
|
||||
|
||||
Status = NvmeDisableController (Private);
|
||||
|
||||
if (EFI_ERROR(Status)) {
|
||||
if (EFI_ERROR (Status)) {
|
||||
return Status;
|
||||
}
|
||||
|
||||
@@ -869,7 +865,7 @@ NvmeControllerInit (
|
||||
//
|
||||
Status = WriteNvmeAdminQueueAttributes (Private, &Aqa);
|
||||
|
||||
if (EFI_ERROR(Status)) {
|
||||
if (EFI_ERROR (Status)) {
|
||||
return Status;
|
||||
}
|
||||
|
||||
@@ -878,7 +874,7 @@ NvmeControllerInit (
|
||||
//
|
||||
Status = WriteNvmeAdminSubmissionQueueBaseAddress (Private, &Asq);
|
||||
|
||||
if (EFI_ERROR(Status)) {
|
||||
if (EFI_ERROR (Status)) {
|
||||
return Status;
|
||||
}
|
||||
|
||||
@@ -887,12 +883,12 @@ NvmeControllerInit (
|
||||
//
|
||||
Status = WriteNvmeAdminCompletionQueueBaseAddress (Private, &Acq);
|
||||
|
||||
if (EFI_ERROR(Status)) {
|
||||
if (EFI_ERROR (Status)) {
|
||||
return Status;
|
||||
}
|
||||
|
||||
Status = NvmeEnableController (Private);
|
||||
if (EFI_ERROR(Status)) {
|
||||
if (EFI_ERROR (Status)) {
|
||||
return Status;
|
||||
}
|
||||
|
||||
@@ -900,7 +896,7 @@ NvmeControllerInit (
|
||||
// Allocate buffer for Identify Controller data
|
||||
//
|
||||
if (Private->ControllerData == NULL) {
|
||||
Private->ControllerData = (NVME_ADMIN_CONTROLLER_DATA *)AllocateZeroPool (sizeof(NVME_ADMIN_CONTROLLER_DATA));
|
||||
Private->ControllerData = (NVME_ADMIN_CONTROLLER_DATA *)AllocateZeroPool (sizeof (NVME_ADMIN_CONTROLLER_DATA));
|
||||
|
||||
if (Private->ControllerData == NULL) {
|
||||
return EFI_OUT_OF_RESOURCES;
|
||||
@@ -912,8 +908,8 @@ NvmeControllerInit (
|
||||
//
|
||||
Status = NvmeIdentifyController (Private, Private->ControllerData);
|
||||
|
||||
if (EFI_ERROR(Status)) {
|
||||
FreePool(Private->ControllerData);
|
||||
if (EFI_ERROR (Status)) {
|
||||
FreePool (Private->ControllerData);
|
||||
Private->ControllerData = NULL;
|
||||
return EFI_NOT_FOUND;
|
||||
}
|
||||
@@ -928,13 +924,13 @@ NvmeControllerInit (
|
||||
DEBUG ((DEBUG_INFO, " == NVME IDENTIFY CONTROLLER DATA ==\n"));
|
||||
DEBUG ((DEBUG_INFO, " PCI VID : 0x%x\n", Private->ControllerData->Vid));
|
||||
DEBUG ((DEBUG_INFO, " PCI SSVID : 0x%x\n", Private->ControllerData->Ssvid));
|
||||
DEBUG ((DEBUG_INFO, " SN : %a\n", Sn));
|
||||
DEBUG ((DEBUG_INFO, " MN : %a\n", Mn));
|
||||
DEBUG ((DEBUG_INFO, " FR : 0x%x\n", *((UINT64*)Private->ControllerData->Fr)));
|
||||
DEBUG ((DEBUG_INFO, " TNVMCAP (high 8-byte) : 0x%lx\n", *((UINT64*)(Private->ControllerData->Tnvmcap + 8))));
|
||||
DEBUG ((DEBUG_INFO, " TNVMCAP (low 8-byte) : 0x%lx\n", *((UINT64*)Private->ControllerData->Tnvmcap)));
|
||||
DEBUG ((DEBUG_INFO, " SN : %a\n", Sn));
|
||||
DEBUG ((DEBUG_INFO, " MN : %a\n", Mn));
|
||||
DEBUG ((DEBUG_INFO, " FR : 0x%x\n", *((UINT64 *)Private->ControllerData->Fr)));
|
||||
DEBUG ((DEBUG_INFO, " TNVMCAP (high 8-byte) : 0x%lx\n", *((UINT64 *)(Private->ControllerData->Tnvmcap + 8))));
|
||||
DEBUG ((DEBUG_INFO, " TNVMCAP (low 8-byte) : 0x%lx\n", *((UINT64 *)Private->ControllerData->Tnvmcap)));
|
||||
DEBUG ((DEBUG_INFO, " RAB : 0x%x\n", Private->ControllerData->Rab));
|
||||
DEBUG ((DEBUG_INFO, " IEEE : 0x%x\n", *(UINT32*)Private->ControllerData->Ieee_oui));
|
||||
DEBUG ((DEBUG_INFO, " IEEE : 0x%x\n", *(UINT32 *)Private->ControllerData->Ieee_oui));
|
||||
DEBUG ((DEBUG_INFO, " AERL : 0x%x\n", Private->ControllerData->Aerl));
|
||||
DEBUG ((DEBUG_INFO, " SQES : 0x%x\n", Private->ControllerData->Sqes));
|
||||
DEBUG ((DEBUG_INFO, " CQES : 0x%x\n", Private->ControllerData->Cqes));
|
||||
@@ -945,8 +941,8 @@ NvmeControllerInit (
|
||||
// One for blocking I/O, one for non-blocking I/O.
|
||||
//
|
||||
Status = NvmeCreateIoCompletionQueue (Private);
|
||||
if (EFI_ERROR(Status)) {
|
||||
return Status;
|
||||
if (EFI_ERROR (Status)) {
|
||||
return Status;
|
||||
}
|
||||
|
||||
//
|
||||
@@ -976,24 +972,24 @@ NvmeControllerInit (
|
||||
VOID
|
||||
EFIAPI
|
||||
NvmeShutdownAllControllers (
|
||||
IN EFI_RESET_TYPE ResetType,
|
||||
IN EFI_STATUS ResetStatus,
|
||||
IN UINTN DataSize,
|
||||
IN VOID *ResetData OPTIONAL
|
||||
IN EFI_RESET_TYPE ResetType,
|
||||
IN EFI_STATUS ResetStatus,
|
||||
IN UINTN DataSize,
|
||||
IN VOID *ResetData OPTIONAL
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
EFI_HANDLE *Handles;
|
||||
UINTN HandleCount;
|
||||
UINTN HandleIndex;
|
||||
EFI_OPEN_PROTOCOL_INFORMATION_ENTRY *OpenInfos;
|
||||
UINTN OpenInfoCount;
|
||||
UINTN OpenInfoIndex;
|
||||
EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *NvmePassThru;
|
||||
NVME_CC Cc;
|
||||
NVME_CSTS Csts;
|
||||
UINTN Index;
|
||||
NVME_CONTROLLER_PRIVATE_DATA *Private;
|
||||
EFI_STATUS Status;
|
||||
EFI_HANDLE *Handles;
|
||||
UINTN HandleCount;
|
||||
UINTN HandleIndex;
|
||||
EFI_OPEN_PROTOCOL_INFORMATION_ENTRY *OpenInfos;
|
||||
UINTN OpenInfoCount;
|
||||
UINTN OpenInfoIndex;
|
||||
EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *NvmePassThru;
|
||||
NVME_CC Cc;
|
||||
NVME_CSTS Csts;
|
||||
UINTN Index;
|
||||
NVME_CONTROLLER_PRIVATE_DATA *Private;
|
||||
|
||||
Status = gBS->LocateHandleBuffer (
|
||||
ByProtocol,
|
||||
@@ -1023,11 +1019,12 @@ NvmeShutdownAllControllers (
|
||||
// gImageHandle equals to DriverBinding handle for this driver.
|
||||
//
|
||||
if (((OpenInfos[OpenInfoIndex].Attributes & EFI_OPEN_PROTOCOL_BY_DRIVER) != 0) &&
|
||||
(OpenInfos[OpenInfoIndex].AgentHandle == gImageHandle)) {
|
||||
(OpenInfos[OpenInfoIndex].AgentHandle == gImageHandle))
|
||||
{
|
||||
Status = gBS->OpenProtocol (
|
||||
OpenInfos[OpenInfoIndex].ControllerHandle,
|
||||
&gEfiNvmExpressPassThruProtocolGuid,
|
||||
(VOID **) &NvmePassThru,
|
||||
(VOID **)&NvmePassThru,
|
||||
NULL,
|
||||
NULL,
|
||||
EFI_OPEN_PROTOCOL_GET_PROTOCOL
|
||||
@@ -1035,22 +1032,24 @@ NvmeShutdownAllControllers (
|
||||
if (EFI_ERROR (Status)) {
|
||||
continue;
|
||||
}
|
||||
|
||||
Private = NVME_CONTROLLER_PRIVATE_DATA_FROM_PASS_THRU (NvmePassThru);
|
||||
|
||||
//
|
||||
// Read Controller Configuration Register.
|
||||
//
|
||||
Status = ReadNvmeControllerConfiguration (Private, &Cc);
|
||||
if (EFI_ERROR(Status)) {
|
||||
if (EFI_ERROR (Status)) {
|
||||
continue;
|
||||
}
|
||||
|
||||
//
|
||||
// The host should set the Shutdown Notification (CC.SHN) field to 01b
|
||||
// to indicate a normal shutdown operation.
|
||||
//
|
||||
Cc.Shn = NVME_CC_SHN_NORMAL_SHUTDOWN;
|
||||
Status = WriteNvmeControllerConfiguration (Private, &Cc);
|
||||
if (EFI_ERROR(Status)) {
|
||||
if (EFI_ERROR (Status)) {
|
||||
continue;
|
||||
}
|
||||
|
||||
@@ -1061,10 +1060,11 @@ NvmeShutdownAllControllers (
|
||||
//
|
||||
for (Index = 0; Index < NVME_SHUTDOWN_PROCESS_TIMEOUT * 100; Index++) {
|
||||
Status = ReadNvmeControllerStatus (Private, &Csts);
|
||||
if (!EFI_ERROR(Status) && (Csts.Shst == NVME_CSTS_SHST_SHUTDOWN_COMPLETED)) {
|
||||
DEBUG((DEBUG_INFO, "NvmeShutdownController: shutdown processing is completed after %dms.\n", Index * 10));
|
||||
if (!EFI_ERROR (Status) && (Csts.Shst == NVME_CSTS_SHST_SHUTDOWN_COMPLETED)) {
|
||||
DEBUG ((DEBUG_INFO, "NvmeShutdownController: shutdown processing is completed after %dms.\n", Index * 10));
|
||||
break;
|
||||
}
|
||||
|
||||
//
|
||||
// Stall for 10ms
|
||||
//
|
||||
@@ -1072,7 +1072,7 @@ NvmeShutdownAllControllers (
|
||||
}
|
||||
|
||||
if (Index == NVME_SHUTDOWN_PROCESS_TIMEOUT * 100) {
|
||||
DEBUG((DEBUG_ERROR, "NvmeShutdownController: shutdown processing is timed out\n"));
|
||||
DEBUG ((DEBUG_ERROR, "NvmeShutdownController: shutdown processing is timed out\n"));
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -1089,12 +1089,12 @@ NvmeRegisterShutdownNotification (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
EFI_RESET_NOTIFICATION_PROTOCOL *ResetNotify;
|
||||
EFI_STATUS Status;
|
||||
EFI_RESET_NOTIFICATION_PROTOCOL *ResetNotify;
|
||||
|
||||
mNvmeControllerNumber++;
|
||||
if (mNvmeControllerNumber == 1) {
|
||||
Status = gBS->LocateProtocol (&gEfiResetNotificationProtocolGuid, NULL, (VOID **) &ResetNotify);
|
||||
Status = gBS->LocateProtocol (&gEfiResetNotificationProtocolGuid, NULL, (VOID **)&ResetNotify);
|
||||
if (!EFI_ERROR (Status)) {
|
||||
Status = ResetNotify->RegisterResetNotify (ResetNotify, NvmeShutdownAllControllers);
|
||||
ASSERT_EFI_ERROR (Status);
|
||||
@@ -1114,12 +1114,12 @@ NvmeUnregisterShutdownNotification (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
EFI_RESET_NOTIFICATION_PROTOCOL *ResetNotify;
|
||||
EFI_STATUS Status;
|
||||
EFI_RESET_NOTIFICATION_PROTOCOL *ResetNotify;
|
||||
|
||||
mNvmeControllerNumber--;
|
||||
if (mNvmeControllerNumber == 0) {
|
||||
Status = gBS->LocateProtocol (&gEfiResetNotificationProtocolGuid, NULL, (VOID **) &ResetNotify);
|
||||
Status = gBS->LocateProtocol (&gEfiResetNotificationProtocolGuid, NULL, (VOID **)&ResetNotify);
|
||||
if (!EFI_ERROR (Status)) {
|
||||
Status = ResetNotify->UnregisterResetNotify (ResetNotify, NvmeShutdownAllControllers);
|
||||
ASSERT_EFI_ERROR (Status);
|
||||
|
||||
Reference in New Issue
Block a user