MdeModulePkg: Apply uncrustify changes
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737 Apply uncrustify changes to .c/.h files in the MdeModulePkg package Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
This commit is contained in:
Michael Kubacki
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mergify[bot]
mergify[bot]
parent
7c7184e201
commit
1436aea4d5
@@ -44,68 +44,68 @@ typedef struct _PEI_NVME_CONTROLLER_PRIVATE_DATA PEI_NVME_CONTROLLER_PRIVATE_DA
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//
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// NVME PEI driver implementation related definitions
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//
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#define NVME_MAX_QUEUES 2 // Number of I/O queues supported by the driver, 1 for AQ, 1 for CQ
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#define NVME_ASQ_SIZE 1 // Number of admin submission queue entries, which is 0-based
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#define NVME_ACQ_SIZE 1 // Number of admin completion queue entries, which is 0-based
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#define NVME_CSQ_SIZE 63 // Number of I/O submission queue entries, which is 0-based
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#define NVME_CCQ_SIZE 63 // Number of I/O completion queue entries, which is 0-based
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#define NVME_PRP_SIZE (8) // Pages of PRP list
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#define NVME_MAX_QUEUES 2 // Number of I/O queues supported by the driver, 1 for AQ, 1 for CQ
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#define NVME_ASQ_SIZE 1 // Number of admin submission queue entries, which is 0-based
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#define NVME_ACQ_SIZE 1 // Number of admin completion queue entries, which is 0-based
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#define NVME_CSQ_SIZE 63 // Number of I/O submission queue entries, which is 0-based
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#define NVME_CCQ_SIZE 63 // Number of I/O completion queue entries, which is 0-based
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#define NVME_PRP_SIZE (8) // Pages of PRP list
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#define NVME_MEM_MAX_PAGES \
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( \
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1 /* ASQ */ + \
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1 /* ACQ */ + \
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1 /* SQs */ + \
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1 /* CQs */ + \
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1 /* ASQ */ + \
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1 /* ACQ */ + \
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1 /* SQs */ + \
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1 /* CQs */ + \
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NVME_PRP_SIZE) /* PRPs */
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#define NVME_ADMIN_QUEUE 0x00
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#define NVME_IO_QUEUE 0x01
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#define NVME_GENERIC_TIMEOUT 5000000 // Generic PassThru command timeout value, in us unit
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#define NVME_POLL_INTERVAL 100 // Poll interval for PassThru command, in us unit
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#define NVME_ADMIN_QUEUE 0x00
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#define NVME_IO_QUEUE 0x01
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#define NVME_GENERIC_TIMEOUT 5000000 // Generic PassThru command timeout value, in us unit
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#define NVME_POLL_INTERVAL 100 // Poll interval for PassThru command, in us unit
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//
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// Nvme namespace data structure.
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//
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struct _PEI_NVME_NAMESPACE_INFO {
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UINT32 NamespaceId;
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UINT64 NamespaceUuid;
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EFI_PEI_BLOCK_IO2_MEDIA Media;
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UINT32 NamespaceId;
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UINT64 NamespaceUuid;
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EFI_PEI_BLOCK_IO2_MEDIA Media;
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PEI_NVME_CONTROLLER_PRIVATE_DATA *Controller;
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PEI_NVME_CONTROLLER_PRIVATE_DATA *Controller;
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};
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#define NVME_CONTROLLER_NSID 0
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#define NVME_CONTROLLER_NSID 0
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//
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// Unique signature for private data structure.
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//
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#define NVME_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('N','V','P','C')
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#define NVME_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('N','V','P','C')
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//
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// Nvme controller private data structure.
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//
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struct _PEI_NVME_CONTROLLER_PRIVATE_DATA {
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UINT32 Signature;
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UINTN MmioBase;
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EFI_NVM_EXPRESS_PASS_THRU_MODE PassThruMode;
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UINTN DevicePathLength;
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EFI_DEVICE_PATH_PROTOCOL *DevicePath;
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UINT32 Signature;
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UINTN MmioBase;
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EFI_NVM_EXPRESS_PASS_THRU_MODE PassThruMode;
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UINTN DevicePathLength;
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EFI_DEVICE_PATH_PROTOCOL *DevicePath;
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EFI_PEI_RECOVERY_BLOCK_IO_PPI BlkIoPpi;
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EFI_PEI_RECOVERY_BLOCK_IO2_PPI BlkIo2Ppi;
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EDKII_PEI_STORAGE_SECURITY_CMD_PPI StorageSecurityPpi;
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EDKII_PEI_NVM_EXPRESS_PASS_THRU_PPI NvmePassThruPpi;
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EFI_PEI_PPI_DESCRIPTOR BlkIoPpiList;
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EFI_PEI_PPI_DESCRIPTOR BlkIo2PpiList;
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EFI_PEI_PPI_DESCRIPTOR StorageSecurityPpiList;
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EFI_PEI_PPI_DESCRIPTOR NvmePassThruPpiList;
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EFI_PEI_NOTIFY_DESCRIPTOR EndOfPeiNotifyList;
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EFI_PEI_RECOVERY_BLOCK_IO_PPI BlkIoPpi;
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EFI_PEI_RECOVERY_BLOCK_IO2_PPI BlkIo2Ppi;
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EDKII_PEI_STORAGE_SECURITY_CMD_PPI StorageSecurityPpi;
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EDKII_PEI_NVM_EXPRESS_PASS_THRU_PPI NvmePassThruPpi;
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EFI_PEI_PPI_DESCRIPTOR BlkIoPpiList;
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EFI_PEI_PPI_DESCRIPTOR BlkIo2PpiList;
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EFI_PEI_PPI_DESCRIPTOR StorageSecurityPpiList;
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EFI_PEI_PPI_DESCRIPTOR NvmePassThruPpiList;
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EFI_PEI_NOTIFY_DESCRIPTOR EndOfPeiNotifyList;
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//
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// Pointer to identify controller data
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//
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NVME_ADMIN_CONTROLLER_DATA *ControllerData;
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NVME_ADMIN_CONTROLLER_DATA *ControllerData;
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//
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// (4 + NVME_PRP_SIZE) x 4kB aligned buffers will be carved out of this buffer
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@@ -115,34 +115,34 @@ struct _PEI_NVME_CONTROLLER_PRIVATE_DATA {
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// 4th 4kB boundary is the start of I/O completion queue
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// 5th 4kB boundary is the start of PRP list buffers
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//
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VOID *Buffer;
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VOID *BufferMapping;
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VOID *Buffer;
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VOID *BufferMapping;
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//
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// Pointers to 4kB aligned submission & completion queues
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//
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NVME_SQ *SqBuffer[NVME_MAX_QUEUES];
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NVME_CQ *CqBuffer[NVME_MAX_QUEUES];
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NVME_SQ *SqBuffer[NVME_MAX_QUEUES];
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NVME_CQ *CqBuffer[NVME_MAX_QUEUES];
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//
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// Submission and completion queue indices
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//
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NVME_SQTDBL SqTdbl[NVME_MAX_QUEUES];
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NVME_CQHDBL CqHdbl[NVME_MAX_QUEUES];
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NVME_SQTDBL SqTdbl[NVME_MAX_QUEUES];
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NVME_CQHDBL CqHdbl[NVME_MAX_QUEUES];
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UINT8 Pt[NVME_MAX_QUEUES];
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UINT16 Cid[NVME_MAX_QUEUES];
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UINT8 Pt[NVME_MAX_QUEUES];
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UINT16 Cid[NVME_MAX_QUEUES];
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//
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// Nvme controller capabilities
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//
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NVME_CAP Cap;
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NVME_CAP Cap;
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//
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// Namespaces information on the controller
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//
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UINT32 ActiveNamespaceNum;
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PEI_NVME_NAMESPACE_INFO *NamespaceInfo;
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UINT32 ActiveNamespaceNum;
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PEI_NVME_NAMESPACE_INFO *NamespaceInfo;
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};
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#define GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_BLKIO(a) \
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@@ -156,7 +156,6 @@ struct _PEI_NVME_CONTROLLER_PRIVATE_DATA {
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#define GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_NOTIFY(a) \
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CR (a, PEI_NVME_CONTROLLER_PRIVATE_DATA, EndOfPeiNotifyList, NVME_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)
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//
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// Internal functions
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//
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@@ -201,9 +200,9 @@ IoMmuAllocateBuffer (
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**/
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EFI_STATUS
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IoMmuFreeBuffer (
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IN UINTN Pages,
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IN VOID *HostAddress,
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IN VOID *Mapping
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IN UINTN Pages,
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IN VOID *HostAddress,
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IN VOID *Mapping
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);
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/**
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@@ -227,11 +226,11 @@ IoMmuFreeBuffer (
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**/
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EFI_STATUS
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IoMmuMap (
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IN EDKII_IOMMU_OPERATION Operation,
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IN VOID *HostAddress,
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IN OUT UINTN *NumberOfBytes,
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OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
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OUT VOID **Mapping
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IN EDKII_IOMMU_OPERATION Operation,
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IN VOID *HostAddress,
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IN OUT UINTN *NumberOfBytes,
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OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
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OUT VOID **Mapping
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);
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/**
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@@ -245,7 +244,7 @@ IoMmuMap (
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**/
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EFI_STATUS
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IoMmuUnmap (
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IN VOID *Mapping
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IN VOID *Mapping
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);
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/**
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@@ -282,9 +281,9 @@ NvmePeimEndOfPei (
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**/
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EFI_STATUS
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GetDevicePathInstanceSize (
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IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
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OUT UINTN *InstanceSize,
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OUT BOOLEAN *EntireDevicePathEnd
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IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
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OUT UINTN *InstanceSize,
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OUT BOOLEAN *EntireDevicePathEnd
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);
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/**
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@@ -300,8 +299,8 @@ GetDevicePathInstanceSize (
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**/
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EFI_STATUS
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NvmeIsHcDevicePathValid (
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IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
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IN UINTN DevicePathLength
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IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
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IN UINTN DevicePathLength
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);
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/**
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@@ -323,11 +322,11 @@ NvmeIsHcDevicePathValid (
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**/
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EFI_STATUS
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NvmeBuildDevicePath (
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IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,
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IN UINT32 NamespaceId,
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IN UINT64 NamespaceUuid,
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OUT UINTN *DevicePathLength,
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OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath
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IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,
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IN UINT32 NamespaceId,
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IN UINT64 NamespaceUuid,
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OUT UINTN *DevicePathLength,
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OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath
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);
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/**
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@@ -342,8 +341,8 @@ NvmeBuildDevicePath (
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**/
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BOOLEAN
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NvmeS3SkipThisController (
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IN EFI_DEVICE_PATH_PROTOCOL *HcDevicePath,
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IN UINTN HcDevicePathLength
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IN EFI_DEVICE_PATH_PROTOCOL *HcDevicePath,
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IN UINTN HcDevicePathLength
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);
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#endif
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