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MdeModulePkg: Apply uncrustify changes

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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737

Apply uncrustify changes to .c/.h files in the MdeModulePkg package

Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
This commit is contained in:
Michael Kubacki
2021-12-05 14:54:02 -08:00
committed by mergify[bot]
parent 7c7184e201
commit 1436aea4d5
994 changed files with 107608 additions and 101311 deletions
Download Patch File Download Diff File Expand all files Collapse all files

23
MdeModulePkg/Bus/Pci/PciBusDxe/ComponentName.c
View File

@@ -20,16 +20,15 @@ GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME_PROTOCOL gPciBusComponentName
//
// EFI Component Name 2 Protocol
//
GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gPciBusComponentName2 = {
(EFI_COMPONENT_NAME2_GET_DRIVER_NAME) PciBusComponentNameGetDriverName,
(EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME) PciBusComponentNameGetControllerName,
GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gPciBusComponentName2 = {
(EFI_COMPONENT_NAME2_GET_DRIVER_NAME)PciBusComponentNameGetDriverName,
(EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME)PciBusComponentNameGetControllerName,
"en"
};
GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mPciBusDriverNameTable[] = {
{ "eng;en", (CHAR16 *) L"PCI Bus Driver" },
{ NULL , NULL }
GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mPciBusDriverNameTable[] = {
{ "eng;en", (CHAR16 *)L"PCI Bus Driver" },
{ NULL, NULL }
};
/**
@@ -159,11 +158,11 @@ PciBusComponentNameGetDriverName (
EFI_STATUS
EFIAPI
PciBusComponentNameGetControllerName (
IN EFI_COMPONENT_NAME_PROTOCOL *This,
IN EFI_HANDLE ControllerHandle,
IN EFI_HANDLE ChildHandle OPTIONAL,
IN CHAR8 *Language,
OUT CHAR16 **ControllerName
IN EFI_COMPONENT_NAME_PROTOCOL *This,
IN EFI_HANDLE ControllerHandle,
IN EFI_HANDLE ChildHandle OPTIONAL,
IN CHAR8 *Language,
OUT CHAR16 **ControllerName
)
{
return EFI_UNSUPPORTED;

14
MdeModulePkg/Bus/Pci/PciBusDxe/ComponentName.h
View File

@@ -6,7 +6,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _EFI_PCI_BUS_COMPONENT_NAME_H_
#define _EFI_PCI_BUS_COMPONENT_NAME_H_
@@ -16,6 +15,7 @@ extern EFI_COMPONENT_NAME2_PROTOCOL gPciBusComponentName2;
//
// EFI Component Name Functions
//
/**
Retrieves a Unicode string that is the user readable name of the driver.
@@ -63,7 +63,6 @@ PciBusComponentNameGetDriverName (
OUT CHAR16 **DriverName
);
/**
Retrieves a Unicode string that is the user readable name of the controller
that is being managed by a driver.
@@ -135,12 +134,11 @@ PciBusComponentNameGetDriverName (
EFI_STATUS
EFIAPI
PciBusComponentNameGetControllerName (
IN EFI_COMPONENT_NAME_PROTOCOL *This,
IN EFI_HANDLE ControllerHandle,
IN EFI_HANDLE ChildHandle OPTIONAL,
IN CHAR8 *Language,
OUT CHAR16 **ControllerName
IN EFI_COMPONENT_NAME_PROTOCOL *This,
IN EFI_HANDLE ControllerHandle,
IN EFI_HANDLE ChildHandle OPTIONAL,
IN CHAR8 *Language,
OUT CHAR16 **ControllerName
);
#endif

145
MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c
View File

@@ -18,7 +18,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
//
// PCI Bus Driver Global Variables
//
EFI_DRIVER_BINDING_PROTOCOL gPciBusDriverBinding = {
EFI_DRIVER_BINDING_PROTOCOL gPciBusDriverBinding = {
PciBusDriverBindingSupported,
PciBusDriverBindingStart,
PciBusDriverBindingStop,
@@ -29,17 +29,17 @@ EFI_DRIVER_BINDING_PROTOCOL gPciBusDriverBinding = {
EFI_HANDLE gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM];
EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *gIncompatiblePciDeviceSupport = NULL;
UINTN gPciHostBridgeNumber = 0;
BOOLEAN gFullEnumeration = TRUE;
UINT64 gAllOne = 0xFFFFFFFFFFFFFFFFULL;
UINT64 gAllZero = 0;
UINTN gPciHostBridgeNumber = 0;
BOOLEAN gFullEnumeration = TRUE;
UINT64 gAllOne = 0xFFFFFFFFFFFFFFFFULL;
UINT64 gAllZero = 0;
EFI_PCI_PLATFORM_PROTOCOL *gPciPlatformProtocol;
EFI_PCI_OVERRIDE_PROTOCOL *gPciOverrideProtocol;
EDKII_IOMMU_PROTOCOL *mIoMmuProtocol;
EDKII_DEVICE_SECURITY_PROTOCOL *mDeviceSecurityProtocol;
EFI_PCI_PLATFORM_PROTOCOL *gPciPlatformProtocol;
EFI_PCI_OVERRIDE_PROTOCOL *gPciOverrideProtocol;
EDKII_IOMMU_PROTOCOL *mIoMmuProtocol;
EDKII_DEVICE_SECURITY_PROTOCOL *mDeviceSecurityProtocol;
GLOBAL_REMOVE_IF_UNREFERENCED EFI_PCI_HOTPLUG_REQUEST_PROTOCOL mPciHotPlugRequest = {
GLOBAL_REMOVE_IF_UNREFERENCED EFI_PCI_HOTPLUG_REQUEST_PROTOCOL mPciHotPlugRequest = {
PciHotPlugRequestNotify
};
@@ -61,8 +61,8 @@ GLOBAL_REMOVE_IF_UNREFERENCED EFI_PCI_HOTPLUG_REQUEST_PROTOCOL mPciHotPlugReques
EFI_STATUS
EFIAPI
PciBusEntryPoint (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
@@ -119,15 +119,15 @@ PciBusEntryPoint (
EFI_STATUS
EFIAPI
PciBusDriverBindingSupported (
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
)
{
EFI_STATUS Status;
EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath;
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
EFI_DEV_PATH_PTR Node;
EFI_STATUS Status;
EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath;
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
EFI_DEV_PATH_PTR Node;
//
// Check RemainingDevicePath validation
@@ -143,9 +143,10 @@ PciBusDriverBindingSupported (
// check its validation
//
Node.DevPath = RemainingDevicePath;
if (Node.DevPath->Type != HARDWARE_DEVICE_PATH ||
Node.DevPath->SubType != HW_PCI_DP ||
DevicePathNodeLength(Node.DevPath) != sizeof(PCI_DEVICE_PATH)) {
if ((Node.DevPath->Type != HARDWARE_DEVICE_PATH) ||
(Node.DevPath->SubType != HW_PCI_DP) ||
(DevicePathNodeLength (Node.DevPath) != sizeof (PCI_DEVICE_PATH)))
{
return EFI_UNSUPPORTED;
}
}
@@ -157,7 +158,7 @@ PciBusDriverBindingSupported (
Status = gBS->OpenProtocol (
Controller,
&gEfiPciRootBridgeIoProtocolGuid,
(VOID **) &PciRootBridgeIo,
(VOID **)&PciRootBridgeIo,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_BY_DRIVER
@@ -174,11 +175,11 @@ PciBusDriverBindingSupported (
// Close the I/O Abstraction(s) used to perform the supported test
//
gBS->CloseProtocol (
Controller,
&gEfiPciRootBridgeIoProtocolGuid,
This->DriverBindingHandle,
Controller
);
Controller,
&gEfiPciRootBridgeIoProtocolGuid,
This->DriverBindingHandle,
Controller
);
//
// Open the EFI Device Path protocol needed to perform the supported test
@@ -186,7 +187,7 @@ PciBusDriverBindingSupported (
Status = gBS->OpenProtocol (
Controller,
&gEfiDevicePathProtocolGuid,
(VOID **) &ParentDevicePath,
(VOID **)&ParentDevicePath,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_BY_DRIVER
@@ -203,11 +204,11 @@ PciBusDriverBindingSupported (
// Close protocol, don't use device path protocol in the Support() function
//
gBS->CloseProtocol (
Controller,
&gEfiDevicePathProtocolGuid,
This->DriverBindingHandle,
Controller
);
Controller,
&gEfiDevicePathProtocolGuid,
This->DriverBindingHandle,
Controller
);
return EFI_SUCCESS;
}
@@ -234,9 +235,9 @@ PciBusDriverBindingStart (
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
)
{
EFI_STATUS Status;
EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath;
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
EFI_STATUS Status;
EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath;
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
//
// Initialize PciRootBridgeIo to suppress incorrect compiler warning.
@@ -259,7 +260,7 @@ PciBusDriverBindingStart (
gBS->LocateProtocol (
&gEfiIncompatiblePciDeviceSupportProtocolGuid,
NULL,
(VOID **) &gIncompatiblePciDeviceSupport
(VOID **)&gIncompatiblePciDeviceSupport
);
//
@@ -268,10 +269,10 @@ PciBusDriverBindingStart (
//
gPciPlatformProtocol = NULL;
gBS->LocateProtocol (
&gEfiPciPlatformProtocolGuid,
NULL,
(VOID **) &gPciPlatformProtocol
);
&gEfiPciPlatformProtocolGuid,
NULL,
(VOID **)&gPciPlatformProtocol
);
//
// If PCI Platform protocol doesn't exist, try to Pci Override Protocol.
@@ -279,32 +280,32 @@ PciBusDriverBindingStart (
if (gPciPlatformProtocol == NULL) {
gPciOverrideProtocol = NULL;
gBS->LocateProtocol (
&gEfiPciOverrideProtocolGuid,
NULL,
(VOID **) &gPciOverrideProtocol
);
&gEfiPciOverrideProtocolGuid,
NULL,
(VOID **)&gPciOverrideProtocol
);
}
if (mIoMmuProtocol == NULL) {
gBS->LocateProtocol (
&gEdkiiIoMmuProtocolGuid,
NULL,
(VOID **) &mIoMmuProtocol
);
&gEdkiiIoMmuProtocolGuid,
NULL,
(VOID **)&mIoMmuProtocol
);
}
if (mDeviceSecurityProtocol == NULL) {
gBS->LocateProtocol (
&gEdkiiDeviceSecurityProtocolGuid,
NULL,
(VOID **) &mDeviceSecurityProtocol
);
&gEdkiiDeviceSecurityProtocolGuid,
NULL,
(VOID **)&mDeviceSecurityProtocol
);
}
if (PcdGetBool (PcdPciDisableBusEnumeration)) {
gFullEnumeration = FALSE;
} else {
gFullEnumeration = (BOOLEAN) ((SearchHostBridgeHandle (Controller) ? FALSE : TRUE));
gFullEnumeration = (BOOLEAN)((SearchHostBridgeHandle (Controller) ? FALSE : TRUE));
}
//
@@ -313,7 +314,7 @@ PciBusDriverBindingStart (
Status = gBS->OpenProtocol (
Controller,
&gEfiDevicePathProtocolGuid,
(VOID **) &ParentDevicePath,
(VOID **)&ParentDevicePath,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_GET_PROTOCOL
@@ -342,7 +343,7 @@ PciBusDriverBindingStart (
Status = gBS->OpenProtocol (
Controller,
&gEfiPciRootBridgeIoProtocolGuid,
(VOID **) &PciRootBridgeIo,
(VOID **)&PciRootBridgeIo,
gPciBusDriverBinding.DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_GET_PROTOCOL
@@ -399,10 +400,10 @@ PciBusDriverBindingStart (
EFI_STATUS
EFIAPI
PciBusDriverBindingStop (
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN UINTN NumberOfChildren,
IN EFI_HANDLE *ChildHandleBuffer
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN UINTN NumberOfChildren,
IN EFI_HANDLE *ChildHandleBuffer
)
{
EFI_STATUS Status;
@@ -414,17 +415,17 @@ PciBusDriverBindingStop (
// Close the bus driver
//
gBS->CloseProtocol (
Controller,
&gEfiDevicePathProtocolGuid,
This->DriverBindingHandle,
Controller
);
Controller,
&gEfiDevicePathProtocolGuid,
This->DriverBindingHandle,
Controller
);
gBS->CloseProtocol (
Controller,
&gEfiPciRootBridgeIoProtocolGuid,
This->DriverBindingHandle,
Controller
);
Controller,
&gEfiPciRootBridgeIoProtocolGuid,
This->DriverBindingHandle,
Controller
);
DestroyRootBridgeByHandle (
Controller
@@ -440,7 +441,6 @@ PciBusDriverBindingStop (
AllChildrenStopped = TRUE;
for (Index = 0; Index < NumberOfChildren; Index++) {
//
// De register all the pci device
//
@@ -457,4 +457,3 @@ PciBusDriverBindingStop (
return EFI_SUCCESS;
}

245
MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h
View File

@@ -6,7 +6,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _EFI_PCI_BUS_H_
#define _EFI_PCI_BUS_H_
@@ -44,15 +43,15 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <IndustryStandard/PeImage.h>
#include <IndustryStandard/Acpi.h>
typedef struct _PCI_IO_DEVICE PCI_IO_DEVICE;
typedef struct _PCI_BAR PCI_BAR;
typedef struct _PCI_IO_DEVICE PCI_IO_DEVICE;
typedef struct _PCI_BAR PCI_BAR;
#define EFI_PCI_RID(Bus, Device, Function) (((UINT32)Bus << 8) + ((UINT32)Device << 3) + (UINT32)Function)
#define EFI_PCI_BUS_OF_RID(RID) ((UINT32)RID >> 8)
#define EFI_PCI_IOV_POLICY_ARI 0x0001
#define EFI_PCI_IOV_POLICY_SRIOV 0x0002
#define EFI_PCI_IOV_POLICY_MRIOV 0x0004
#define EFI_PCI_IOV_POLICY_ARI 0x0001
#define EFI_PCI_IOV_POLICY_SRIOV 0x0002
#define EFI_PCI_IOV_POLICY_MRIOV 0x0004
typedef enum {
PciBarTypeUnknown = 0,
@@ -81,11 +80,11 @@ typedef enum {
#include "PciHotPlugSupport.h"
#include "PciLib.h"
#define VGABASE1 0x3B0
#define VGALIMIT1 0x3BB
#define VGABASE1 0x3B0
#define VGALIMIT1 0x3BB
#define VGABASE2 0x3C0
#define VGALIMIT2 0x3DF
#define VGABASE2 0x3C0
#define VGALIMIT2 0x3DF
#define ISABASE 0x100
#define ISALIMIT 0x3FF
@@ -94,63 +93,63 @@ typedef enum {
// PCI BAR parameters
//
struct _PCI_BAR {
UINT64 BaseAddress;
UINT64 Length;
UINT64 Alignment;
PCI_BAR_TYPE BarType;
BOOLEAN BarTypeFixed;
UINT16 Offset;
UINT64 BaseAddress;
UINT64 Length;
UINT64 Alignment;
PCI_BAR_TYPE BarType;
BOOLEAN BarTypeFixed;
UINT16 Offset;
};
//
// defined in PCI Card Specification, 8.0
//
#define PCI_CARD_MEMORY_BASE_0 0x1C
#define PCI_CARD_MEMORY_LIMIT_0 0x20
#define PCI_CARD_MEMORY_BASE_1 0x24
#define PCI_CARD_MEMORY_LIMIT_1 0x28
#define PCI_CARD_IO_BASE_0_LOWER 0x2C
#define PCI_CARD_IO_BASE_0_UPPER 0x2E
#define PCI_CARD_IO_LIMIT_0_LOWER 0x30
#define PCI_CARD_IO_LIMIT_0_UPPER 0x32
#define PCI_CARD_IO_BASE_1_LOWER 0x34
#define PCI_CARD_IO_BASE_1_UPPER 0x36
#define PCI_CARD_IO_LIMIT_1_LOWER 0x38
#define PCI_CARD_IO_LIMIT_1_UPPER 0x3A
#define PCI_CARD_BRIDGE_CONTROL 0x3E
#define PCI_CARD_MEMORY_BASE_0 0x1C
#define PCI_CARD_MEMORY_LIMIT_0 0x20
#define PCI_CARD_MEMORY_BASE_1 0x24
#define PCI_CARD_MEMORY_LIMIT_1 0x28
#define PCI_CARD_IO_BASE_0_LOWER 0x2C
#define PCI_CARD_IO_BASE_0_UPPER 0x2E
#define PCI_CARD_IO_LIMIT_0_LOWER 0x30
#define PCI_CARD_IO_LIMIT_0_UPPER 0x32
#define PCI_CARD_IO_BASE_1_LOWER 0x34
#define PCI_CARD_IO_BASE_1_UPPER 0x36
#define PCI_CARD_IO_LIMIT_1_LOWER 0x38
#define PCI_CARD_IO_LIMIT_1_UPPER 0x3A
#define PCI_CARD_BRIDGE_CONTROL 0x3E
#define PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE BIT8
#define PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE BIT9
#define PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE BIT8
#define PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE BIT9
#define RB_IO_RANGE 1
#define RB_MEM32_RANGE 2
#define RB_PMEM32_RANGE 3
#define RB_MEM64_RANGE 4
#define RB_PMEM64_RANGE 5
#define RB_IO_RANGE 1
#define RB_MEM32_RANGE 2
#define RB_PMEM32_RANGE 3
#define RB_MEM64_RANGE 4
#define RB_PMEM64_RANGE 5
#define PPB_BAR_0 0
#define PPB_BAR_1 1
#define PPB_IO_RANGE 2
#define PPB_MEM32_RANGE 3
#define PPB_PMEM32_RANGE 4
#define PPB_PMEM64_RANGE 5
#define PPB_MEM64_RANGE 0xFF
#define PPB_BAR_0 0
#define PPB_BAR_1 1
#define PPB_IO_RANGE 2
#define PPB_MEM32_RANGE 3
#define PPB_PMEM32_RANGE 4
#define PPB_PMEM64_RANGE 5
#define PPB_MEM64_RANGE 0xFF
#define P2C_BAR_0 0
#define P2C_MEM_1 1
#define P2C_MEM_2 2
#define P2C_IO_1 3
#define P2C_IO_2 4
#define P2C_BAR_0 0
#define P2C_MEM_1 1
#define P2C_MEM_2 2
#define P2C_IO_1 3
#define P2C_IO_2 4
#define EFI_BRIDGE_IO32_DECODE_SUPPORTED 0x0001
#define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED 0x0002
#define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED 0x0004
#define EFI_BRIDGE_IO16_DECODE_SUPPORTED 0x0008
#define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED 0x0010
#define EFI_BRIDGE_MEM64_DECODE_SUPPORTED 0x0020
#define EFI_BRIDGE_MEM32_DECODE_SUPPORTED 0x0040
#define EFI_BRIDGE_IO32_DECODE_SUPPORTED 0x0001
#define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED 0x0002
#define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED 0x0004
#define EFI_BRIDGE_IO16_DECODE_SUPPORTED 0x0008
#define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED 0x0010
#define EFI_BRIDGE_MEM64_DECODE_SUPPORTED 0x0020
#define EFI_BRIDGE_MEM32_DECODE_SUPPORTED 0x0040
#define PCI_MAX_HOST_BRIDGE_NUM 0x0010
#define PCI_MAX_HOST_BRIDGE_NUM 0x0010
//
// Define option for attribute
@@ -158,130 +157,130 @@ struct _PCI_BAR {
#define EFI_SET_SUPPORTS 0
#define EFI_SET_ATTRIBUTES 1
#define PCI_IO_DEVICE_SIGNATURE SIGNATURE_32 ('p', 'c', 'i', 'o')
#define PCI_IO_DEVICE_SIGNATURE SIGNATURE_32 ('p', 'c', 'i', 'o')
struct _PCI_IO_DEVICE {
UINT32 Signature;
EFI_HANDLE Handle;
EFI_PCI_IO_PROTOCOL PciIo;
LIST_ENTRY Link;
UINT32 Signature;
EFI_HANDLE Handle;
EFI_PCI_IO_PROTOCOL PciIo;
LIST_ENTRY Link;
EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL PciDriverOverride;
EFI_DEVICE_PATH_PROTOCOL *DevicePath;
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
EFI_LOAD_FILE2_PROTOCOL LoadFile2;
EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL PciDriverOverride;
EFI_DEVICE_PATH_PROTOCOL *DevicePath;
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
EFI_LOAD_FILE2_PROTOCOL LoadFile2;
//
// PCI configuration space header type
//
PCI_TYPE00 Pci;
PCI_TYPE00 Pci;
//
// Bus number, Device number, Function number
//
UINT8 BusNumber;
UINT8 DeviceNumber;
UINT8 FunctionNumber;
UINT8 BusNumber;
UINT8 DeviceNumber;
UINT8 FunctionNumber;
//
// BAR for this PCI Device
//
PCI_BAR PciBar[PCI_MAX_BAR];
PCI_BAR PciBar[PCI_MAX_BAR];
//
// The bridge device this pci device is subject to
//
PCI_IO_DEVICE *Parent;
PCI_IO_DEVICE *Parent;
//
// A linked list for children Pci Device if it is bridge device
//
LIST_ENTRY ChildList;
LIST_ENTRY ChildList;
//
// TRUE if the PCI bus driver creates the handle for this PCI device
//
BOOLEAN Registered;
BOOLEAN Registered;
//
// TRUE if the PCI bus driver successfully allocates the resource required by
// this PCI device
//
BOOLEAN Allocated;
BOOLEAN Allocated;
//
// The attribute this PCI device currently set
//
UINT64 Attributes;
UINT64 Attributes;
//
// The attributes this PCI device actually supports
//
UINT64 Supports;
UINT64 Supports;
//
// The resource decode the bridge supports
//
UINT32 Decodes;
UINT32 Decodes;
//
// TRUE if the ROM image is from the PCI Option ROM BAR
//
BOOLEAN EmbeddedRom;
BOOLEAN EmbeddedRom;
//
// The OptionRom Size
//
UINT32 RomSize;
UINT32 RomSize;
//
// TRUE if all OpROM (in device or in platform specific position) have been processed
//
BOOLEAN AllOpRomProcessed;
BOOLEAN AllOpRomProcessed;
//
// TRUE if there is any EFI driver in the OptionRom
//
BOOLEAN BusOverride;
BOOLEAN BusOverride;
//
// A list tracking reserved resource on a bridge device
//
LIST_ENTRY ReservedResourceList;
LIST_ENTRY ReservedResourceList;
//
// A list tracking image handle of platform specific overriding driver
//
LIST_ENTRY OptionRomDriverList;
LIST_ENTRY OptionRomDriverList;
EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *ResourcePaddingDescriptors;
EFI_HPC_PADDING_ATTRIBUTES PaddingAttributes;
EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *ResourcePaddingDescriptors;
EFI_HPC_PADDING_ATTRIBUTES PaddingAttributes;
//
// Bus number ranges for a PCI Root Bridge device
//
EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *BusNumberRanges;
EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *BusNumberRanges;
BOOLEAN IsPciExp;
BOOLEAN IsPciExp;
//
// For SR-IOV
//
UINT8 PciExpressCapabilityOffset;
UINT32 AriCapabilityOffset;
UINT32 SrIovCapabilityOffset;
UINT32 MrIovCapabilityOffset;
PCI_BAR VfPciBar[PCI_MAX_BAR];
UINT32 SystemPageSize;
UINT16 InitialVFs;
UINT16 ReservedBusNum;
UINT8 PciExpressCapabilityOffset;
UINT32 AriCapabilityOffset;
UINT32 SrIovCapabilityOffset;
UINT32 MrIovCapabilityOffset;
PCI_BAR VfPciBar[PCI_MAX_BAR];
UINT32 SystemPageSize;
UINT16 InitialVFs;
UINT16 ReservedBusNum;
//
// Per PCI to PCI Bridge spec, I/O window is 4K aligned,
// but some chipsets support non-standard I/O window alignments less than 4K.
// This field is used to support this case.
//
UINT16 BridgeIoAlignment;
UINT32 ResizableBarOffset;
UINT32 ResizableBarNumber;
UINT16 BridgeIoAlignment;
UINT32 ResizableBarOffset;
UINT32 ResizableBarNumber;
};
#define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \
@@ -296,24 +295,22 @@ struct _PCI_IO_DEVICE {
#define PCI_IO_DEVICE_FROM_LOAD_FILE2_THIS(a) \
CR (a, PCI_IO_DEVICE, LoadFile2, PCI_IO_DEVICE_SIGNATURE)
//
// Global Variables
//
extern EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *gIncompatiblePciDeviceSupport;
extern EFI_DRIVER_BINDING_PROTOCOL gPciBusDriverBinding;
extern EFI_COMPONENT_NAME_PROTOCOL gPciBusComponentName;
extern EFI_COMPONENT_NAME2_PROTOCOL gPciBusComponentName2;
extern BOOLEAN gFullEnumeration;
extern UINTN gPciHostBridgeNumber;
extern EFI_HANDLE gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM];
extern UINT64 gAllOne;
extern UINT64 gAllZero;
extern EFI_PCI_PLATFORM_PROTOCOL *gPciPlatformProtocol;
extern EFI_PCI_OVERRIDE_PROTOCOL *gPciOverrideProtocol;
extern BOOLEAN mReserveIsaAliases;
extern BOOLEAN mReserveVgaAliases;
extern EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *gIncompatiblePciDeviceSupport;
extern EFI_DRIVER_BINDING_PROTOCOL gPciBusDriverBinding;
extern EFI_COMPONENT_NAME_PROTOCOL gPciBusComponentName;
extern EFI_COMPONENT_NAME2_PROTOCOL gPciBusComponentName2;
extern BOOLEAN gFullEnumeration;
extern UINTN gPciHostBridgeNumber;
extern EFI_HANDLE gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM];
extern UINT64 gAllOne;
extern UINT64 gAllZero;
extern EFI_PCI_PLATFORM_PROTOCOL *gPciPlatformProtocol;
extern EFI_PCI_OVERRIDE_PROTOCOL *gPciOverrideProtocol;
extern BOOLEAN mReserveIsaAliases;
extern BOOLEAN mReserveVgaAliases;
/**
Macro that checks whether device is a GFX device.
@@ -324,7 +321,7 @@ extern BOOLEAN mReserveVgaAliases;
@retval FALSE Device is not a GFX device.
**/
#define IS_PCI_GFX(_p) IS_CLASS2 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_OTHER)
#define IS_PCI_GFX(_p) IS_CLASS2 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_OTHER)
/**
Test to see if this driver supports ControllerHandle. Any ControllerHandle
@@ -343,9 +340,9 @@ extern BOOLEAN mReserveVgaAliases;
EFI_STATUS
EFIAPI
PciBusDriverBindingSupported (
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
);
/**
@@ -365,9 +362,9 @@ PciBusDriverBindingSupported (
EFI_STATUS
EFIAPI
PciBusDriverBindingStart (
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
);
/**
@@ -387,10 +384,10 @@ PciBusDriverBindingStart (
EFI_STATUS
EFIAPI
PciBusDriverBindingStop (
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN UINTN NumberOfChildren,
IN EFI_HANDLE *ChildHandleBuffer
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN UINTN NumberOfChildren,
IN EFI_HANDLE *ChildHandleBuffer
);
#endif

67
MdeModulePkg/Bus/Pci/PciBusDxe/PciCommand.c
View File

@@ -22,19 +22,19 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
EFI_STATUS
PciOperateRegister (
IN PCI_IO_DEVICE *PciIoDevice,
IN UINT16 Command,
IN UINT8 Offset,
IN UINT8 Operation,
OUT UINT16 *PtrCommand
IN PCI_IO_DEVICE *PciIoDevice,
IN UINT16 Command,
IN UINT8 Offset,
IN UINT8 Operation,
OUT UINT16 *PtrCommand
)
{
UINT16 OldCommand;
EFI_STATUS Status;
EFI_PCI_IO_PROTOCOL *PciIo;
UINT16 OldCommand;
EFI_STATUS Status;
EFI_PCI_IO_PROTOCOL *PciIo;
OldCommand = 0;
PciIo = &PciIoDevice->PciIo;
OldCommand = 0;
PciIo = &PciIoDevice->PciIo;
if (Operation != EFI_SET_REGISTER) {
Status = PciIo->Pci.Read (
@@ -52,9 +52,9 @@ PciOperateRegister (
}
if (Operation == EFI_ENABLE_REGISTER) {
OldCommand = (UINT16) (OldCommand | Command);
OldCommand = (UINT16)(OldCommand | Command);
} else if (Operation == EFI_DISABLE_REGISTER) {
OldCommand = (UINT16) (OldCommand & ~(Command));
OldCommand = (UINT16)(OldCommand & ~(Command));
} else {
OldCommand = Command;
}
@@ -124,10 +124,8 @@ LocateCapabilityRegBlock (
if (*Offset != 0) {
CapabilityPtr = *Offset;
} else {
CapabilityPtr = 0;
if (IS_CARDBUS_BRIDGE (&PciIoDevice->Pci)) {
PciIoDevice->PciIo.Pci.Read (
&PciIoDevice->PciIo,
EfiPciIoWidthUint8,
@@ -136,7 +134,6 @@ LocateCapabilityRegBlock (
&CapabilityPtr
);
} else {
PciIoDevice->PciIo.Pci.Read (
&PciIoDevice->PciIo,
EfiPciIoWidthUint8,
@@ -156,12 +153,12 @@ LocateCapabilityRegBlock (
&CapabilityEntry
);
CapabilityID = (UINT8) CapabilityEntry;
CapabilityID = (UINT8)CapabilityEntry;
if (CapabilityID == CapId) {
*Offset = CapabilityPtr;
if (NextRegBlock != NULL) {
*NextRegBlock = (UINT8) (CapabilityEntry >> 8);
*NextRegBlock = (UINT8)(CapabilityEntry >> 8);
}
return EFI_SUCCESS;
@@ -171,11 +168,11 @@ LocateCapabilityRegBlock (
// Certain PCI device may incorrectly have capability pointing to itself,
// break to avoid dead loop.
//
if (CapabilityPtr == (UINT8) (CapabilityEntry >> 8)) {
if (CapabilityPtr == (UINT8)(CapabilityEntry >> 8)) {
break;
}
CapabilityPtr = (UINT8) (CapabilityEntry >> 8);
CapabilityPtr = (UINT8)(CapabilityEntry >> 8);
}
return EFI_NOT_FOUND;
@@ -196,16 +193,16 @@ LocateCapabilityRegBlock (
**/
EFI_STATUS
LocatePciExpressCapabilityRegBlock (
IN PCI_IO_DEVICE *PciIoDevice,
IN UINT16 CapId,
IN OUT UINT32 *Offset,
OUT UINT32 *NextRegBlock OPTIONAL
IN PCI_IO_DEVICE *PciIoDevice,
IN UINT16 CapId,
IN OUT UINT32 *Offset,
OUT UINT32 *NextRegBlock OPTIONAL
)
{
EFI_STATUS Status;
UINT32 CapabilityPtr;
UINT32 CapabilityEntry;
UINT16 CapabilityID;
EFI_STATUS Status;
UINT32 CapabilityPtr;
UINT32 CapabilityEntry;
UINT16 CapabilityID;
//
// To check the capability of this device supports
@@ -225,13 +222,13 @@ LocatePciExpressCapabilityRegBlock (
// Mask it to DWORD alignment per PCI spec
//
CapabilityPtr &= 0xFFC;
Status = PciIoDevice->PciIo.Pci.Read (
&PciIoDevice->PciIo,
EfiPciIoWidthUint32,
CapabilityPtr,
1,
&CapabilityEntry
);
Status = PciIoDevice->PciIo.Pci.Read (
&PciIoDevice->PciIo,
EfiPciIoWidthUint32,
CapabilityPtr,
1,
&CapabilityEntry
);
if (EFI_ERROR (Status)) {
break;
}
@@ -249,7 +246,7 @@ LocatePciExpressCapabilityRegBlock (
break;
}
CapabilityID = (UINT16) CapabilityEntry;
CapabilityID = (UINT16)CapabilityEntry;
if (CapabilityID == CapId) {
*Offset = CapabilityPtr;

42
MdeModulePkg/Bus/Pci/PciBusDxe/PciCommand.h
View File

@@ -6,7 +6,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _EFI_PCI_COMMAND_H_
#define _EFI_PCI_COMMAND_H_
@@ -16,7 +15,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
// They should be cleared at the beginning. The other registers
// are owned by chipset, we should not touch them.
//
#define EFI_PCI_COMMAND_BITS_OWNED ( \
#define EFI_PCI_COMMAND_BITS_OWNED ( \
EFI_PCI_COMMAND_IO_SPACE | \
EFI_PCI_COMMAND_MEMORY_SPACE | \
EFI_PCI_COMMAND_BUS_MASTER | \
@@ -31,7 +30,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
// They should be cleared at the beginning. The other registers
// are owned by chipset, we should not touch them.
//
#define EFI_PCI_BRIDGE_CONTROL_BITS_OWNED ( \
#define EFI_PCI_BRIDGE_CONTROL_BITS_OWNED ( \
EFI_PCI_BRIDGE_CONTROL_ISA | \
EFI_PCI_BRIDGE_CONTROL_VGA | \
EFI_PCI_BRIDGE_CONTROL_VGA_16 | \
@@ -44,13 +43,12 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
// They should be cleared at the beginning. The other registers
// are owned by chipset, we should not touch them.
//
#define EFI_PCCARD_BRIDGE_CONTROL_BITS_OWNED ( \
#define EFI_PCCARD_BRIDGE_CONTROL_BITS_OWNED ( \
EFI_PCI_BRIDGE_CONTROL_ISA | \
EFI_PCI_BRIDGE_CONTROL_VGA | \
EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK \
)
#define EFI_GET_REGISTER 1
#define EFI_SET_REGISTER 2
#define EFI_ENABLE_REGISTER 3
@@ -70,11 +68,11 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
EFI_STATUS
PciOperateRegister (
IN PCI_IO_DEVICE *PciIoDevice,
IN UINT16 Command,
IN UINT8 Offset,
IN UINT8 Operation,
OUT UINT16 *PtrCommand
IN PCI_IO_DEVICE *PciIoDevice,
IN UINT16 Command,
IN UINT8 Offset,
IN UINT8 Operation,
OUT UINT16 *PtrCommand
);
/**
@@ -127,10 +125,10 @@ LocateCapabilityRegBlock (
**/
EFI_STATUS
LocatePciExpressCapabilityRegBlock (
IN PCI_IO_DEVICE *PciIoDevice,
IN UINT16 CapId,
IN OUT UINT32 *Offset,
OUT UINT32 *NextRegBlock OPTIONAL
IN PCI_IO_DEVICE *PciIoDevice,
IN UINT16 CapId,
IN OUT UINT32 *Offset,
OUT UINT32 *NextRegBlock OPTIONAL
);
/**
@@ -142,7 +140,7 @@ LocatePciExpressCapabilityRegBlock (
@return status of PciIo operation
**/
#define PCI_READ_COMMAND_REGISTER(a,b) \
#define PCI_READ_COMMAND_REGISTER(a, b) \
PciOperateRegister (a, 0, PCI_COMMAND_OFFSET, EFI_GET_REGISTER, b)
/**
@@ -154,7 +152,7 @@ LocatePciExpressCapabilityRegBlock (
@return status of PciIo operation
**/
#define PCI_SET_COMMAND_REGISTER(a,b) \
#define PCI_SET_COMMAND_REGISTER(a, b) \
PciOperateRegister (a, b, PCI_COMMAND_OFFSET, EFI_SET_REGISTER, NULL)
/**
@@ -166,7 +164,7 @@ LocatePciExpressCapabilityRegBlock (
@return status of PciIo operation
**/
#define PCI_ENABLE_COMMAND_REGISTER(a,b) \
#define PCI_ENABLE_COMMAND_REGISTER(a, b) \
PciOperateRegister (a, b, PCI_COMMAND_OFFSET, EFI_ENABLE_REGISTER, NULL)
/**
@@ -178,7 +176,7 @@ LocatePciExpressCapabilityRegBlock (
@return status of PciIo operation
**/
#define PCI_DISABLE_COMMAND_REGISTER(a,b) \
#define PCI_DISABLE_COMMAND_REGISTER(a, b) \
PciOperateRegister (a, b, PCI_COMMAND_OFFSET, EFI_DISABLE_REGISTER, NULL)
/**
@@ -190,7 +188,7 @@ LocatePciExpressCapabilityRegBlock (
@return status of PciIo operation
**/
#define PCI_READ_BRIDGE_CONTROL_REGISTER(a,b) \
#define PCI_READ_BRIDGE_CONTROL_REGISTER(a, b) \
PciOperateRegister (a, 0, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_GET_REGISTER, b)
/**
@@ -202,7 +200,7 @@ LocatePciExpressCapabilityRegBlock (
@return status of PciIo operation
**/
#define PCI_SET_BRIDGE_CONTROL_REGISTER(a,b) \
#define PCI_SET_BRIDGE_CONTROL_REGISTER(a, b) \
PciOperateRegister (a, b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_SET_REGISTER, NULL)
/**
@@ -214,7 +212,7 @@ LocatePciExpressCapabilityRegBlock (
@return status of PciIo operation
**/
#define PCI_ENABLE_BRIDGE_CONTROL_REGISTER(a,b) \
#define PCI_ENABLE_BRIDGE_CONTROL_REGISTER(a, b) \
PciOperateRegister (a, b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_ENABLE_REGISTER, NULL)
/**
@@ -226,7 +224,7 @@ LocatePciExpressCapabilityRegBlock (
@return status of PciIo operation
**/
#define PCI_DISABLE_BRIDGE_CONTROL_REGISTER(a,b) \
#define PCI_DISABLE_BRIDGE_CONTROL_REGISTER(a, b) \
PciOperateRegister (a, b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_DISABLE_REGISTER, NULL)
#endif

214
MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c
View File

@@ -35,7 +35,7 @@ InitializePciDevicePool (
**/
VOID
InsertRootBridge (
IN PCI_IO_DEVICE *RootBridge
IN PCI_IO_DEVICE *RootBridge
)
{
InsertTailList (&mPciDevicePool, &(RootBridge->Link));
@@ -51,8 +51,8 @@ InsertRootBridge (
**/
VOID
InsertPciDevice (
IN PCI_IO_DEVICE *Bridge,
IN PCI_IO_DEVICE *PciDeviceNode
IN PCI_IO_DEVICE *Bridge,
IN PCI_IO_DEVICE *PciDeviceNode
)
{
InsertTailList (&Bridge->ChildList, &(PciDeviceNode->Link));
@@ -67,7 +67,7 @@ InsertPciDevice (
**/
VOID
DestroyRootBridge (
IN PCI_IO_DEVICE *RootBridge
IN PCI_IO_DEVICE *RootBridge
)
{
DestroyPciDeviceTree (RootBridge);
@@ -85,7 +85,7 @@ DestroyRootBridge (
**/
VOID
FreePciDevice (
IN PCI_IO_DEVICE *PciIoDevice
IN PCI_IO_DEVICE *PciIoDevice
)
{
ASSERT (PciIoDevice != NULL);
@@ -116,14 +116,13 @@ FreePciDevice (
**/
VOID
DestroyPciDeviceTree (
IN PCI_IO_DEVICE *Bridge
IN PCI_IO_DEVICE *Bridge
)
{
LIST_ENTRY *CurrentLink;
PCI_IO_DEVICE *Temp;
LIST_ENTRY *CurrentLink;
PCI_IO_DEVICE *Temp;
while (!IsListEmpty (&Bridge->ChildList)) {
CurrentLink = Bridge->ChildList.ForwardLink;
//
@@ -156,12 +155,11 @@ DestroyPciDeviceTree (
**/
EFI_STATUS
DestroyRootBridgeByHandle (
IN EFI_HANDLE Controller
IN EFI_HANDLE Controller
)
{
LIST_ENTRY *CurrentLink;
PCI_IO_DEVICE *Temp;
LIST_ENTRY *CurrentLink;
PCI_IO_DEVICE *Temp;
CurrentLink = mPciDevicePool.ForwardLink;
@@ -169,7 +167,6 @@ DestroyRootBridgeByHandle (
Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
if (Temp->Handle == Controller) {
RemoveEntryList (CurrentLink);
DestroyPciDeviceTree (Temp);
@@ -202,17 +199,17 @@ DestroyRootBridgeByHandle (
**/
EFI_STATUS
RegisterPciDevice (
IN EFI_HANDLE Controller,
IN PCI_IO_DEVICE *PciIoDevice,
OUT EFI_HANDLE *Handle OPTIONAL
IN EFI_HANDLE Controller,
IN PCI_IO_DEVICE *PciIoDevice,
OUT EFI_HANDLE *Handle OPTIONAL
)
{
EFI_STATUS Status;
VOID *PlatformOpRomBuffer;
UINTN PlatformOpRomSize;
EFI_PCI_IO_PROTOCOL *PciIo;
UINT8 Data8;
BOOLEAN HasEfiImage;
EFI_STATUS Status;
VOID *PlatformOpRomBuffer;
UINTN PlatformOpRomSize;
EFI_PCI_IO_PROTOCOL *PciIo;
UINT8 Data8;
BOOLEAN HasEfiImage;
//
// Install the pciio protocol, device path protocol
@@ -240,7 +237,6 @@ RegisterPciDevice (
// Process OpRom
//
if (!PciIoDevice->AllOpRomProcessed) {
//
// Get the OpRom provided by platform
//
@@ -253,7 +249,7 @@ RegisterPciDevice (
);
if (!EFI_ERROR (Status)) {
PciIoDevice->EmbeddedRom = FALSE;
PciIoDevice->RomSize = (UINT32) PlatformOpRomSize;
PciIoDevice->RomSize = (UINT32)PlatformOpRomSize;
PciIoDevice->PciIo.RomSize = PlatformOpRomSize;
PciIoDevice->PciIo.RomImage = PlatformOpRomBuffer;
//
@@ -279,7 +275,7 @@ RegisterPciDevice (
);
if (!EFI_ERROR (Status)) {
PciIoDevice->EmbeddedRom = FALSE;
PciIoDevice->RomSize = (UINT32) PlatformOpRomSize;
PciIoDevice->RomSize = (UINT32)PlatformOpRomSize;
PciIoDevice->PciIo.RomSize = PlatformOpRomSize;
PciIoDevice->PciIo.RomImage = PlatformOpRomBuffer;
//
@@ -324,9 +320,7 @@ RegisterPciDevice (
}
}
if (!PciIoDevice->AllOpRomProcessed) {
PciIoDevice->AllOpRomProcessed = TRUE;
//
@@ -374,7 +368,7 @@ RegisterPciDevice (
Status = gBS->OpenProtocol (
Controller,
&gEfiPciRootBridgeIoProtocolGuid,
(VOID **) &(PciIoDevice->PciRootBridgeIo),
(VOID **)&(PciIoDevice->PciRootBridgeIo),
gPciBusDriverBinding.DriverBindingHandle,
PciIoDevice->Handle,
EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER
@@ -405,15 +399,14 @@ RegisterPciDevice (
**/
VOID
RemoveAllPciDeviceOnBridge (
EFI_HANDLE RootBridgeHandle,
PCI_IO_DEVICE *Bridge
EFI_HANDLE RootBridgeHandle,
PCI_IO_DEVICE *Bridge
)
{
LIST_ENTRY *CurrentLink;
PCI_IO_DEVICE *Temp;
LIST_ENTRY *CurrentLink;
PCI_IO_DEVICE *Temp;
while (!IsListEmpty (&Bridge->ChildList)) {
CurrentLink = Bridge->ChildList.ForwardLink;
Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
@@ -453,22 +446,22 @@ RemoveAllPciDeviceOnBridge (
**/
EFI_STATUS
DeRegisterPciDevice (
IN EFI_HANDLE Controller,
IN EFI_HANDLE Handle
IN EFI_HANDLE Controller,
IN EFI_HANDLE Handle
)
{
EFI_PCI_IO_PROTOCOL *PciIo;
EFI_STATUS Status;
PCI_IO_DEVICE *PciIoDevice;
PCI_IO_DEVICE *Node;
LIST_ENTRY *CurrentLink;
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
EFI_PCI_IO_PROTOCOL *PciIo;
EFI_STATUS Status;
PCI_IO_DEVICE *PciIoDevice;
PCI_IO_DEVICE *Node;
LIST_ENTRY *CurrentLink;
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
Status = gBS->OpenProtocol (
Handle,
&gEfiPciIoProtocolGuid,
(VOID **) &PciIo,
(VOID **)&PciIo,
gPciBusDriverBinding.DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_GET_PROTOCOL
@@ -488,12 +481,11 @@ DeRegisterPciDevice (
//
if (!IsListEmpty (&PciIoDevice->ChildList)) {
CurrentLink = PciIoDevice->ChildList.ForwardLink;
while (CurrentLink != NULL && CurrentLink != &PciIoDevice->ChildList) {
Node = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
Status = DeRegisterPciDevice (Controller, Node->Handle);
Node = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
Status = DeRegisterPciDevice (Controller, Node->Handle);
if (EFI_ERROR (Status)) {
return Status;
@@ -559,22 +551,22 @@ DeRegisterPciDevice (
NULL
);
}
//
// Restore Status
//
Status = EFI_SUCCESS;
}
if (EFI_ERROR (Status)) {
gBS->OpenProtocol (
Controller,
&gEfiPciRootBridgeIoProtocolGuid,
(VOID **) &PciRootBridgeIo,
gPciBusDriverBinding.DriverBindingHandle,
Handle,
EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER
);
Controller,
&gEfiPciRootBridgeIoProtocolGuid,
(VOID **)&PciRootBridgeIo,
gPciBusDriverBinding.DriverBindingHandle,
Handle,
EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER
);
return Status;
}
@@ -586,7 +578,6 @@ DeRegisterPciDevice (
PciIoDevice->Registered = FALSE;
PciIoDevice->Handle = NULL;
} else {
//
// Handle may be closed before
//
@@ -613,11 +604,11 @@ DeRegisterPciDevice (
**/
EFI_STATUS
StartPciDevicesOnBridge (
IN EFI_HANDLE Controller,
IN PCI_IO_DEVICE *RootBridge,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath,
IN OUT UINT8 *NumberOfChildren,
IN OUT EFI_HANDLE *ChildHandleBuffer
IN EFI_HANDLE Controller,
IN PCI_IO_DEVICE *RootBridge,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath,
IN OUT UINT8 *NumberOfChildren,
IN OUT EFI_HANDLE *ChildHandleBuffer
)
{
@@ -632,14 +623,13 @@ StartPciDevicesOnBridge (
CurrentLink = RootBridge->ChildList.ForwardLink;
while (CurrentLink != NULL && CurrentLink != &RootBridge->ChildList) {
PciIoDevice = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
if (RemainingDevicePath != NULL) {
Node.DevPath = RemainingDevicePath;
if (Node.Pci->Device != PciIoDevice->DeviceNumber ||
Node.Pci->Function != PciIoDevice->FunctionNumber) {
if ((Node.Pci->Device != PciIoDevice->DeviceNumber) ||
(Node.Pci->Function != PciIoDevice->FunctionNumber))
{
CurrentLink = CurrentLink->ForwardLink;
continue;
}
@@ -661,10 +651,9 @@ StartPciDevicesOnBridge (
PciIoDevice,
NULL
);
}
if (NumberOfChildren != NULL && ChildHandleBuffer != NULL && PciIoDevice->Registered) {
if ((NumberOfChildren != NULL) && (ChildHandleBuffer != NULL) && PciIoDevice->Registered) {
ChildHandleBuffer[*NumberOfChildren] = PciIoDevice->Handle;
(*NumberOfChildren)++;
}
@@ -705,15 +694,12 @@ StartPciDevicesOnBridge (
return Status;
} else {
//
// Currently, the PCI bus driver only support PCI-PCI bridge
//
return EFI_UNSUPPORTED;
}
} else {
//
// If remaining device path is NULL,
// try to enable all the pci devices under this bridge
@@ -724,10 +710,9 @@ StartPciDevicesOnBridge (
PciIoDevice,
NULL
);
}
if (NumberOfChildren != NULL && ChildHandleBuffer != NULL && PciIoDevice->Registered) {
if ((NumberOfChildren != NULL) && (ChildHandleBuffer != NULL) && PciIoDevice->Registered) {
ChildHandleBuffer[*NumberOfChildren] = PciIoDevice->Handle;
(*NumberOfChildren)++;
}
@@ -754,7 +739,6 @@ StartPciDevicesOnBridge (
Supports,
NULL
);
}
CurrentLink = CurrentLink->ForwardLink;
@@ -780,12 +764,12 @@ StartPciDevicesOnBridge (
**/
EFI_STATUS
StartPciDevices (
IN EFI_HANDLE Controller
IN EFI_HANDLE Controller
)
{
PCI_IO_DEVICE *RootBridge;
EFI_HANDLE ThisHostBridge;
LIST_ENTRY *CurrentLink;
PCI_IO_DEVICE *RootBridge;
EFI_HANDLE ThisHostBridge;
LIST_ENTRY *CurrentLink;
RootBridge = GetRootBridgeByHandle (Controller);
ASSERT (RootBridge != NULL);
@@ -794,19 +778,18 @@ StartPciDevices (
CurrentLink = mPciDevicePool.ForwardLink;
while (CurrentLink != NULL && CurrentLink != &mPciDevicePool) {
RootBridge = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
//
// Locate the right root bridge to start
//
if (RootBridge->PciRootBridgeIo->ParentHandle == ThisHostBridge) {
StartPciDevicesOnBridge (
RootBridge->Handle,
RootBridge,
NULL,
NULL,
NULL
);
RootBridge->Handle,
RootBridge,
NULL,
NULL,
NULL
);
}
CurrentLink = CurrentLink->ForwardLink;
@@ -826,27 +809,27 @@ StartPciDevices (
**/
PCI_IO_DEVICE *
CreateRootBridge (
IN EFI_HANDLE RootBridgeHandle
IN EFI_HANDLE RootBridgeHandle
)
{
EFI_STATUS Status;
PCI_IO_DEVICE *Dev;
EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath;
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
EFI_STATUS Status;
PCI_IO_DEVICE *Dev;
EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath;
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
Dev = AllocateZeroPool (sizeof (PCI_IO_DEVICE));
if (Dev == NULL) {
return NULL;
}
Dev->Signature = PCI_IO_DEVICE_SIGNATURE;
Dev->Handle = RootBridgeHandle;
Dev->Signature = PCI_IO_DEVICE_SIGNATURE;
Dev->Handle = RootBridgeHandle;
InitializeListHead (&Dev->ChildList);
Status = gBS->OpenProtocol (
RootBridgeHandle,
&gEfiDevicePathProtocolGuid,
(VOID **) &ParentDevicePath,
(VOID **)&ParentDevicePath,
gPciBusDriverBinding.DriverBindingHandle,
RootBridgeHandle,
EFI_OPEN_PROTOCOL_GET_PROTOCOL
@@ -868,7 +851,7 @@ CreateRootBridge (
Status = gBS->OpenProtocol (
RootBridgeHandle,
&gEfiPciRootBridgeIoProtocolGuid,
(VOID **) &PciRootBridgeIo,
(VOID **)&PciRootBridgeIo,
gPciBusDriverBinding.DriverBindingHandle,
RootBridgeHandle,
EFI_OPEN_PROTOCOL_GET_PROTOCOL
@@ -909,16 +892,15 @@ CreateRootBridge (
**/
PCI_IO_DEVICE *
GetRootBridgeByHandle (
EFI_HANDLE RootBridgeHandle
EFI_HANDLE RootBridgeHandle
)
{
PCI_IO_DEVICE *RootBridgeDev;
LIST_ENTRY *CurrentLink;
PCI_IO_DEVICE *RootBridgeDev;
LIST_ENTRY *CurrentLink;
CurrentLink = mPciDevicePool.ForwardLink;
while (CurrentLink != NULL && CurrentLink != &mPciDevicePool) {
RootBridgeDev = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
if (RootBridgeDev->Handle == RootBridgeHandle) {
return RootBridgeDev;
@@ -942,18 +924,16 @@ GetRootBridgeByHandle (
**/
BOOLEAN
PciDeviceExisted (
IN PCI_IO_DEVICE *Bridge,
IN PCI_IO_DEVICE *PciIoDevice
IN PCI_IO_DEVICE *Bridge,
IN PCI_IO_DEVICE *PciIoDevice
)
{
PCI_IO_DEVICE *Temp;
LIST_ENTRY *CurrentLink;
PCI_IO_DEVICE *Temp;
LIST_ENTRY *CurrentLink;
CurrentLink = Bridge->ChildList.ForwardLink;
while (CurrentLink != NULL && CurrentLink != &Bridge->ChildList) {
Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
if (Temp == PciIoDevice) {
@@ -982,20 +962,18 @@ PciDeviceExisted (
**/
PCI_IO_DEVICE *
LocateVgaDeviceOnHostBridge (
IN EFI_HANDLE HostBridgeHandle
IN EFI_HANDLE HostBridgeHandle
)
{
LIST_ENTRY *CurrentLink;
PCI_IO_DEVICE *PciIoDevice;
LIST_ENTRY *CurrentLink;
PCI_IO_DEVICE *PciIoDevice;
CurrentLink = mPciDevicePool.ForwardLink;
while (CurrentLink != NULL && CurrentLink != &mPciDevicePool) {
PciIoDevice = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
if (PciIoDevice->PciRootBridgeIo->ParentHandle== HostBridgeHandle) {
if (PciIoDevice->PciRootBridgeIo->ParentHandle == HostBridgeHandle) {
PciIoDevice = LocateVgaDevice (PciIoDevice);
if (PciIoDevice != NULL) {
@@ -1019,28 +997,27 @@ LocateVgaDeviceOnHostBridge (
**/
PCI_IO_DEVICE *
LocateVgaDevice (
IN PCI_IO_DEVICE *Bridge
IN PCI_IO_DEVICE *Bridge
)
{
LIST_ENTRY *CurrentLink;
PCI_IO_DEVICE *PciIoDevice;
LIST_ENTRY *CurrentLink;
PCI_IO_DEVICE *PciIoDevice;
CurrentLink = Bridge->ChildList.ForwardLink;
while (CurrentLink != NULL && CurrentLink != &Bridge->ChildList) {
PciIoDevice = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
if (IS_PCI_VGA(&PciIoDevice->Pci) &&
(PciIoDevice->Attributes &
(EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY |
EFI_PCI_IO_ATTRIBUTE_VGA_IO |
EFI_PCI_IO_ATTRIBUTE_VGA_IO_16)) != 0) {
if (IS_PCI_VGA (&PciIoDevice->Pci) &&
((PciIoDevice->Attributes &
(EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY |
EFI_PCI_IO_ATTRIBUTE_VGA_IO |
EFI_PCI_IO_ATTRIBUTE_VGA_IO_16)) != 0))
{
return PciIoDevice;
}
if (IS_PCI_BRIDGE (&PciIoDevice->Pci)) {
PciIoDevice = LocateVgaDevice (PciIoDevice);
if (PciIoDevice != NULL) {
@@ -1053,4 +1030,3 @@ LocateVgaDevice (
return NULL;
}

54
MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.h
View File

@@ -26,7 +26,7 @@ InitializePciDevicePool (
**/
VOID
InsertRootBridge (
IN PCI_IO_DEVICE *RootBridge
IN PCI_IO_DEVICE *RootBridge
);
/**
@@ -39,8 +39,8 @@ InsertRootBridge (
**/
VOID
InsertPciDevice (
IN PCI_IO_DEVICE *Bridge,
IN PCI_IO_DEVICE *PciDeviceNode
IN PCI_IO_DEVICE *Bridge,
IN PCI_IO_DEVICE *PciDeviceNode
);
/**
@@ -51,7 +51,7 @@ InsertPciDevice (
**/
VOID
DestroyRootBridge (
IN PCI_IO_DEVICE *RootBridge
IN PCI_IO_DEVICE *RootBridge
);
/**
@@ -63,7 +63,7 @@ DestroyRootBridge (
**/
VOID
DestroyPciDeviceTree (
IN PCI_IO_DEVICE *Bridge
IN PCI_IO_DEVICE *Bridge
);
/**
@@ -81,7 +81,7 @@ DestroyPciDeviceTree (
**/
EFI_STATUS
DestroyRootBridgeByHandle (
IN EFI_HANDLE Controller
IN EFI_HANDLE Controller
);
/**
@@ -101,9 +101,9 @@ DestroyRootBridgeByHandle (
**/
EFI_STATUS
RegisterPciDevice (
IN EFI_HANDLE Controller,
IN PCI_IO_DEVICE *PciIoDevice,
OUT EFI_HANDLE *Handle OPTIONAL
IN EFI_HANDLE Controller,
IN PCI_IO_DEVICE *PciIoDevice,
OUT EFI_HANDLE *Handle OPTIONAL
);
/**
@@ -116,8 +116,8 @@ RegisterPciDevice (
**/
VOID
RemoveAllPciDeviceOnBridge (
EFI_HANDLE RootBridgeHandle,
PCI_IO_DEVICE *Bridge
EFI_HANDLE RootBridgeHandle,
PCI_IO_DEVICE *Bridge
);
/**
@@ -135,8 +135,8 @@ RemoveAllPciDeviceOnBridge (
**/
EFI_STATUS
DeRegisterPciDevice (
IN EFI_HANDLE Controller,
IN EFI_HANDLE Handle
IN EFI_HANDLE Controller,
IN EFI_HANDLE Handle
);
/**
@@ -156,11 +156,11 @@ DeRegisterPciDevice (
**/
EFI_STATUS
StartPciDevicesOnBridge (
IN EFI_HANDLE Controller,
IN PCI_IO_DEVICE *RootBridge,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath,
IN OUT UINT8 *NumberOfChildren,
IN OUT EFI_HANDLE *ChildHandleBuffer
IN EFI_HANDLE Controller,
IN PCI_IO_DEVICE *RootBridge,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath,
IN OUT UINT8 *NumberOfChildren,
IN OUT EFI_HANDLE *ChildHandleBuffer
);
/**
@@ -175,7 +175,7 @@ StartPciDevicesOnBridge (
**/
EFI_STATUS
StartPciDevices (
IN EFI_HANDLE Controller
IN EFI_HANDLE Controller
);
/**
@@ -189,7 +189,7 @@ StartPciDevices (
**/
PCI_IO_DEVICE *
CreateRootBridge (
IN EFI_HANDLE RootBridgeHandle
IN EFI_HANDLE RootBridgeHandle
);
/**
@@ -203,10 +203,9 @@ CreateRootBridge (
**/
PCI_IO_DEVICE *
GetRootBridgeByHandle (
EFI_HANDLE RootBridgeHandle
EFI_HANDLE RootBridgeHandle
);
/**
Judge whether Pci device existed.
@@ -219,8 +218,8 @@ GetRootBridgeByHandle (
**/
BOOLEAN
PciDeviceExisted (
IN PCI_IO_DEVICE *Bridge,
IN PCI_IO_DEVICE *PciIoDevice
IN PCI_IO_DEVICE *Bridge,
IN PCI_IO_DEVICE *PciIoDevice
);
/**
@@ -233,7 +232,7 @@ PciDeviceExisted (
**/
PCI_IO_DEVICE *
LocateVgaDeviceOnHostBridge (
IN EFI_HANDLE HostBridgeHandle
IN EFI_HANDLE HostBridgeHandle
);
/**
@@ -246,10 +245,9 @@ LocateVgaDeviceOnHostBridge (
**/
PCI_IO_DEVICE *
LocateVgaDevice (
IN PCI_IO_DEVICE *Bridge
IN PCI_IO_DEVICE *Bridge
);
/**
Destroy a pci device node.
@@ -260,7 +258,7 @@ LocateVgaDevice (
**/
VOID
FreePciDevice (
IN PCI_IO_DEVICE *PciIoDevice
IN PCI_IO_DEVICE *PciIoDevice
);
#endif

49
MdeModulePkg/Bus/Pci/PciBusDxe/PciDriverOverride.c
View File

@@ -16,7 +16,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
VOID
InitializePciDriverOverrideInstance (
IN OUT PCI_IO_DEVICE *PciIoDevice
IN OUT PCI_IO_DEVICE *PciIoDevice
)
{
PciIoDevice->PciDriverOverride.GetDriver = GetDriver;
@@ -31,16 +31,16 @@ InitializePciDriverOverrideInstance (
**/
EFI_HANDLE
LocateImageHandle (
IN EFI_DEVICE_PATH_PROTOCOL *ImagePath
IN EFI_DEVICE_PATH_PROTOCOL *ImagePath
)
{
EFI_STATUS Status;
EFI_HANDLE *Handles;
UINTN Index;
UINTN HandleNum;
EFI_DEVICE_PATH_PROTOCOL *DevicePath;
UINTN ImagePathSize;
EFI_HANDLE ImageHandle;
EFI_STATUS Status;
EFI_HANDLE *Handles;
UINTN Index;
UINTN HandleNum;
EFI_DEVICE_PATH_PROTOCOL *DevicePath;
UINTN ImagePathSize;
EFI_HANDLE ImageHandle;
Status = gBS->LocateHandleBuffer (
ByProtocol,
@@ -57,13 +57,15 @@ LocateImageHandle (
ImagePathSize = GetDevicePathSize (ImagePath);
for (Index = 0; Index < HandleNum; Index++) {
Status = gBS->HandleProtocol (Handles[Index], &gEfiLoadedImageDevicePathProtocolGuid, (VOID **) &DevicePath);
Status = gBS->HandleProtocol (Handles[Index], &gEfiLoadedImageDevicePathProtocolGuid, (VOID **)&DevicePath);
if (EFI_ERROR (Status)) {
continue;
}
if ((ImagePathSize == GetDevicePathSize (DevicePath)) &&
(CompareMem (ImagePath, DevicePath, ImagePathSize) == 0)
) {
)
{
ImageHandle = Handles[Index];
break;
}
@@ -92,8 +94,8 @@ LocateImageHandle (
EFI_STATUS
EFIAPI
GetDriver (
IN EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL *This,
IN OUT EFI_HANDLE *DriverImageHandle
IN EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL *This,
IN OUT EFI_HANDLE *DriverImageHandle
)
{
PCI_IO_DEVICE *PciIoDevice;
@@ -103,12 +105,12 @@ GetDriver (
Override = NULL;
PciIoDevice = PCI_IO_DEVICE_FROM_PCI_DRIVER_OVERRIDE_THIS (This);
ReturnNext = (BOOLEAN) (*DriverImageHandle == NULL);
ReturnNext = (BOOLEAN)(*DriverImageHandle == NULL);
for ( Link = GetFirstNode (&PciIoDevice->OptionRomDriverList)
; !IsNull (&PciIoDevice->OptionRomDriverList, Link)
; Link = GetNextNode (&PciIoDevice->OptionRomDriverList, Link)
) {
; !IsNull (&PciIoDevice->OptionRomDriverList, Link)
; Link = GetNextNode (&PciIoDevice->OptionRomDriverList, Link)
)
{
Override = DRIVER_OVERRIDE_FROM_LINK (Link);
if (ReturnNext) {
@@ -159,12 +161,12 @@ GetDriver (
**/
EFI_STATUS
AddDriver (
IN PCI_IO_DEVICE *PciIoDevice,
IN EFI_HANDLE DriverImageHandle,
IN EFI_DEVICE_PATH_PROTOCOL *DriverImagePath
IN PCI_IO_DEVICE *PciIoDevice,
IN EFI_HANDLE DriverImageHandle,
IN EFI_DEVICE_PATH_PROTOCOL *DriverImagePath
)
{
PCI_DRIVER_OVERRIDE_LIST *Node;
PCI_DRIVER_OVERRIDE_LIST *Node;
//
// Caller should pass in either Image Handle or Image Path, but not both.
@@ -182,7 +184,6 @@ AddDriver (
InsertTailList (&PciIoDevice->OptionRomDriverList, &Node->Link);
PciIoDevice->BusOverride = TRUE;
PciIoDevice->BusOverride = TRUE;
return EFI_SUCCESS;
}

25
MdeModulePkg/Bus/Pci/PciBusDxe/PciDriverOverride.h
View File

@@ -6,23 +6,21 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _EFI_PCI_DRIVER_OVERRRIDE_H_
#define _EFI_PCI_DRIVER_OVERRRIDE_H_
#define DRIVER_OVERRIDE_SIGNATURE SIGNATURE_32 ('d', 'r', 'o', 'v')
#define DRIVER_OVERRIDE_SIGNATURE SIGNATURE_32 ('d', 'r', 'o', 'v')
//
// PCI driver override driver image list
//
typedef struct {
UINT32 Signature;
LIST_ENTRY Link;
EFI_HANDLE DriverImageHandle;
EFI_DEVICE_PATH_PROTOCOL *DriverImagePath;
UINT32 Signature;
LIST_ENTRY Link;
EFI_HANDLE DriverImageHandle;
EFI_DEVICE_PATH_PROTOCOL *DriverImagePath;
} PCI_DRIVER_OVERRIDE_LIST;
#define DRIVER_OVERRIDE_FROM_LINK(a) \
CR (a, PCI_DRIVER_OVERRIDE_LIST, Link, DRIVER_OVERRIDE_SIGNATURE)
@@ -34,7 +32,7 @@ typedef struct {
**/
VOID
InitializePciDriverOverrideInstance (
IN OUT PCI_IO_DEVICE *PciIoDevice
IN OUT PCI_IO_DEVICE *PciIoDevice
);
/**
@@ -51,12 +49,11 @@ InitializePciDriverOverrideInstance (
**/
EFI_STATUS
AddDriver (
IN PCI_IO_DEVICE *PciIoDevice,
IN EFI_HANDLE DriverImageHandle,
IN EFI_DEVICE_PATH_PROTOCOL *DriverImagePath
IN PCI_IO_DEVICE *PciIoDevice,
IN EFI_HANDLE DriverImageHandle,
IN EFI_DEVICE_PATH_PROTOCOL *DriverImagePath
);
/**
Uses a bus specific algorithm to retrieve a driver image handle for a controller.
@@ -76,8 +73,8 @@ AddDriver (
EFI_STATUS
EFIAPI
GetDriver (
IN EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL *This,
IN OUT EFI_HANDLE *DriverImageHandle
IN EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL *This,
IN OUT EFI_HANDLE *DriverImageHandle
);
#endif

726
MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.c
View File

File diff suppressed because it is too large Load Diff

100
MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.h
View File

@@ -24,8 +24,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
EFI_STATUS
PciEnumerator (
IN EFI_HANDLE Controller,
IN EFI_HANDLE HostBridgeHandle
IN EFI_HANDLE Controller,
IN EFI_HANDLE HostBridgeHandle
);
/**
@@ -55,9 +55,9 @@ PciRootBridgeEnumerator (
**/
VOID
ProcessOptionRom (
IN PCI_IO_DEVICE *Bridge,
IN UINT64 RomBase,
IN UINT64 MaxLength
IN PCI_IO_DEVICE *Bridge,
IN UINT64 RomBase,
IN UINT64 MaxLength
);
/**
@@ -73,9 +73,9 @@ ProcessOptionRom (
**/
EFI_STATUS
PciAssignBusNumber (
IN PCI_IO_DEVICE *Bridge,
IN UINT8 StartBusNumber,
OUT UINT8 *SubBusNumber
IN PCI_IO_DEVICE *Bridge,
IN UINT8 StartBusNumber,
OUT UINT8 *SubBusNumber
);
/**
@@ -91,8 +91,8 @@ PciAssignBusNumber (
**/
EFI_STATUS
DetermineRootBridgeAttributes (
IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc,
IN PCI_IO_DEVICE *RootBridgeDev
IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc,
IN PCI_IO_DEVICE *RootBridgeDev
);
/**
@@ -105,7 +105,7 @@ DetermineRootBridgeAttributes (
**/
UINT32
GetMaxOptionRomSize (
IN PCI_IO_DEVICE *Bridge
IN PCI_IO_DEVICE *Bridge
);
/**
@@ -120,7 +120,7 @@ GetMaxOptionRomSize (
**/
EFI_STATUS
PciHostBridgeDeviceAttribute (
IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc
IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc
);
/**
@@ -155,7 +155,7 @@ GetResourceAllocationStatus (
**/
EFI_STATUS
RejectPciDevice (
IN PCI_IO_DEVICE *PciDevice
IN PCI_IO_DEVICE *PciDevice
);
/**
@@ -169,7 +169,7 @@ RejectPciDevice (
**/
BOOLEAN
IsRejectiveDevice (
IN PCI_RESOURCE_NODE *PciResNode
IN PCI_RESOURCE_NODE *PciResNode
);
/**
@@ -183,8 +183,8 @@ IsRejectiveDevice (
**/
PCI_RESOURCE_NODE *
GetLargerConsumerDevice (
IN PCI_RESOURCE_NODE *PciResNode1,
IN PCI_RESOURCE_NODE *PciResNode2
IN PCI_RESOURCE_NODE *PciResNode1,
IN PCI_RESOURCE_NODE *PciResNode2
);
/**
@@ -197,7 +197,7 @@ GetLargerConsumerDevice (
**/
PCI_RESOURCE_NODE *
GetMaxResourceConsumerDevice (
IN PCI_RESOURCE_NODE *ResPool
IN PCI_RESOURCE_NODE *ResPool
);
/**
@@ -220,16 +220,16 @@ GetMaxResourceConsumerDevice (
**/
EFI_STATUS
PciHostBridgeAdjustAllocation (
IN PCI_RESOURCE_NODE *IoPool,
IN PCI_RESOURCE_NODE *Mem32Pool,
IN PCI_RESOURCE_NODE *PMem32Pool,
IN PCI_RESOURCE_NODE *Mem64Pool,
IN PCI_RESOURCE_NODE *PMem64Pool,
IN UINT64 IoResStatus,
IN UINT64 Mem32ResStatus,
IN UINT64 PMem32ResStatus,
IN UINT64 Mem64ResStatus,
IN UINT64 PMem64ResStatus
IN PCI_RESOURCE_NODE *IoPool,
IN PCI_RESOURCE_NODE *Mem32Pool,
IN PCI_RESOURCE_NODE *PMem32Pool,
IN PCI_RESOURCE_NODE *Mem64Pool,
IN PCI_RESOURCE_NODE *PMem64Pool,
IN UINT64 IoResStatus,
IN UINT64 Mem32ResStatus,
IN UINT64 PMem32ResStatus,
IN UINT64 Mem64ResStatus,
IN UINT64 PMem64ResStatus
);
/**
@@ -292,7 +292,7 @@ GetResourceBase (
**/
EFI_STATUS
PciBridgeEnumerator (
IN PCI_IO_DEVICE *BridgeDev
IN PCI_IO_DEVICE *BridgeDev
);
/**
@@ -325,12 +325,12 @@ PciBridgeResourceAllocator (
**/
EFI_STATUS
GetResourceBaseFromBridge (
IN PCI_IO_DEVICE *Bridge,
OUT UINT64 *IoBase,
OUT UINT64 *Mem32Base,
OUT UINT64 *PMem32Base,
OUT UINT64 *Mem64Base,
OUT UINT64 *PMem64Base
IN PCI_IO_DEVICE *Bridge,
OUT UINT64 *IoBase,
OUT UINT64 *Mem32Base,
OUT UINT64 *PMem32Base,
OUT UINT64 *Mem64Base,
OUT UINT64 *PMem64Base
);
/**
@@ -343,7 +343,7 @@ GetResourceBaseFromBridge (
**/
EFI_STATUS
PciHostBridgeP2CProcess (
IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc
IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc
);
/**
@@ -412,8 +412,8 @@ PciHostBridgeP2CProcess (
**/
EFI_STATUS
NotifyPhase (
IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc,
EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase
IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc,
EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase
);
/**
@@ -442,11 +442,11 @@ NotifyPhase (
**/
EFI_STATUS
PreprocessController (
IN PCI_IO_DEVICE *Bridge,
IN UINT8 Bus,
IN UINT8 Device,
IN UINT8 Func,
IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase
IN PCI_IO_DEVICE *Bridge,
IN UINT8 Bus,
IN UINT8 Device,
IN UINT8 Func,
IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase
);
/**
@@ -475,12 +475,12 @@ PreprocessController (
EFI_STATUS
EFIAPI
PciHotPlugRequestNotify (
IN EFI_PCI_HOTPLUG_REQUEST_PROTOCOL * This,
IN EFI_PCI_HOTPLUG_OPERATION Operation,
IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL * RemainingDevicePath OPTIONAL,
IN OUT UINT8 *NumberOfChildren,
IN OUT EFI_HANDLE * ChildHandleBuffer
IN EFI_PCI_HOTPLUG_REQUEST_PROTOCOL *This,
IN EFI_PCI_HOTPLUG_OPERATION Operation,
IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath OPTIONAL,
IN OUT UINT8 *NumberOfChildren,
IN OUT EFI_HANDLE *ChildHandleBuffer
);
/**
@@ -494,7 +494,7 @@ PciHotPlugRequestNotify (
**/
BOOLEAN
SearchHostBridgeHandle (
IN EFI_HANDLE RootBridgeHandle
IN EFI_HANDLE RootBridgeHandle
);
/**
@@ -509,7 +509,7 @@ SearchHostBridgeHandle (
**/
EFI_STATUS
AddHostBridgeEnumerator (
IN EFI_HANDLE HostBridgeHandle
IN EFI_HANDLE HostBridgeHandle
);
#endif

1298
MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
View File

File diff suppressed because it is too large Load Diff

138
MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.h
View File

@@ -24,11 +24,11 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
EFI_STATUS
PciDevicePresent (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,
OUT PCI_TYPE00 *Pci,
IN UINT8 Bus,
IN UINT8 Device,
IN UINT8 Func
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,
OUT PCI_TYPE00 *Pci,
IN UINT8 Bus,
IN UINT8 Device,
IN UINT8 Func
);
/**
@@ -46,8 +46,8 @@ PciDevicePresent (
**/
EFI_STATUS
PciPciDeviceInfoCollector (
IN PCI_IO_DEVICE *Bridge,
IN UINT8 StartBusNumber
IN PCI_IO_DEVICE *Bridge,
IN UINT8 StartBusNumber
);
/**
@@ -66,12 +66,12 @@ PciPciDeviceInfoCollector (
**/
EFI_STATUS
PciSearchDevice (
IN PCI_IO_DEVICE *Bridge,
IN PCI_TYPE00 *Pci,
IN UINT8 Bus,
IN UINT8 Device,
IN UINT8 Func,
OUT PCI_IO_DEVICE **PciDevice
IN PCI_IO_DEVICE *Bridge,
IN PCI_TYPE00 *Pci,
IN UINT8 Bus,
IN UINT8 Device,
IN UINT8 Func,
OUT PCI_IO_DEVICE **PciDevice
);
/**
@@ -88,11 +88,11 @@ PciSearchDevice (
**/
PCI_IO_DEVICE *
GatherDeviceInfo (
IN PCI_IO_DEVICE *Bridge,
IN PCI_TYPE00 *Pci,
IN UINT8 Bus,
IN UINT8 Device,
IN UINT8 Func
IN PCI_IO_DEVICE *Bridge,
IN PCI_TYPE00 *Pci,
IN UINT8 Bus,
IN UINT8 Device,
IN UINT8 Func
);
/**
@@ -109,11 +109,11 @@ GatherDeviceInfo (
**/
PCI_IO_DEVICE *
GatherPpbInfo (
IN PCI_IO_DEVICE *Bridge,
IN PCI_TYPE00 *Pci,
IN UINT8 Bus,
IN UINT8 Device,
IN UINT8 Func
IN PCI_IO_DEVICE *Bridge,
IN PCI_TYPE00 *Pci,
IN UINT8 Bus,
IN UINT8 Device,
IN UINT8 Func
);
/**
@@ -130,11 +130,11 @@ GatherPpbInfo (
**/
PCI_IO_DEVICE *
GatherP2CInfo (
IN PCI_IO_DEVICE *Bridge,
IN PCI_TYPE00 *Pci,
IN UINT8 Bus,
IN UINT8 Device,
IN UINT8 Func
IN PCI_IO_DEVICE *Bridge,
IN PCI_TYPE00 *Pci,
IN UINT8 Bus,
IN UINT8 Device,
IN UINT8 Func
);
/**
@@ -148,8 +148,8 @@ GatherP2CInfo (
**/
EFI_DEVICE_PATH_PROTOCOL *
CreatePciDevicePath (
IN EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath,
IN PCI_IO_DEVICE *PciIoDevice
IN EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath,
IN PCI_IO_DEVICE *PciIoDevice
);
/**
@@ -166,10 +166,10 @@ CreatePciDevicePath (
**/
EFI_STATUS
VfBarExisted (
IN PCI_IO_DEVICE *PciIoDevice,
IN UINTN Offset,
OUT UINT32 *BarLengthValue,
OUT UINT32 *OriginalBarValue
IN PCI_IO_DEVICE *PciIoDevice,
IN UINTN Offset,
OUT UINT32 *BarLengthValue,
OUT UINT32 *OriginalBarValue
);
/**
@@ -186,10 +186,10 @@ VfBarExisted (
**/
EFI_STATUS
BarExisted (
IN PCI_IO_DEVICE *PciIoDevice,
IN UINTN Offset,
OUT UINT32 *BarLengthValue,
OUT UINT32 *OriginalBarValue
IN PCI_IO_DEVICE *PciIoDevice,
IN UINTN Offset,
OUT UINT32 *BarLengthValue,
OUT UINT32 *OriginalBarValue
);
/**
@@ -206,11 +206,11 @@ BarExisted (
**/
VOID
PciTestSupportedAttribute (
IN PCI_IO_DEVICE *PciIoDevice,
IN OUT UINT16 *Command,
IN OUT UINT16 *BridgeControl,
OUT UINT16 *OldCommand,
OUT UINT16 *OldBridgeControl
IN PCI_IO_DEVICE *PciIoDevice,
IN OUT UINT16 *Command,
IN OUT UINT16 *BridgeControl,
OUT UINT16 *OldCommand,
OUT UINT16 *OldBridgeControl
);
/**
@@ -224,10 +224,10 @@ PciTestSupportedAttribute (
**/
VOID
PciSetDeviceAttribute (
IN PCI_IO_DEVICE *PciIoDevice,
IN UINT16 Command,
IN UINT16 BridgeControl,
IN UINTN Option
IN PCI_IO_DEVICE *PciIoDevice,
IN UINT16 Command,
IN UINT16 BridgeControl,
IN UINTN Option
);
/**
@@ -242,8 +242,8 @@ PciSetDeviceAttribute (
**/
EFI_STATUS
GetFastBackToBackSupport (
IN PCI_IO_DEVICE *PciIoDevice,
IN UINT8 StatusIndex
IN PCI_IO_DEVICE *PciIoDevice,
IN UINT8 StatusIndex
);
/**
@@ -254,7 +254,7 @@ GetFastBackToBackSupport (
**/
EFI_STATUS
DetermineDeviceAttribute (
IN PCI_IO_DEVICE *PciIoDevice
IN PCI_IO_DEVICE *PciIoDevice
);
/**
@@ -269,7 +269,7 @@ DetermineDeviceAttribute (
**/
EFI_STATUS
UpdatePciInfo (
IN OUT PCI_IO_DEVICE *PciIoDevice
IN OUT PCI_IO_DEVICE *PciIoDevice
);
/**
@@ -281,8 +281,8 @@ UpdatePciInfo (
**/
VOID
SetNewAlign (
IN OUT UINT64 *Alignment,
IN UINT64 NewAlignment
IN OUT UINT64 *Alignment,
IN UINT64 NewAlignment
);
/**
@@ -329,7 +329,7 @@ PciIovParseVfBar (
**/
VOID
InitializePciDevice (
IN PCI_IO_DEVICE *PciIoDevice
IN PCI_IO_DEVICE *PciIoDevice
);
/**
@@ -340,7 +340,7 @@ InitializePciDevice (
**/
VOID
InitializePpb (
IN PCI_IO_DEVICE *PciIoDevice
IN PCI_IO_DEVICE *PciIoDevice
);
/**
@@ -351,7 +351,7 @@ InitializePpb (
**/
VOID
InitializeP2C (
IN PCI_IO_DEVICE *PciIoDevice
IN PCI_IO_DEVICE *PciIoDevice
);
/**
@@ -369,11 +369,11 @@ InitializeP2C (
**/
PCI_IO_DEVICE *
CreatePciIoDevice (
IN PCI_IO_DEVICE *Bridge,
IN PCI_TYPE00 *Pci,
IN UINT8 Bus,
IN UINT8 Device,
IN UINT8 Func
IN PCI_IO_DEVICE *Bridge,
IN PCI_TYPE00 *Pci,
IN UINT8 Bus,
IN UINT8 Device,
IN UINT8 Func
);
/**
@@ -390,7 +390,7 @@ CreatePciIoDevice (
**/
EFI_STATUS
PciEnumeratorLight (
IN EFI_HANDLE Controller
IN EFI_HANDLE Controller
);
/**
@@ -424,7 +424,7 @@ PciGetBusRange (
**/
EFI_STATUS
StartManagingRootBridge (
IN PCI_IO_DEVICE *RootBridgeDev
IN PCI_IO_DEVICE *RootBridgeDev
);
/**
@@ -438,7 +438,7 @@ StartManagingRootBridge (
**/
BOOLEAN
IsPciDeviceRejected (
IN PCI_IO_DEVICE *PciIoDevice
IN PCI_IO_DEVICE *PciIoDevice
);
/**
@@ -450,8 +450,8 @@ IsPciDeviceRejected (
**/
VOID
ResetAllPpbBusNumber (
IN PCI_IO_DEVICE *Bridge,
IN UINT8 StartBusNumber
IN PCI_IO_DEVICE *Bridge,
IN UINT8 StartBusNumber
);
/**
@@ -463,8 +463,8 @@ ResetAllPpbBusNumber (
**/
VOID
DumpPpbPaddingResource (
IN PCI_IO_DEVICE *PciIoDevice,
IN PCI_BAR_TYPE ResourceType
IN PCI_IO_DEVICE *PciIoDevice,
IN PCI_BAR_TYPE ResourceType
);
/**
@@ -474,7 +474,7 @@ DumpPpbPaddingResource (
**/
VOID
DumpPciBars (
IN PCI_IO_DEVICE *PciIoDevice
IN PCI_IO_DEVICE *PciIoDevice
);
#endif

121
MdeModulePkg/Bus/Pci/PciBusDxe/PciHotPlugSupport.c
View File

@@ -13,7 +13,6 @@ EFI_HPC_LOCATION *gPciRootHpcPool = NULL;
UINTN gPciRootHpcCount = 0;
ROOT_HPC_DATA *gPciRootHpcData = NULL;
/**
Event notification function to set Hot Plug controller status.
@@ -24,14 +23,14 @@ ROOT_HPC_DATA *gPciRootHpcData = NULL;
VOID
EFIAPI
PciHPCInitialized (
IN EFI_EVENT Event,
IN VOID *Context
IN EFI_EVENT Event,
IN VOID *Context
)
{
ROOT_HPC_DATA *HpcData;
ROOT_HPC_DATA *HpcData;
HpcData = (ROOT_HPC_DATA *) Context;
HpcData->Initialized = TRUE;
HpcData = (ROOT_HPC_DATA *)Context;
HpcData->Initialized = TRUE;
}
/**
@@ -46,12 +45,12 @@ PciHPCInitialized (
**/
BOOLEAN
EfiCompareDevicePath (
IN EFI_DEVICE_PATH_PROTOCOL *DevicePath1,
IN EFI_DEVICE_PATH_PROTOCOL *DevicePath2
IN EFI_DEVICE_PATH_PROTOCOL *DevicePath1,
IN EFI_DEVICE_PATH_PROTOCOL *DevicePath2
)
{
UINTN Size1;
UINTN Size2;
UINTN Size1;
UINTN Size2;
Size1 = GetDevicePathSize (DevicePath1);
Size2 = GetDevicePathSize (DevicePath2);
@@ -100,7 +99,7 @@ InitializeHotPlugSupport (
Status = gBS->LocateProtocol (
&gEfiPciHotPlugInitProtocolGuid,
NULL,
(VOID **) &gPciHotPlugInit
(VOID **)&gPciHotPlugInit
);
if (EFI_ERROR (Status)) {
@@ -114,10 +113,9 @@ InitializeHotPlugSupport (
);
if (!EFI_ERROR (Status)) {
gPciRootHpcPool = HpcList;
gPciRootHpcCount = HpcCount;
gPciRootHpcData = AllocateZeroPool (sizeof (ROOT_HPC_DATA) * gPciRootHpcCount);
gPciRootHpcPool = HpcList;
gPciRootHpcCount = HpcCount;
gPciRootHpcData = AllocateZeroPool (sizeof (ROOT_HPC_DATA) * gPciRootHpcCount);
if (gPciRootHpcData == NULL) {
return EFI_OUT_OF_RESOURCES;
}
@@ -139,16 +137,14 @@ InitializeHotPlugSupport (
**/
BOOLEAN
IsRootPciHotPlugBus (
IN EFI_DEVICE_PATH_PROTOCOL *HpbDevicePath,
OUT UINTN *HpIndex OPTIONAL
IN EFI_DEVICE_PATH_PROTOCOL *HpbDevicePath,
OUT UINTN *HpIndex OPTIONAL
)
{
UINTN Index;
UINTN Index;
for (Index = 0; Index < gPciRootHpcCount; Index++) {
if (EfiCompareDevicePath (gPciRootHpcPool[Index].HpbDevicePath, HpbDevicePath)) {
if (HpIndex != NULL) {
*HpIndex = Index;
}
@@ -173,16 +169,14 @@ IsRootPciHotPlugBus (
**/
BOOLEAN
IsRootPciHotPlugController (
IN EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath,
OUT UINTN *HpIndex
IN EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath,
OUT UINTN *HpIndex
)
{
UINTN Index;
UINTN Index;
for (Index = 0; Index < gPciRootHpcCount; Index++) {
if (EfiCompareDevicePath (gPciRootHpcPool[Index].HpcDevicePath, HpcDevicePath)) {
if (HpIndex != NULL) {
*HpIndex = Index;
}
@@ -237,17 +231,16 @@ CreateEventForHpc (
**/
EFI_STATUS
AllRootHPCInitialized (
IN UINTN TimeoutInMicroSeconds
IN UINTN TimeoutInMicroSeconds
)
{
UINT32 Delay;
UINTN Index;
Delay = (UINT32) ((TimeoutInMicroSeconds / 30) + 1);
Delay = (UINT32)((TimeoutInMicroSeconds / 30) + 1);
do {
for (Index = 0; Index < gPciRootHpcCount; Index++) {
if (gPciRootHpcData[Index].Found && !gPciRootHpcData[Index].Initialized) {
break;
}
@@ -263,7 +256,6 @@ AllRootHPCInitialized (
gBS->Stall (30);
Delay--;
} while (Delay > 0);
return EFI_TIMEOUT;
@@ -280,10 +272,9 @@ AllRootHPCInitialized (
**/
BOOLEAN
IsSHPC (
IN PCI_IO_DEVICE *PciIoDevice
IN PCI_IO_DEVICE *PciIoDevice
)
{
EFI_STATUS Status;
UINT8 Offset;
@@ -293,11 +284,11 @@ IsSHPC (
Offset = 0;
Status = LocateCapabilityRegBlock (
PciIoDevice,
EFI_PCI_CAPABILITY_ID_SHPC,
&Offset,
NULL
);
PciIoDevice,
EFI_PCI_CAPABILITY_ID_SHPC,
&Offset,
NULL
);
//
// If the PCI-PCI bridge has the hot plug controller build-in,
@@ -328,13 +319,13 @@ IsSHPC (
**/
BOOLEAN
SupportsPcieHotplug (
IN PCI_IO_DEVICE *PciIoDevice
IN PCI_IO_DEVICE *PciIoDevice
)
{
UINT32 Offset;
EFI_STATUS Status;
PCI_REG_PCIE_CAPABILITY Capability;
PCI_REG_PCIE_SLOT_CAPABILITY SlotCapability;
UINT32 Offset;
EFI_STATUS Status;
PCI_REG_PCIE_CAPABILITY Capability;
PCI_REG_PCIE_SLOT_CAPABILITY SlotCapability;
if (PciIoDevice == NULL) {
return FALSE;
@@ -346,6 +337,7 @@ SupportsPcieHotplug (
if (!PciIoDevice->IsPciExp) {
return FALSE;
}
Offset = PciIoDevice->PciExpressCapabilityOffset +
OFFSET_OF (PCI_CAPABILITY_PCIEXP, Capability);
Status = PciIoDevice->PciIo.Pci.Read (
@@ -363,12 +355,13 @@ SupportsPcieHotplug (
// Check the contents of the register
//
switch (Capability.Bits.DevicePortType) {
case PCIE_DEVICE_PORT_TYPE_ROOT_PORT:
case PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT:
break;
default:
return FALSE;
case PCIE_DEVICE_PORT_TYPE_ROOT_PORT:
case PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT:
break;
default:
return FALSE;
}
if (!Capability.Bits.SlotImplemented) {
return FALSE;
}
@@ -395,6 +388,7 @@ SupportsPcieHotplug (
if (SlotCapability.Bits.HotPlugCapable) {
return TRUE;
}
return FALSE;
}
@@ -406,34 +400,34 @@ SupportsPcieHotplug (
**/
VOID
GetResourcePaddingForHpb (
IN PCI_IO_DEVICE *PciIoDevice
IN PCI_IO_DEVICE *PciIoDevice
)
{
EFI_STATUS Status;
EFI_HPC_STATE State;
UINT64 PciAddress;
EFI_HPC_PADDING_ATTRIBUTES Attributes;
EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;
EFI_STATUS Status;
EFI_HPC_STATE State;
UINT64 PciAddress;
EFI_HPC_PADDING_ATTRIBUTES Attributes;
EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;
if (IsPciHotPlugBus (PciIoDevice)) {
//
// If PCI-PCI bridge device is PCI Hot Plug bus.
//
PciAddress = EFI_PCI_ADDRESS (PciIoDevice->BusNumber, PciIoDevice->DeviceNumber, PciIoDevice->FunctionNumber, 0);
Status = gPciHotPlugInit->GetResourcePadding (
gPciHotPlugInit,
PciIoDevice->DevicePath,
PciAddress,
&State,
(VOID **) &Descriptors,
&Attributes
);
Status = gPciHotPlugInit->GetResourcePadding (
gPciHotPlugInit,
PciIoDevice->DevicePath,
PciAddress,
&State,
(VOID **)&Descriptors,
&Attributes
);
if (EFI_ERROR (Status)) {
return;
}
if ((State & EFI_HPC_STATE_ENABLED) != 0 && (State & EFI_HPC_STATE_INITIALIZED) != 0) {
if (((State & EFI_HPC_STATE_ENABLED) != 0) && ((State & EFI_HPC_STATE_INITIALIZED) != 0)) {
PciIoDevice->ResourcePaddingDescriptors = Descriptors;
PciIoDevice->PaddingAttributes = Attributes;
}
@@ -453,7 +447,7 @@ GetResourcePaddingForHpb (
**/
BOOLEAN
IsPciHotPlugBus (
PCI_IO_DEVICE *PciIoDevice
PCI_IO_DEVICE *PciIoDevice
)
{
if (IsSHPC (PciIoDevice)) {
@@ -475,10 +469,9 @@ IsPciHotPlugBus (
//
// Otherwise, see if it is a Root HPC
//
if(IsRootPciHotPlugBus (PciIoDevice->DevicePath, NULL)) {
if (IsRootPciHotPlugBus (PciIoDevice->DevicePath, NULL)) {
return TRUE;
}
return FALSE;
}

42
MdeModulePkg/Bus/Pci/PciBusDxe/PciHotPlugSupport.h
View File

@@ -12,24 +12,24 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
//
// stall 1 second, its unit is 100ns
//
#define STALL_1_SECOND 1000000
#define STALL_1_SECOND 1000000
//
// PCI Hot Plug controller private data
//
typedef struct {
EFI_EVENT Event;
BOOLEAN Found;
BOOLEAN Initialized;
VOID *Padding;
EFI_EVENT Event;
BOOLEAN Found;
BOOLEAN Initialized;
VOID *Padding;
} ROOT_HPC_DATA;
//
// Reference of some global variables
//
extern EFI_PCI_HOT_PLUG_INIT_PROTOCOL *gPciHotPlugInit;
extern EFI_HPC_LOCATION *gPciRootHpcPool;
extern ROOT_HPC_DATA *gPciRootHpcData;
extern EFI_PCI_HOT_PLUG_INIT_PROTOCOL *gPciHotPlugInit;
extern EFI_HPC_LOCATION *gPciRootHpcPool;
extern ROOT_HPC_DATA *gPciRootHpcData;
/**
Event notification function to set Hot Plug controller status.
@@ -41,8 +41,8 @@ extern ROOT_HPC_DATA *gPciRootHpcData;
VOID
EFIAPI
PciHPCInitialized (
IN EFI_EVENT Event,
IN VOID *Context
IN EFI_EVENT Event,
IN VOID *Context
);
/**
@@ -57,8 +57,8 @@ PciHPCInitialized (
**/
BOOLEAN
EfiCompareDevicePath (
IN EFI_DEVICE_PATH_PROTOCOL *DevicePath1,
IN EFI_DEVICE_PATH_PROTOCOL *DevicePath2
IN EFI_DEVICE_PATH_PROTOCOL *DevicePath1,
IN EFI_DEVICE_PATH_PROTOCOL *DevicePath2
);
/**
@@ -90,7 +90,7 @@ InitializeHotPlugSupport (
**/
BOOLEAN
IsPciHotPlugBus (
PCI_IO_DEVICE *PciIoDevice
PCI_IO_DEVICE *PciIoDevice
);
/**
@@ -106,8 +106,8 @@ IsPciHotPlugBus (
**/
BOOLEAN
IsRootPciHotPlugBus (
IN EFI_DEVICE_PATH_PROTOCOL *HpbDevicePath,
OUT UINTN *HpIndex OPTIONAL
IN EFI_DEVICE_PATH_PROTOCOL *HpbDevicePath,
OUT UINTN *HpIndex OPTIONAL
);
/**
@@ -123,8 +123,8 @@ IsRootPciHotPlugBus (
**/
BOOLEAN
IsRootPciHotPlugController (
IN EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath,
OUT UINTN *HpIndex
IN EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath,
OUT UINTN *HpIndex
);
/**
@@ -153,7 +153,7 @@ CreateEventForHpc (
**/
EFI_STATUS
AllRootHPCInitialized (
IN UINTN TimeoutInMicroSeconds
IN UINTN TimeoutInMicroSeconds
);
/**
@@ -167,7 +167,7 @@ AllRootHPCInitialized (
**/
BOOLEAN
IsSHPC (
IN PCI_IO_DEVICE *PciIoDevice
IN PCI_IO_DEVICE *PciIoDevice
);
/**
@@ -188,7 +188,7 @@ IsSHPC (
**/
BOOLEAN
SupportsPcieHotplug (
IN PCI_IO_DEVICE *PciIoDevice
IN PCI_IO_DEVICE *PciIoDevice
);
/**
@@ -199,7 +199,7 @@ SupportsPcieHotplug (
**/
VOID
GetResourcePaddingForHpb (
IN PCI_IO_DEVICE *PciIoDevice
IN PCI_IO_DEVICE *PciIoDevice
);
#endif

692
MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c
View File

File diff suppressed because it is too large Load Diff

77
MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.h
View File

@@ -17,7 +17,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
VOID
InitializePciIoInstance (
IN PCI_IO_DEVICE *PciIoDevice
IN PCI_IO_DEVICE *PciIoDevice
);
/**
@@ -37,12 +37,12 @@ InitializePciIoInstance (
**/
EFI_STATUS
PciIoVerifyBarAccess (
IN PCI_IO_DEVICE *PciIoDevice,
IN UINT8 BarIndex,
IN PCI_BAR_TYPE Type,
IN IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
IN IN UINTN Count,
IN UINT64 *Offset
IN PCI_IO_DEVICE *PciIoDevice,
IN UINT8 BarIndex,
IN PCI_BAR_TYPE Type,
IN IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
IN IN UINTN Count,
IN UINT64 *Offset
);
/**
@@ -347,13 +347,13 @@ PciIoConfigWrite (
EFI_STATUS
EFIAPI
PciIoCopyMem (
IN EFI_PCI_IO_PROTOCOL *This,
IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
IN UINT8 DestBarIndex,
IN UINT64 DestOffset,
IN UINT8 SrcBarIndex,
IN UINT64 SrcOffset,
IN UINTN Count
IN EFI_PCI_IO_PROTOCOL *This,
IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
IN UINT8 DestBarIndex,
IN UINT64 DestOffset,
IN UINT8 SrcBarIndex,
IN UINT64 SrcOffset,
IN UINTN Count
);
/**
@@ -426,12 +426,12 @@ PciIoUnmap (
EFI_STATUS
EFIAPI
PciIoAllocateBuffer (
IN EFI_PCI_IO_PROTOCOL *This,
IN EFI_ALLOCATE_TYPE Type,
IN EFI_MEMORY_TYPE MemoryType,
IN UINTN Pages,
OUT VOID **HostAddress,
IN UINT64 Attributes
IN EFI_PCI_IO_PROTOCOL *This,
IN EFI_ALLOCATE_TYPE Type,
IN EFI_MEMORY_TYPE MemoryType,
IN UINTN Pages,
OUT VOID **HostAddress,
IN UINT64 Attributes
);
/**
@@ -449,9 +449,9 @@ PciIoAllocateBuffer (
EFI_STATUS
EFIAPI
PciIoFreeBuffer (
IN EFI_PCI_IO_PROTOCOL *This,
IN UINTN Pages,
IN VOID *HostAddress
IN EFI_PCI_IO_PROTOCOL *This,
IN UINTN Pages,
IN VOID *HostAddress
);
/**
@@ -508,9 +508,9 @@ PciIoGetLocation (
**/
BOOLEAN
CheckBarType (
IN PCI_IO_DEVICE *PciIoDevice,
IN UINT8 BarIndex,
IN PCI_BAR_TYPE BarType
IN PCI_IO_DEVICE *PciIoDevice,
IN UINT8 BarIndex,
IN PCI_BAR_TYPE BarType
);
/**
@@ -569,7 +569,7 @@ SupportPaletteSnoopAttributes (
EFI_STATUS
EFIAPI
PciIoAttributes (
IN EFI_PCI_IO_PROTOCOL * This,
IN EFI_PCI_IO_PROTOCOL *This,
IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation,
IN UINT64 Attributes,
OUT UINT64 *Result OPTIONAL
@@ -600,10 +600,10 @@ PciIoAttributes (
EFI_STATUS
EFIAPI
PciIoGetBarAttributes (
IN EFI_PCI_IO_PROTOCOL * This,
IN UINT8 BarIndex,
OUT UINT64 *Supports OPTIONAL,
OUT VOID **Resources OPTIONAL
IN EFI_PCI_IO_PROTOCOL *This,
IN UINT8 BarIndex,
OUT UINT64 *Supports OPTIONAL,
OUT VOID **Resources OPTIONAL
);
/**
@@ -633,14 +633,13 @@ PciIoGetBarAttributes (
EFI_STATUS
EFIAPI
PciIoSetBarAttributes (
IN EFI_PCI_IO_PROTOCOL *This,
IN UINT64 Attributes,
IN UINT8 BarIndex,
IN OUT UINT64 *Offset,
IN OUT UINT64 *Length
IN EFI_PCI_IO_PROTOCOL *This,
IN UINT64 Attributes,
IN UINT8 BarIndex,
IN OUT UINT64 *Offset,
IN OUT UINT64 *Length
);
/**
Test whether two Pci devices has same parent bridge.
@@ -653,8 +652,8 @@ PciIoSetBarAttributes (
**/
BOOLEAN
PciDevicesOnTheSamePath (
IN PCI_IO_DEVICE *PciDevice1,
IN PCI_IO_DEVICE *PciDevice2
IN PCI_IO_DEVICE *PciDevice1,
IN PCI_IO_DEVICE *PciDevice2
);
#endif

629
MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c
View File

File diff suppressed because it is too large Load Diff

46
MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.h
View File

@@ -9,19 +9,18 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#ifndef _EFI_PCI_LIB_H_
#define _EFI_PCI_LIB_H_
typedef struct {
EFI_HANDLE Handle;
EFI_HANDLE Handle;
} EFI_DEVICE_HANDLE_EXTENDED_DATA_PAYLOAD;
typedef struct {
UINT32 Bar;
UINT16 DevicePathSize;
UINT16 ReqResSize;
UINT16 AllocResSize;
UINT8 *DevicePath;
UINT8 *ReqRes;
UINT8 *AllocRes;
UINT32 Bar;
UINT16 DevicePathSize;
UINT16 ReqResSize;
UINT16 AllocResSize;
UINT8 *DevicePath;
UINT8 *ReqRes;
UINT8 *AllocRes;
} EFI_RESOURCE_ALLOC_FAILURE_ERROR_DATA_PAYLOAD;
typedef enum {
@@ -37,7 +36,7 @@ typedef enum {
**/
VOID
GetBackPcCardBar (
IN PCI_IO_DEVICE *PciIoDevice
IN PCI_IO_DEVICE *PciIoDevice
);
/**
@@ -50,8 +49,8 @@ GetBackPcCardBar (
**/
VOID
RemoveRejectedPciDevices (
IN EFI_HANDLE RootBridgeHandle,
IN PCI_IO_DEVICE *Bridge
IN EFI_HANDLE RootBridgeHandle,
IN PCI_IO_DEVICE *Bridge
);
/**
@@ -69,7 +68,7 @@ RemoveRejectedPciDevices (
**/
EFI_STATUS
PciHostBridgeResourceAllocator (
IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc
IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc
);
/**
@@ -87,10 +86,10 @@ PciHostBridgeResourceAllocator (
**/
EFI_STATUS
PciAllocateBusNumber (
IN PCI_IO_DEVICE *Bridge,
IN UINT8 StartBusNumber,
IN UINT8 NumberOfBuses,
OUT UINT8 *NextBusNumber
IN PCI_IO_DEVICE *Bridge,
IN UINT8 StartBusNumber,
IN UINT8 NumberOfBuses,
OUT UINT8 *NextBusNumber
);
/**
@@ -109,10 +108,10 @@ PciAllocateBusNumber (
**/
EFI_STATUS
PciScanBus (
IN PCI_IO_DEVICE *Bridge,
IN UINT8 StartBusNumber,
OUT UINT8 *SubBusNumber,
OUT UINT8 *PaddedBusRange
IN PCI_IO_DEVICE *Bridge,
IN UINT8 StartBusNumber,
OUT UINT8 *SubBusNumber,
OUT UINT8 *PaddedBusRange
);
/**
@@ -126,7 +125,7 @@ PciScanBus (
**/
EFI_STATUS
PciRootBridgeP2CProcess (
IN PCI_IO_DEVICE *Bridge
IN PCI_IO_DEVICE *Bridge
);
/**
@@ -141,7 +140,7 @@ PciRootBridgeP2CProcess (
**/
EFI_STATUS
PciHostBridgeP2CProcess (
IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc
IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc
);
/**
@@ -176,4 +175,5 @@ PciProgramResizableBar (
IN PCI_IO_DEVICE *PciIoDevice,
IN PCI_RESIZABLE_BAR_OPERATION ResizableBarOp
);
#endif

242
MdeModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.c
View File

@@ -30,26 +30,26 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
EFI_STATUS
LocalLoadFile2 (
IN PCI_IO_DEVICE *PciIoDevice,
IN EFI_DEVICE_PATH_PROTOCOL *FilePath,
IN OUT UINTN *BufferSize,
IN VOID *Buffer OPTIONAL
IN PCI_IO_DEVICE *PciIoDevice,
IN EFI_DEVICE_PATH_PROTOCOL *FilePath,
IN OUT UINTN *BufferSize,
IN VOID *Buffer OPTIONAL
)
{
EFI_STATUS Status;
MEDIA_RELATIVE_OFFSET_RANGE_DEVICE_PATH *EfiOpRomImageNode;
EFI_PCI_EXPANSION_ROM_HEADER *EfiRomHeader;
PCI_DATA_STRUCTURE *Pcir;
UINT32 ImageSize;
UINT8 *ImageBuffer;
UINT32 ImageLength;
UINT32 DestinationSize;
UINT32 ScratchSize;
VOID *Scratch;
EFI_DECOMPRESS_PROTOCOL *Decompress;
UINT32 InitializationSize;
EFI_STATUS Status;
MEDIA_RELATIVE_OFFSET_RANGE_DEVICE_PATH *EfiOpRomImageNode;
EFI_PCI_EXPANSION_ROM_HEADER *EfiRomHeader;
PCI_DATA_STRUCTURE *Pcir;
UINT32 ImageSize;
UINT8 *ImageBuffer;
UINT32 ImageLength;
UINT32 DestinationSize;
UINT32 ScratchSize;
VOID *Scratch;
EFI_DECOMPRESS_PROTOCOL *Decompress;
UINT32 InitializationSize;
EfiOpRomImageNode = (MEDIA_RELATIVE_OFFSET_RANGE_DEVICE_PATH *) FilePath;
EfiOpRomImageNode = (MEDIA_RELATIVE_OFFSET_RANGE_DEVICE_PATH *)FilePath;
if ((EfiOpRomImageNode == NULL) ||
(DevicePathType (FilePath) != MEDIA_DEVICE_PATH) ||
(DevicePathSubType (FilePath) != MEDIA_RELATIVE_OFFSET_RANGE_DP) ||
@@ -58,19 +58,19 @@ LocalLoadFile2 (
(EfiOpRomImageNode->StartingOffset > EfiOpRomImageNode->EndingOffset) ||
(EfiOpRomImageNode->EndingOffset >= PciIoDevice->RomSize) ||
(BufferSize == NULL)
) {
)
{
return EFI_INVALID_PARAMETER;
}
EfiRomHeader = (EFI_PCI_EXPANSION_ROM_HEADER *) (
(UINT8 *) PciIoDevice->PciIo.RomImage + EfiOpRomImageNode->StartingOffset
);
EfiRomHeader = (EFI_PCI_EXPANSION_ROM_HEADER *)(
(UINT8 *)PciIoDevice->PciIo.RomImage + EfiOpRomImageNode->StartingOffset
);
if (EfiRomHeader->Signature != PCI_EXPANSION_ROM_HEADER_SIGNATURE) {
return EFI_NOT_FOUND;
}
Pcir = (PCI_DATA_STRUCTURE *) ((UINT8 *) EfiRomHeader + EfiRomHeader->PcirOffset);
Pcir = (PCI_DATA_STRUCTURE *)((UINT8 *)EfiRomHeader + EfiRomHeader->PcirOffset);
ASSERT (Pcir->Signature == PCI_DATA_STRUCTURE_SIGNATURE);
if ((Pcir->CodeType == PCI_CODE_TYPE_EFI_IMAGE) &&
@@ -78,22 +78,22 @@ LocalLoadFile2 (
((EfiRomHeader->EfiSubsystem == EFI_IMAGE_SUBSYSTEM_EFI_BOOT_SERVICE_DRIVER) ||
(EfiRomHeader->EfiSubsystem == EFI_IMAGE_SUBSYSTEM_EFI_RUNTIME_DRIVER)) &&
(EfiRomHeader->CompressionType <= EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED)
) {
ImageSize = Pcir->ImageLength * 512;
InitializationSize = (UINT32) EfiRomHeader->InitializationSize * 512;
if (InitializationSize > ImageSize || EfiRomHeader->EfiImageHeaderOffset >= InitializationSize) {
)
{
ImageSize = Pcir->ImageLength * 512;
InitializationSize = (UINT32)EfiRomHeader->InitializationSize * 512;
if ((InitializationSize > ImageSize) || (EfiRomHeader->EfiImageHeaderOffset >= InitializationSize)) {
return EFI_NOT_FOUND;
}
ImageBuffer = (UINT8 *) EfiRomHeader + EfiRomHeader->EfiImageHeaderOffset;
ImageLength = InitializationSize - EfiRomHeader->EfiImageHeaderOffset;
ImageBuffer = (UINT8 *)EfiRomHeader + EfiRomHeader->EfiImageHeaderOffset;
ImageLength = InitializationSize - EfiRomHeader->EfiImageHeaderOffset;
if (EfiRomHeader->CompressionType != EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED) {
//
// Uncompressed: Copy the EFI Image directly to user's buffer
//
if (Buffer == NULL || *BufferSize < ImageLength) {
if ((Buffer == NULL) || (*BufferSize < ImageLength)) {
*BufferSize = ImageLength;
return EFI_BUFFER_TOO_SMALL;
}
@@ -101,15 +101,15 @@ LocalLoadFile2 (
*BufferSize = ImageLength;
CopyMem (Buffer, ImageBuffer, ImageLength);
return EFI_SUCCESS;
} else {
//
// Compressed: Uncompress before copying
//
Status = gBS->LocateProtocol (&gEfiDecompressProtocolGuid, NULL, (VOID **) &Decompress);
Status = gBS->LocateProtocol (&gEfiDecompressProtocolGuid, NULL, (VOID **)&Decompress);
if (EFI_ERROR (Status)) {
return EFI_DEVICE_ERROR;
}
Status = Decompress->GetInfo (
Decompress,
ImageBuffer,
@@ -121,13 +121,13 @@ LocalLoadFile2 (
return EFI_DEVICE_ERROR;
}
if (Buffer == NULL || *BufferSize < DestinationSize) {
if ((Buffer == NULL) || (*BufferSize < DestinationSize)) {
*BufferSize = DestinationSize;
return EFI_BUFFER_TOO_SMALL;
}
*BufferSize = DestinationSize;
Scratch = AllocatePool (ScratchSize);
Scratch = AllocatePool (ScratchSize);
if (Scratch == NULL) {
return EFI_DEVICE_ERROR;
}
@@ -146,6 +146,7 @@ LocalLoadFile2 (
if (EFI_ERROR (Status)) {
return EFI_DEVICE_ERROR;
}
return EFI_SUCCESS;
}
}
@@ -161,7 +162,7 @@ LocalLoadFile2 (
**/
VOID
InitializePciLoadFile2 (
IN PCI_IO_DEVICE *PciIoDevice
IN PCI_IO_DEVICE *PciIoDevice
)
{
PciIoDevice->LoadFile2.LoadFile = LoadFile2;
@@ -193,18 +194,19 @@ InitializePciLoadFile2 (
EFI_STATUS
EFIAPI
LoadFile2 (
IN EFI_LOAD_FILE2_PROTOCOL *This,
IN EFI_DEVICE_PATH_PROTOCOL *FilePath,
IN BOOLEAN BootPolicy,
IN OUT UINTN *BufferSize,
IN VOID *Buffer OPTIONAL
IN EFI_LOAD_FILE2_PROTOCOL *This,
IN EFI_DEVICE_PATH_PROTOCOL *FilePath,
IN BOOLEAN BootPolicy,
IN OUT UINTN *BufferSize,
IN VOID *Buffer OPTIONAL
)
{
PCI_IO_DEVICE *PciIoDevice;
PCI_IO_DEVICE *PciIoDevice;
if (BootPolicy) {
return EFI_UNSUPPORTED;
}
PciIoDevice = PCI_IO_DEVICE_FROM_LOAD_FILE2_THIS (This);
return LocalLoadFile2 (
@@ -227,21 +229,21 @@ LoadFile2 (
**/
EFI_STATUS
GetOpRomInfo (
IN OUT PCI_IO_DEVICE *PciIoDevice
IN OUT PCI_IO_DEVICE *PciIoDevice
)
{
UINT8 RomBarIndex;
UINT32 AllOnes;
UINT64 Address;
EFI_STATUS Status;
UINT8 Bus;
UINT8 Device;
UINT8 Function;
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
UINT8 RomBarIndex;
UINT32 AllOnes;
UINT64 Address;
EFI_STATUS Status;
UINT8 Bus;
UINT8 Device;
UINT8 Function;
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
Bus = PciIoDevice->BusNumber;
Device = PciIoDevice->DeviceNumber;
Function = PciIoDevice->FunctionNumber;
Bus = PciIoDevice->BusNumber;
Device = PciIoDevice->DeviceNumber;
Function = PciIoDevice->FunctionNumber;
PciRootBridgeIo = PciIoDevice->PciRootBridgeIo;
@@ -260,6 +262,7 @@ GetOpRomInfo (
//
RomBarIndex = PCI_BRIDGE_ROMBAR;
}
//
// The bit0 is 0 to prevent the enabling of the Rom address decoder
//
@@ -280,7 +283,7 @@ GetOpRomInfo (
//
// Read back
//
Status = PciRootBridgeIo->Pci.Read(
Status = PciRootBridgeIo->Pci.Read (
PciRootBridgeIo,
EfiPciWidthUint32,
Address,
@@ -315,8 +318,8 @@ GetOpRomInfo (
**/
BOOLEAN
ContainEfiImage (
IN VOID *RomImage,
IN UINT64 RomSize
IN VOID *RomImage,
IN UINT64 RomSize
)
{
PCI_EXPANSION_ROM_HEADER *RomHeader;
@@ -331,20 +334,21 @@ ContainEfiImage (
do {
if (RomHeader->Signature != PCI_EXPANSION_ROM_HEADER_SIGNATURE) {
RomHeader = (PCI_EXPANSION_ROM_HEADER *) ((UINT8 *) RomHeader + 512);
RomHeader = (PCI_EXPANSION_ROM_HEADER *)((UINT8 *)RomHeader + 512);
continue;
}
//
// The PCI Data Structure must be DWORD aligned.
//
if (RomHeader->PcirOffset == 0 ||
(RomHeader->PcirOffset & 3) != 0 ||
(UINT8 *) RomHeader + RomHeader->PcirOffset + sizeof (PCI_DATA_STRUCTURE) > (UINT8 *) RomImage + RomSize) {
if ((RomHeader->PcirOffset == 0) ||
((RomHeader->PcirOffset & 3) != 0) ||
((UINT8 *)RomHeader + RomHeader->PcirOffset + sizeof (PCI_DATA_STRUCTURE) > (UINT8 *)RomImage + RomSize))
{
break;
}
RomPcir = (PCI_DATA_STRUCTURE *) ((UINT8 *) RomHeader + RomHeader->PcirOffset);
RomPcir = (PCI_DATA_STRUCTURE *)((UINT8 *)RomHeader + RomHeader->PcirOffset);
if (RomPcir->Signature != PCI_DATA_STRUCTURE_SIGNATURE) {
break;
}
@@ -354,8 +358,8 @@ ContainEfiImage (
}
Indicator = RomPcir->Indicator;
RomHeader = (PCI_EXPANSION_ROM_HEADER *) ((UINT8 *) RomHeader + RomPcir->ImageLength * 512);
} while (((UINT8 *) RomHeader < (UINT8 *) RomImage + RomSize) && ((Indicator & 0x80) == 0x00));
RomHeader = (PCI_EXPANSION_ROM_HEADER *)((UINT8 *)RomHeader + RomPcir->ImageLength * 512);
} while (((UINT8 *)RomHeader < (UINT8 *)RomImage + RomSize) && ((Indicator & 0x80) == 0x00));
return FALSE;
}
@@ -372,8 +376,8 @@ ContainEfiImage (
**/
EFI_STATUS
LoadOpRomImage (
IN PCI_IO_DEVICE *PciDevice,
IN UINT64 RomBase
IN PCI_IO_DEVICE *PciDevice,
IN UINT64 RomBase
)
{
UINT8 RomBarIndex;
@@ -392,12 +396,12 @@ LoadOpRomImage (
UINT8 *RomInMemory;
UINT8 CodeType;
RomSize = PciDevice->RomSize;
RomSize = PciDevice->RomSize;
Indicator = 0;
RomImageSize = 0;
RomInMemory = NULL;
CodeType = 0xFF;
Indicator = 0;
RomImageSize = 0;
RomInMemory = NULL;
CodeType = 0xFF;
//
// Get the RomBarIndex
@@ -417,6 +421,7 @@ LoadOpRomImage (
//
RomBarIndex = PCI_BRIDGE_ROMBAR;
}
//
// Allocate memory for Rom header and PCIR
//
@@ -431,16 +436,16 @@ LoadOpRomImage (
return EFI_OUT_OF_RESOURCES;
}
RomBar = (UINT32) RomBase;
RomBar = (UINT32)RomBase;
//
// Enable RomBar
//
RomDecode (PciDevice, RomBarIndex, RomBar, TRUE);
RomBarOffset = RomBar;
RetStatus = EFI_NOT_FOUND;
FirstCheck = TRUE;
RomBarOffset = RomBar;
RetStatus = EFI_NOT_FOUND;
FirstCheck = TRUE;
LegacyImageLength = 0;
do {
@@ -449,7 +454,7 @@ LoadOpRomImage (
EfiPciWidthUint8,
RomBarOffset,
sizeof (PCI_EXPANSION_ROM_HEADER),
(UINT8 *) RomHeader
(UINT8 *)RomHeader
);
if (RomHeader->Signature != PCI_EXPANSION_ROM_HEADER_SIGNATURE) {
@@ -462,23 +467,25 @@ LoadOpRomImage (
}
}
FirstCheck = FALSE;
OffsetPcir = RomHeader->PcirOffset;
FirstCheck = FALSE;
OffsetPcir = RomHeader->PcirOffset;
//
// If the pointer to the PCI Data Structure is invalid, no further images can be located.
// The PCI Data Structure must be DWORD aligned.
//
if (OffsetPcir == 0 ||
(OffsetPcir & 3) != 0 ||
RomImageSize + OffsetPcir + sizeof (PCI_DATA_STRUCTURE) > RomSize) {
if ((OffsetPcir == 0) ||
((OffsetPcir & 3) != 0) ||
(RomImageSize + OffsetPcir + sizeof (PCI_DATA_STRUCTURE) > RomSize))
{
break;
}
PciDevice->PciRootBridgeIo->Mem.Read (
PciDevice->PciRootBridgeIo,
EfiPciWidthUint8,
RomBarOffset + OffsetPcir,
sizeof (PCI_DATA_STRUCTURE),
(UINT8 *) RomPcir
(UINT8 *)RomPcir
);
//
// If a valid signature is not present in the PCI Data Structure, no further images can be located.
@@ -486,16 +493,19 @@ LoadOpRomImage (
if (RomPcir->Signature != PCI_DATA_STRUCTURE_SIGNATURE) {
break;
}
if (RomImageSize + RomPcir->ImageLength * 512 > RomSize) {
break;
}
if (RomPcir->CodeType == PCI_CODE_TYPE_PCAT_IMAGE) {
CodeType = PCI_CODE_TYPE_PCAT_IMAGE;
CodeType = PCI_CODE_TYPE_PCAT_IMAGE;
LegacyImageLength = ((UINT32)((EFI_LEGACY_EXPANSION_ROM_HEADER *)RomHeader)->Size512) * 512;
}
Indicator = RomPcir->Indicator;
RomImageSize = RomImageSize + RomPcir->ImageLength * 512;
RomBarOffset = RomBarOffset + RomPcir->ImageLength * 512;
Indicator = RomPcir->Indicator;
RomImageSize = RomImageSize + RomPcir->ImageLength * 512;
RomBarOffset = RomBarOffset + RomPcir->ImageLength * 512;
} while (((Indicator & 0x80) == 0x00) && ((RomBarOffset - RomBar) < RomSize));
//
@@ -508,7 +518,7 @@ LoadOpRomImage (
if (RomImageSize > 0) {
RetStatus = EFI_SUCCESS;
Image = AllocatePool ((UINT32) RomImageSize);
Image = AllocatePool ((UINT32)RomImageSize);
if (Image == NULL) {
RomDecode (PciDevice, RomBarIndex, RomBar, FALSE);
FreePool (RomHeader);
@@ -523,7 +533,7 @@ LoadOpRomImage (
PciDevice->PciRootBridgeIo,
EfiPciWidthUint32,
RomBar,
(UINT32) RomImageSize/sizeof(UINT32),
(UINT32)RomImageSize/sizeof (UINT32),
Image
);
RomInMemory = Image;
@@ -570,18 +580,17 @@ LoadOpRomImage (
**/
VOID
RomDecode (
IN PCI_IO_DEVICE *PciDevice,
IN UINT8 RomBarIndex,
IN UINT32 RomBar,
IN BOOLEAN Enable
IN PCI_IO_DEVICE *PciDevice,
IN UINT8 RomBarIndex,
IN UINT32 RomBar,
IN BOOLEAN Enable
)
{
UINT32 Value32;
EFI_PCI_IO_PROTOCOL *PciIo;
UINT32 Value32;
EFI_PCI_IO_PROTOCOL *PciIo;
PciIo = &PciDevice->PciIo;
if (Enable) {
//
// set the Rom base address: now is hardcode
// enable its decoder
@@ -589,7 +598,7 @@ RomDecode (
Value32 = RomBar | 0x1;
PciIo->Pci.Write (
PciIo,
(EFI_PCI_IO_PROTOCOL_WIDTH) EfiPciWidthUint32,
(EFI_PCI_IO_PROTOCOL_WIDTH)EfiPciWidthUint32,
RomBarIndex,
1,
&Value32
@@ -603,14 +612,12 @@ RomDecode (
//
// Setting the memory space bit in the function's command register
//
PCI_ENABLE_COMMAND_REGISTER(PciDevice, EFI_PCI_COMMAND_MEMORY_SPACE);
PCI_ENABLE_COMMAND_REGISTER (PciDevice, EFI_PCI_COMMAND_MEMORY_SPACE);
} else {
//
// disable command register decode to memory
//
PCI_DISABLE_COMMAND_REGISTER(PciDevice, EFI_PCI_COMMAND_MEMORY_SPACE);
PCI_DISABLE_COMMAND_REGISTER (PciDevice, EFI_PCI_COMMAND_MEMORY_SPACE);
//
// Destroy the programmed bar in all the upstream bridge.
@@ -623,12 +630,11 @@ RomDecode (
Value32 = 0xFFFFFFFE;
PciIo->Pci.Write (
PciIo,
(EFI_PCI_IO_PROTOCOL_WIDTH) EfiPciWidthUint32,
(EFI_PCI_IO_PROTOCOL_WIDTH)EfiPciWidthUint32,
RomBarIndex,
1,
&Value32
);
}
}
@@ -643,7 +649,7 @@ RomDecode (
**/
EFI_STATUS
ProcessOpRomImage (
IN PCI_IO_DEVICE *PciDevice
IN PCI_IO_DEVICE *PciDevice
)
{
UINT8 Indicator;
@@ -665,26 +671,27 @@ ProcessOpRomImage (
//
// Get the Address of the Option Rom image
//
RomBar = PciDevice->PciIo.RomImage;
RomBarOffset = (UINT8 *) RomBar;
RetStatus = EFI_NOT_FOUND;
RomBar = PciDevice->PciIo.RomImage;
RomBarOffset = (UINT8 *)RomBar;
RetStatus = EFI_NOT_FOUND;
if (RomBar == NULL) {
return RetStatus;
}
ASSERT (((EFI_PCI_EXPANSION_ROM_HEADER *) RomBarOffset)->Signature == PCI_EXPANSION_ROM_HEADER_SIGNATURE);
ASSERT (((EFI_PCI_EXPANSION_ROM_HEADER *)RomBarOffset)->Signature == PCI_EXPANSION_ROM_HEADER_SIGNATURE);
do {
EfiRomHeader = (EFI_PCI_EXPANSION_ROM_HEADER *) RomBarOffset;
EfiRomHeader = (EFI_PCI_EXPANSION_ROM_HEADER *)RomBarOffset;
if (EfiRomHeader->Signature != PCI_EXPANSION_ROM_HEADER_SIGNATURE) {
RomBarOffset += 512;
continue;
}
Pcir = (PCI_DATA_STRUCTURE *) (RomBarOffset + EfiRomHeader->PcirOffset);
Pcir = (PCI_DATA_STRUCTURE *)(RomBarOffset + EfiRomHeader->PcirOffset);
ASSERT (Pcir->Signature == PCI_DATA_STRUCTURE_SIGNATURE);
ImageSize = (UINT32) (Pcir->ImageLength * 512);
Indicator = Pcir->Indicator;
ImageSize = (UINT32)(Pcir->ImageLength * 512);
Indicator = Pcir->Indicator;
//
// Skip the image if it is not an EFI PCI Option ROM image
@@ -703,11 +710,11 @@ ProcessOpRomImage (
//
// Create Pci Option Rom Image device path header
//
EfiOpRomImageNode.Header.Type = MEDIA_DEVICE_PATH;
EfiOpRomImageNode.Header.SubType = MEDIA_RELATIVE_OFFSET_RANGE_DP;
EfiOpRomImageNode.Header.Type = MEDIA_DEVICE_PATH;
EfiOpRomImageNode.Header.SubType = MEDIA_RELATIVE_OFFSET_RANGE_DP;
SetDevicePathNodeLength (&EfiOpRomImageNode.Header, sizeof (EfiOpRomImageNode));
EfiOpRomImageNode.StartingOffset = (UINTN) RomBarOffset - (UINTN) RomBar;
EfiOpRomImageNode.EndingOffset = (UINTN) RomBarOffset + ImageSize - 1 - (UINTN) RomBar;
EfiOpRomImageNode.StartingOffset = (UINTN)RomBarOffset - (UINTN)RomBar;
EfiOpRomImageNode.EndingOffset = (UINTN)RomBarOffset + ImageSize - 1 - (UINTN)RomBar;
PciOptionRomImageDevicePath = AppendDevicePathNode (PciDevice->DevicePath, &EfiOpRomImageNode.Header);
ASSERT (PciOptionRomImageDevicePath != NULL);
@@ -752,13 +759,12 @@ ProcessOpRomImage (
RetStatus = EFI_SUCCESS;
}
}
FreePool (PciOptionRomImageDevicePath);
NextImage:
RomBarOffset += ImageSize;
} while (((Indicator & 0x80) == 0x00) && (((UINTN) RomBarOffset - (UINTN) RomBar) < PciDevice->RomSize));
} while (((Indicator & 0x80) == 0x00) && (((UINTN)RomBarOffset - (UINTN)RomBar) < PciDevice->RomSize));
return RetStatus;
}

33
MdeModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.h
View File

@@ -9,7 +9,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#ifndef _EFI_PCI_OPTION_ROM_SUPPORT_H_
#define _EFI_PCI_OPTION_ROM_SUPPORT_H_
/**
Initialize a PCI LoadFile2 instance.
@@ -18,7 +17,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
VOID
InitializePciLoadFile2 (
IN PCI_IO_DEVICE *PciIoDevice
IN PCI_IO_DEVICE *PciIoDevice
);
/**
@@ -47,11 +46,11 @@ InitializePciLoadFile2 (
EFI_STATUS
EFIAPI
LoadFile2 (
IN EFI_LOAD_FILE2_PROTOCOL *This,
IN EFI_DEVICE_PATH_PROTOCOL *FilePath,
IN BOOLEAN BootPolicy,
IN OUT UINTN *BufferSize,
IN VOID *Buffer OPTIONAL
IN EFI_LOAD_FILE2_PROTOCOL *This,
IN EFI_DEVICE_PATH_PROTOCOL *FilePath,
IN BOOLEAN BootPolicy,
IN OUT UINTN *BufferSize,
IN VOID *Buffer OPTIONAL
);
/**
@@ -66,8 +65,8 @@ LoadFile2 (
**/
BOOLEAN
ContainEfiImage (
IN VOID *RomImage,
IN UINT64 RomSize
IN VOID *RomImage,
IN UINT64 RomSize
);
/**
@@ -82,7 +81,7 @@ ContainEfiImage (
**/
EFI_STATUS
GetOpRomInfo (
IN OUT PCI_IO_DEVICE *PciIoDevice
IN OUT PCI_IO_DEVICE *PciIoDevice
);
/**
@@ -97,8 +96,8 @@ GetOpRomInfo (
**/
EFI_STATUS
LoadOpRomImage (
IN PCI_IO_DEVICE *PciDevice,
IN UINT64 RomBase
IN PCI_IO_DEVICE *PciDevice,
IN UINT64 RomBase
);
/**
@@ -113,10 +112,10 @@ LoadOpRomImage (
**/
VOID
RomDecode (
IN PCI_IO_DEVICE *PciDevice,
IN UINT8 RomBarIndex,
IN UINT32 RomBar,
IN BOOLEAN Enable
IN PCI_IO_DEVICE *PciDevice,
IN UINT8 RomBarIndex,
IN UINT32 RomBar,
IN BOOLEAN Enable
);
/**
@@ -130,7 +129,7 @@ RomDecode (
**/
EFI_STATUS
ProcessOpRomImage (
IN PCI_IO_DEVICE *PciDevice
IN PCI_IO_DEVICE *PciDevice
);
#endif

14
MdeModulePkg/Bus/Pci/PciBusDxe/PciPowerManagement.c
View File

@@ -21,7 +21,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
EFI_STATUS
ResetPowerManagementFeature (
IN PCI_IO_DEVICE *PciIoDevice
IN PCI_IO_DEVICE *PciIoDevice
)
{
EFI_STATUS Status;
@@ -31,11 +31,11 @@ ResetPowerManagementFeature (
PowerManagementRegBlock = 0;
Status = LocateCapabilityRegBlock (
PciIoDevice,
EFI_PCI_CAPABILITY_ID_PMI,
&PowerManagementRegBlock,
NULL
);
PciIoDevice,
EFI_PCI_CAPABILITY_ID_PMI,
&PowerManagementRegBlock,
NULL
);
if (EFI_ERROR (Status)) {
return EFI_UNSUPPORTED;
@@ -77,6 +77,6 @@ ResetPowerManagementFeature (
&PowerManagementCSR
);
}
return Status;
}

2
MdeModulePkg/Bus/Pci/PciBusDxe/PciPowerManagement.h
View File

@@ -22,7 +22,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
EFI_STATUS
ResetPowerManagementFeature (
IN PCI_IO_DEVICE *PciIoDevice
IN PCI_IO_DEVICE *PciIoDevice
);
#endif

1539
MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c
View File

File diff suppressed because it is too large Load Diff

180
MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.h
View File

@@ -17,18 +17,18 @@ typedef enum {
#define PCI_RESOURCE_SIGNATURE SIGNATURE_32 ('p', 'c', 'r', 'c')
typedef struct {
UINT32 Signature;
LIST_ENTRY Link;
LIST_ENTRY ChildList;
PCI_IO_DEVICE *PciDev;
UINT64 Alignment;
UINT64 Offset;
UINT8 Bar;
PCI_BAR_TYPE ResType;
UINT64 Length;
BOOLEAN Reserved;
PCI_RESOURCE_USAGE ResourceUsage;
BOOLEAN Virtual;
UINT32 Signature;
LIST_ENTRY Link;
LIST_ENTRY ChildList;
PCI_IO_DEVICE *PciDev;
UINT64 Alignment;
UINT64 Offset;
UINT8 Bar;
PCI_BAR_TYPE ResType;
UINT64 Length;
BOOLEAN Reserved;
PCI_RESOURCE_USAGE ResourceUsage;
BOOLEAN Virtual;
} PCI_RESOURCE_NODE;
#define RESOURCE_NODE_FROM_LINK(a) \
@@ -43,8 +43,8 @@ typedef struct {
**/
VOID
SkipVGAAperture (
OUT UINT64 *Start,
IN UINT64 Length
OUT UINT64 *Start,
IN UINT64 Length
);
/**
@@ -56,8 +56,8 @@ SkipVGAAperture (
**/
VOID
SkipIsaAliasAperture (
OUT UINT64 *Start,
IN UINT64 Length
OUT UINT64 *Start,
IN UINT64 Length
);
/**
@@ -70,8 +70,8 @@ SkipIsaAliasAperture (
**/
VOID
InsertResourceNode (
IN OUT PCI_RESOURCE_NODE *Bridge,
IN PCI_RESOURCE_NODE *ResNode
IN OUT PCI_RESOURCE_NODE *Bridge,
IN PCI_RESOURCE_NODE *ResNode
);
/**
@@ -94,9 +94,9 @@ InsertResourceNode (
**/
VOID
MergeResourceTree (
IN PCI_RESOURCE_NODE *Dst,
IN PCI_RESOURCE_NODE *Res,
IN BOOLEAN TypeMerge
IN PCI_RESOURCE_NODE *Dst,
IN PCI_RESOURCE_NODE *Res,
IN BOOLEAN TypeMerge
);
/**
@@ -108,7 +108,7 @@ MergeResourceTree (
**/
VOID
CalculateApertureIo16 (
IN PCI_RESOURCE_NODE *Bridge
IN PCI_RESOURCE_NODE *Bridge
);
/**
@@ -120,7 +120,7 @@ CalculateApertureIo16 (
**/
VOID
CalculateResourceAperture (
IN PCI_RESOURCE_NODE *Bridge
IN PCI_RESOURCE_NODE *Bridge
);
/**
@@ -136,12 +136,12 @@ CalculateResourceAperture (
**/
VOID
GetResourceFromDevice (
IN PCI_IO_DEVICE *PciDev,
IN OUT PCI_RESOURCE_NODE *IoNode,
IN OUT PCI_RESOURCE_NODE *Mem32Node,
IN OUT PCI_RESOURCE_NODE *PMem32Node,
IN OUT PCI_RESOURCE_NODE *Mem64Node,
IN OUT PCI_RESOURCE_NODE *PMem64Node
IN PCI_IO_DEVICE *PciDev,
IN OUT PCI_RESOURCE_NODE *IoNode,
IN OUT PCI_RESOURCE_NODE *Mem32Node,
IN OUT PCI_RESOURCE_NODE *PMem32Node,
IN OUT PCI_RESOURCE_NODE *Mem64Node,
IN OUT PCI_RESOURCE_NODE *PMem64Node
);
/**
@@ -160,12 +160,12 @@ GetResourceFromDevice (
**/
PCI_RESOURCE_NODE *
CreateResourceNode (
IN PCI_IO_DEVICE *PciDev,
IN UINT64 Length,
IN UINT64 Alignment,
IN UINT8 Bar,
IN PCI_BAR_TYPE ResType,
IN PCI_RESOURCE_USAGE ResUsage
IN PCI_IO_DEVICE *PciDev,
IN UINT64 Length,
IN UINT64 Alignment,
IN UINT8 Bar,
IN PCI_BAR_TYPE ResType,
IN PCI_RESOURCE_USAGE ResUsage
);
/**
@@ -184,12 +184,12 @@ CreateResourceNode (
**/
PCI_RESOURCE_NODE *
CreateVfResourceNode (
IN PCI_IO_DEVICE *PciDev,
IN UINT64 Length,
IN UINT64 Alignment,
IN UINT8 Bar,
IN PCI_BAR_TYPE ResType,
IN PCI_RESOURCE_USAGE ResUsage
IN PCI_IO_DEVICE *PciDev,
IN UINT64 Length,
IN UINT64 Alignment,
IN UINT8 Bar,
IN PCI_BAR_TYPE ResType,
IN PCI_RESOURCE_USAGE ResUsage
);
/**
@@ -206,12 +206,12 @@ CreateVfResourceNode (
**/
VOID
CreateResourceMap (
IN PCI_IO_DEVICE *Bridge,
IN OUT PCI_RESOURCE_NODE *IoNode,
IN OUT PCI_RESOURCE_NODE *Mem32Node,
IN OUT PCI_RESOURCE_NODE *PMem32Node,
IN OUT PCI_RESOURCE_NODE *Mem64Node,
IN OUT PCI_RESOURCE_NODE *PMem64Node
IN PCI_IO_DEVICE *Bridge,
IN OUT PCI_RESOURCE_NODE *IoNode,
IN OUT PCI_RESOURCE_NODE *Mem32Node,
IN OUT PCI_RESOURCE_NODE *PMem32Node,
IN OUT PCI_RESOURCE_NODE *Mem64Node,
IN OUT PCI_RESOURCE_NODE *PMem64Node
);
/**
@@ -227,12 +227,12 @@ CreateResourceMap (
**/
VOID
ResourcePaddingPolicy (
IN PCI_IO_DEVICE *PciDev,
IN PCI_RESOURCE_NODE *IoNode,
IN PCI_RESOURCE_NODE *Mem32Node,
IN PCI_RESOURCE_NODE *PMem32Node,
IN PCI_RESOURCE_NODE *Mem64Node,
IN PCI_RESOURCE_NODE *PMem64Node
IN PCI_IO_DEVICE *PciDev,
IN PCI_RESOURCE_NODE *IoNode,
IN PCI_RESOURCE_NODE *Mem32Node,
IN PCI_RESOURCE_NODE *PMem32Node,
IN PCI_RESOURCE_NODE *Mem64Node,
IN PCI_RESOURCE_NODE *PMem64Node
);
/**
@@ -251,11 +251,11 @@ ResourcePaddingPolicy (
**/
VOID
DegradeResource (
IN PCI_IO_DEVICE *Bridge,
IN PCI_RESOURCE_NODE *Mem32Node,
IN PCI_RESOURCE_NODE *PMem32Node,
IN PCI_RESOURCE_NODE *Mem64Node,
IN PCI_RESOURCE_NODE *PMem64Node
IN PCI_IO_DEVICE *Bridge,
IN PCI_RESOURCE_NODE *Mem32Node,
IN PCI_RESOURCE_NODE *PMem32Node,
IN PCI_RESOURCE_NODE *Mem64Node,
IN PCI_RESOURCE_NODE *PMem64Node
);
/**
@@ -270,8 +270,8 @@ DegradeResource (
**/
BOOLEAN
BridgeSupportResourceDecode (
IN PCI_IO_DEVICE *Bridge,
IN UINT32 Decode
IN PCI_IO_DEVICE *Bridge,
IN UINT32 Decode
);
/**
@@ -288,8 +288,8 @@ BridgeSupportResourceDecode (
**/
EFI_STATUS
ProgramResource (
IN UINT64 Base,
IN PCI_RESOURCE_NODE *Bridge
IN UINT64 Base,
IN PCI_RESOURCE_NODE *Bridge
);
/**
@@ -301,8 +301,8 @@ ProgramResource (
**/
VOID
ProgramBar (
IN UINT64 Base,
IN PCI_RESOURCE_NODE *Node
IN UINT64 Base,
IN PCI_RESOURCE_NODE *Node
);
/**
@@ -314,8 +314,8 @@ ProgramBar (
**/
EFI_STATUS
ProgramVfBar (
IN UINT64 Base,
IN PCI_RESOURCE_NODE *Node
IN UINT64 Base,
IN PCI_RESOURCE_NODE *Node
);
/**
@@ -327,8 +327,8 @@ ProgramVfBar (
**/
VOID
ProgramPpbApperture (
IN UINT64 Base,
IN PCI_RESOURCE_NODE *Node
IN UINT64 Base,
IN PCI_RESOURCE_NODE *Node
);
/**
@@ -341,9 +341,9 @@ ProgramPpbApperture (
**/
VOID
ProgramUpstreamBridgeForRom (
IN PCI_IO_DEVICE *PciDevice,
IN UINT32 OptionRomBase,
IN BOOLEAN Enable
IN PCI_IO_DEVICE *PciDevice,
IN UINT32 OptionRomBase,
IN BOOLEAN Enable
);
/**
@@ -357,7 +357,7 @@ ProgramUpstreamBridgeForRom (
**/
BOOLEAN
ResourceRequestExisted (
IN PCI_RESOURCE_NODE *Bridge
IN PCI_RESOURCE_NODE *Bridge
);
/**
@@ -370,8 +370,8 @@ ResourceRequestExisted (
**/
VOID
InitializeResourcePool (
IN OUT PCI_RESOURCE_NODE *ResourcePool,
IN PCI_BAR_TYPE ResourceType
IN OUT PCI_RESOURCE_NODE *ResourcePool,
IN PCI_BAR_TYPE ResourceType
);
/**
@@ -382,7 +382,7 @@ InitializeResourcePool (
**/
VOID
DestroyResourceTree (
IN PCI_RESOURCE_NODE *Bridge
IN PCI_RESOURCE_NODE *Bridge
);
/**
@@ -398,12 +398,12 @@ DestroyResourceTree (
**/
VOID
ResourcePaddingForCardBusBridge (
IN PCI_IO_DEVICE *PciDev,
IN PCI_RESOURCE_NODE *IoNode,
IN PCI_RESOURCE_NODE *Mem32Node,
IN PCI_RESOURCE_NODE *PMem32Node,
IN PCI_RESOURCE_NODE *Mem64Node,
IN PCI_RESOURCE_NODE *PMem64Node
IN PCI_IO_DEVICE *PciDev,
IN PCI_RESOURCE_NODE *IoNode,
IN PCI_RESOURCE_NODE *Mem32Node,
IN PCI_RESOURCE_NODE *PMem32Node,
IN PCI_RESOURCE_NODE *Mem64Node,
IN PCI_RESOURCE_NODE *PMem64Node
);
/**
@@ -415,8 +415,8 @@ ResourcePaddingForCardBusBridge (
**/
VOID
ProgramP2C (
IN UINT64 Base,
IN PCI_RESOURCE_NODE *Node
IN UINT64 Base,
IN PCI_RESOURCE_NODE *Node
);
/**
@@ -432,12 +432,12 @@ ProgramP2C (
**/
VOID
ApplyResourcePadding (
IN PCI_IO_DEVICE *PciDev,
IN PCI_RESOURCE_NODE *IoNode,
IN PCI_RESOURCE_NODE *Mem32Node,
IN PCI_RESOURCE_NODE *PMem32Node,
IN PCI_RESOURCE_NODE *Mem64Node,
IN PCI_RESOURCE_NODE *PMem64Node
IN PCI_IO_DEVICE *PciDev,
IN PCI_RESOURCE_NODE *IoNode,
IN PCI_RESOURCE_NODE *Mem32Node,
IN PCI_RESOURCE_NODE *PMem32Node,
IN PCI_RESOURCE_NODE *Mem64Node,
IN PCI_RESOURCE_NODE *PMem64Node
);
/**
@@ -450,7 +450,7 @@ ApplyResourcePadding (
**/
VOID
GetResourcePaddingPpb (
IN PCI_IO_DEVICE *PciIoDevice
IN PCI_IO_DEVICE *PciIoDevice
);
#endif

55
MdeModulePkg/Bus/Pci/PciBusDxe/PciRomTable.c
View File

@@ -12,18 +12,18 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
// PCI ROM image information
//
typedef struct {
EFI_HANDLE ImageHandle;
UINTN Seg;
UINT8 Bus;
UINT8 Dev;
UINT8 Func;
VOID *RomImage;
UINT64 RomSize;
EFI_HANDLE ImageHandle;
UINTN Seg;
UINT8 Bus;
UINT8 Dev;
UINT8 Func;
VOID *RomImage;
UINT64 RomSize;
} PCI_ROM_IMAGE;
UINTN mNumberOfPciRomImages = 0;
UINTN mMaxNumberOfPciRomImages = 0;
PCI_ROM_IMAGE *mRomImageTable = NULL;
UINTN mNumberOfPciRomImages = 0;
UINTN mMaxNumberOfPciRomImages = 0;
PCI_ROM_IMAGE *mRomImageTable = NULL;
/**
Add the Rom Image to internal database for later PCI light enumeration.
@@ -47,20 +47,21 @@ PciRomAddImageMapping (
IN UINT64 RomSize
)
{
UINTN Index;
PCI_ROM_IMAGE *NewTable;
UINTN Index;
PCI_ROM_IMAGE *NewTable;
for (Index = 0; Index < mNumberOfPciRomImages; Index++) {
if (mRomImageTable[Index].Seg == Seg &&
mRomImageTable[Index].Bus == Bus &&
mRomImageTable[Index].Dev == Dev &&
mRomImageTable[Index].Func == Func) {
if ((mRomImageTable[Index].Seg == Seg) &&
(mRomImageTable[Index].Bus == Bus) &&
(mRomImageTable[Index].Dev == Dev) &&
(mRomImageTable[Index].Func == Func))
{
//
// Expect once RomImage and RomSize are recorded, they will be passed in
// later when updating ImageHandle
//
ASSERT ((mRomImageTable[Index].RomImage == NULL) || (RomImage == mRomImageTable[Index].RomImage));
ASSERT ((mRomImageTable[Index].RomSize == 0 ) || (RomSize == mRomImageTable[Index].RomSize ));
ASSERT ((mRomImageTable[Index].RomSize == 0) || (RomSize == mRomImageTable[Index].RomSize));
break;
}
}
@@ -76,12 +77,13 @@ PciRomAddImageMapping (
mRomImageTable
);
if (NewTable == NULL) {
return ;
return;
}
mRomImageTable = NewTable;
mMaxNumberOfPciRomImages += 0x20;
}
//
// Record the new PCI device
//
@@ -108,23 +110,24 @@ PciRomAddImageMapping (
**/
BOOLEAN
PciRomGetImageMapping (
IN PCI_IO_DEVICE *PciIoDevice
IN PCI_IO_DEVICE *PciIoDevice
)
{
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
UINTN Index;
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
UINTN Index;
PciRootBridgeIo = PciIoDevice->PciRootBridgeIo;
for (Index = 0; Index < mNumberOfPciRomImages; Index++) {
if (mRomImageTable[Index].Seg == PciRootBridgeIo->SegmentNumber &&
mRomImageTable[Index].Bus == PciIoDevice->BusNumber &&
mRomImageTable[Index].Dev == PciIoDevice->DeviceNumber &&
mRomImageTable[Index].Func == PciIoDevice->FunctionNumber ) {
if ((mRomImageTable[Index].Seg == PciRootBridgeIo->SegmentNumber) &&
(mRomImageTable[Index].Bus == PciIoDevice->BusNumber) &&
(mRomImageTable[Index].Dev == PciIoDevice->DeviceNumber) &&
(mRomImageTable[Index].Func == PciIoDevice->FunctionNumber))
{
if (mRomImageTable[Index].ImageHandle != NULL) {
AddDriver (PciIoDevice, mRomImageTable[Index].ImageHandle, NULL);
}
PciIoDevice->PciIo.RomImage = mRomImageTable[Index].RomImage;
PciIoDevice->PciIo.RomSize = mRomImageTable[Index].RomSize;
return TRUE;

2
MdeModulePkg/Bus/Pci/PciBusDxe/PciRomTable.h
View File

@@ -42,7 +42,7 @@ PciRomAddImageMapping (
**/
BOOLEAN
PciRomGetImageMapping (
IN PCI_IO_DEVICE *PciIoDevice
IN PCI_IO_DEVICE *PciIoDevice
);
#endif