MdeModulePkg: Apply uncrustify changes
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737 Apply uncrustify changes to .c/.h files in the MdeModulePkg package Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
This commit is contained in:
Michael Kubacki
committed by
mergify[bot]
mergify[bot]
parent
7c7184e201
commit
1436aea4d5
@@ -9,7 +9,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
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#ifndef _SERIAL_H_
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#define _SERIAL_H_
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#include <Uefi.h>
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#include <IndustryStandard/Pci.h>
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@@ -34,13 +33,13 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
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//
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// Driver Binding Externs
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//
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extern EFI_DRIVER_BINDING_PROTOCOL gSerialControllerDriver;
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extern EFI_COMPONENT_NAME_PROTOCOL gPciSioSerialComponentName;
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extern EFI_COMPONENT_NAME2_PROTOCOL gPciSioSerialComponentName2;
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extern EFI_DRIVER_BINDING_PROTOCOL gSerialControllerDriver;
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extern EFI_COMPONENT_NAME_PROTOCOL gPciSioSerialComponentName;
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extern EFI_COMPONENT_NAME2_PROTOCOL gPciSioSerialComponentName2;
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#define SIO_SERIAL_PORT_NAME L"SIO Serial Port #%d"
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#define PCI_SERIAL_PORT_NAME L"PCI Serial Port #%d"
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#define SERIAL_PORT_NAME_LEN (sizeof (SIO_SERIAL_PORT_NAME) / sizeof (CHAR16) + MAXIMUM_VALUE_CHARACTERS)
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#define SIO_SERIAL_PORT_NAME L"SIO Serial Port #%d"
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#define PCI_SERIAL_PORT_NAME L"PCI Serial Port #%d"
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#define SERIAL_PORT_NAME_LEN (sizeof (SIO_SERIAL_PORT_NAME) / sizeof (CHAR16) + MAXIMUM_VALUE_CHARACTERS)
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//
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// Internal Data Structures
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@@ -61,73 +60,73 @@ extern EFI_COMPONENT_NAME2_PROTOCOL gPciSioSerialComponentName2;
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/// RegisterStride equals to 4.
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///
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typedef struct {
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UINT16 VendorId; ///< Vendor ID to match the PCI device. The value 0xFFFF terminates the list of entries.
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UINT16 DeviceId; ///< Device ID to match the PCI device
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UINT32 ClockRate; ///< UART clock rate. Set to 0 for default clock rate of 1843200 Hz
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UINT64 Offset; ///< The byte offset into to the BAR
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UINT8 BarIndex; ///< Which BAR to get the UART base address
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UINT8 RegisterStride; ///< UART register stride in bytes. Set to 0 for default register stride of 1 byte.
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UINT16 ReceiveFifoDepth; ///< UART receive FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.
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UINT16 TransmitFifoDepth; ///< UART transmit FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.
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UINT8 Reserved[2];
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UINT16 VendorId; ///< Vendor ID to match the PCI device. The value 0xFFFF terminates the list of entries.
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UINT16 DeviceId; ///< Device ID to match the PCI device
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UINT32 ClockRate; ///< UART clock rate. Set to 0 for default clock rate of 1843200 Hz
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UINT64 Offset; ///< The byte offset into to the BAR
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UINT8 BarIndex; ///< Which BAR to get the UART base address
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UINT8 RegisterStride; ///< UART register stride in bytes. Set to 0 for default register stride of 1 byte.
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UINT16 ReceiveFifoDepth; ///< UART receive FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.
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UINT16 TransmitFifoDepth; ///< UART transmit FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.
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UINT8 Reserved[2];
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} PCI_SERIAL_PARAMETER;
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#pragma pack()
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#define SERIAL_MAX_FIFO_SIZE 17 ///< Actual FIFO size is 16. FIFO based on circular wastes one unit.
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#define SERIAL_MAX_FIFO_SIZE 17 ///< Actual FIFO size is 16. FIFO based on circular wastes one unit.
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typedef struct {
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UINT16 Head; ///< Head pointer of the FIFO. Empty when (Head == Tail).
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UINT16 Tail; ///< Tail pointer of the FIFO. Full when ((Tail + 1) % SERIAL_MAX_FIFO_SIZE == Head).
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UINT8 Data[SERIAL_MAX_FIFO_SIZE]; ///< Store the FIFO data.
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UINT16 Head; ///< Head pointer of the FIFO. Empty when (Head == Tail).
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UINT16 Tail; ///< Tail pointer of the FIFO. Full when ((Tail + 1) % SERIAL_MAX_FIFO_SIZE == Head).
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UINT8 Data[SERIAL_MAX_FIFO_SIZE]; ///< Store the FIFO data.
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} SERIAL_DEV_FIFO;
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typedef union {
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EFI_PCI_IO_PROTOCOL *PciIo;
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EFI_SIO_PROTOCOL *Sio;
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EFI_PCI_IO_PROTOCOL *PciIo;
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EFI_SIO_PROTOCOL *Sio;
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} PARENT_IO_PROTOCOL_PTR;
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typedef struct {
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EFI_PCI_IO_PROTOCOL *PciIo; // Pointer to parent PciIo instance.
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UINTN ChildCount; // Count of child SerialIo instance.
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UINT64 PciAttributes; // Original PCI attributes.
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EFI_PCI_IO_PROTOCOL *PciIo; // Pointer to parent PciIo instance.
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UINTN ChildCount; // Count of child SerialIo instance.
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UINT64 PciAttributes; // Original PCI attributes.
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} PCI_DEVICE_INFO;
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typedef struct {
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UINT32 Signature;
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EFI_HANDLE Handle;
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EFI_SERIAL_IO_PROTOCOL SerialIo;
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EFI_SERIAL_IO_MODE SerialMode;
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EFI_DEVICE_PATH_PROTOCOL *DevicePath;
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UINT32 Signature;
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EFI_HANDLE Handle;
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EFI_SERIAL_IO_PROTOCOL SerialIo;
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EFI_SERIAL_IO_MODE SerialMode;
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EFI_DEVICE_PATH_PROTOCOL *DevicePath;
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EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath;
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UART_DEVICE_PATH UartDevicePath;
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EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath;
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UART_DEVICE_PATH UartDevicePath;
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EFI_PHYSICAL_ADDRESS BaseAddress; ///< UART base address
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BOOLEAN MmioAccess; ///< TRUE for MMIO, FALSE for IO
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UINT8 RegisterStride; ///< UART Register Stride
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UINT32 ClockRate; ///< UART clock rate
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EFI_PHYSICAL_ADDRESS BaseAddress; ///< UART base address
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BOOLEAN MmioAccess; ///< TRUE for MMIO, FALSE for IO
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UINT8 RegisterStride; ///< UART Register Stride
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UINT32 ClockRate; ///< UART clock rate
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UINT16 ReceiveFifoDepth; ///< UART receive FIFO depth in bytes.
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SERIAL_DEV_FIFO Receive; ///< The FIFO used to store received data
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UINT16 ReceiveFifoDepth; ///< UART receive FIFO depth in bytes.
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SERIAL_DEV_FIFO Receive; ///< The FIFO used to store received data
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UINT16 TransmitFifoDepth; ///< UART transmit FIFO depth in bytes.
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SERIAL_DEV_FIFO Transmit; ///< The FIFO used to store to-transmit data
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UINT16 TransmitFifoDepth; ///< UART transmit FIFO depth in bytes.
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SERIAL_DEV_FIFO Transmit; ///< The FIFO used to store to-transmit data
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BOOLEAN SoftwareLoopbackEnable;
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BOOLEAN HardwareFlowControl;
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EFI_UNICODE_STRING_TABLE *ControllerNameTable;
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BOOLEAN ContainsControllerNode; ///< TRUE if the device produced contains Controller node
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UINT32 Instance;
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PCI_DEVICE_INFO *PciDeviceInfo;
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BOOLEAN SoftwareLoopbackEnable;
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BOOLEAN HardwareFlowControl;
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EFI_UNICODE_STRING_TABLE *ControllerNameTable;
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BOOLEAN ContainsControllerNode; ///< TRUE if the device produced contains Controller node
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UINT32 Instance;
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PCI_DEVICE_INFO *PciDeviceInfo;
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} SERIAL_DEV;
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#define SERIAL_DEV_SIGNATURE SIGNATURE_32 ('s', 'e', 'r', 'd')
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#define SERIAL_DEV_FROM_THIS(a) CR (a, SERIAL_DEV, SerialIo, SERIAL_DEV_SIGNATURE)
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#define SERIAL_DEV_SIGNATURE SIGNATURE_32 ('s', 'e', 'r', 'd')
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#define SERIAL_DEV_FROM_THIS(a) CR (a, SERIAL_DEV, SerialIo, SERIAL_DEV_SIGNATURE)
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//
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// Serial Driver Defaults
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//
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#define SERIAL_PORT_DEFAULT_TIMEOUT 1000000
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#define SERIAL_PORT_SUPPORT_CONTROL_MASK (EFI_SERIAL_CLEAR_TO_SEND | \
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#define SERIAL_PORT_DEFAULT_TIMEOUT 1000000
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#define SERIAL_PORT_SUPPORT_CONTROL_MASK (EFI_SERIAL_CLEAR_TO_SEND | \
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EFI_SERIAL_DATA_SET_READY | \
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EFI_SERIAL_RING_INDICATE | \
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EFI_SERIAL_CARRIER_DETECT | \
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@@ -139,23 +138,23 @@ typedef struct {
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EFI_SERIAL_OUTPUT_BUFFER_EMPTY | \
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EFI_SERIAL_INPUT_BUFFER_EMPTY)
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#define SERIAL_PORT_MIN_TIMEOUT 1 // 1 uS
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#define SERIAL_PORT_MAX_TIMEOUT 100000000 // 100 seconds
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#define SERIAL_PORT_MIN_TIMEOUT 1 // 1 uS
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#define SERIAL_PORT_MAX_TIMEOUT 100000000 // 100 seconds
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//
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// UART Registers
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//
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#define SERIAL_REGISTER_THR 0 ///< WO Transmit Holding Register
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#define SERIAL_REGISTER_RBR 0 ///< RO Receive Buffer Register
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#define SERIAL_REGISTER_DLL 0 ///< R/W Divisor Latch LSB
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#define SERIAL_REGISTER_DLM 1 ///< R/W Divisor Latch MSB
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#define SERIAL_REGISTER_IER 1 ///< R/W Interrupt Enable Register
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#define SERIAL_REGISTER_IIR 2 ///< RO Interrupt Identification Register
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#define SERIAL_REGISTER_FCR 2 ///< WO FIFO Cotrol Register
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#define SERIAL_REGISTER_LCR 3 ///< R/W Line Control Register
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#define SERIAL_REGISTER_MCR 4 ///< R/W Modem Control Register
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#define SERIAL_REGISTER_LSR 5 ///< R/W Line Status Register
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#define SERIAL_REGISTER_MSR 6 ///< R/W Modem Status Register
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#define SERIAL_REGISTER_SCR 7 ///< R/W Scratch Pad Register
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#define SERIAL_REGISTER_THR 0 ///< WO Transmit Holding Register
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#define SERIAL_REGISTER_RBR 0 ///< RO Receive Buffer Register
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#define SERIAL_REGISTER_DLL 0 ///< R/W Divisor Latch LSB
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#define SERIAL_REGISTER_DLM 1 ///< R/W Divisor Latch MSB
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#define SERIAL_REGISTER_IER 1 ///< R/W Interrupt Enable Register
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#define SERIAL_REGISTER_IIR 2 ///< RO Interrupt Identification Register
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#define SERIAL_REGISTER_FCR 2 ///< WO FIFO Cotrol Register
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#define SERIAL_REGISTER_LCR 3 ///< R/W Line Control Register
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#define SERIAL_REGISTER_MCR 4 ///< R/W Modem Control Register
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#define SERIAL_REGISTER_LSR 5 ///< R/W Line Status Register
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#define SERIAL_REGISTER_MSR 6 ///< R/W Modem Status Register
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#define SERIAL_REGISTER_SCR 7 ///< R/W Scratch Pad Register
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#pragma pack(1)
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///
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@@ -163,13 +162,13 @@ typedef struct {
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///
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typedef union {
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struct {
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UINT8 Ravie : 1; ///< Receiver Data Available Interrupt Enable
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UINT8 Theie : 1; ///< Transmistter Holding Register Empty Interrupt Enable
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UINT8 Rie : 1; ///< Receiver Interrupt Enable
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UINT8 Mie : 1; ///< Modem Interrupt Enable
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UINT8 Reserved : 4;
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UINT8 Ravie : 1; ///< Receiver Data Available Interrupt Enable
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UINT8 Theie : 1; ///< Transmistter Holding Register Empty Interrupt Enable
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UINT8 Rie : 1; ///< Receiver Interrupt Enable
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UINT8 Mie : 1; ///< Modem Interrupt Enable
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UINT8 Reserved : 4;
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} Bits;
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UINT8 Data;
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UINT8 Data;
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} SERIAL_PORT_IER;
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///
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@@ -177,15 +176,15 @@ typedef union {
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///
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typedef union {
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struct {
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UINT8 TrFIFOE : 1; ///< Transmit and Receive FIFO Enable
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UINT8 ResetRF : 1; ///< Reset Reciever FIFO
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UINT8 ResetTF : 1; ///< Reset Transmistter FIFO
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UINT8 Dms : 1; ///< DMA Mode Select
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UINT8 Reserved : 1;
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UINT8 TrFIFO64 : 1; ///< Enable 64 byte FIFO
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UINT8 Rtb : 2; ///< Receive Trigger Bits
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UINT8 TrFIFOE : 1; ///< Transmit and Receive FIFO Enable
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UINT8 ResetRF : 1; ///< Reset Reciever FIFO
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UINT8 ResetTF : 1; ///< Reset Transmistter FIFO
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UINT8 Dms : 1; ///< DMA Mode Select
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UINT8 Reserved : 1;
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UINT8 TrFIFO64 : 1; ///< Enable 64 byte FIFO
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UINT8 Rtb : 2; ///< Receive Trigger Bits
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} Bits;
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UINT8 Data;
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UINT8 Data;
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} SERIAL_PORT_FCR;
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///
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@@ -193,15 +192,15 @@ typedef union {
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///
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typedef union {
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struct {
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UINT8 SerialDB : 2; ///< Number of Serial Data Bits
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UINT8 StopB : 1; ///< Number of Stop Bits
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UINT8 ParEn : 1; ///< Parity Enable
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UINT8 EvenPar : 1; ///< Even Parity Select
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UINT8 SticPar : 1; ///< Sticky Parity
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UINT8 BrCon : 1; ///< Break Control
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UINT8 DLab : 1; ///< Divisor Latch Access Bit
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UINT8 SerialDB : 2; ///< Number of Serial Data Bits
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UINT8 StopB : 1; ///< Number of Stop Bits
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UINT8 ParEn : 1; ///< Parity Enable
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UINT8 EvenPar : 1; ///< Even Parity Select
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UINT8 SticPar : 1; ///< Sticky Parity
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UINT8 BrCon : 1; ///< Break Control
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UINT8 DLab : 1; ///< Divisor Latch Access Bit
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} Bits;
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UINT8 Data;
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UINT8 Data;
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} SERIAL_PORT_LCR;
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///
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@@ -209,14 +208,14 @@ typedef union {
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///
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typedef union {
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struct {
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UINT8 DtrC : 1; ///< Data Terminal Ready Control
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UINT8 Rts : 1; ///< Request To Send Control
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UINT8 Out1 : 1; ///< Output1
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UINT8 Out2 : 1; ///< Output2, used to disable interrupt
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UINT8 Lme : 1; ///< Loopback Mode Enable
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UINT8 Reserved : 3;
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UINT8 DtrC : 1; ///< Data Terminal Ready Control
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UINT8 Rts : 1; ///< Request To Send Control
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UINT8 Out1 : 1; ///< Output1
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UINT8 Out2 : 1; ///< Output2, used to disable interrupt
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UINT8 Lme : 1; ///< Loopback Mode Enable
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UINT8 Reserved : 3;
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} Bits;
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UINT8 Data;
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UINT8 Data;
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} SERIAL_PORT_MCR;
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///
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@@ -224,16 +223,16 @@ typedef union {
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///
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typedef union {
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struct {
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UINT8 Dr : 1; ///< Receiver Data Ready Status
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UINT8 Oe : 1; ///< Overrun Error Status
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UINT8 Pe : 1; ///< Parity Error Status
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UINT8 Fe : 1; ///< Framing Error Status
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UINT8 Bi : 1; ///< Break Interrupt Status
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UINT8 Thre : 1; ///< Transmistter Holding Register Status
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UINT8 Temt : 1; ///< Transmitter Empty Status
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UINT8 FIFOe : 1; ///< FIFO Error Status
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UINT8 Dr : 1; ///< Receiver Data Ready Status
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UINT8 Oe : 1; ///< Overrun Error Status
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UINT8 Pe : 1; ///< Parity Error Status
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UINT8 Fe : 1; ///< Framing Error Status
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UINT8 Bi : 1; ///< Break Interrupt Status
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UINT8 Thre : 1; ///< Transmistter Holding Register Status
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UINT8 Temt : 1; ///< Transmitter Empty Status
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UINT8 FIFOe : 1; ///< FIFO Error Status
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} Bits;
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UINT8 Data;
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UINT8 Data;
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} SERIAL_PORT_LSR;
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///
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@@ -241,48 +240,49 @@ typedef union {
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///
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typedef union {
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struct {
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UINT8 DeltaCTS : 1; ///< Delta Clear To Send Status
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UINT8 DeltaDSR : 1; ///< Delta Data Set Ready Status
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UINT8 TrailingEdgeRI : 1; ///< Trailing Edge of Ring Indicator Status
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UINT8 DeltaDCD : 1; ///< Delta Data Carrier Detect Status
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UINT8 Cts : 1; ///< Clear To Send Status
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UINT8 Dsr : 1; ///< Data Set Ready Status
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UINT8 Ri : 1; ///< Ring Indicator Status
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UINT8 Dcd : 1; ///< Data Carrier Detect Status
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UINT8 DeltaCTS : 1; ///< Delta Clear To Send Status
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UINT8 DeltaDSR : 1; ///< Delta Data Set Ready Status
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UINT8 TrailingEdgeRI : 1; ///< Trailing Edge of Ring Indicator Status
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UINT8 DeltaDCD : 1; ///< Delta Data Carrier Detect Status
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UINT8 Cts : 1; ///< Clear To Send Status
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UINT8 Dsr : 1; ///< Data Set Ready Status
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UINT8 Ri : 1; ///< Ring Indicator Status
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UINT8 Dcd : 1; ///< Data Carrier Detect Status
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} Bits;
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UINT8 Data;
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UINT8 Data;
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} SERIAL_PORT_MSR;
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#pragma pack()
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//
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// Define serial register I/O macros
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//
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#define READ_RBR(S) SerialReadRegister (S, SERIAL_REGISTER_RBR)
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#define READ_DLL(S) SerialReadRegister (S, SERIAL_REGISTER_DLL)
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#define READ_DLM(S) SerialReadRegister (S, SERIAL_REGISTER_DLM)
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#define READ_IER(S) SerialReadRegister (S, SERIAL_REGISTER_IER)
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#define READ_IIR(S) SerialReadRegister (S, SERIAL_REGISTER_IIR)
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#define READ_LCR(S) SerialReadRegister (S, SERIAL_REGISTER_LCR)
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#define READ_MCR(S) SerialReadRegister (S, SERIAL_REGISTER_MCR)
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#define READ_LSR(S) SerialReadRegister (S, SERIAL_REGISTER_LSR)
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#define READ_MSR(S) SerialReadRegister (S, SERIAL_REGISTER_MSR)
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#define READ_SCR(S) SerialReadRegister (S, SERIAL_REGISTER_SCR)
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#define READ_RBR(S) SerialReadRegister (S, SERIAL_REGISTER_RBR)
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#define READ_DLL(S) SerialReadRegister (S, SERIAL_REGISTER_DLL)
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#define READ_DLM(S) SerialReadRegister (S, SERIAL_REGISTER_DLM)
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#define READ_IER(S) SerialReadRegister (S, SERIAL_REGISTER_IER)
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#define READ_IIR(S) SerialReadRegister (S, SERIAL_REGISTER_IIR)
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#define READ_LCR(S) SerialReadRegister (S, SERIAL_REGISTER_LCR)
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#define READ_MCR(S) SerialReadRegister (S, SERIAL_REGISTER_MCR)
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#define READ_LSR(S) SerialReadRegister (S, SERIAL_REGISTER_LSR)
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#define READ_MSR(S) SerialReadRegister (S, SERIAL_REGISTER_MSR)
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#define READ_SCR(S) SerialReadRegister (S, SERIAL_REGISTER_SCR)
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#define WRITE_THR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_THR, D)
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#define WRITE_DLL(S, D) SerialWriteRegister (S, SERIAL_REGISTER_DLL, D)
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#define WRITE_DLM(S, D) SerialWriteRegister (S, SERIAL_REGISTER_DLM, D)
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#define WRITE_IER(S, D) SerialWriteRegister (S, SERIAL_REGISTER_IER, D)
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#define WRITE_FCR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_FCR, D)
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#define WRITE_LCR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_LCR, D)
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#define WRITE_MCR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_MCR, D)
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#define WRITE_LSR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_LSR, D)
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#define WRITE_MSR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_MSR, D)
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#define WRITE_SCR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_SCR, D)
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#define WRITE_THR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_THR, D)
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#define WRITE_DLL(S, D) SerialWriteRegister (S, SERIAL_REGISTER_DLL, D)
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#define WRITE_DLM(S, D) SerialWriteRegister (S, SERIAL_REGISTER_DLM, D)
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#define WRITE_IER(S, D) SerialWriteRegister (S, SERIAL_REGISTER_IER, D)
|
||||
#define WRITE_FCR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_FCR, D)
|
||||
#define WRITE_LCR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_LCR, D)
|
||||
#define WRITE_MCR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_MCR, D)
|
||||
#define WRITE_LSR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_LSR, D)
|
||||
#define WRITE_MSR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_MSR, D)
|
||||
#define WRITE_SCR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_SCR, D)
|
||||
|
||||
//
|
||||
// Prototypes
|
||||
// Driver model protocol interface
|
||||
//
|
||||
|
||||
/**
|
||||
Check to see if this driver supports the given controller
|
||||
|
||||
@@ -296,9 +296,9 @@ typedef union {
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
SerialControllerDriverSupported (
|
||||
IN EFI_DRIVER_BINDING_PROTOCOL *This,
|
||||
IN EFI_HANDLE Controller,
|
||||
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
|
||||
IN EFI_DRIVER_BINDING_PROTOCOL *This,
|
||||
IN EFI_HANDLE Controller,
|
||||
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
|
||||
);
|
||||
|
||||
/**
|
||||
@@ -313,9 +313,9 @@ SerialControllerDriverSupported (
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
SerialControllerDriverStart (
|
||||
IN EFI_DRIVER_BINDING_PROTOCOL *This,
|
||||
IN EFI_HANDLE Controller,
|
||||
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
|
||||
IN EFI_DRIVER_BINDING_PROTOCOL *This,
|
||||
IN EFI_HANDLE Controller,
|
||||
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
|
||||
);
|
||||
|
||||
/**
|
||||
@@ -333,15 +333,16 @@ SerialControllerDriverStart (
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
SerialControllerDriverStop (
|
||||
IN EFI_DRIVER_BINDING_PROTOCOL *This,
|
||||
IN EFI_HANDLE Controller,
|
||||
IN UINTN NumberOfChildren,
|
||||
IN EFI_HANDLE *ChildHandleBuffer
|
||||
IN EFI_DRIVER_BINDING_PROTOCOL *This,
|
||||
IN EFI_HANDLE Controller,
|
||||
IN UINTN NumberOfChildren,
|
||||
IN EFI_HANDLE *ChildHandleBuffer
|
||||
);
|
||||
|
||||
//
|
||||
// Serial I/O Protocol Interface
|
||||
//
|
||||
|
||||
/**
|
||||
Reset serial device.
|
||||
|
||||
@@ -354,7 +355,7 @@ SerialControllerDriverStop (
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
SerialReset (
|
||||
IN EFI_SERIAL_IO_PROTOCOL *This
|
||||
IN EFI_SERIAL_IO_PROTOCOL *This
|
||||
);
|
||||
|
||||
/**
|
||||
@@ -377,13 +378,13 @@ SerialReset (
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
SerialSetAttributes (
|
||||
IN EFI_SERIAL_IO_PROTOCOL *This,
|
||||
IN UINT64 BaudRate,
|
||||
IN UINT32 ReceiveFifoDepth,
|
||||
IN UINT32 Timeout,
|
||||
IN EFI_PARITY_TYPE Parity,
|
||||
IN UINT8 DataBits,
|
||||
IN EFI_STOP_BITS_TYPE StopBits
|
||||
IN EFI_SERIAL_IO_PROTOCOL *This,
|
||||
IN UINT64 BaudRate,
|
||||
IN UINT32 ReceiveFifoDepth,
|
||||
IN UINT32 Timeout,
|
||||
IN EFI_PARITY_TYPE Parity,
|
||||
IN UINT8 DataBits,
|
||||
IN EFI_STOP_BITS_TYPE StopBits
|
||||
);
|
||||
|
||||
/**
|
||||
@@ -399,8 +400,8 @@ SerialSetAttributes (
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
SerialSetControl (
|
||||
IN EFI_SERIAL_IO_PROTOCOL *This,
|
||||
IN UINT32 Control
|
||||
IN EFI_SERIAL_IO_PROTOCOL *This,
|
||||
IN UINT32 Control
|
||||
);
|
||||
|
||||
/**
|
||||
@@ -415,8 +416,8 @@ SerialSetControl (
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
SerialGetControl (
|
||||
IN EFI_SERIAL_IO_PROTOCOL *This,
|
||||
OUT UINT32 *Control
|
||||
IN EFI_SERIAL_IO_PROTOCOL *This,
|
||||
OUT UINT32 *Control
|
||||
);
|
||||
|
||||
/**
|
||||
@@ -435,9 +436,9 @@ SerialGetControl (
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
SerialWrite (
|
||||
IN EFI_SERIAL_IO_PROTOCOL *This,
|
||||
IN OUT UINTN *BufferSize,
|
||||
IN VOID *Buffer
|
||||
IN EFI_SERIAL_IO_PROTOCOL *This,
|
||||
IN OUT UINTN *BufferSize,
|
||||
IN VOID *Buffer
|
||||
);
|
||||
|
||||
/**
|
||||
@@ -456,14 +457,15 @@ SerialWrite (
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
SerialRead (
|
||||
IN EFI_SERIAL_IO_PROTOCOL *This,
|
||||
IN OUT UINTN *BufferSize,
|
||||
OUT VOID *Buffer
|
||||
IN EFI_SERIAL_IO_PROTOCOL *This,
|
||||
IN OUT UINTN *BufferSize,
|
||||
OUT VOID *Buffer
|
||||
);
|
||||
|
||||
//
|
||||
// Internal Functions
|
||||
//
|
||||
|
||||
/**
|
||||
Use scratchpad register to test if this serial port is present.
|
||||
|
||||
@@ -473,7 +475,7 @@ SerialRead (
|
||||
**/
|
||||
BOOLEAN
|
||||
SerialPresent (
|
||||
IN SERIAL_DEV *SerialDevice
|
||||
IN SERIAL_DEV *SerialDevice
|
||||
);
|
||||
|
||||
/**
|
||||
@@ -486,7 +488,7 @@ SerialPresent (
|
||||
**/
|
||||
BOOLEAN
|
||||
SerialFifoFull (
|
||||
IN SERIAL_DEV_FIFO *Fifo
|
||||
IN SERIAL_DEV_FIFO *Fifo
|
||||
);
|
||||
|
||||
/**
|
||||
@@ -499,7 +501,7 @@ SerialFifoFull (
|
||||
**/
|
||||
BOOLEAN
|
||||
SerialFifoEmpty (
|
||||
IN SERIAL_DEV_FIFO *Fifo
|
||||
IN SERIAL_DEV_FIFO *Fifo
|
||||
);
|
||||
|
||||
/**
|
||||
@@ -514,8 +516,8 @@ SerialFifoEmpty (
|
||||
**/
|
||||
EFI_STATUS
|
||||
SerialFifoAdd (
|
||||
IN SERIAL_DEV_FIFO *Fifo,
|
||||
IN UINT8 Data
|
||||
IN SERIAL_DEV_FIFO *Fifo,
|
||||
IN UINT8 Data
|
||||
);
|
||||
|
||||
/**
|
||||
@@ -530,8 +532,8 @@ SerialFifoAdd (
|
||||
**/
|
||||
EFI_STATUS
|
||||
SerialFifoRemove (
|
||||
IN SERIAL_DEV_FIFO *Fifo,
|
||||
OUT UINT8 *Data
|
||||
IN SERIAL_DEV_FIFO *Fifo,
|
||||
OUT UINT8 *Data
|
||||
);
|
||||
|
||||
/**
|
||||
@@ -546,7 +548,7 @@ SerialFifoRemove (
|
||||
**/
|
||||
EFI_STATUS
|
||||
SerialReceiveTransmit (
|
||||
IN SERIAL_DEV *SerialDevice
|
||||
IN SERIAL_DEV *SerialDevice
|
||||
);
|
||||
|
||||
/**
|
||||
@@ -559,8 +561,8 @@ SerialReceiveTransmit (
|
||||
**/
|
||||
UINT8
|
||||
SerialReadRegister (
|
||||
IN SERIAL_DEV *SerialDev,
|
||||
IN UINT32 Offset
|
||||
IN SERIAL_DEV *SerialDev,
|
||||
IN UINT32 Offset
|
||||
);
|
||||
|
||||
/**
|
||||
@@ -572,15 +574,15 @@ SerialReadRegister (
|
||||
**/
|
||||
VOID
|
||||
SerialWriteRegister (
|
||||
IN SERIAL_DEV *SerialDev,
|
||||
IN UINT32 Offset,
|
||||
IN UINT8 Data
|
||||
IN SERIAL_DEV *SerialDev,
|
||||
IN UINT32 Offset,
|
||||
IN UINT8 Data
|
||||
);
|
||||
|
||||
|
||||
//
|
||||
// EFI Component Name Functions
|
||||
//
|
||||
|
||||
/**
|
||||
Retrieves a Unicode string that is the user readable name of the driver.
|
||||
|
||||
@@ -628,7 +630,6 @@ SerialComponentNameGetDriverName (
|
||||
OUT CHAR16 **DriverName
|
||||
);
|
||||
|
||||
|
||||
/**
|
||||
Retrieves a Unicode string that is the user readable name of the controller
|
||||
that is being managed by a driver.
|
||||
@@ -700,11 +701,11 @@ SerialComponentNameGetDriverName (
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
SerialComponentNameGetControllerName (
|
||||
IN EFI_COMPONENT_NAME_PROTOCOL *This,
|
||||
IN EFI_HANDLE ControllerHandle,
|
||||
IN EFI_HANDLE ChildHandle OPTIONAL,
|
||||
IN CHAR8 *Language,
|
||||
OUT CHAR16 **ControllerName
|
||||
IN EFI_COMPONENT_NAME_PROTOCOL *This,
|
||||
IN EFI_HANDLE ControllerHandle,
|
||||
IN EFI_HANDLE ChildHandle OPTIONAL,
|
||||
IN CHAR8 *Language,
|
||||
OUT CHAR16 **ControllerName
|
||||
);
|
||||
|
||||
/**
|
||||
@@ -715,8 +716,8 @@ SerialComponentNameGetControllerName (
|
||||
**/
|
||||
VOID
|
||||
AddName (
|
||||
IN SERIAL_DEV *SerialDevice,
|
||||
IN UINT32 Uid
|
||||
IN SERIAL_DEV *SerialDevice,
|
||||
IN UINT32 Uid
|
||||
);
|
||||
|
||||
/**
|
||||
@@ -741,13 +742,13 @@ AddName (
|
||||
**/
|
||||
BOOLEAN
|
||||
VerifyUartParameters (
|
||||
IN UINT32 ClockRate,
|
||||
IN UINT64 BaudRate,
|
||||
IN UINT8 DataBits,
|
||||
IN EFI_PARITY_TYPE Parity,
|
||||
IN EFI_STOP_BITS_TYPE StopBits,
|
||||
OUT UINT64 *Divisor,
|
||||
OUT UINT64 *ActualBaudRate
|
||||
IN UINT32 ClockRate,
|
||||
IN UINT64 BaudRate,
|
||||
IN UINT8 DataBits,
|
||||
IN EFI_PARITY_TYPE Parity,
|
||||
IN EFI_STOP_BITS_TYPE StopBits,
|
||||
OUT UINT64 *Divisor,
|
||||
OUT UINT64 *ActualBaudRate
|
||||
);
|
||||
|
||||
/**
|
||||
@@ -762,9 +763,9 @@ VerifyUartParameters (
|
||||
**/
|
||||
UART_DEVICE_PATH *
|
||||
SkipControllerDevicePathNode (
|
||||
EFI_DEVICE_PATH_PROTOCOL *DevicePath,
|
||||
BOOLEAN *ContainsControllerNode,
|
||||
UINT32 *ControllerNumber
|
||||
EFI_DEVICE_PATH_PROTOCOL *DevicePath,
|
||||
BOOLEAN *ContainsControllerNode,
|
||||
UINT32 *ControllerNumber
|
||||
);
|
||||
|
||||
/**
|
||||
@@ -778,6 +779,7 @@ SkipControllerDevicePathNode (
|
||||
**/
|
||||
BOOLEAN
|
||||
IsUartFlowControlDevicePathNode (
|
||||
IN UART_FLOW_CONTROL_DEVICE_PATH *FlowControl
|
||||
IN UART_FLOW_CONTROL_DEVICE_PATH *FlowControl
|
||||
);
|
||||
|
||||
#endif
|
||||
|
||||
Reference in New Issue
Block a user