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MdeModulePkg: Apply uncrustify changes

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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737

Apply uncrustify changes to .c/.h files in the MdeModulePkg package

Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
This commit is contained in:
Michael Kubacki
2021-12-05 14:54:02 -08:00
committed by mergify[bot]
parent 7c7184e201
commit 1436aea4d5
994 changed files with 107608 additions and 101311 deletions
Download Patch File Download Diff File Expand all files Collapse all files

284
MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
View File

@@ -14,9 +14,9 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
//
// SD Host Controller SlotInfo Register Offset
//
#define SD_MMC_HC_SLOT_OFFSET 0x40
#define SD_MMC_HC_SLOT_OFFSET 0x40
#define SD_MMC_HC_MAX_SLOT 6
#define SD_MMC_HC_MAX_SLOT 6
//
// SD Host Controller MMIO Register Offset
@@ -60,17 +60,17 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
//
// SD Host Controller bits to HOST_CTRL2 register
//
#define SD_MMC_HC_CTRL_UHS_MASK 0x0007
#define SD_MMC_HC_CTRL_UHS_SDR12 0x0000
#define SD_MMC_HC_CTRL_UHS_SDR25 0x0001
#define SD_MMC_HC_CTRL_UHS_SDR50 0x0002
#define SD_MMC_HC_CTRL_UHS_SDR104 0x0003
#define SD_MMC_HC_CTRL_UHS_DDR50 0x0004
#define SD_MMC_HC_CTRL_MMC_LEGACY 0x0000
#define SD_MMC_HC_CTRL_MMC_HS_SDR 0x0001
#define SD_MMC_HC_CTRL_MMC_HS_DDR 0x0004
#define SD_MMC_HC_CTRL_MMC_HS200 0x0003
#define SD_MMC_HC_CTRL_MMC_HS400 0x0005
#define SD_MMC_HC_CTRL_UHS_MASK 0x0007
#define SD_MMC_HC_CTRL_UHS_SDR12 0x0000
#define SD_MMC_HC_CTRL_UHS_SDR25 0x0001
#define SD_MMC_HC_CTRL_UHS_SDR50 0x0002
#define SD_MMC_HC_CTRL_UHS_SDR104 0x0003
#define SD_MMC_HC_CTRL_UHS_DDR50 0x0004
#define SD_MMC_HC_CTRL_MMC_LEGACY 0x0000
#define SD_MMC_HC_CTRL_MMC_HS_SDR 0x0001
#define SD_MMC_HC_CTRL_MMC_HS_DDR 0x0004
#define SD_MMC_HC_CTRL_MMC_HS200 0x0003
#define SD_MMC_HC_CTRL_MMC_HS400 0x0005
#define SD_MMC_HC_CTRL_DRIVER_STRENGTH_MASK 0x0030
@@ -97,113 +97,113 @@ typedef enum {
//
// The maximum data length of each descriptor line
//
#define ADMA_MAX_DATA_PER_LINE_16B SIZE_64KB
#define ADMA_MAX_DATA_PER_LINE_26B SIZE_64MB
#define ADMA_MAX_DATA_PER_LINE_16B SIZE_64KB
#define ADMA_MAX_DATA_PER_LINE_26B SIZE_64MB
//
// ADMA descriptor for 32b addressing.
//
typedef struct {
UINT32 Valid:1;
UINT32 End:1;
UINT32 Int:1;
UINT32 Reserved:1;
UINT32 Act:2;
UINT32 UpperLength:10;
UINT32 LowerLength:16;
UINT32 Address;
UINT32 Valid : 1;
UINT32 End : 1;
UINT32 Int : 1;
UINT32 Reserved : 1;
UINT32 Act : 2;
UINT32 UpperLength : 10;
UINT32 LowerLength : 16;
UINT32 Address;
} SD_MMC_HC_ADMA_32_DESC_LINE;
//
// ADMA descriptor for 64b addressing.
//
typedef struct {
UINT32 Valid:1;
UINT32 End:1;
UINT32 Int:1;
UINT32 Reserved:1;
UINT32 Act:2;
UINT32 UpperLength:10;
UINT32 LowerLength:16;
UINT32 LowerAddress;
UINT32 UpperAddress;
UINT32 Valid : 1;
UINT32 End : 1;
UINT32 Int : 1;
UINT32 Reserved : 1;
UINT32 Act : 2;
UINT32 UpperLength : 10;
UINT32 LowerLength : 16;
UINT32 LowerAddress;
UINT32 UpperAddress;
} SD_MMC_HC_ADMA_64_V3_DESC_LINE;
typedef struct {
UINT32 Valid:1;
UINT32 End:1;
UINT32 Int:1;
UINT32 Reserved:1;
UINT32 Act:2;
UINT32 UpperLength:10;
UINT32 LowerLength:16;
UINT32 LowerAddress;
UINT32 UpperAddress;
UINT32 Reserved1;
UINT32 Valid : 1;
UINT32 End : 1;
UINT32 Int : 1;
UINT32 Reserved : 1;
UINT32 Act : 2;
UINT32 UpperLength : 10;
UINT32 LowerLength : 16;
UINT32 LowerAddress;
UINT32 UpperAddress;
UINT32 Reserved1;
} SD_MMC_HC_ADMA_64_V4_DESC_LINE;
#define SD_MMC_SDMA_BOUNDARY 512 * 1024
#define SD_MMC_SDMA_ROUND_UP(x, n) (((x) + n) & ~(n - 1))
#define SD_MMC_SDMA_BOUNDARY 512 * 1024
#define SD_MMC_SDMA_ROUND_UP(x, n) (((x) + n) & ~(n - 1))
typedef struct {
UINT8 FirstBar:3; // bit 0:2
UINT8 Reserved:1; // bit 3
UINT8 SlotNum:3; // bit 4:6
UINT8 Reserved1:1; // bit 7
UINT8 FirstBar : 3; // bit 0:2
UINT8 Reserved : 1; // bit 3
UINT8 SlotNum : 3; // bit 4:6
UINT8 Reserved1 : 1; // bit 7
} SD_MMC_HC_SLOT_INFO;
typedef struct {
UINT32 TimeoutFreq:6; // bit 0:5
UINT32 Reserved:1; // bit 6
UINT32 TimeoutUnit:1; // bit 7
UINT32 BaseClkFreq:8; // bit 8:15
UINT32 MaxBlkLen:2; // bit 16:17
UINT32 BusWidth8:1; // bit 18
UINT32 Adma2:1; // bit 19
UINT32 Reserved2:1; // bit 20
UINT32 HighSpeed:1; // bit 21
UINT32 Sdma:1; // bit 22
UINT32 SuspRes:1; // bit 23
UINT32 Voltage33:1; // bit 24
UINT32 Voltage30:1; // bit 25
UINT32 Voltage18:1; // bit 26
UINT32 SysBus64V4:1; // bit 27
UINT32 SysBus64V3:1; // bit 28
UINT32 AsyncInt:1; // bit 29
UINT32 SlotType:2; // bit 30:31
UINT32 Sdr50:1; // bit 32
UINT32 Sdr104:1; // bit 33
UINT32 Ddr50:1; // bit 34
UINT32 Reserved3:1; // bit 35
UINT32 DriverTypeA:1; // bit 36
UINT32 DriverTypeC:1; // bit 37
UINT32 DriverTypeD:1; // bit 38
UINT32 DriverType4:1; // bit 39
UINT32 TimerCount:4; // bit 40:43
UINT32 Reserved4:1; // bit 44
UINT32 TuningSDR50:1; // bit 45
UINT32 RetuningMod:2; // bit 46:47
UINT32 ClkMultiplier:8; // bit 48:55
UINT32 Reserved5:7; // bit 56:62
UINT32 Hs400:1; // bit 63
UINT32 TimeoutFreq : 6; // bit 0:5
UINT32 Reserved : 1; // bit 6
UINT32 TimeoutUnit : 1; // bit 7
UINT32 BaseClkFreq : 8; // bit 8:15
UINT32 MaxBlkLen : 2; // bit 16:17
UINT32 BusWidth8 : 1; // bit 18
UINT32 Adma2 : 1; // bit 19
UINT32 Reserved2 : 1; // bit 20
UINT32 HighSpeed : 1; // bit 21
UINT32 Sdma : 1; // bit 22
UINT32 SuspRes : 1; // bit 23
UINT32 Voltage33 : 1; // bit 24
UINT32 Voltage30 : 1; // bit 25
UINT32 Voltage18 : 1; // bit 26
UINT32 SysBus64V4 : 1; // bit 27
UINT32 SysBus64V3 : 1; // bit 28
UINT32 AsyncInt : 1; // bit 29
UINT32 SlotType : 2; // bit 30:31
UINT32 Sdr50 : 1; // bit 32
UINT32 Sdr104 : 1; // bit 33
UINT32 Ddr50 : 1; // bit 34
UINT32 Reserved3 : 1; // bit 35
UINT32 DriverTypeA : 1; // bit 36
UINT32 DriverTypeC : 1; // bit 37
UINT32 DriverTypeD : 1; // bit 38
UINT32 DriverType4 : 1; // bit 39
UINT32 TimerCount : 4; // bit 40:43
UINT32 Reserved4 : 1; // bit 44
UINT32 TuningSDR50 : 1; // bit 45
UINT32 RetuningMod : 2; // bit 46:47
UINT32 ClkMultiplier : 8; // bit 48:55
UINT32 Reserved5 : 7; // bit 56:62
UINT32 Hs400 : 1; // bit 63
} SD_MMC_HC_SLOT_CAP;
//
// SD Host controller version
//
#define SD_MMC_HC_CTRL_VER_100 0x00
#define SD_MMC_HC_CTRL_VER_200 0x01
#define SD_MMC_HC_CTRL_VER_300 0x02
#define SD_MMC_HC_CTRL_VER_400 0x03
#define SD_MMC_HC_CTRL_VER_410 0x04
#define SD_MMC_HC_CTRL_VER_420 0x05
#define SD_MMC_HC_CTRL_VER_100 0x00
#define SD_MMC_HC_CTRL_VER_200 0x01
#define SD_MMC_HC_CTRL_VER_300 0x02
#define SD_MMC_HC_CTRL_VER_400 0x03
#define SD_MMC_HC_CTRL_VER_410 0x04
#define SD_MMC_HC_CTRL_VER_420 0x05
//
// SD Host controller V4 enhancements
//
#define SD_MMC_HC_V4_EN BIT12
#define SD_MMC_HC_64_ADDR_EN BIT13
#define SD_MMC_HC_26_DATA_LEN_ADMA_EN BIT10
#define SD_MMC_HC_V4_EN BIT12
#define SD_MMC_HC_64_ADDR_EN BIT13
#define SD_MMC_HC_26_DATA_LEN_ADMA_EN BIT10
/**
Dump the content of SD/MMC host controller's Capability Register.
@@ -214,8 +214,8 @@ typedef struct {
**/
VOID
DumpCapabilityReg (
IN UINT8 Slot,
IN SD_MMC_HC_SLOT_CAP *Capability
IN UINT8 Slot,
IN SD_MMC_HC_SLOT_CAP *Capability
);
/**
@@ -232,9 +232,9 @@ DumpCapabilityReg (
EFI_STATUS
EFIAPI
SdMmcHcGetSlotInfo (
IN EFI_PCI_IO_PROTOCOL *PciIo,
OUT UINT8 *FirstBar,
OUT UINT8 *SlotNum
IN EFI_PCI_IO_PROTOCOL *PciIo,
OUT UINT8 *FirstBar,
OUT UINT8 *SlotNum
);
/**
@@ -263,12 +263,12 @@ SdMmcHcGetSlotInfo (
EFI_STATUS
EFIAPI
SdMmcHcRwMmio (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT8 BarIndex,
IN UINT32 Offset,
IN BOOLEAN Read,
IN UINT8 Count,
IN OUT VOID *Data
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT8 BarIndex,
IN UINT32 Offset,
IN BOOLEAN Read,
IN UINT8 Count,
IN OUT VOID *Data
);
/**
@@ -295,11 +295,11 @@ SdMmcHcRwMmio (
EFI_STATUS
EFIAPI
SdMmcHcOrMmio (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT8 BarIndex,
IN UINT32 Offset,
IN UINT8 Count,
IN VOID *OrData
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT8 BarIndex,
IN UINT32 Offset,
IN UINT8 Count,
IN VOID *OrData
);
/**
@@ -326,11 +326,11 @@ SdMmcHcOrMmio (
EFI_STATUS
EFIAPI
SdMmcHcAndMmio (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT8 BarIndex,
IN UINT32 Offset,
IN UINT8 Count,
IN VOID *AndData
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT8 BarIndex,
IN UINT32 Offset,
IN UINT8 Count,
IN VOID *AndData
);
/**
@@ -358,13 +358,13 @@ SdMmcHcAndMmio (
EFI_STATUS
EFIAPI
SdMmcHcWaitMmioSet (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT8 BarIndex,
IN UINT32 Offset,
IN UINT8 Count,
IN UINT64 MaskValue,
IN UINT64 TestValue,
IN UINT64 Timeout
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT8 BarIndex,
IN UINT32 Offset,
IN UINT8 Count,
IN UINT64 MaskValue,
IN UINT64 TestValue,
IN UINT64 Timeout
);
/**
@@ -398,8 +398,8 @@ SdMmcHcGetControllerVersion (
**/
EFI_STATUS
SdMmcHcEnableInterrupt (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT8 Slot
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT8 Slot
);
/**
@@ -417,7 +417,7 @@ EFI_STATUS
SdMmcHcGetCapability (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT8 Slot,
OUT SD_MMC_HC_SLOT_CAP *Capability
OUT SD_MMC_HC_SLOT_CAP *Capability
);
/**
@@ -435,7 +435,7 @@ EFI_STATUS
SdMmcHcGetMaxCurrent (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT8 Slot,
OUT UINT64 *MaxCurrent
OUT UINT64 *MaxCurrent
);
/**
@@ -455,9 +455,9 @@ SdMmcHcGetMaxCurrent (
**/
EFI_STATUS
SdMmcHcCardDetect (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT8 Slot,
OUT BOOLEAN *MediaPresent
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT8 Slot,
OUT BOOLEAN *MediaPresent
);
/**
@@ -474,8 +474,8 @@ SdMmcHcCardDetect (
**/
EFI_STATUS
SdMmcHcStopClock (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT8 Slot
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT8 Slot
);
/**
@@ -508,9 +508,9 @@ SdMmcHcStartSdClock (
**/
EFI_STATUS
SdMmcHcPowerControl (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT8 Slot,
IN UINT8 PowerCtrl
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT8 Slot,
IN UINT8 PowerCtrl
);
/**
@@ -528,9 +528,9 @@ SdMmcHcPowerControl (
**/
EFI_STATUS
SdMmcHcSetBusWidth (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT8 Slot,
IN UINT16 BusWidth
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT8 Slot,
IN UINT16 BusWidth
);
/**
@@ -548,9 +548,9 @@ SdMmcHcSetBusWidth (
**/
EFI_STATUS
SdMmcHcInitPowerVoltage (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT8 Slot,
IN SD_MMC_HC_SLOT_CAP Capability
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT8 Slot,
IN SD_MMC_HC_SLOT_CAP Capability
);
/**
@@ -567,8 +567,8 @@ SdMmcHcInitPowerVoltage (
**/
EFI_STATUS
SdMmcHcInitTimeoutCtrl (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT8 Slot
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT8 Slot
);
/**
@@ -584,10 +584,10 @@ SdMmcHcInitTimeoutCtrl (
**/
EFI_STATUS
SdMmcHcUhsSignaling (
IN EFI_HANDLE ControllerHandle,
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT8 Slot,
IN SD_MMC_BUS_MODE Timing
IN EFI_HANDLE ControllerHandle,
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT8 Slot,
IN SD_MMC_BUS_MODE Timing
);
/**