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MdeModulePkg: Apply uncrustify changes

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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737

Apply uncrustify changes to .c/.h files in the MdeModulePkg package

Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
This commit is contained in:
Michael Kubacki
2021-12-05 14:54:02 -08:00
committed by mergify[bot]
parent 7c7184e201
commit 1436aea4d5
994 changed files with 107608 additions and 101311 deletions
Download Patch File Download Diff File Expand all files Collapse all files

32
MdeModulePkg/Bus/Pci/UhciDxe/ComponentName.c
View File

@@ -8,7 +8,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include "Uhci.h"
//
// EFI Component Name Protocol
//
@@ -22,19 +21,17 @@ GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME_PROTOCOL gUhciComponentName =
//
// EFI Component Name 2 Protocol
//
GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gUhciComponentName2 = {
(EFI_COMPONENT_NAME2_GET_DRIVER_NAME) UhciComponentNameGetDriverName,
(EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME) UhciComponentNameGetControllerName,
GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gUhciComponentName2 = {
(EFI_COMPONENT_NAME2_GET_DRIVER_NAME)UhciComponentNameGetDriverName,
(EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME)UhciComponentNameGetControllerName,
"en"
};
GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mUhciDriverNameTable[] = {
GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mUhciDriverNameTable[] = {
{ "eng;en", L"Usb Uhci Driver" },
{ NULL, NULL }
{ NULL, NULL }
};
//
// EFI Component Name Functions
//
@@ -166,16 +163,16 @@ UhciComponentNameGetDriverName (
EFI_STATUS
EFIAPI
UhciComponentNameGetControllerName (
IN EFI_COMPONENT_NAME_PROTOCOL *This,
IN EFI_HANDLE ControllerHandle,
IN EFI_HANDLE ChildHandle OPTIONAL,
IN CHAR8 *Language,
OUT CHAR16 **ControllerName
IN EFI_COMPONENT_NAME_PROTOCOL *This,
IN EFI_HANDLE ControllerHandle,
IN EFI_HANDLE ChildHandle OPTIONAL,
IN CHAR8 *Language,
OUT CHAR16 **ControllerName
)
{
EFI_STATUS Status;
USB_HC_DEV *UhciDev;
EFI_USB2_HC_PROTOCOL *Usb2Hc;
EFI_STATUS Status;
USB_HC_DEV *UhciDev;
EFI_USB2_HC_PROTOCOL *Usb2Hc;
//
// This is a device driver, so ChildHandle must be NULL.
@@ -202,7 +199,7 @@ UhciComponentNameGetControllerName (
Status = gBS->OpenProtocol (
ControllerHandle,
&gEfiUsb2HcProtocolGuid,
(VOID **) &Usb2Hc,
(VOID **)&Usb2Hc,
gUhciDriverBinding.DriverBindingHandle,
ControllerHandle,
EFI_OPEN_PROTOCOL_GET_PROTOCOL
@@ -221,5 +218,4 @@ UhciComponentNameGetControllerName (
ControllerName,
(BOOLEAN)(This == &gUhciComponentName)
);
}

11
MdeModulePkg/Bus/Pci/UhciDxe/ComponentName.h
View File

@@ -57,7 +57,6 @@ UhciComponentNameGetDriverName (
OUT CHAR16 **DriverName
);
/**
Retrieves a Unicode string that is the user readable name of the controller
that is being managed by a driver.
@@ -129,11 +128,11 @@ UhciComponentNameGetDriverName (
EFI_STATUS
EFIAPI
UhciComponentNameGetControllerName (
IN EFI_COMPONENT_NAME_PROTOCOL *This,
IN EFI_HANDLE ControllerHandle,
IN EFI_HANDLE ChildHandle OPTIONAL,
IN CHAR8 *Language,
OUT CHAR16 **ControllerName
IN EFI_COMPONENT_NAME_PROTOCOL *This,
IN EFI_HANDLE ControllerHandle,
IN EFI_HANDLE ChildHandle OPTIONAL,
IN CHAR8 *Language,
OUT CHAR16 **ControllerName
);
#endif

848
MdeModulePkg/Bus/Pci/UhciDxe/Uhci.c
View File

File diff suppressed because it is too large Load Diff

86
MdeModulePkg/Bus/Pci/UhciDxe/Uhci.h
View File

@@ -10,7 +10,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#ifndef _EFI_UHCI_H_
#define _EFI_UHCI_H_
#include <Uefi.h>
#include <Protocol/Usb2HostController.h>
@@ -31,7 +30,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <IndustryStandard/Pci.h>
typedef struct _USB_HC_DEV USB_HC_DEV;
typedef struct _USB_HC_DEV USB_HC_DEV;
#include "UsbHcMem.h"
#include "UhciQueue.h"
@@ -44,20 +43,20 @@ typedef struct _USB_HC_DEV USB_HC_DEV;
// UHC timeout experience values
//
#define UHC_1_MICROSECOND 1
#define UHC_1_MILLISECOND (1000 * UHC_1_MICROSECOND)
#define UHC_1_SECOND (1000 * UHC_1_MILLISECOND)
#define UHC_1_MICROSECOND 1
#define UHC_1_MILLISECOND (1000 * UHC_1_MICROSECOND)
#define UHC_1_SECOND (1000 * UHC_1_MILLISECOND)
//
// UHCI register operation timeout, set by experience
//
#define UHC_GENERIC_TIMEOUT UHC_1_SECOND
#define UHC_GENERIC_TIMEOUT UHC_1_SECOND
//
// Wait for force global resume(FGR) complete, refers to
// specification[UHCI11-2.1.1]
//
#define UHC_FORCE_GLOBAL_RESUME_STALL (20 * UHC_1_MILLISECOND)
#define UHC_FORCE_GLOBAL_RESUME_STALL (20 * UHC_1_MILLISECOND)
//
// Wait for roothub port reset and recovery, reset stall
@@ -71,22 +70,22 @@ typedef struct _USB_HC_DEV USB_HC_DEV;
// Sync and Async transfer polling interval, set by experience,
// and the unit of Async is 100us.
//
#define UHC_SYNC_POLL_INTERVAL (1 * UHC_1_MILLISECOND)
#define UHC_ASYNC_POLL_INTERVAL EFI_TIMER_PERIOD_MILLISECONDS(1)
#define UHC_SYNC_POLL_INTERVAL (1 * UHC_1_MILLISECOND)
#define UHC_ASYNC_POLL_INTERVAL EFI_TIMER_PERIOD_MILLISECONDS(1)
//
// UHC raises TPL to TPL_NOTIFY to serialize all its operations
// to protect shared data structures.
//
#define UHCI_TPL TPL_NOTIFY
#define UHCI_TPL TPL_NOTIFY
#define USB_HC_DEV_SIGNATURE SIGNATURE_32 ('u', 'h', 'c', 'i')
#define USB_HC_DEV_SIGNATURE SIGNATURE_32 ('u', 'h', 'c', 'i')
#pragma pack(1)
typedef struct {
UINT8 ProgInterface;
UINT8 SubClassCode;
UINT8 BaseCode;
UINT8 ProgInterface;
UINT8 SubClassCode;
UINT8 BaseCode;
} USB_CLASSC;
#pragma pack()
@@ -104,20 +103,20 @@ typedef struct {
// device requires this bandwidth reclamation capability.
//
struct _USB_HC_DEV {
UINT32 Signature;
EFI_USB2_HC_PROTOCOL Usb2Hc;
EFI_PCI_IO_PROTOCOL *PciIo;
EFI_DEVICE_PATH_PROTOCOL *DevicePath;
UINT64 OriginalPciAttributes;
UINT32 Signature;
EFI_USB2_HC_PROTOCOL Usb2Hc;
EFI_PCI_IO_PROTOCOL *PciIo;
EFI_DEVICE_PATH_PROTOCOL *DevicePath;
UINT64 OriginalPciAttributes;
//
// Schedule data structures
//
UINT32 *FrameBase; // the buffer pointed by this pointer is used to store pci bus address of the QH descriptor.
UINT32 *FrameBaseHostAddr; // the buffer pointed by this pointer is used to store host memory address of the QH descriptor.
UHCI_QH_SW *SyncIntQh;
UHCI_QH_SW *CtrlQh;
UHCI_QH_SW *BulkQh;
UINT32 *FrameBase; // the buffer pointed by this pointer is used to store pci bus address of the QH descriptor.
UINT32 *FrameBaseHostAddr; // the buffer pointed by this pointer is used to store host memory address of the QH descriptor.
UHCI_QH_SW *SyncIntQh;
UHCI_QH_SW *CtrlQh;
UHCI_QH_SW *BulkQh;
//
// Structures to maintain asynchronus interrupt transfers.
@@ -127,22 +126,21 @@ struct _USB_HC_DEV {
// released in two steps using Recycle and RecycleWait.
// Check the asynchronous interrupt management routines.
//
LIST_ENTRY AsyncIntList;
EFI_EVENT AsyncIntMonitor;
UHCI_ASYNC_REQUEST *Recycle;
UHCI_ASYNC_REQUEST *RecycleWait;
LIST_ENTRY AsyncIntList;
EFI_EVENT AsyncIntMonitor;
UHCI_ASYNC_REQUEST *Recycle;
UHCI_ASYNC_REQUEST *RecycleWait;
UINTN RootPorts;
USBHC_MEM_POOL *MemPool;
EFI_UNICODE_STRING_TABLE *CtrlNameTable;
VOID *FrameMapping;
UINTN RootPorts;
USBHC_MEM_POOL *MemPool;
EFI_UNICODE_STRING_TABLE *CtrlNameTable;
VOID *FrameMapping;
//
// ExitBootServicesEvent is used to stop the EHC DMA operation
// after exit boot service.
//
EFI_EVENT ExitBootServiceEvent;
EFI_EVENT ExitBootServiceEvent;
};
extern EFI_DRIVER_BINDING_PROTOCOL gUhciDriverBinding;
@@ -164,9 +162,9 @@ extern EFI_COMPONENT_NAME2_PROTOCOL gUhciComponentName2;
EFI_STATUS
EFIAPI
UhciDriverBindingSupported (
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
);
/**
@@ -185,9 +183,9 @@ UhciDriverBindingSupported (
EFI_STATUS
EFIAPI
UhciDriverBindingStart (
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
);
/**
@@ -206,10 +204,10 @@ UhciDriverBindingStart (
EFI_STATUS
EFIAPI
UhciDriverBindingStop (
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN UINTN NumberOfChildren,
IN EFI_HANDLE *ChildHandleBuffer
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN UINTN NumberOfChildren,
IN EFI_HANDLE *ChildHandleBuffer
);
#endif

43
MdeModulePkg/Bus/Pci/UhciDxe/UhciDebug.c
View File

@@ -17,7 +17,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
VOID
UhciDumpQh (
IN UHCI_QH_SW *QhSw
IN UHCI_QH_SW *QhSw
)
{
DEBUG ((DEBUG_VERBOSE, "&QhSw @ 0x%p\n", QhSw));
@@ -28,7 +28,6 @@ UhciDumpQh (
DEBUG ((DEBUG_VERBOSE, " Vertical Link - %x\n\n", QhSw->QhHw.VerticalLink));
}
/**
Dump the content of TD structure.
@@ -37,33 +36,33 @@ UhciDumpQh (
**/
VOID
UhciDumpTds (
IN UHCI_TD_SW *TdSw
IN UHCI_TD_SW *TdSw
)
{
UHCI_TD_SW *CurTdSw;
UHCI_TD_SW *CurTdSw;
CurTdSw = TdSw;
while (CurTdSw != NULL) {
DEBUG ((DEBUG_VERBOSE, "TdSw @ 0x%p\n", CurTdSw));
DEBUG ((DEBUG_VERBOSE, "TdSw.NextTd - 0x%p\n", CurTdSw->NextTd));
DEBUG ((DEBUG_VERBOSE, "TdSw.DataLen - %d\n", CurTdSw->DataLen));
DEBUG ((DEBUG_VERBOSE, "TdSw.Data - 0x%p\n", CurTdSw->Data));
DEBUG ((DEBUG_VERBOSE, "TdSw @ 0x%p\n", CurTdSw));
DEBUG ((DEBUG_VERBOSE, "TdSw.NextTd - 0x%p\n", CurTdSw->NextTd));
DEBUG ((DEBUG_VERBOSE, "TdSw.DataLen - %d\n", CurTdSw->DataLen));
DEBUG ((DEBUG_VERBOSE, "TdSw.Data - 0x%p\n", CurTdSw->Data));
DEBUG ((DEBUG_VERBOSE, "TdHw:\n"));
DEBUG ((DEBUG_VERBOSE, " NextLink - 0x%x\n", CurTdSw->TdHw.NextLink));
DEBUG ((DEBUG_VERBOSE, " ActualLen - %d\n", CurTdSw->TdHw.ActualLen));
DEBUG ((DEBUG_VERBOSE, " Status - 0x%x\n", CurTdSw->TdHw.Status));
DEBUG ((DEBUG_VERBOSE, " IOC - %d\n", CurTdSw->TdHw.IntOnCpl));
DEBUG ((DEBUG_VERBOSE, " IsIsoCh - %d\n", CurTdSw->TdHw.IsIsoch));
DEBUG ((DEBUG_VERBOSE, " LowSpeed - %d\n", CurTdSw->TdHw.LowSpeed));
DEBUG ((DEBUG_VERBOSE, " ErrorCount - %d\n", CurTdSw->TdHw.ErrorCount));
DEBUG ((DEBUG_VERBOSE, " ShortPacket - %d\n", CurTdSw->TdHw.ShortPacket));
DEBUG ((DEBUG_VERBOSE, " PidCode - 0x%x\n", CurTdSw->TdHw.PidCode));
DEBUG ((DEBUG_VERBOSE, " DevAddr - %d\n", CurTdSw->TdHw.DeviceAddr));
DEBUG ((DEBUG_VERBOSE, " EndPoint - %d\n", CurTdSw->TdHw.EndPoint));
DEBUG ((DEBUG_VERBOSE, " DataToggle - %d\n", CurTdSw->TdHw.DataToggle));
DEBUG ((DEBUG_VERBOSE, " MaxPacketLen - %d\n", CurTdSw->TdHw.MaxPacketLen));
DEBUG ((DEBUG_VERBOSE, " DataBuffer - 0x%x\n\n",CurTdSw->TdHw.DataBuffer));
DEBUG ((DEBUG_VERBOSE, " NextLink - 0x%x\n", CurTdSw->TdHw.NextLink));
DEBUG ((DEBUG_VERBOSE, " ActualLen - %d\n", CurTdSw->TdHw.ActualLen));
DEBUG ((DEBUG_VERBOSE, " Status - 0x%x\n", CurTdSw->TdHw.Status));
DEBUG ((DEBUG_VERBOSE, " IOC - %d\n", CurTdSw->TdHw.IntOnCpl));
DEBUG ((DEBUG_VERBOSE, " IsIsoCh - %d\n", CurTdSw->TdHw.IsIsoch));
DEBUG ((DEBUG_VERBOSE, " LowSpeed - %d\n", CurTdSw->TdHw.LowSpeed));
DEBUG ((DEBUG_VERBOSE, " ErrorCount - %d\n", CurTdSw->TdHw.ErrorCount));
DEBUG ((DEBUG_VERBOSE, " ShortPacket - %d\n", CurTdSw->TdHw.ShortPacket));
DEBUG ((DEBUG_VERBOSE, " PidCode - 0x%x\n", CurTdSw->TdHw.PidCode));
DEBUG ((DEBUG_VERBOSE, " DevAddr - %d\n", CurTdSw->TdHw.DeviceAddr));
DEBUG ((DEBUG_VERBOSE, " EndPoint - %d\n", CurTdSw->TdHw.EndPoint));
DEBUG ((DEBUG_VERBOSE, " DataToggle - %d\n", CurTdSw->TdHw.DataToggle));
DEBUG ((DEBUG_VERBOSE, " MaxPacketLen - %d\n", CurTdSw->TdHw.MaxPacketLen));
DEBUG ((DEBUG_VERBOSE, " DataBuffer - 0x%x\n\n", CurTdSw->TdHw.DataBuffer));
CurTdSw = CurTdSw->NextTd;
}

6
MdeModulePkg/Bus/Pci/UhciDxe/UhciDebug.h
View File

@@ -10,7 +10,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#ifndef _EFI_UHCI_DEBUG_H_
#define _EFI_UHCI_DEBUG_H_
/**
Dump the content of QH structure.
@@ -21,10 +20,9 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
VOID
UhciDumpQh (
IN UHCI_QH_SW *QhSw
IN UHCI_QH_SW *QhSw
);
/**
Dump the content of TD structure.
@@ -35,7 +33,7 @@ UhciDumpQh (
**/
VOID
UhciDumpTds (
IN UHCI_TD_SW *TdSw
IN UHCI_TD_SW *TdSw
);
#endif

304
MdeModulePkg/Bus/Pci/UhciDxe/UhciQueue.c
View File

@@ -9,7 +9,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include "Uhci.h"
/**
Map address of request structure buffer.
@@ -24,10 +23,10 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
EFI_STATUS
UhciMapUserRequest (
IN USB_HC_DEV *Uhc,
IN OUT VOID *Request,
OUT UINT8 **MappedAddr,
OUT VOID **Map
IN USB_HC_DEV *Uhc,
IN OUT VOID *Request,
OUT UINT8 **MappedAddr,
OUT VOID **Map
)
{
EFI_STATUS Status;
@@ -45,13 +44,12 @@ UhciMapUserRequest (
);
if (!EFI_ERROR (Status)) {
*MappedAddr = (UINT8 *) (UINTN) PhyAddr;
*MappedAddr = (UINT8 *)(UINTN)PhyAddr;
}
return Status;
}
/**
Map address of user data buffer.
@@ -84,65 +82,64 @@ UhciMapUserData (
Status = EFI_SUCCESS;
switch (Direction) {
case EfiUsbDataIn:
//
// BusMasterWrite means cpu read
//
*PktId = INPUT_PACKET_ID;
Status = Uhc->PciIo->Map (
Uhc->PciIo,
EfiPciIoOperationBusMasterWrite,
Data,
Len,
&PhyAddr,
Map
);
case EfiUsbDataIn:
//
// BusMasterWrite means cpu read
//
*PktId = INPUT_PACKET_ID;
Status = Uhc->PciIo->Map (
Uhc->PciIo,
EfiPciIoOperationBusMasterWrite,
Data,
Len,
&PhyAddr,
Map
);
if (EFI_ERROR (Status)) {
goto EXIT;
}
if (EFI_ERROR (Status)) {
goto EXIT;
}
*MappedAddr = (UINT8 *) (UINTN) PhyAddr;
break;
*MappedAddr = (UINT8 *)(UINTN)PhyAddr;
break;
case EfiUsbDataOut:
*PktId = OUTPUT_PACKET_ID;
Status = Uhc->PciIo->Map (
Uhc->PciIo,
EfiPciIoOperationBusMasterRead,
Data,
Len,
&PhyAddr,
Map
);
case EfiUsbDataOut:
*PktId = OUTPUT_PACKET_ID;
Status = Uhc->PciIo->Map (
Uhc->PciIo,
EfiPciIoOperationBusMasterRead,
Data,
Len,
&PhyAddr,
Map
);
if (EFI_ERROR (Status)) {
goto EXIT;
}
if (EFI_ERROR (Status)) {
goto EXIT;
}
*MappedAddr = (UINT8 *) (UINTN) PhyAddr;
break;
*MappedAddr = (UINT8 *)(UINTN)PhyAddr;
break;
case EfiUsbNoData:
if ((Len != NULL) && (*Len != 0)) {
Status = EFI_INVALID_PARAMETER;
goto EXIT;
}
case EfiUsbNoData:
if ((Len != NULL) && (*Len != 0)) {
Status = EFI_INVALID_PARAMETER;
goto EXIT;
}
*PktId = OUTPUT_PACKET_ID;
*MappedAddr = NULL;
*Map = NULL;
break;
*PktId = OUTPUT_PACKET_ID;
*MappedAddr = NULL;
*Map = NULL;
break;
default:
Status = EFI_INVALID_PARAMETER;
default:
Status = EFI_INVALID_PARAMETER;
}
EXIT:
return Status;
}
/**
Link the TD To QH.
@@ -153,9 +150,9 @@ EXIT:
**/
VOID
UhciLinkTdToQh (
IN USB_HC_DEV *Uhc,
IN UHCI_QH_SW *Qh,
IN UHCI_TD_SW *Td
IN USB_HC_DEV *Uhc,
IN UHCI_QH_SW *Qh,
IN UHCI_TD_SW *Td
)
{
EFI_PHYSICAL_ADDRESS PhyAddr;
@@ -165,10 +162,9 @@ UhciLinkTdToQh (
ASSERT ((Qh != NULL) && (Td != NULL));
Qh->QhHw.VerticalLink = QH_VLINK (PhyAddr, FALSE);
Qh->TDs = (VOID *) Td;
Qh->TDs = (VOID *)Td;
}
/**
Unlink TD from the QH.
@@ -178,8 +174,8 @@ UhciLinkTdToQh (
**/
VOID
UhciUnlinkTdFromQh (
IN UHCI_QH_SW *Qh,
IN UHCI_TD_SW *Td
IN UHCI_QH_SW *Qh,
IN UHCI_TD_SW *Td
)
{
ASSERT ((Qh != NULL) && (Td != NULL));
@@ -188,7 +184,6 @@ UhciUnlinkTdFromQh (
Qh->TDs = NULL;
}
/**
Append a new TD To the previous TD.
@@ -199,9 +194,9 @@ UhciUnlinkTdFromQh (
**/
VOID
UhciAppendTd (
IN USB_HC_DEV *Uhc,
IN UHCI_TD_SW *PrevTd,
IN UHCI_TD_SW *ThisTd
IN USB_HC_DEV *Uhc,
IN UHCI_TD_SW *PrevTd,
IN UHCI_TD_SW *ThisTd
)
{
EFI_PHYSICAL_ADDRESS PhyAddr;
@@ -211,10 +206,9 @@ UhciAppendTd (
ASSERT ((PrevTd != NULL) && (ThisTd != NULL));
PrevTd->TdHw.NextLink = TD_LINK (PhyAddr, TRUE, FALSE);
PrevTd->NextTd = (VOID *) ThisTd;
PrevTd->NextTd = (VOID *)ThisTd;
}
/**
Delete a list of TDs.
@@ -226,23 +220,22 @@ UhciAppendTd (
**/
VOID
UhciDestoryTds (
IN USB_HC_DEV *Uhc,
IN UHCI_TD_SW *FirstTd
IN USB_HC_DEV *Uhc,
IN UHCI_TD_SW *FirstTd
)
{
UHCI_TD_SW *NextTd;
UHCI_TD_SW *ThisTd;
UHCI_TD_SW *NextTd;
UHCI_TD_SW *ThisTd;
NextTd = FirstTd;
while (NextTd != NULL) {
ThisTd = NextTd;
NextTd = ThisTd->NextTd;
ThisTd = NextTd;
NextTd = ThisTd->NextTd;
UsbHcFreeMem (Uhc->MemPool, ThisTd, sizeof (UHCI_TD_SW));
}
}
/**
Create an initialize a new queue head.
@@ -254,11 +247,11 @@ UhciDestoryTds (
**/
UHCI_QH_SW *
UhciCreateQh (
IN USB_HC_DEV *Uhc,
IN UINTN Interval
IN USB_HC_DEV *Uhc,
IN UINTN Interval
)
{
UHCI_QH_SW *Qh;
UHCI_QH_SW *Qh;
Qh = UsbHcAllocateMem (Uhc->MemPool, sizeof (UHCI_QH_SW));
@@ -268,14 +261,13 @@ UhciCreateQh (
Qh->QhHw.HorizonLink = QH_HLINK (NULL, TRUE);
Qh->QhHw.VerticalLink = QH_VLINK (NULL, TRUE);
Qh->Interval = UhciConvertPollRate(Interval);
Qh->Interval = UhciConvertPollRate (Interval);
Qh->TDs = NULL;
Qh->NextQh = NULL;
return Qh;
}
/**
Create and intialize a TD.
@@ -286,12 +278,12 @@ UhciCreateQh (
**/
UHCI_TD_SW *
UhciCreateTd (
IN USB_HC_DEV *Uhc
IN USB_HC_DEV *Uhc
)
{
UHCI_TD_SW *Td;
UHCI_TD_SW *Td;
Td = UsbHcAllocateMem (Uhc->MemPool, sizeof (UHCI_TD_SW));
Td = UsbHcAllocateMem (Uhc->MemPool, sizeof (UHCI_TD_SW));
if (Td == NULL) {
return NULL;
}
@@ -304,7 +296,6 @@ UhciCreateTd (
return Td;
}
/**
Create and initialize a TD for Setup Stage of a control transfer.
@@ -319,14 +310,14 @@ UhciCreateTd (
**/
UHCI_TD_SW *
UhciCreateSetupTd (
IN USB_HC_DEV *Uhc,
IN UINT8 DevAddr,
IN UINT8 *Request,
IN UINT8 *RequestPhy,
IN BOOLEAN IsLow
IN USB_HC_DEV *Uhc,
IN UINT8 DevAddr,
IN UINT8 *Request,
IN UINT8 *RequestPhy,
IN BOOLEAN IsLow
)
{
UHCI_TD_SW *Td;
UHCI_TD_SW *Td;
Td = UhciCreateTd (Uhc);
@@ -344,17 +335,16 @@ UhciCreateSetupTd (
Td->TdHw.EndPoint = 0;
Td->TdHw.LowSpeed = IsLow ? 1 : 0;
Td->TdHw.DeviceAddr = DevAddr & 0x7F;
Td->TdHw.MaxPacketLen = (UINT32) (sizeof (EFI_USB_DEVICE_REQUEST) - 1);
Td->TdHw.MaxPacketLen = (UINT32)(sizeof (EFI_USB_DEVICE_REQUEST) - 1);
Td->TdHw.PidCode = SETUP_PACKET_ID;
Td->TdHw.DataBuffer = (UINT32) (UINTN) RequestPhy;
Td->TdHw.DataBuffer = (UINT32)(UINTN)RequestPhy;
Td->Data = Request;
Td->DataLen = (UINT16) sizeof (EFI_USB_DEVICE_REQUEST);
Td->Data = Request;
Td->DataLen = (UINT16)sizeof (EFI_USB_DEVICE_REQUEST);
return Td;
}
/**
Create a TD for data.
@@ -373,15 +363,15 @@ UhciCreateSetupTd (
**/
UHCI_TD_SW *
UhciCreateDataTd (
IN USB_HC_DEV *Uhc,
IN UINT8 DevAddr,
IN UINT8 Endpoint,
IN UINT8 *DataPtr,
IN UINT8 *DataPhyPtr,
IN UINTN Len,
IN UINT8 PktId,
IN UINT8 Toggle,
IN BOOLEAN IsLow
IN USB_HC_DEV *Uhc,
IN UINT8 DevAddr,
IN UINT8 Endpoint,
IN UINT8 *DataPtr,
IN UINT8 *DataPhyPtr,
IN UINTN Len,
IN UINT8 PktId,
IN UINT8 Toggle,
IN BOOLEAN IsLow
)
{
UHCI_TD_SW *Td;
@@ -391,7 +381,7 @@ UhciCreateDataTd (
//
ASSERT (Len <= 0x500);
Td = UhciCreateTd (Uhc);
Td = UhciCreateTd (Uhc);
if (Td == NULL) {
return NULL;
@@ -407,17 +397,16 @@ UhciCreateDataTd (
Td->TdHw.DataToggle = Toggle & 0x01;
Td->TdHw.EndPoint = Endpoint & 0x0F;
Td->TdHw.DeviceAddr = DevAddr & 0x7F;
Td->TdHw.MaxPacketLen = (UINT32) (Len - 1);
Td->TdHw.PidCode = (UINT8) PktId;
Td->TdHw.DataBuffer = (UINT32) (UINTN) DataPhyPtr;
Td->TdHw.MaxPacketLen = (UINT32)(Len - 1);
Td->TdHw.PidCode = (UINT8)PktId;
Td->TdHw.DataBuffer = (UINT32)(UINTN)DataPhyPtr;
Td->Data = DataPtr;
Td->DataLen = (UINT16) Len;
Td->Data = DataPtr;
Td->DataLen = (UINT16)Len;
return Td;
}
/**
Create TD for the Status Stage of control transfer.
@@ -431,13 +420,13 @@ UhciCreateDataTd (
**/
UHCI_TD_SW *
UhciCreateStatusTd (
IN USB_HC_DEV *Uhc,
IN UINT8 DevAddr,
IN UINT8 PktId,
IN BOOLEAN IsLow
IN USB_HC_DEV *Uhc,
IN UINT8 DevAddr,
IN UINT8 PktId,
IN BOOLEAN IsLow
)
{
UHCI_TD_SW *Td;
UHCI_TD_SW *Td;
Td = UhciCreateTd (Uhc);
@@ -451,21 +440,20 @@ UhciCreateStatusTd (
Td->TdHw.IntOnCpl = FALSE;
Td->TdHw.ErrorCount = 0x03;
Td->TdHw.Status |= USBTD_ACTIVE;
Td->TdHw.MaxPacketLen = 0x7FF; //0x7FF: there is no data (refer to UHCI spec)
Td->TdHw.MaxPacketLen = 0x7FF; // 0x7FF: there is no data (refer to UHCI spec)
Td->TdHw.DataToggle = 1;
Td->TdHw.EndPoint = 0;
Td->TdHw.LowSpeed = IsLow ? 1 : 0;
Td->TdHw.DeviceAddr = DevAddr & 0x7F;
Td->TdHw.PidCode = (UINT8) PktId;
Td->TdHw.DataBuffer = (UINT32) (UINTN) NULL;
Td->TdHw.PidCode = (UINT8)PktId;
Td->TdHw.DataBuffer = (UINT32)(UINTN)NULL;
Td->Data = NULL;
Td->DataLen = 0;
Td->Data = NULL;
Td->DataLen = 0;
return Td;
}
/**
Create Tds list for Control Transfer.
@@ -485,27 +473,26 @@ UhciCreateStatusTd (
**/
UHCI_TD_SW *
UhciCreateCtrlTds (
IN USB_HC_DEV *Uhc,
IN UINT8 DeviceAddr,
IN UINT8 DataPktId,
IN UINT8 *Request,
IN UINT8 *RequestPhy,
IN UINT8 *Data,
IN UINT8 *DataPhy,
IN UINTN DataLen,
IN UINT8 MaxPacket,
IN BOOLEAN IsLow
IN USB_HC_DEV *Uhc,
IN UINT8 DeviceAddr,
IN UINT8 DataPktId,
IN UINT8 *Request,
IN UINT8 *RequestPhy,
IN UINT8 *Data,
IN UINT8 *DataPhy,
IN UINTN DataLen,
IN UINT8 MaxPacket,
IN BOOLEAN IsLow
)
{
UHCI_TD_SW *SetupTd;
UHCI_TD_SW *FirstDataTd;
UHCI_TD_SW *DataTd;
UHCI_TD_SW *PrevDataTd;
UHCI_TD_SW *StatusTd;
UINT8 DataToggle;
UINT8 StatusPktId;
UINTN ThisTdLen;
UHCI_TD_SW *SetupTd;
UHCI_TD_SW *FirstDataTd;
UHCI_TD_SW *DataTd;
UHCI_TD_SW *PrevDataTd;
UHCI_TD_SW *StatusTd;
UINT8 DataToggle;
UINT8 StatusPktId;
UINTN ThisTdLen;
DataTd = NULL;
SetupTd = NULL;
@@ -537,8 +524,8 @@ UhciCreateCtrlTds (
Uhc,
DeviceAddr,
0,
Data, //cpu memory address
DataPhy, //Pci memory address
Data, // cpu memory address
DataPhy, // Pci memory address
ThisTdLen,
DataPktId,
DataToggle,
@@ -557,10 +544,10 @@ UhciCreateCtrlTds (
}
DataToggle ^= 1;
PrevDataTd = DataTd;
Data += ThisTdLen;
DataPhy += ThisTdLen;
DataLen -= ThisTdLen;
PrevDataTd = DataTd;
Data += ThisTdLen;
DataPhy += ThisTdLen;
DataLen -= ThisTdLen;
}
//
@@ -602,7 +589,6 @@ FREE_TD:
return NULL;
}
/**
Create Tds list for Bulk/Interrupt Transfer.
@@ -622,22 +608,22 @@ FREE_TD:
**/
UHCI_TD_SW *
UhciCreateBulkOrIntTds (
IN USB_HC_DEV *Uhc,
IN UINT8 DevAddr,
IN UINT8 EndPoint,
IN UINT8 PktId,
IN UINT8 *Data,
IN UINT8 *DataPhy,
IN UINTN DataLen,
IN OUT UINT8 *DataToggle,
IN UINT8 MaxPacket,
IN BOOLEAN IsLow
IN USB_HC_DEV *Uhc,
IN UINT8 DevAddr,
IN UINT8 EndPoint,
IN UINT8 PktId,
IN UINT8 *Data,
IN UINT8 *DataPhy,
IN UINTN DataLen,
IN OUT UINT8 *DataToggle,
IN UINT8 MaxPacket,
IN BOOLEAN IsLow
)
{
UHCI_TD_SW *DataTd;
UHCI_TD_SW *FirstDataTd;
UHCI_TD_SW *PrevDataTd;
UINTN ThisTdLen;
UHCI_TD_SW *DataTd;
UHCI_TD_SW *FirstDataTd;
UHCI_TD_SW *PrevDataTd;
UINTN ThisTdLen;
DataTd = NULL;
FirstDataTd = NULL;

132
MdeModulePkg/Bus/Pci/UhciDxe/UhciQueue.h
View File

@@ -30,9 +30,9 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
(((UINT32) ((UINTN) (Pointer)) & 0xFFFFFFF0) | \
((VertFirst) ? 0x04 : 0) | ((Terminate) ? 0x01 : 0))
#define LINK_TERMINATED(Link) (((Link) & 0x01) != 0)
#define LINK_TERMINATED(Link) (((Link) & 0x01) != 0)
#define UHCI_ADDR(QhOrTd) ((VOID *) (UINTN) ((QhOrTd) & 0xFFFFFFF0))
#define UHCI_ADDR(QhOrTd) ((VOID *) (UINTN) ((QhOrTd) & 0xFFFFFFF0))
#pragma pack(1)
//
@@ -41,8 +41,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
// This is the same as frame list entry.
//
typedef struct {
UINT32 HorizonLink;
UINT32 VerticalLink;
UINT32 HorizonLink;
UINT32 VerticalLink;
} UHCI_QH_HW;
//
@@ -50,23 +50,23 @@ typedef struct {
// Next pointer: 28, Reserved: 1, Vertical First: 1, NextIsQh: 1, Terminate: 1
//
typedef struct {
UINT32 NextLink;
UINT32 ActualLen : 11;
UINT32 Reserved1 : 5;
UINT32 Status : 8;
UINT32 IntOnCpl : 1;
UINT32 IsIsoch : 1;
UINT32 LowSpeed : 1;
UINT32 ErrorCount : 2;
UINT32 ShortPacket : 1;
UINT32 Reserved2 : 2;
UINT32 PidCode : 8;
UINT32 DeviceAddr : 7;
UINT32 EndPoint : 4;
UINT32 DataToggle : 1;
UINT32 Reserved3 : 1;
UINT32 MaxPacketLen: 11;
UINT32 DataBuffer;
UINT32 NextLink;
UINT32 ActualLen : 11;
UINT32 Reserved1 : 5;
UINT32 Status : 8;
UINT32 IntOnCpl : 1;
UINT32 IsIsoch : 1;
UINT32 LowSpeed : 1;
UINT32 ErrorCount : 2;
UINT32 ShortPacket : 1;
UINT32 Reserved2 : 2;
UINT32 PidCode : 8;
UINT32 DeviceAddr : 7;
UINT32 EndPoint : 4;
UINT32 DataToggle : 1;
UINT32 Reserved3 : 1;
UINT32 MaxPacketLen : 11;
UINT32 DataBuffer;
} UHCI_TD_HW;
#pragma pack()
@@ -74,20 +74,19 @@ typedef struct _UHCI_TD_SW UHCI_TD_SW;
typedef struct _UHCI_QH_SW UHCI_QH_SW;
struct _UHCI_QH_SW {
UHCI_QH_HW QhHw;
UHCI_QH_SW *NextQh;
UHCI_TD_SW *TDs;
UINTN Interval;
UHCI_QH_HW QhHw;
UHCI_QH_SW *NextQh;
UHCI_TD_SW *TDs;
UINTN Interval;
};
struct _UHCI_TD_SW {
UHCI_TD_HW TdHw;
UHCI_TD_SW *NextTd;
UINT8 *Data;
UINT16 DataLen;
UHCI_TD_HW TdHw;
UHCI_TD_SW *NextTd;
UINT8 *Data;
UINT16 DataLen;
};
/**
Link the TD To QH.
@@ -98,12 +97,11 @@ struct _UHCI_TD_SW {
**/
VOID
UhciLinkTdToQh (
IN USB_HC_DEV *Uhc,
IN UHCI_QH_SW *Qh,
IN UHCI_TD_SW *Td
IN USB_HC_DEV *Uhc,
IN UHCI_QH_SW *Qh,
IN UHCI_TD_SW *Td
);
/**
Unlink TD from the QH.
@@ -115,11 +113,10 @@ UhciLinkTdToQh (
**/
VOID
UhciUnlinkTdFromQh (
IN UHCI_QH_SW *Qh,
IN UHCI_TD_SW *Td
IN UHCI_QH_SW *Qh,
IN UHCI_TD_SW *Td
);
/**
Map address of request structure buffer.
@@ -134,13 +131,12 @@ UhciUnlinkTdFromQh (
**/
EFI_STATUS
UhciMapUserRequest (
IN USB_HC_DEV *Uhc,
IN OUT VOID *Request,
OUT UINT8 **MappedAddr,
OUT VOID **Map
IN USB_HC_DEV *Uhc,
IN OUT VOID *Request,
OUT UINT8 **MappedAddr,
OUT VOID **Map
);
/**
Map address of user data buffer.
@@ -167,7 +163,6 @@ UhciMapUserData (
OUT VOID **Map
);
/**
Delete a list of TDs.
@@ -179,11 +174,10 @@ UhciMapUserData (
**/
VOID
UhciDestoryTds (
IN USB_HC_DEV *Uhc,
IN UHCI_TD_SW *FirstTd
IN USB_HC_DEV *Uhc,
IN UHCI_TD_SW *FirstTd
);
/**
Create an initialize a new queue head.
@@ -195,11 +189,10 @@ UhciDestoryTds (
**/
UHCI_QH_SW *
UhciCreateQh (
IN USB_HC_DEV *Uhc,
IN UINTN Interval
IN USB_HC_DEV *Uhc,
IN UINTN Interval
);
/**
Create Tds list for Control Transfer.
@@ -219,19 +212,18 @@ UhciCreateQh (
**/
UHCI_TD_SW *
UhciCreateCtrlTds (
IN USB_HC_DEV *Uhc,
IN UINT8 DeviceAddr,
IN UINT8 DataPktId,
IN UINT8 *Request,
IN UINT8 *RequestPhy,
IN UINT8 *Data,
IN UINT8 *DataPhy,
IN UINTN DataLen,
IN UINT8 MaxPacket,
IN BOOLEAN IsLow
IN USB_HC_DEV *Uhc,
IN UINT8 DeviceAddr,
IN UINT8 DataPktId,
IN UINT8 *Request,
IN UINT8 *RequestPhy,
IN UINT8 *Data,
IN UINT8 *DataPhy,
IN UINTN DataLen,
IN UINT8 MaxPacket,
IN BOOLEAN IsLow
);
/**
Create Tds list for Bulk/Interrupt Transfer.
@@ -251,16 +243,16 @@ UhciCreateCtrlTds (
**/
UHCI_TD_SW *
UhciCreateBulkOrIntTds (
IN USB_HC_DEV *Uhc,
IN UINT8 DevAddr,
IN UINT8 EndPoint,
IN UINT8 PktId,
IN UINT8 *Data,
IN UINT8 *DataPhy,
IN UINTN DataLen,
IN OUT UINT8 *DataToggle,
IN UINT8 MaxPacket,
IN BOOLEAN IsLow
IN USB_HC_DEV *Uhc,
IN UINT8 DevAddr,
IN UINT8 EndPoint,
IN UINT8 PktId,
IN UINT8 *Data,
IN UINT8 *DataPhy,
IN UINTN DataLen,
IN OUT UINT8 *DataToggle,
IN UINT8 MaxPacket,
IN BOOLEAN IsLow
);
#endif

93
MdeModulePkg/Bus/Pci/UhciDxe/UhciReg.c
View File

@@ -9,7 +9,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include "Uhci.h"
/**
Read a UHCI register.
@@ -21,21 +20,21 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
UINT16
UhciReadReg (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT32 Offset
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT32 Offset
)
{
UINT16 Data;
EFI_STATUS Status;
Status = PciIo->Io.Read (
PciIo,
EfiPciIoWidthUint16,
USB_BAR_INDEX,
Offset,
1,
&Data
);
PciIo,
EfiPciIoWidthUint16,
USB_BAR_INDEX,
Offset,
1,
&Data
);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "UhciReadReg: PciIo Io.Read error: %r at offset %d\n", Status, Offset));
@@ -46,7 +45,6 @@ UhciReadReg (
return Data;
}
/**
Write data to UHCI register.
@@ -57,28 +55,27 @@ UhciReadReg (
**/
VOID
UhciWriteReg (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT32 Offset,
IN UINT16 Data
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT32 Offset,
IN UINT16 Data
)
{
EFI_STATUS Status;
Status = PciIo->Io.Write (
PciIo,
EfiPciIoWidthUint16,
USB_BAR_INDEX,
Offset,
1,
&Data
);
PciIo,
EfiPciIoWidthUint16,
USB_BAR_INDEX,
Offset,
1,
&Data
);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "UhciWriteReg: PciIo Io.Write error: %r at offset %d\n", Status, Offset));
}
}
/**
Set a bit of the UHCI Register.
@@ -89,19 +86,18 @@ UhciWriteReg (
**/
VOID
UhciSetRegBit (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT32 Offset,
IN UINT16 Bit
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT32 Offset,
IN UINT16 Bit
)
{
UINT16 Data;
Data = UhciReadReg (PciIo, Offset);
Data = (UINT16) (Data |Bit);
Data = (UINT16)(Data |Bit);
UhciWriteReg (PciIo, Offset, Data);
}
/**
Clear a bit of the UHCI Register.
@@ -112,19 +108,18 @@ UhciSetRegBit (
**/
VOID
UhciClearRegBit (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT32 Offset,
IN UINT16 Bit
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT32 Offset,
IN UINT16 Bit
)
{
UINT16 Data;
Data = UhciReadReg (PciIo, Offset);
Data = (UINT16) (Data & ~Bit);
Data = (UINT16)(Data & ~Bit);
UhciWriteReg (PciIo, Offset, Data);
}
/**
Clear all the interrutp status bits, these bits
are Write-Clean.
@@ -134,7 +129,7 @@ UhciClearRegBit (
**/
VOID
UhciAckAllInterrupt (
IN USB_HC_DEV *Uhc
IN USB_HC_DEV *Uhc
)
{
UhciWriteReg (Uhc->PciIo, USBSTS_OFFSET, 0x3F);
@@ -149,7 +144,6 @@ UhciAckAllInterrupt (
}
}
/**
Stop the host controller.
@@ -162,12 +156,12 @@ UhciAckAllInterrupt (
**/
EFI_STATUS
UhciStopHc (
IN USB_HC_DEV *Uhc,
IN UINTN Timeout
IN USB_HC_DEV *Uhc,
IN UINTN Timeout
)
{
UINT16 UsbSts;
UINTN Index;
UINT16 UsbSts;
UINTN Index;
UhciClearRegBit (Uhc->PciIo, USBCMD_OFFSET, USBCMD_RS);
@@ -188,7 +182,6 @@ UhciStopHc (
return EFI_TIMEOUT;
}
/**
Check whether the host controller operates well.
@@ -200,10 +193,10 @@ UhciStopHc (
**/
BOOLEAN
UhciIsHcWorking (
IN EFI_PCI_IO_PROTOCOL *PciIo
IN EFI_PCI_IO_PROTOCOL *PciIo
)
{
UINT16 UsbSts;
UINT16 UsbSts;
UsbSts = UhciReadReg (PciIo, USBSTS_OFFSET);
@@ -215,7 +208,6 @@ UhciIsHcWorking (
return TRUE;
}
/**
Set the UHCI frame list base address. It can't use
UhciWriteReg which access memory in UINT16.
@@ -226,20 +218,20 @@ UhciIsHcWorking (
**/
VOID
UhciSetFrameListBaseAddr (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN VOID *Addr
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN VOID *Addr
)
{
EFI_STATUS Status;
UINT32 Data;
EFI_STATUS Status;
UINT32 Data;
Data = (UINT32) ((UINTN) Addr & 0xFFFFF000);
Data = (UINT32)((UINTN)Addr & 0xFFFFF000);
Status = PciIo->Io.Write (
PciIo,
EfiPciIoWidthUint32,
USB_BAR_INDEX,
(UINT64) USB_FRAME_BASE_OFFSET,
(UINT64)USB_FRAME_BASE_OFFSET,
1,
&Data
);
@@ -249,7 +241,6 @@ UhciSetFrameListBaseAddr (
}
}
/**
Disable USB Emulation.
@@ -258,10 +249,10 @@ UhciSetFrameListBaseAddr (
**/
VOID
UhciTurnOffUsbEmulation (
IN EFI_PCI_IO_PROTOCOL *PciIo
IN EFI_PCI_IO_PROTOCOL *PciIo
)
{
UINT16 Command;
UINT16 Command;
Command = 0;

138
MdeModulePkg/Bus/Pci/UhciDxe/UhciReg.h
View File

@@ -14,42 +14,42 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
// UHCI register offset
//
#define UHCI_FRAME_NUM 1024
#define UHCI_FRAME_NUM 1024
//
// Register offset and PCI related staff
//
#define USB_BAR_INDEX 4
#define USB_BAR_INDEX 4
#define USBCMD_OFFSET 0
#define USBSTS_OFFSET 2
#define USBINTR_OFFSET 4
#define USBPORTSC_OFFSET 0x10
#define USB_FRAME_NO_OFFSET 6
#define USB_FRAME_BASE_OFFSET 8
#define USB_EMULATION_OFFSET 0xC0
#define USBCMD_OFFSET 0
#define USBSTS_OFFSET 2
#define USBINTR_OFFSET 4
#define USBPORTSC_OFFSET 0x10
#define USB_FRAME_NO_OFFSET 6
#define USB_FRAME_BASE_OFFSET 8
#define USB_EMULATION_OFFSET 0xC0
//
// Packet IDs
//
#define SETUP_PACKET_ID 0x2D
#define INPUT_PACKET_ID 0x69
#define OUTPUT_PACKET_ID 0xE1
#define ERROR_PACKET_ID 0x55
#define SETUP_PACKET_ID 0x2D
#define INPUT_PACKET_ID 0x69
#define OUTPUT_PACKET_ID 0xE1
#define ERROR_PACKET_ID 0x55
//
// USB port status and control bit definition.
//
#define USBPORTSC_CCS BIT0 // Current Connect Status
#define USBPORTSC_CSC BIT1 // Connect Status Change
#define USBPORTSC_PED BIT2 // Port Enable / Disable
#define USBPORTSC_PEDC BIT3 // Port Enable / Disable Change
#define USBPORTSC_LSL BIT4 // Line Status Low BIT
#define USBPORTSC_LSH BIT5 // Line Status High BIT
#define USBPORTSC_RD BIT6 // Resume Detect
#define USBPORTSC_LSDA BIT8 // Low Speed Device Attached
#define USBPORTSC_PR BIT9 // Port Reset
#define USBPORTSC_SUSP BIT12 // Suspend
#define USBPORTSC_CCS BIT0 // Current Connect Status
#define USBPORTSC_CSC BIT1 // Connect Status Change
#define USBPORTSC_PED BIT2 // Port Enable / Disable
#define USBPORTSC_PEDC BIT3 // Port Enable / Disable Change
#define USBPORTSC_LSL BIT4 // Line Status Low BIT
#define USBPORTSC_LSH BIT5 // Line Status High BIT
#define USBPORTSC_RD BIT6 // Resume Detect
#define USBPORTSC_LSDA BIT8 // Low Speed Device Attached
#define USBPORTSC_PR BIT9 // Port Reset
#define USBPORTSC_SUSP BIT12 // Suspend
//
// UHCI Spec said it must implement 2 ports each host at least,
@@ -61,33 +61,32 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
//
// Command register bit definitions
//
#define USBCMD_RS BIT0 // Run/Stop
#define USBCMD_HCRESET BIT1 // Host reset
#define USBCMD_GRESET BIT2 // Global reset
#define USBCMD_EGSM BIT3 // Global Suspend Mode
#define USBCMD_FGR BIT4 // Force Global Resume
#define USBCMD_SWDBG BIT5 // SW Debug mode
#define USBCMD_CF BIT6 // Config Flag (sw only)
#define USBCMD_MAXP BIT7 // Max Packet (0 = 32, 1 = 64)
#define USBCMD_RS BIT0 // Run/Stop
#define USBCMD_HCRESET BIT1 // Host reset
#define USBCMD_GRESET BIT2 // Global reset
#define USBCMD_EGSM BIT3 // Global Suspend Mode
#define USBCMD_FGR BIT4 // Force Global Resume
#define USBCMD_SWDBG BIT5 // SW Debug mode
#define USBCMD_CF BIT6 // Config Flag (sw only)
#define USBCMD_MAXP BIT7 // Max Packet (0 = 32, 1 = 64)
//
// USB Status register bit definitions
//
#define USBSTS_USBINT BIT0 // Interrupt due to IOC
#define USBSTS_ERROR BIT1 // Interrupt due to error
#define USBSTS_RD BIT2 // Resume Detect
#define USBSTS_HSE BIT3 // Host System Error
#define USBSTS_HCPE BIT4 // Host Controller Process Error
#define USBSTS_HCH BIT5 // HC Halted
#define USBTD_ACTIVE BIT7 // TD is still active
#define USBTD_STALLED BIT6 // TD is stalled
#define USBTD_BUFFERR BIT5 // Buffer underflow or overflow
#define USBTD_BABBLE BIT4 // Babble condition
#define USBTD_NAK BIT3 // NAK is received
#define USBTD_CRC BIT2 // CRC/Time out error
#define USBTD_BITSTUFF BIT1 // Bit stuff error
#define USBSTS_USBINT BIT0 // Interrupt due to IOC
#define USBSTS_ERROR BIT1 // Interrupt due to error
#define USBSTS_RD BIT2 // Resume Detect
#define USBSTS_HSE BIT3 // Host System Error
#define USBSTS_HCPE BIT4 // Host Controller Process Error
#define USBSTS_HCH BIT5 // HC Halted
#define USBTD_ACTIVE BIT7 // TD is still active
#define USBTD_STALLED BIT6 // TD is stalled
#define USBTD_BUFFERR BIT5 // Buffer underflow or overflow
#define USBTD_BABBLE BIT4 // Babble condition
#define USBTD_NAK BIT3 // NAK is received
#define USBTD_CRC BIT2 // CRC/Time out error
#define USBTD_BITSTUFF BIT1 // Bit stuff error
/**
Read a UHCI register.
@@ -100,12 +99,10 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
UINT16
UhciReadReg (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT32 Offset
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT32 Offset
);
/**
Write data to UHCI register.
@@ -118,13 +115,11 @@ UhciReadReg (
**/
VOID
UhciWriteReg (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT32 Offset,
IN UINT16 Data
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT32 Offset,
IN UINT16 Data
);
/**
Set a bit of the UHCI Register.
@@ -137,13 +132,11 @@ UhciWriteReg (
**/
VOID
UhciSetRegBit (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT32 Offset,
IN UINT16 Bit
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT32 Offset,
IN UINT16 Bit
);
/**
Clear a bit of the UHCI Register.
@@ -156,12 +149,11 @@ UhciSetRegBit (
**/
VOID
UhciClearRegBit (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT32 Offset,
IN UINT16 Bit
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT32 Offset,
IN UINT16 Bit
);
/**
Clear all the interrutp status bits, these bits
are Write-Clean.
@@ -173,10 +165,9 @@ UhciClearRegBit (
**/
VOID
UhciAckAllInterrupt (
IN USB_HC_DEV *Uhc
IN USB_HC_DEV *Uhc
);
/**
Stop the host controller.
@@ -189,12 +180,10 @@ UhciAckAllInterrupt (
**/
EFI_STATUS
UhciStopHc (
IN USB_HC_DEV *Uhc,
IN UINTN Timeout
IN USB_HC_DEV *Uhc,
IN UINTN Timeout
);
/**
Check whether the host controller operates well.
@@ -206,10 +195,9 @@ UhciStopHc (
**/
BOOLEAN
UhciIsHcWorking (
IN EFI_PCI_IO_PROTOCOL *PciIo
IN EFI_PCI_IO_PROTOCOL *PciIo
);
/**
Set the UHCI frame list base address. It can't use
UhciWriteReg which access memory in UINT16.
@@ -222,11 +210,10 @@ UhciIsHcWorking (
**/
VOID
UhciSetFrameListBaseAddr (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN VOID *Addr
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN VOID *Addr
);
/**
Disable USB Emulation.
@@ -237,6 +224,7 @@ UhciSetFrameListBaseAddr (
**/
VOID
UhciTurnOffUsbEmulation (
IN EFI_PCI_IO_PROTOCOL *PciIo
IN EFI_PCI_IO_PROTOCOL *PciIo
);
#endif

293
MdeModulePkg/Bus/Pci/UhciDxe/UhciSched.c
View File

@@ -9,7 +9,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include "Uhci.h"
/**
Create Frame List Structure.
@@ -22,7 +21,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
EFI_STATUS
UhciInitFrameList (
IN USB_HC_DEV *Uhc
IN USB_HC_DEV *Uhc
)
{
EFI_PHYSICAL_ADDRESS MappedAddr;
@@ -70,14 +69,14 @@ UhciInitFrameList (
goto ON_ERROR;
}
Uhc->FrameBase = (UINT32 *) (UINTN) Buffer;
Uhc->FrameMapping = Mapping;
Uhc->FrameBase = (UINT32 *)(UINTN)Buffer;
Uhc->FrameMapping = Mapping;
//
// Tell the Host Controller where the Frame List lies,
// by set the Frame List Base Address Register.
//
UhciSetFrameListBaseAddr (Uhc->PciIo, (VOID *) (UINTN) MappedAddr);
UhciSetFrameListBaseAddr (Uhc->PciIo, (VOID *)(UINTN)MappedAddr);
//
// Allocate the QH used by sync interrupt/control/bulk transfer.
@@ -85,9 +84,9 @@ UhciInitFrameList (
// can be reclaimed. Notice, LS don't support bulk transfer and
// also doesn't support BW reclamation.
//
Uhc->SyncIntQh = UhciCreateQh (Uhc, 1);
Uhc->CtrlQh = UhciCreateQh (Uhc, 1);
Uhc->BulkQh = UhciCreateQh (Uhc, 1);
Uhc->SyncIntQh = UhciCreateQh (Uhc, 1);
Uhc->CtrlQh = UhciCreateQh (Uhc, 1);
Uhc->BulkQh = UhciCreateQh (Uhc, 1);
if ((Uhc->SyncIntQh == NULL) || (Uhc->CtrlQh == NULL) || (Uhc->BulkQh == NULL)) {
Uhc->PciIo->Unmap (Uhc->PciIo, Mapping);
@@ -102,22 +101,22 @@ UhciInitFrameList (
// Each frame entry is linked to this sequence of QH. These QH
// will remain on the schedul, never got removed
//
PhyAddr = UsbHcGetPciAddressForHostMem (Uhc->MemPool, Uhc->CtrlQh, sizeof (UHCI_QH_HW));
Uhc->SyncIntQh->QhHw.HorizonLink = QH_HLINK (PhyAddr, FALSE);
Uhc->SyncIntQh->NextQh = Uhc->CtrlQh;
PhyAddr = UsbHcGetPciAddressForHostMem (Uhc->MemPool, Uhc->CtrlQh, sizeof (UHCI_QH_HW));
Uhc->SyncIntQh->QhHw.HorizonLink = QH_HLINK (PhyAddr, FALSE);
Uhc->SyncIntQh->NextQh = Uhc->CtrlQh;
PhyAddr = UsbHcGetPciAddressForHostMem (Uhc->MemPool, Uhc->BulkQh, sizeof (UHCI_QH_HW));
Uhc->CtrlQh->QhHw.HorizonLink = QH_HLINK (PhyAddr, FALSE);
Uhc->CtrlQh->NextQh = Uhc->BulkQh;
PhyAddr = UsbHcGetPciAddressForHostMem (Uhc->MemPool, Uhc->BulkQh, sizeof (UHCI_QH_HW));
Uhc->CtrlQh->QhHw.HorizonLink = QH_HLINK (PhyAddr, FALSE);
Uhc->CtrlQh->NextQh = Uhc->BulkQh;
//
// Some old platform such as Intel's Tiger 4 has a difficult time
// in supporting the full speed bandwidth reclamation in the previous
// mentioned form. Most new platforms don't suffer it.
//
Uhc->BulkQh->QhHw.HorizonLink = QH_HLINK (PhyAddr, FALSE);
Uhc->BulkQh->QhHw.HorizonLink = QH_HLINK (PhyAddr, FALSE);
Uhc->BulkQh->NextQh = NULL;
Uhc->BulkQh->NextQh = NULL;
Uhc->FrameBaseHostAddr = AllocateZeroPool (4096);
if (Uhc->FrameBaseHostAddr == NULL) {
@@ -127,7 +126,7 @@ UhciInitFrameList (
PhyAddr = UsbHcGetPciAddressForHostMem (Uhc->MemPool, Uhc->SyncIntQh, sizeof (UHCI_QH_HW));
for (Index = 0; Index < UHCI_FRAME_NUM; Index++) {
Uhc->FrameBase[Index] = QH_HLINK (PhyAddr, FALSE);
Uhc->FrameBase[Index] = QH_HLINK (PhyAddr, FALSE);
Uhc->FrameBaseHostAddr[Index] = (UINT32)(UINTN)Uhc->SyncIntQh;
}
@@ -150,7 +149,6 @@ ON_ERROR:
return Status;
}
/**
Destory FrameList buffer.
@@ -159,7 +157,7 @@ ON_ERROR:
**/
VOID
UhciDestoryFrameList (
IN USB_HC_DEV *Uhc
IN USB_HC_DEV *Uhc
)
{
//
@@ -172,7 +170,7 @@ UhciDestoryFrameList (
Uhc->PciIo->FreeBuffer (
Uhc->PciIo,
EFI_SIZE_TO_PAGES (4096),
(VOID *) Uhc->FrameBase
(VOID *)Uhc->FrameBase
);
if (Uhc->FrameBaseHostAddr != NULL) {
@@ -191,14 +189,13 @@ UhciDestoryFrameList (
UsbHcFreeMem (Uhc->MemPool, Uhc->BulkQh, sizeof (UHCI_QH_SW));
}
Uhc->FrameBase = NULL;
Uhc->FrameBaseHostAddr = NULL;
Uhc->SyncIntQh = NULL;
Uhc->CtrlQh = NULL;
Uhc->BulkQh = NULL;
Uhc->FrameBase = NULL;
Uhc->FrameBaseHostAddr = NULL;
Uhc->SyncIntQh = NULL;
Uhc->CtrlQh = NULL;
Uhc->BulkQh = NULL;
}
/**
Convert the poll rate to the maxium 2^n that is smaller
than Interval.
@@ -210,10 +207,10 @@ UhciDestoryFrameList (
**/
UINTN
UhciConvertPollRate (
IN UINTN Interval
IN UINTN Interval
)
{
UINTN BitCount;
UINTN BitCount;
ASSERT (Interval != 0);
@@ -230,7 +227,6 @@ UhciConvertPollRate (
return (UINTN)1 << (BitCount - 1);
}
/**
Link a queue head (for asynchronous interrupt transfer) to
the frame list.
@@ -241,15 +237,15 @@ UhciConvertPollRate (
**/
VOID
UhciLinkQhToFrameList (
USB_HC_DEV *Uhc,
UHCI_QH_SW *Qh
USB_HC_DEV *Uhc,
UHCI_QH_SW *Qh
)
{
UINTN Index;
UHCI_QH_SW *Prev;
UHCI_QH_SW *Next;
EFI_PHYSICAL_ADDRESS PhyAddr;
EFI_PHYSICAL_ADDRESS QhPciAddr;
UINTN Index;
UHCI_QH_SW *Prev;
UHCI_QH_SW *Next;
EFI_PHYSICAL_ADDRESS PhyAddr;
EFI_PHYSICAL_ADDRESS QhPciAddr;
ASSERT ((Uhc->FrameBase != NULL) && (Qh != NULL));
@@ -261,8 +257,8 @@ UhciLinkQhToFrameList (
// heads on the frame list
//
ASSERT (!LINK_TERMINATED (Uhc->FrameBase[Index]));
Next = (UHCI_QH_SW*)(UINTN)Uhc->FrameBaseHostAddr[Index];
Prev = NULL;
Next = (UHCI_QH_SW *)(UINTN)Uhc->FrameBaseHostAddr[Index];
Prev = NULL;
//
// Now, insert the queue head (Qh) into this frame:
@@ -279,8 +275,8 @@ UhciLinkQhToFrameList (
// rate is correct.
//
while (Next->Interval > Qh->Interval) {
Prev = Next;
Next = Next->NextQh;
Prev = Next;
Next = Next->NextQh;
ASSERT (Next != NULL);
}
@@ -305,15 +301,15 @@ UhciLinkQhToFrameList (
//
ASSERT ((Index == 0) && (Qh->NextQh == NULL));
Prev = Next;
Next = Next->NextQh;
Prev = Next;
Next = Next->NextQh;
Qh->NextQh = Next;
Prev->NextQh = Qh;
Qh->NextQh = Next;
Prev->NextQh = Qh;
Qh->QhHw.HorizonLink = Prev->QhHw.HorizonLink;
Qh->QhHw.HorizonLink = Prev->QhHw.HorizonLink;
Prev->QhHw.HorizonLink = QH_HLINK (QhPciAddr, FALSE);
Prev->QhHw.HorizonLink = QH_HLINK (QhPciAddr, FALSE);
break;
}
@@ -323,22 +319,21 @@ UhciLinkQhToFrameList (
// guarranted by 2^n polling interval.
//
if (Qh->NextQh == NULL) {
Qh->NextQh = Next;
PhyAddr = UsbHcGetPciAddressForHostMem (Uhc->MemPool, Next, sizeof (UHCI_QH_HW));
Qh->QhHw.HorizonLink = QH_HLINK (PhyAddr, FALSE);
Qh->NextQh = Next;
PhyAddr = UsbHcGetPciAddressForHostMem (Uhc->MemPool, Next, sizeof (UHCI_QH_HW));
Qh->QhHw.HorizonLink = QH_HLINK (PhyAddr, FALSE);
}
if (Prev == NULL) {
Uhc->FrameBase[Index] = QH_HLINK (QhPciAddr, FALSE);
Uhc->FrameBaseHostAddr[Index] = (UINT32)(UINTN)Qh;
Uhc->FrameBase[Index] = QH_HLINK (QhPciAddr, FALSE);
Uhc->FrameBaseHostAddr[Index] = (UINT32)(UINTN)Qh;
} else {
Prev->NextQh = Qh;
Prev->QhHw.HorizonLink = QH_HLINK (QhPciAddr, FALSE);
Prev->NextQh = Qh;
Prev->QhHw.HorizonLink = QH_HLINK (QhPciAddr, FALSE);
}
}
}
/**
Unlink QH from the frame list is easier: find all
the precedence node, and pointer there next to QhSw's
@@ -350,13 +345,13 @@ UhciLinkQhToFrameList (
**/
VOID
UhciUnlinkQhFromFrameList (
USB_HC_DEV *Uhc,
UHCI_QH_SW *Qh
USB_HC_DEV *Uhc,
UHCI_QH_SW *Qh
)
{
UINTN Index;
UHCI_QH_SW *Prev;
UHCI_QH_SW *This;
UINTN Index;
UHCI_QH_SW *Prev;
UHCI_QH_SW *This;
ASSERT ((Uhc->FrameBase != NULL) && (Qh != NULL));
@@ -366,16 +361,16 @@ UhciUnlinkQhFromFrameList (
// queue heads on the frame list
//
ASSERT (!LINK_TERMINATED (Uhc->FrameBase[Index]));
This = (UHCI_QH_SW*)(UINTN)Uhc->FrameBaseHostAddr[Index];
Prev = NULL;
This = (UHCI_QH_SW *)(UINTN)Uhc->FrameBaseHostAddr[Index];
Prev = NULL;
//
// Walk through the frame's QH list to find the
// queue head to remove
//
while ((This != NULL) && (This != Qh)) {
Prev = This;
This = This->NextQh;
Prev = This;
This = This->NextQh;
}
//
@@ -390,16 +385,15 @@ UhciUnlinkQhFromFrameList (
//
// Qh is the first entry in the frame
//
Uhc->FrameBase[Index] = Qh->QhHw.HorizonLink;
Uhc->FrameBaseHostAddr[Index] = (UINT32)(UINTN)Qh->NextQh;
Uhc->FrameBase[Index] = Qh->QhHw.HorizonLink;
Uhc->FrameBaseHostAddr[Index] = (UINT32)(UINTN)Qh->NextQh;
} else {
Prev->NextQh = Qh->NextQh;
Prev->QhHw.HorizonLink = Qh->QhHw.HorizonLink;
Prev->NextQh = Qh->NextQh;
Prev->QhHw.HorizonLink = Qh->QhHw.HorizonLink;
}
}
}
/**
Check TDs Results.
@@ -413,18 +407,18 @@ UhciUnlinkQhFromFrameList (
**/
BOOLEAN
UhciCheckTdStatus (
IN USB_HC_DEV *Uhc,
IN UHCI_TD_SW *Td,
IN BOOLEAN IsLow,
OUT UHCI_QH_RESULT *QhResult
IN USB_HC_DEV *Uhc,
IN UHCI_TD_SW *Td,
IN BOOLEAN IsLow,
OUT UHCI_QH_RESULT *QhResult
)
{
UINTN Len;
UINT8 State;
UHCI_TD_HW *TdHw;
BOOLEAN Finished;
UINTN Len;
UINT8 State;
UHCI_TD_HW *TdHw;
BOOLEAN Finished;
Finished = TRUE;
Finished = TRUE;
//
// Initialize the data toggle to that of the first
@@ -457,7 +451,6 @@ UhciCheckTdStatus (
if ((State & USBTD_STALLED) != 0) {
if ((State & USBTD_BABBLE) != 0) {
QhResult->Result |= EFI_USB_ERR_BABBLE;
} else if (TdHw->ErrorCount != 0) {
QhResult->Result |= EFI_USB_ERR_STALL;
}
@@ -480,7 +473,6 @@ UhciCheckTdStatus (
Finished = TRUE;
goto ON_EXIT;
} else if ((State & USBTD_ACTIVE) != 0) {
//
// The TD is still active, no need to check further.
@@ -489,14 +481,13 @@ UhciCheckTdStatus (
Finished = FALSE;
goto ON_EXIT;
} else {
//
// Update the next data toggle, it is always the
// next to the last known-good TD's data toggle if
// any TD is executed OK
//
QhResult->NextToggle = (UINT8) (1 - (UINT8)TdHw->DataToggle);
QhResult->NextToggle = (UINT8)(1 - (UINT8)TdHw->DataToggle);
//
// This TD is finished OK or met short packet read. Update the
@@ -530,7 +521,7 @@ ON_EXIT:
//
if (!UhciIsHcWorking (Uhc->PciIo)) {
QhResult->Result |= EFI_USB_ERR_SYSTEM;
Finished = TRUE;
Finished = TRUE;
}
if (Finished) {
@@ -541,7 +532,6 @@ ON_EXIT:
return Finished;
}
/**
Check the result of the transfer.
@@ -558,19 +548,19 @@ ON_EXIT:
**/
EFI_STATUS
UhciExecuteTransfer (
IN USB_HC_DEV *Uhc,
IN UHCI_QH_SW *Qh,
IN UHCI_TD_SW *Td,
IN UINTN TimeOut,
IN BOOLEAN IsLow,
OUT UHCI_QH_RESULT *QhResult
IN USB_HC_DEV *Uhc,
IN UHCI_QH_SW *Qh,
IN UHCI_TD_SW *Td,
IN UINTN TimeOut,
IN BOOLEAN IsLow,
OUT UHCI_QH_RESULT *QhResult
)
{
UINTN Index;
UINTN Delay;
BOOLEAN Finished;
EFI_STATUS Status;
BOOLEAN InfiniteLoop;
UINTN Index;
UINTN Delay;
BOOLEAN Finished;
EFI_STATUS Status;
BOOLEAN InfiniteLoop;
Finished = FALSE;
Status = EFI_SUCCESS;
@@ -605,7 +595,6 @@ UhciExecuteTransfer (
UhciDumpTds (Td);
Status = EFI_TIMEOUT;
} else if (QhResult->Result != EFI_USB_NOERROR) {
DEBUG ((DEBUG_ERROR, "UhciExecuteTransfer: execution failed with result %x\n", QhResult->Result));
UhciDumpQh (Qh);
@@ -617,7 +606,6 @@ UhciExecuteTransfer (
return Status;
}
/**
Update Async Request, QH and TDs.
@@ -635,12 +623,12 @@ UhciUpdateAsyncReq (
IN UINT32 NextToggle
)
{
UHCI_QH_SW *Qh;
UHCI_TD_SW *FirstTd;
UHCI_TD_SW *Td;
UHCI_QH_SW *Qh;
UHCI_TD_SW *FirstTd;
UHCI_TD_SW *Td;
Qh = AsyncReq->QhSw;
FirstTd = AsyncReq->FirstTd;
Qh = AsyncReq->QhSw;
FirstTd = AsyncReq->FirstTd;
if (Result == EFI_USB_NOERROR) {
//
@@ -659,11 +647,10 @@ UhciUpdateAsyncReq (
}
UhciLinkTdToQh (Uhc, Qh, FirstTd);
return ;
return;
}
}
/**
Create Async Request node, and Link to List.
@@ -699,7 +686,7 @@ UhciCreateAsyncReq (
IN BOOLEAN IsLow
)
{
UHCI_ASYNC_REQUEST *AsyncReq;
UHCI_ASYNC_REQUEST *AsyncReq;
AsyncReq = AllocatePool (sizeof (UHCI_ASYNC_REQUEST));
@@ -710,17 +697,17 @@ UhciCreateAsyncReq (
//
// Fill Request field. Data is allocated host memory, not mapped
//
AsyncReq->Signature = UHCI_ASYNC_INT_SIGNATURE;
AsyncReq->DevAddr = DevAddr;
AsyncReq->EndPoint = EndPoint;
AsyncReq->DataLen = DataLen;
AsyncReq->Interval = UhciConvertPollRate(Interval);
AsyncReq->Data = Data;
AsyncReq->Callback = Callback;
AsyncReq->Context = Context;
AsyncReq->QhSw = Qh;
AsyncReq->FirstTd = FirstTd;
AsyncReq->IsLow = IsLow;
AsyncReq->Signature = UHCI_ASYNC_INT_SIGNATURE;
AsyncReq->DevAddr = DevAddr;
AsyncReq->EndPoint = EndPoint;
AsyncReq->DataLen = DataLen;
AsyncReq->Interval = UhciConvertPollRate (Interval);
AsyncReq->Data = Data;
AsyncReq->Callback = Callback;
AsyncReq->Context = Context;
AsyncReq->QhSw = Qh;
AsyncReq->FirstTd = FirstTd;
AsyncReq->IsLow = IsLow;
//
// Insert the new interrupt transfer to the head of the list.
@@ -733,7 +720,6 @@ UhciCreateAsyncReq (
return EFI_SUCCESS;
}
/**
Free an asynchronous request's resource such as memory.
@@ -743,8 +729,8 @@ UhciCreateAsyncReq (
**/
VOID
UhciFreeAsyncReq (
IN USB_HC_DEV *Uhc,
IN UHCI_ASYNC_REQUEST *AsyncReq
IN USB_HC_DEV *Uhc,
IN UHCI_ASYNC_REQUEST *AsyncReq
)
{
ASSERT ((Uhc != NULL) && (AsyncReq != NULL));
@@ -759,7 +745,6 @@ UhciFreeAsyncReq (
gBS->FreePool (AsyncReq);
}
/**
Unlink an asynchronous request's from UHC's asynchronus list.
also remove the queue head from the frame list. If FreeNow,
@@ -775,9 +760,9 @@ UhciFreeAsyncReq (
**/
VOID
UhciUnlinkAsyncReq (
IN USB_HC_DEV *Uhc,
IN UHCI_ASYNC_REQUEST *AsyncReq,
IN BOOLEAN FreeNow
IN USB_HC_DEV *Uhc,
IN UHCI_ASYNC_REQUEST *AsyncReq,
IN BOOLEAN FreeNow
)
{
ASSERT ((Uhc != NULL) && (AsyncReq != NULL));
@@ -793,12 +778,11 @@ UhciUnlinkAsyncReq (
// then add AsyncReq to UHC's recycle list
//
AsyncReq->QhSw->QhHw.VerticalLink = QH_VLINK (NULL, TRUE);
AsyncReq->Recycle = Uhc->RecycleWait;
Uhc->RecycleWait = AsyncReq;
AsyncReq->Recycle = Uhc->RecycleWait;
Uhc->RecycleWait = AsyncReq;
}
}
/**
Delete Async Interrupt QH and TDs.
@@ -814,10 +798,10 @@ UhciUnlinkAsyncReq (
**/
EFI_STATUS
UhciRemoveAsyncReq (
IN USB_HC_DEV *Uhc,
IN UINT8 DevAddr,
IN UINT8 EndPoint,
OUT UINT8 *Toggle
IN USB_HC_DEV *Uhc,
IN UINT8 DevAddr,
IN UINT8 EndPoint,
OUT UINT8 *Toggle
)
{
EFI_STATUS Status;
@@ -842,14 +826,13 @@ UhciRemoveAsyncReq (
Link = Uhc->AsyncIntList.ForwardLink;
do {
AsyncReq = UHCI_ASYNC_INT_FROM_LINK (Link);
Link = Link->ForwardLink;
AsyncReq = UHCI_ASYNC_INT_FROM_LINK (Link);
Link = Link->ForwardLink;
if ((AsyncReq->DevAddr == DevAddr) && (AsyncReq->EndPoint == EndPoint)) {
Found = TRUE;
break;
}
} while (Link != &(Uhc->AsyncIntList));
if (!Found) {
@@ -870,7 +853,6 @@ UhciRemoveAsyncReq (
return Status;
}
/**
Recycle the asynchronouse request. When a queue head
is unlinked from frame list, host controller hardware
@@ -889,26 +871,24 @@ UhciRemoveAsyncReq (
**/
VOID
UhciRecycleAsyncReq (
IN USB_HC_DEV *Uhc
IN USB_HC_DEV *Uhc
)
{
UHCI_ASYNC_REQUEST *Req;
UHCI_ASYNC_REQUEST *Next;
UHCI_ASYNC_REQUEST *Req;
UHCI_ASYNC_REQUEST *Next;
Req = Uhc->Recycle;
while (Req != NULL) {
Next = Req->Recycle;
UhciFreeAsyncReq (Uhc, Req);
Req = Next;
Req = Next;
}
Uhc->Recycle = Uhc->RecycleWait;
Uhc->RecycleWait = NULL;
}
/**
Release all the asynchronous transfers on the lsit.
@@ -917,11 +897,11 @@ UhciRecycleAsyncReq (
**/
VOID
UhciFreeAllAsyncReq (
IN USB_HC_DEV *Uhc
IN USB_HC_DEV *Uhc
)
{
LIST_ENTRY *Head;
UHCI_ASYNC_REQUEST *AsyncReq;
LIST_ENTRY *Head;
UHCI_ASYNC_REQUEST *AsyncReq;
//
// Call UhciRecycleAsyncReq twice. The requests on Recycle
@@ -938,12 +918,11 @@ UhciFreeAllAsyncReq (
}
while (!IsListEmpty (Head)) {
AsyncReq = UHCI_ASYNC_INT_FROM_LINK (Head->ForwardLink);
AsyncReq = UHCI_ASYNC_INT_FROM_LINK (Head->ForwardLink);
UhciUnlinkAsyncReq (Uhc, AsyncReq, TRUE);
}
}
/**
Interrupt transfer periodic check handler.
@@ -954,18 +933,18 @@ UhciFreeAllAsyncReq (
VOID
EFIAPI
UhciMonitorAsyncReqList (
IN EFI_EVENT Event,
IN VOID *Context
IN EFI_EVENT Event,
IN VOID *Context
)
{
UHCI_ASYNC_REQUEST *AsyncReq;
LIST_ENTRY *Link;
USB_HC_DEV *Uhc;
VOID *Data;
BOOLEAN Finished;
UHCI_QH_RESULT QhResult;
UHCI_ASYNC_REQUEST *AsyncReq;
LIST_ENTRY *Link;
USB_HC_DEV *Uhc;
VOID *Data;
BOOLEAN Finished;
UHCI_QH_RESULT QhResult;
Uhc = (USB_HC_DEV *) Context;
Uhc = (USB_HC_DEV *)Context;
//
// Recycle the asynchronous requests expired, and promote
@@ -975,7 +954,7 @@ UhciMonitorAsyncReqList (
UhciRecycleAsyncReq (Uhc);
if (IsListEmpty (&(Uhc->AsyncIntList))) {
return ;
return;
}
//
@@ -984,8 +963,8 @@ UhciMonitorAsyncReqList (
Link = Uhc->AsyncIntList.ForwardLink;
do {
AsyncReq = UHCI_ASYNC_INT_FROM_LINK (Link);
Link = Link->ForwardLink;
AsyncReq = UHCI_ASYNC_INT_FROM_LINK (Link);
Link = Link->ForwardLink;
Finished = UhciCheckTdStatus (Uhc, AsyncReq->FirstTd, AsyncReq->IsLow, &QhResult);
@@ -1004,7 +983,7 @@ UhciMonitorAsyncReqList (
Data = AllocatePool (QhResult.Complete);
if (Data == NULL) {
return ;
return;
}
CopyMem (Data, AsyncReq->FirstTd->Data, QhResult.Complete);

89
MdeModulePkg/Bus/Pci/UhciDxe/UhciSched.h
View File

@@ -10,7 +10,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#ifndef _EFI_UHCI_SCHED_H_
#define _EFI_UHCI_SCHED_H_
#define UHCI_ASYNC_INT_SIGNATURE SIGNATURE_32 ('u', 'h', 'c', 'a')
//
// The failure mask for USB transfer return status. If any of
@@ -23,7 +22,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
EFI_USB_ERR_TIMEOUT | EFI_USB_ERR_BITSTUFF | \
EFI_USB_ERR_SYSTEM)
//
// Structure to return the result of UHCI QH execution.
// Result is the final result of the QH's QTD. NextToggle
@@ -31,49 +29,48 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
// length of data transferred.
//
typedef struct {
UINT32 Result;
UINT8 NextToggle;
UINTN Complete;
UINT32 Result;
UINT8 NextToggle;
UINTN Complete;
} UHCI_QH_RESULT;
typedef struct _UHCI_ASYNC_REQUEST UHCI_ASYNC_REQUEST;
typedef struct _UHCI_ASYNC_REQUEST UHCI_ASYNC_REQUEST;
//
// Structure used to manager the asynchronous interrupt transfers.
//
struct _UHCI_ASYNC_REQUEST{
UINTN Signature;
LIST_ENTRY Link;
UHCI_ASYNC_REQUEST *Recycle;
struct _UHCI_ASYNC_REQUEST {
UINTN Signature;
LIST_ENTRY Link;
UHCI_ASYNC_REQUEST *Recycle;
//
// Endpoint attributes
//
UINT8 DevAddr;
UINT8 EndPoint;
BOOLEAN IsLow;
UINTN Interval;
UINT8 DevAddr;
UINT8 EndPoint;
BOOLEAN IsLow;
UINTN Interval;
//
// Data and UHC structures
//
UHCI_QH_SW *QhSw;
UHCI_TD_SW *FirstTd;
UINT8 *Data; // Allocated host memory, not mapped memory
UINTN DataLen;
VOID *Mapping;
UHCI_QH_SW *QhSw;
UHCI_TD_SW *FirstTd;
UINT8 *Data; // Allocated host memory, not mapped memory
UINTN DataLen;
VOID *Mapping;
//
// User callback and its context
//
EFI_ASYNC_USB_TRANSFER_CALLBACK Callback;
VOID *Context;
EFI_ASYNC_USB_TRANSFER_CALLBACK Callback;
VOID *Context;
};
#define UHCI_ASYNC_INT_FROM_LINK(a) \
CR (a, UHCI_ASYNC_REQUEST, Link, UHCI_ASYNC_INT_SIGNATURE)
/**
Create Frame List Structure.
@@ -86,7 +83,7 @@ struct _UHCI_ASYNC_REQUEST{
**/
EFI_STATUS
UhciInitFrameList (
IN USB_HC_DEV *Uhc
IN USB_HC_DEV *Uhc
);
/**
@@ -99,10 +96,9 @@ UhciInitFrameList (
**/
VOID
UhciDestoryFrameList (
IN USB_HC_DEV *Uhc
IN USB_HC_DEV *Uhc
);
/**
Convert the poll rate to the maxium 2^n that is smaller
than Interval.
@@ -114,10 +110,9 @@ UhciDestoryFrameList (
**/
UINTN
UhciConvertPollRate (
IN UINTN Interval
IN UINTN Interval
);
/**
Link a queue head (for asynchronous interrupt transfer) to
the frame list.
@@ -128,11 +123,10 @@ UhciConvertPollRate (
**/
VOID
UhciLinkQhToFrameList (
USB_HC_DEV *Uhc,
UHCI_QH_SW *Qh
USB_HC_DEV *Uhc,
UHCI_QH_SW *Qh
);
/**
Unlink QH from the frame list is easier: find all
the precedence node, and pointer there next to QhSw's
@@ -144,11 +138,10 @@ UhciLinkQhToFrameList (
**/
VOID
UhciUnlinkQhFromFrameList (
USB_HC_DEV *Uhc,
UHCI_QH_SW *Qh
USB_HC_DEV *Uhc,
UHCI_QH_SW *Qh
);
/**
Check the result of the transfer.
@@ -165,15 +158,14 @@ UhciUnlinkQhFromFrameList (
**/
EFI_STATUS
UhciExecuteTransfer (
IN USB_HC_DEV *Uhc,
IN UHCI_QH_SW *Qh,
IN UHCI_TD_SW *Td,
IN UINTN TimeOut,
IN BOOLEAN IsLow,
OUT UHCI_QH_RESULT *QhResult
IN USB_HC_DEV *Uhc,
IN UHCI_QH_SW *Qh,
IN UHCI_TD_SW *Td,
IN UINTN TimeOut,
IN BOOLEAN IsLow,
OUT UHCI_QH_RESULT *QhResult
);
/**
Create Async Request node, and Link to List.
@@ -209,7 +201,6 @@ UhciCreateAsyncReq (
IN BOOLEAN IsLow
);
/**
Delete Async Interrupt QH and TDs.
@@ -225,13 +216,12 @@ UhciCreateAsyncReq (
**/
EFI_STATUS
UhciRemoveAsyncReq (
IN USB_HC_DEV *Uhc,
IN UINT8 DevAddr,
IN UINT8 EndPoint,
OUT UINT8 *Toggle
IN USB_HC_DEV *Uhc,
IN UINT8 DevAddr,
IN UINT8 EndPoint,
OUT UINT8 *Toggle
);
/**
Release all the asynchronous transfers on the lsit.
@@ -242,10 +232,9 @@ UhciRemoveAsyncReq (
**/
VOID
UhciFreeAllAsyncReq (
IN USB_HC_DEV *Uhc
IN USB_HC_DEV *Uhc
);
/**
Interrupt transfer periodic check handler.
@@ -258,8 +247,8 @@ UhciFreeAllAsyncReq (
VOID
EFIAPI
UhciMonitorAsyncReqList (
IN EFI_EVENT Event,
IN VOID *Context
IN EFI_EVENT Event,
IN VOID *Context
);
#endif

170
MdeModulePkg/Bus/Pci/UhciDxe/UsbHcMem.c
View File

@@ -9,7 +9,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include "Uhci.h"
/**
Allocate a block of memory to be used by the buffer pool.
@@ -21,17 +20,17 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
USBHC_MEM_BLOCK *
UsbHcAllocMemBlock (
IN USBHC_MEM_POOL *Pool,
IN UINTN Pages
IN USBHC_MEM_POOL *Pool,
IN UINTN Pages
)
{
USBHC_MEM_BLOCK *Block;
EFI_PCI_IO_PROTOCOL *PciIo;
VOID *BufHost;
VOID *Mapping;
EFI_PHYSICAL_ADDRESS MappedAddr;
UINTN Bytes;
EFI_STATUS Status;
USBHC_MEM_BLOCK *Block;
EFI_PCI_IO_PROTOCOL *PciIo;
VOID *BufHost;
VOID *Mapping;
EFI_PHYSICAL_ADDRESS MappedAddr;
UINTN Bytes;
EFI_STATUS Status;
PciIo = Pool->PciIo;
@@ -46,9 +45,9 @@ UsbHcAllocMemBlock (
//
ASSERT (USBHC_MEM_UNIT * 8 <= EFI_PAGE_SIZE);
Block->BufLen = EFI_PAGES_TO_SIZE (Pages);
Block->BitsLen = Block->BufLen / (USBHC_MEM_UNIT * 8);
Block->Bits = AllocateZeroPool (Block->BitsLen);
Block->BufLen = EFI_PAGES_TO_SIZE (Pages);
Block->BitsLen = Block->BufLen / (USBHC_MEM_UNIT * 8);
Block->Bits = AllocateZeroPool (Block->BitsLen);
if (Block->Bits == NULL) {
gBS->FreePool (Block);
@@ -72,7 +71,7 @@ UsbHcAllocMemBlock (
goto FREE_BITARRAY;
}
Bytes = EFI_PAGES_TO_SIZE (Pages);
Bytes = EFI_PAGES_TO_SIZE (Pages);
Status = PciIo->Map (
PciIo,
EfiPciIoOperationBusMasterCommonBuffer,
@@ -95,9 +94,9 @@ UsbHcAllocMemBlock (
goto FREE_BUFFER;
}
Block->BufHost = BufHost;
Block->Buf = (UINT8 *) ((UINTN) MappedAddr);
Block->Mapping = Mapping;
Block->BufHost = BufHost;
Block->Buf = (UINT8 *)((UINTN)MappedAddr);
Block->Mapping = Mapping;
return Block;
@@ -110,7 +109,6 @@ FREE_BITARRAY:
return NULL;
}
/**
Free the memory block from the memory pool.
@@ -120,11 +118,11 @@ FREE_BITARRAY:
**/
VOID
UsbHcFreeMemBlock (
IN USBHC_MEM_POOL *Pool,
IN USBHC_MEM_BLOCK *Block
IN USBHC_MEM_POOL *Pool,
IN USBHC_MEM_BLOCK *Block
)
{
EFI_PCI_IO_PROTOCOL *PciIo;
EFI_PCI_IO_PROTOCOL *PciIo;
ASSERT ((Pool != NULL) && (Block != NULL));
@@ -140,7 +138,6 @@ UsbHcFreeMemBlock (
gBS->FreePool (Block);
}
/**
Alloc some memory from the block.
@@ -153,22 +150,22 @@ UsbHcFreeMemBlock (
**/
VOID *
UsbHcAllocMemFromBlock (
IN USBHC_MEM_BLOCK *Block,
IN UINTN Units
IN USBHC_MEM_BLOCK *Block,
IN UINTN Units
)
{
UINTN Byte;
UINT8 Bit;
UINTN StartByte;
UINT8 StartBit;
UINTN Available;
UINTN Count;
UINTN Byte;
UINT8 Bit;
UINTN StartByte;
UINT8 StartBit;
UINTN Available;
UINTN Count;
ASSERT ((Block != 0) && (Units != 0));
StartByte = 0;
StartBit = 0;
Available = 0;
StartByte = 0;
StartBit = 0;
Available = 0;
for (Byte = 0, Bit = 0; Byte < Block->BitsLen;) {
//
@@ -184,13 +181,12 @@ UsbHcAllocMemFromBlock (
}
NEXT_BIT (Byte, Bit);
} else {
NEXT_BIT (Byte, Bit);
Available = 0;
StartByte = Byte;
StartBit = Bit;
Available = 0;
StartByte = Byte;
StartBit = Bit;
}
}
@@ -201,13 +197,13 @@ UsbHcAllocMemFromBlock (
//
// Mark the memory as allocated
//
Byte = StartByte;
Bit = StartBit;
Byte = StartByte;
Bit = StartBit;
for (Count = 0; Count < Units; Count++) {
ASSERT (!USB_HC_BIT_IS_SET (Block->Bits[Byte], Bit));
Block->Bits[Byte] = (UINT8) (Block->Bits[Byte] | (UINT8) USB_HC_BIT (Bit));
Block->Bits[Byte] = (UINT8)(Block->Bits[Byte] | (UINT8)USB_HC_BIT (Bit));
NEXT_BIT (Byte, Bit);
}
@@ -225,16 +221,16 @@ UsbHcAllocMemFromBlock (
**/
EFI_PHYSICAL_ADDRESS
UsbHcGetPciAddressForHostMem (
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
)
{
USBHC_MEM_BLOCK *Head;
USBHC_MEM_BLOCK *Block;
UINTN AllocSize;
EFI_PHYSICAL_ADDRESS PhyAddr;
UINTN Offset;
USBHC_MEM_BLOCK *Head;
USBHC_MEM_BLOCK *Block;
UINTN AllocSize;
EFI_PHYSICAL_ADDRESS PhyAddr;
UINTN Offset;
Head = Pool->Head;
AllocSize = USBHC_MEM_ROUND (Size);
@@ -248,7 +244,7 @@ UsbHcGetPciAddressForHostMem (
// scan the memory block list for the memory block that
// completely contains the allocated memory.
//
if ((Block->BufHost <= (UINT8 *) Mem) && (((UINT8 *) Mem + AllocSize) <= (Block->BufHost + Block->BufLen))) {
if ((Block->BufHost <= (UINT8 *)Mem) && (((UINT8 *)Mem + AllocSize) <= (Block->BufHost + Block->BufLen))) {
break;
}
}
@@ -257,8 +253,8 @@ UsbHcGetPciAddressForHostMem (
//
// calculate the pci memory address for host memory address.
//
Offset = (UINT8 *)Mem - Block->BufHost;
PhyAddr = (EFI_PHYSICAL_ADDRESS)(UINTN) (Block->Buf + Offset);
Offset = (UINT8 *)Mem - Block->BufHost;
PhyAddr = (EFI_PHYSICAL_ADDRESS)(UINTN)(Block->Buf + Offset);
return PhyAddr;
}
@@ -271,8 +267,8 @@ UsbHcGetPciAddressForHostMem (
**/
VOID
UsbHcInsertMemBlockToPool (
IN USBHC_MEM_BLOCK *Head,
IN USBHC_MEM_BLOCK *Block
IN USBHC_MEM_BLOCK *Head,
IN USBHC_MEM_BLOCK *Block
)
{
ASSERT ((Head != NULL) && (Block != NULL));
@@ -280,7 +276,6 @@ UsbHcInsertMemBlockToPool (
Head->Next = Block;
}
/**
Is the memory block empty?
@@ -292,10 +287,10 @@ UsbHcInsertMemBlockToPool (
**/
BOOLEAN
UsbHcIsMemBlockEmpty (
IN USBHC_MEM_BLOCK *Block
IN USBHC_MEM_BLOCK *Block
)
{
UINTN Index;
UINTN Index;
for (Index = 0; Index < Block->BitsLen; Index++) {
if (Block->Bits[Index] != 0) {
@@ -306,7 +301,6 @@ UsbHcIsMemBlockEmpty (
return TRUE;
}
/**
Unlink the memory block from the pool's list.
@@ -316,11 +310,11 @@ UsbHcIsMemBlockEmpty (
**/
VOID
UsbHcUnlinkMemBlock (
IN USBHC_MEM_BLOCK *Head,
IN USBHC_MEM_BLOCK *BlockToUnlink
IN USBHC_MEM_BLOCK *Head,
IN USBHC_MEM_BLOCK *BlockToUnlink
)
{
USBHC_MEM_BLOCK *Block;
USBHC_MEM_BLOCK *Block;
ASSERT ((Head != NULL) && (BlockToUnlink != NULL));
@@ -333,7 +327,6 @@ UsbHcUnlinkMemBlock (
}
}
/**
Initialize the memory management pool for the host controller.
@@ -353,7 +346,7 @@ UsbHcInitMemPool (
IN UINT32 Which4G
)
{
USBHC_MEM_POOL *Pool;
USBHC_MEM_POOL *Pool;
Pool = AllocatePool (sizeof (USBHC_MEM_POOL));
@@ -374,7 +367,6 @@ UsbHcInitMemPool (
return Pool;
}
/**
Release the memory management pool.
@@ -386,10 +378,10 @@ UsbHcInitMemPool (
**/
EFI_STATUS
UsbHcFreeMemPool (
IN USBHC_MEM_POOL *Pool
IN USBHC_MEM_POOL *Pool
)
{
USBHC_MEM_BLOCK *Block;
USBHC_MEM_BLOCK *Block;
ASSERT (Pool->Head != NULL);
@@ -408,7 +400,6 @@ UsbHcFreeMemPool (
return EFI_SUCCESS;
}
/**
Allocate some memory from the host controller's memory pool
which can be used to communicate with host controller.
@@ -421,16 +412,16 @@ UsbHcFreeMemPool (
**/
VOID *
UsbHcAllocateMem (
IN USBHC_MEM_POOL *Pool,
IN UINTN Size
IN USBHC_MEM_POOL *Pool,
IN UINTN Size
)
{
USBHC_MEM_BLOCK *Head;
USBHC_MEM_BLOCK *Block;
USBHC_MEM_BLOCK *NewBlock;
VOID *Mem;
UINTN AllocSize;
UINTN Pages;
USBHC_MEM_BLOCK *Head;
USBHC_MEM_BLOCK *Block;
USBHC_MEM_BLOCK *NewBlock;
VOID *Mem;
UINTN AllocSize;
UINTN Pages;
Mem = NULL;
AllocSize = USBHC_MEM_ROUND (Size);
@@ -485,7 +476,6 @@ UsbHcAllocateMem (
return Mem;
}
/**
Free the allocated memory back to the memory pool.
@@ -496,22 +486,22 @@ UsbHcAllocateMem (
**/
VOID
UsbHcFreeMem (
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
)
{
USBHC_MEM_BLOCK *Head;
USBHC_MEM_BLOCK *Block;
UINT8 *ToFree;
UINTN AllocSize;
UINTN Byte;
UINTN Bit;
UINTN Count;
USBHC_MEM_BLOCK *Head;
USBHC_MEM_BLOCK *Block;
UINT8 *ToFree;
UINTN AllocSize;
UINTN Byte;
UINTN Bit;
UINTN Count;
Head = Pool->Head;
AllocSize = USBHC_MEM_ROUND (Size);
ToFree = (UINT8 *) Mem;
ToFree = (UINT8 *)Mem;
for (Block = Head; Block != NULL; Block = Block->Next) {
//
@@ -522,8 +512,8 @@ UsbHcFreeMem (
//
// compute the start byte and bit in the bit array
//
Byte = ((ToFree - Block->Buf) / USBHC_MEM_UNIT) / 8;
Bit = ((ToFree - Block->Buf) / USBHC_MEM_UNIT) % 8;
Byte = ((ToFree - Block->Buf) / USBHC_MEM_UNIT) / 8;
Bit = ((ToFree - Block->Buf) / USBHC_MEM_UNIT) % 8;
//
// reset associated bits in bit array
@@ -531,7 +521,7 @@ UsbHcFreeMem (
for (Count = 0; Count < (AllocSize / USBHC_MEM_UNIT); Count++) {
ASSERT (USB_HC_BIT_IS_SET (Block->Bits[Byte], Bit));
Block->Bits[Byte] = (UINT8) (Block->Bits[Byte] ^ USB_HC_BIT (Bit));
Block->Bits[Byte] = (UINT8)(Block->Bits[Byte] ^ USB_HC_BIT (Bit));
NEXT_BIT (Byte, Bit);
}
@@ -554,5 +544,5 @@ UsbHcFreeMem (
UsbHcFreeMemBlock (Pool, Block);
}
return ;
return;
}

51
MdeModulePkg/Bus/Pci/UhciDxe/UsbHcMem.h
View File

@@ -10,7 +10,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#ifndef _EFI_EHCI_MEM_H_
#define _EFI_EHCI_MEM_H_
#define USB_HC_BIT(a) ((UINTN)(1 << (a)))
#define USB_HC_BIT(a) ((UINTN)(1 << (a)))
#define USB_HC_BIT_IS_SET(Data, Bit) \
((BOOLEAN)(((Data) & USB_HC_BIT(Bit)) == USB_HC_BIT(Bit)))
@@ -18,16 +18,15 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#define USB_HC_HIGH_32BIT(Addr64) \
((UINT32)(RShiftU64((UINTN)(Addr64), 32) & 0XFFFFFFFF))
typedef struct _USBHC_MEM_BLOCK USBHC_MEM_BLOCK;
struct _USBHC_MEM_BLOCK {
UINT8 *Bits; // Bit array to record which unit is allocated
UINTN BitsLen;
UINT8 *Buf;
UINT8 *BufHost;
UINTN BufLen; // Memory size in bytes
VOID *Mapping;
USBHC_MEM_BLOCK *Next;
UINT8 *Bits; // Bit array to record which unit is allocated
UINTN BitsLen;
UINT8 *Buf;
UINT8 *BufHost;
UINTN BufLen; // Memory size in bytes
VOID *Mapping;
USBHC_MEM_BLOCK *Next;
};
//
@@ -36,16 +35,16 @@ struct _USBHC_MEM_BLOCK {
// data to be on the same 4G memory.
//
typedef struct _USBHC_MEM_POOL {
EFI_PCI_IO_PROTOCOL *PciIo;
BOOLEAN Check4G;
UINT32 Which4G;
USBHC_MEM_BLOCK *Head;
EFI_PCI_IO_PROTOCOL *PciIo;
BOOLEAN Check4G;
UINT32 Which4G;
USBHC_MEM_BLOCK *Head;
} USBHC_MEM_POOL;
//
// Memory allocation unit, must be 2^n, n>4
//
#define USBHC_MEM_UNIT 64
#define USBHC_MEM_UNIT 64
#define USBHC_MEM_UNIT_MASK (USBHC_MEM_UNIT - 1)
#define USBHC_MEM_DEFAULT_PAGES 16
@@ -64,7 +63,6 @@ typedef struct _USBHC_MEM_POOL {
} \
} while (0)
/**
Initialize the memory management pool for the host controller.
@@ -84,7 +82,6 @@ UsbHcInitMemPool (
IN UINT32 Which4G
);
/**
Release the memory management pool.
@@ -96,11 +93,9 @@ UsbHcInitMemPool (
**/
EFI_STATUS
UsbHcFreeMemPool (
IN USBHC_MEM_POOL *Pool
IN USBHC_MEM_POOL *Pool
);
/**
Allocate some memory from the host controller's memory pool
which can be used to communicate with host controller.
@@ -113,12 +108,10 @@ UsbHcFreeMemPool (
**/
VOID *
UsbHcAllocateMem (
IN USBHC_MEM_POOL *Pool,
IN UINTN Size
IN USBHC_MEM_POOL *Pool,
IN UINTN Size
);
/**
Free the allocated memory back to the memory pool.
@@ -131,9 +124,9 @@ UsbHcAllocateMem (
**/
VOID
UsbHcFreeMem (
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
);
/**
@@ -147,9 +140,9 @@ UsbHcFreeMem (
**/
EFI_PHYSICAL_ADDRESS
UsbHcGetPciAddressForHostMem (
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
);
#endif