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MdeModulePkg: Apply uncrustify changes

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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737

Apply uncrustify changes to .c/.h files in the MdeModulePkg package

Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
This commit is contained in:
Michael Kubacki
2021-12-05 14:54:02 -08:00
committed by mergify[bot]
parent 7c7184e201
commit 1436aea4d5
994 changed files with 107608 additions and 101311 deletions
Download Patch File Download Diff File Expand all files Collapse all files

127
MdeModulePkg/Bus/Pci/XhciPei/DmaMem.c
View File

@@ -32,11 +32,11 @@ EDKII_IOMMU_PPI *mIoMmu;
**/
EFI_STATUS
IoMmuMap (
IN EDKII_IOMMU_OPERATION Operation,
IN VOID *HostAddress,
IN OUT UINTN *NumberOfBytes,
OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
OUT VOID **Mapping
IN EDKII_IOMMU_OPERATION Operation,
IN VOID *HostAddress,
IN OUT UINTN *NumberOfBytes,
OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
OUT VOID **Mapping
)
{
EFI_STATUS Status;
@@ -54,23 +54,25 @@ IoMmuMap (
if (EFI_ERROR (Status)) {
return EFI_OUT_OF_RESOURCES;
}
switch (Operation) {
case EdkiiIoMmuOperationBusMasterRead:
case EdkiiIoMmuOperationBusMasterRead64:
Attribute = EDKII_IOMMU_ACCESS_READ;
break;
case EdkiiIoMmuOperationBusMasterWrite:
case EdkiiIoMmuOperationBusMasterWrite64:
Attribute = EDKII_IOMMU_ACCESS_WRITE;
break;
case EdkiiIoMmuOperationBusMasterCommonBuffer:
case EdkiiIoMmuOperationBusMasterCommonBuffer64:
Attribute = EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE;
break;
default:
ASSERT(FALSE);
return EFI_INVALID_PARAMETER;
case EdkiiIoMmuOperationBusMasterRead:
case EdkiiIoMmuOperationBusMasterRead64:
Attribute = EDKII_IOMMU_ACCESS_READ;
break;
case EdkiiIoMmuOperationBusMasterWrite:
case EdkiiIoMmuOperationBusMasterWrite64:
Attribute = EDKII_IOMMU_ACCESS_WRITE;
break;
case EdkiiIoMmuOperationBusMasterCommonBuffer:
case EdkiiIoMmuOperationBusMasterCommonBuffer64:
Attribute = EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE;
break;
default:
ASSERT (FALSE);
return EFI_INVALID_PARAMETER;
}
Status = mIoMmu->SetAttribute (
mIoMmu,
*Mapping,
@@ -81,9 +83,10 @@ IoMmuMap (
}
} else {
*DeviceAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)HostAddress;
*Mapping = NULL;
Status = EFI_SUCCESS;
*Mapping = NULL;
Status = EFI_SUCCESS;
}
return Status;
}
@@ -98,7 +101,7 @@ IoMmuMap (
**/
EFI_STATUS
IoMmuUnmap (
IN VOID *Mapping
IN VOID *Mapping
)
{
EFI_STATUS Status;
@@ -109,6 +112,7 @@ IoMmuUnmap (
} else {
Status = EFI_SUCCESS;
}
return Status;
}
@@ -142,7 +146,7 @@ IoMmuAllocateBuffer (
UINTN NumberOfBytes;
EFI_PHYSICAL_ADDRESS HostPhyAddress;
*HostAddress = NULL;
*HostAddress = NULL;
*DeviceAddress = 0;
if (mIoMmu != NULL) {
@@ -157,18 +161,19 @@ IoMmuAllocateBuffer (
return EFI_OUT_OF_RESOURCES;
}
NumberOfBytes = EFI_PAGES_TO_SIZE(Pages);
Status = mIoMmu->Map (
mIoMmu,
EdkiiIoMmuOperationBusMasterCommonBuffer,
*HostAddress,
&NumberOfBytes,
DeviceAddress,
Mapping
);
NumberOfBytes = EFI_PAGES_TO_SIZE (Pages);
Status = mIoMmu->Map (
mIoMmu,
EdkiiIoMmuOperationBusMasterCommonBuffer,
*HostAddress,
&NumberOfBytes,
DeviceAddress,
Mapping
);
if (EFI_ERROR (Status)) {
return EFI_OUT_OF_RESOURCES;
}
Status = mIoMmu->SetAttribute (
mIoMmu,
*Mapping,
@@ -186,10 +191,12 @@ IoMmuAllocateBuffer (
if (EFI_ERROR (Status)) {
return EFI_OUT_OF_RESOURCES;
}
*HostAddress = (VOID *)(UINTN)HostPhyAddress;
*HostAddress = (VOID *)(UINTN)HostPhyAddress;
*DeviceAddress = HostPhyAddress;
*Mapping = NULL;
*Mapping = NULL;
}
return Status;
}
@@ -207,9 +214,9 @@ IoMmuAllocateBuffer (
**/
EFI_STATUS
IoMmuFreeBuffer (
IN UINTN Pages,
IN VOID *HostAddress,
IN VOID *Mapping
IN UINTN Pages,
IN VOID *HostAddress,
IN VOID *Mapping
)
{
EFI_STATUS Status;
@@ -221,6 +228,7 @@ IoMmuFreeBuffer (
} else {
Status = EFI_SUCCESS;
}
return Status;
}
@@ -286,9 +294,10 @@ IoMmuAllocateAlignedBuffer (
if (EFI_ERROR (Status)) {
return EFI_OUT_OF_RESOURCES;
}
Memory = *HostAddress;
AlignedMemory = ((UINTN) Memory + AlignmentMask) & ~AlignmentMask;
UnalignedPages = EFI_SIZE_TO_PAGES (AlignedMemory - (UINTN) Memory);
AlignedMemory = ((UINTN)Memory + AlignmentMask) & ~AlignmentMask;
UnalignedPages = EFI_SIZE_TO_PAGES (AlignedMemory - (UINTN)Memory);
if (UnalignedPages > 0) {
//
// Free first unaligned page(s).
@@ -296,11 +305,13 @@ IoMmuAllocateAlignedBuffer (
Status = mIoMmu->FreeBuffer (
mIoMmu,
UnalignedPages,
Memory);
Memory
);
if (EFI_ERROR (Status)) {
return Status;
}
}
Memory = (VOID *)(UINTN)(AlignedMemory + EFI_PAGES_TO_SIZE (Pages));
UnalignedPages = RealPages - Pages - UnalignedPages;
if (UnalignedPages > 0) {
@@ -310,24 +321,27 @@ IoMmuAllocateAlignedBuffer (
Status = mIoMmu->FreeBuffer (
mIoMmu,
UnalignedPages,
Memory);
Memory
);
if (EFI_ERROR (Status)) {
return Status;
}
}
*HostAddress = (VOID *) AlignedMemory;
NumberOfBytes = EFI_PAGES_TO_SIZE(Pages);
Status = mIoMmu->Map (
mIoMmu,
EdkiiIoMmuOperationBusMasterCommonBuffer,
*HostAddress,
&NumberOfBytes,
DeviceAddress,
Mapping
);
*HostAddress = (VOID *)AlignedMemory;
NumberOfBytes = EFI_PAGES_TO_SIZE (Pages);
Status = mIoMmu->Map (
mIoMmu,
EdkiiIoMmuOperationBusMasterCommonBuffer,
*HostAddress,
&NumberOfBytes,
DeviceAddress,
Mapping
);
if (EFI_ERROR (Status)) {
return EFI_OUT_OF_RESOURCES;
}
Status = mIoMmu->SetAttribute (
mIoMmu,
*Mapping,
@@ -345,10 +359,12 @@ IoMmuAllocateAlignedBuffer (
if (EFI_ERROR (Status)) {
return EFI_OUT_OF_RESOURCES;
}
*HostAddress = (VOID *)(((UINTN) HostPhyAddress + AlignmentMask) & ~AlignmentMask);
*DeviceAddress = ((UINTN) HostPhyAddress + AlignmentMask) & ~AlignmentMask;
*Mapping = NULL;
*HostAddress = (VOID *)(((UINTN)HostPhyAddress + AlignmentMask) & ~AlignmentMask);
*DeviceAddress = ((UINTN)HostPhyAddress + AlignmentMask) & ~AlignmentMask;
*Mapping = NULL;
}
return Status;
}
@@ -367,4 +383,3 @@ IoMmuInit (
(VOID **)&mIoMmu
);
}

204
MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.c
View File

@@ -20,7 +20,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
USBHC_MEM_BLOCK *
UsbHcAllocMemBlock (
IN UINTN Pages
IN UINTN Pages
)
{
USBHC_MEM_BLOCK *Block;
@@ -32,16 +32,17 @@ UsbHcAllocMemBlock (
EFI_PHYSICAL_ADDRESS TempPtr;
PageNumber = EFI_SIZE_TO_PAGES (sizeof (USBHC_MEM_BLOCK));
Status = PeiServicesAllocatePages (
EfiBootServicesData,
PageNumber,
&TempPtr
);
Status = PeiServicesAllocatePages (
EfiBootServicesData,
PageNumber,
&TempPtr
);
if (EFI_ERROR (Status)) {
return NULL;
}
ZeroMem ((VOID *) (UINTN) TempPtr, EFI_PAGES_TO_SIZE (PageNumber));
ZeroMem ((VOID *)(UINTN)TempPtr, EFI_PAGES_TO_SIZE (PageNumber));
//
// each bit in the bit array represents USBHC_MEM_UNIT
@@ -49,23 +50,24 @@ UsbHcAllocMemBlock (
//
ASSERT (USBHC_MEM_UNIT * 8 <= EFI_PAGE_SIZE);
Block = (USBHC_MEM_BLOCK *) (UINTN) TempPtr;
Block->BufLen = EFI_PAGES_TO_SIZE (Pages);
Block = (USBHC_MEM_BLOCK *)(UINTN)TempPtr;
Block->BufLen = EFI_PAGES_TO_SIZE (Pages);
Block->BitsLen = Block->BufLen / (USBHC_MEM_UNIT * 8);
PageNumber = EFI_SIZE_TO_PAGES (Block->BitsLen);
Status = PeiServicesAllocatePages (
EfiBootServicesData,
PageNumber,
&TempPtr
);
Status = PeiServicesAllocatePages (
EfiBootServicesData,
PageNumber,
&TempPtr
);
if (EFI_ERROR (Status)) {
return NULL;
}
ZeroMem ((VOID *) (UINTN) TempPtr, EFI_PAGES_TO_SIZE (PageNumber));
Block->Bits = (UINT8 *) (UINTN) TempPtr;
ZeroMem ((VOID *)(UINTN)TempPtr, EFI_PAGES_TO_SIZE (PageNumber));
Block->Bits = (UINT8 *)(UINTN)TempPtr;
Status = IoMmuAllocateBuffer (
Pages,
@@ -76,12 +78,13 @@ UsbHcAllocMemBlock (
if (EFI_ERROR (Status)) {
return NULL;
}
ZeroMem ((VOID *) (UINTN) BufHost, EFI_PAGES_TO_SIZE (Pages));
Block->BufHost = (UINT8 *) (UINTN) BufHost;
Block->Buf = (UINT8 *) (UINTN) MappedAddr;
Block->Mapping = Mapping;
Block->Next = NULL;
ZeroMem ((VOID *)(UINTN)BufHost, EFI_PAGES_TO_SIZE (Pages));
Block->BufHost = (UINT8 *)(UINTN)BufHost;
Block->Buf = (UINT8 *)(UINTN)MappedAddr;
Block->Mapping = Mapping;
Block->Next = NULL;
return Block;
}
@@ -95,8 +98,8 @@ UsbHcAllocMemBlock (
**/
VOID
UsbHcFreeMemBlock (
IN USBHC_MEM_POOL *Pool,
IN USBHC_MEM_BLOCK *Block
IN USBHC_MEM_POOL *Pool,
IN USBHC_MEM_BLOCK *Block
)
{
ASSERT ((Pool != NULL) && (Block != NULL));
@@ -120,22 +123,22 @@ UsbHcFreeMemBlock (
**/
VOID *
UsbHcAllocMemFromBlock (
IN USBHC_MEM_BLOCK *Block,
IN UINTN Units
IN USBHC_MEM_BLOCK *Block,
IN UINTN Units
)
{
UINTN Byte;
UINT8 Bit;
UINTN StartByte;
UINT8 StartBit;
UINTN Available;
UINTN Count;
UINTN Byte;
UINT8 Bit;
UINTN StartByte;
UINT8 StartBit;
UINTN Available;
UINTN Count;
ASSERT ((Block != 0) && (Units != 0));
StartByte = 0;
StartBit = 0;
Available = 0;
StartByte = 0;
StartBit = 0;
Available = 0;
for (Byte = 0, Bit = 0; Byte < Block->BitsLen;) {
//
@@ -154,9 +157,9 @@ UsbHcAllocMemFromBlock (
} else {
NEXT_BIT (Byte, Bit);
Available = 0;
StartByte = Byte;
StartBit = Bit;
Available = 0;
StartByte = Byte;
StartBit = Bit;
}
}
@@ -167,13 +170,13 @@ UsbHcAllocMemFromBlock (
//
// Mark the memory as allocated
//
Byte = StartByte;
Bit = StartBit;
Byte = StartByte;
Bit = StartBit;
for (Count = 0; Count < Units; Count++) {
ASSERT (!USB_HC_BIT_IS_SET (Block->Bits[Byte], Bit));
Block->Bits[Byte] = (UINT8) (Block->Bits[Byte] | (UINT8) USB_HC_BIT (Bit));
Block->Bits[Byte] = (UINT8)(Block->Bits[Byte] | (UINT8)USB_HC_BIT (Bit));
NEXT_BIT (Byte, Bit);
}
@@ -192,9 +195,9 @@ UsbHcAllocMemFromBlock (
**/
EFI_PHYSICAL_ADDRESS
UsbHcGetPciAddrForHostAddr (
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
)
{
USBHC_MEM_BLOCK *Head;
@@ -215,7 +218,7 @@ UsbHcGetPciAddrForHostAddr (
// scan the memory block list for the memory block that
// completely contains the allocated memory.
//
if ((Block->BufHost <= (UINT8 *) Mem) && (((UINT8 *) Mem + AllocSize) <= (Block->BufHost + Block->BufLen))) {
if ((Block->BufHost <= (UINT8 *)Mem) && (((UINT8 *)Mem + AllocSize) <= (Block->BufHost + Block->BufLen))) {
break;
}
}
@@ -224,8 +227,8 @@ UsbHcGetPciAddrForHostAddr (
//
// calculate the pci memory address for host memory address.
//
Offset = (UINT8 *) Mem - Block->BufHost;
PhyAddr = (EFI_PHYSICAL_ADDRESS) (UINTN) (Block->Buf + Offset);
Offset = (UINT8 *)Mem - Block->BufHost;
PhyAddr = (EFI_PHYSICAL_ADDRESS)(UINTN)(Block->Buf + Offset);
return PhyAddr;
}
@@ -241,9 +244,9 @@ UsbHcGetPciAddrForHostAddr (
**/
EFI_PHYSICAL_ADDRESS
UsbHcGetHostAddrForPciAddr (
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
)
{
USBHC_MEM_BLOCK *Head;
@@ -264,7 +267,7 @@ UsbHcGetHostAddrForPciAddr (
// scan the memory block list for the memory block that
// completely contains the allocated memory.
//
if ((Block->Buf <= (UINT8 *) Mem) && (((UINT8 *) Mem + AllocSize) <= (Block->Buf + Block->BufLen))) {
if ((Block->Buf <= (UINT8 *)Mem) && (((UINT8 *)Mem + AllocSize) <= (Block->Buf + Block->BufLen))) {
break;
}
}
@@ -273,8 +276,8 @@ UsbHcGetHostAddrForPciAddr (
//
// calculate the host memory address for pci memory address.
//
Offset = (UINT8 *) Mem - Block->Buf;
HostAddr = (EFI_PHYSICAL_ADDRESS) (UINTN) (Block->BufHost + Offset);
Offset = (UINT8 *)Mem - Block->Buf;
HostAddr = (EFI_PHYSICAL_ADDRESS)(UINTN)(Block->BufHost + Offset);
return HostAddr;
}
@@ -287,8 +290,8 @@ UsbHcGetHostAddrForPciAddr (
**/
VOID
UsbHcInsertMemBlockToPool (
IN USBHC_MEM_BLOCK *Head,
IN USBHC_MEM_BLOCK *Block
IN USBHC_MEM_BLOCK *Head,
IN USBHC_MEM_BLOCK *Block
)
{
ASSERT ((Head != NULL) && (Block != NULL));
@@ -307,10 +310,10 @@ UsbHcInsertMemBlockToPool (
**/
BOOLEAN
UsbHcIsMemBlockEmpty (
IN USBHC_MEM_BLOCK *Block
IN USBHC_MEM_BLOCK *Block
)
{
UINTN Index;
UINTN Index;
for (Index = 0; Index < Block->BitsLen; Index++) {
if (Block->Bits[Index] != 0) {
@@ -321,8 +324,6 @@ UsbHcIsMemBlockEmpty (
return TRUE;
}
/**
Initialize the memory management pool for the host controller.
@@ -340,17 +341,18 @@ UsbHcInitMemPool (
EFI_PHYSICAL_ADDRESS TempPtr;
PageNumber = EFI_SIZE_TO_PAGES (sizeof (USBHC_MEM_POOL));
Status = PeiServicesAllocatePages (
EfiBootServicesData,
PageNumber,
&TempPtr
);
Status = PeiServicesAllocatePages (
EfiBootServicesData,
PageNumber,
&TempPtr
);
if (EFI_ERROR (Status)) {
return NULL;
}
ZeroMem ((VOID *) (UINTN) TempPtr, EFI_PAGES_TO_SIZE (PageNumber));
Pool = (USBHC_MEM_POOL *) ((UINTN) TempPtr);
ZeroMem ((VOID *)(UINTN)TempPtr, EFI_PAGES_TO_SIZE (PageNumber));
Pool = (USBHC_MEM_POOL *)((UINTN)TempPtr);
Pool->Head = UsbHcAllocMemBlock (USBHC_MEM_DEFAULT_PAGES);
if (Pool->Head == NULL) {
@@ -371,10 +373,10 @@ UsbHcInitMemPool (
**/
VOID
UsbHcFreeMemPool (
IN USBHC_MEM_POOL *Pool
IN USBHC_MEM_POOL *Pool
)
{
USBHC_MEM_BLOCK *Block;
USBHC_MEM_BLOCK *Block;
ASSERT (Pool->Head != NULL);
@@ -384,7 +386,7 @@ UsbHcFreeMemPool (
// first block.
//
for (Block = Pool->Head->Next; Block != NULL; Block = Pool->Head->Next) {
//UsbHcUnlinkMemBlock (Pool->Head, Block);
// UsbHcUnlinkMemBlock (Pool->Head, Block);
UsbHcFreeMemBlock (Pool, Block);
}
@@ -403,16 +405,16 @@ UsbHcFreeMemPool (
**/
VOID *
UsbHcAllocateMem (
IN USBHC_MEM_POOL *Pool,
IN UINTN Size
IN USBHC_MEM_POOL *Pool,
IN UINTN Size
)
{
USBHC_MEM_BLOCK *Head;
USBHC_MEM_BLOCK *Block;
USBHC_MEM_BLOCK *NewBlock;
VOID *Mem;
UINTN AllocSize;
UINTN Pages;
USBHC_MEM_BLOCK *Head;
USBHC_MEM_BLOCK *Block;
USBHC_MEM_BLOCK *NewBlock;
VOID *Mem;
UINTN AllocSize;
UINTN Pages;
Mem = NULL;
AllocSize = USBHC_MEM_ROUND (Size);
@@ -446,6 +448,7 @@ UsbHcAllocateMem (
} else {
Pages = USBHC_MEM_DEFAULT_PAGES;
}
NewBlock = UsbHcAllocMemBlock (Pages);
if (NewBlock == NULL) {
@@ -475,22 +478,22 @@ UsbHcAllocateMem (
**/
VOID
UsbHcFreeMem (
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
)
{
USBHC_MEM_BLOCK *Head;
USBHC_MEM_BLOCK *Block;
UINT8 *ToFree;
UINTN AllocSize;
UINTN Byte;
UINTN Bit;
UINTN Count;
USBHC_MEM_BLOCK *Head;
USBHC_MEM_BLOCK *Block;
UINT8 *ToFree;
UINTN AllocSize;
UINTN Byte;
UINTN Bit;
UINTN Count;
Head = Pool->Head;
AllocSize = USBHC_MEM_ROUND (Size);
ToFree = (UINT8 *) Mem;
ToFree = (UINT8 *)Mem;
for (Block = Head; Block != NULL; Block = Block->Next) {
//
@@ -501,8 +504,8 @@ UsbHcFreeMem (
//
// compute the start byte and bit in the bit array
//
Byte = ((ToFree - Block->BufHost) / USBHC_MEM_UNIT) / 8;
Bit = ((ToFree - Block->BufHost) / USBHC_MEM_UNIT) % 8;
Byte = ((ToFree - Block->BufHost) / USBHC_MEM_UNIT) / 8;
Bit = ((ToFree - Block->BufHost) / USBHC_MEM_UNIT) % 8;
//
// reset associated bits in bit array
@@ -510,7 +513,7 @@ UsbHcFreeMem (
for (Count = 0; Count < (AllocSize / USBHC_MEM_UNIT); Count++) {
ASSERT (USB_HC_BIT_IS_SET (Block->Bits[Byte], Bit));
Block->Bits[Byte] = (UINT8) (Block->Bits[Byte] ^ USB_HC_BIT (Bit));
Block->Bits[Byte] = (UINT8)(Block->Bits[Byte] ^ USB_HC_BIT (Bit));
NEXT_BIT (Byte, Bit);
}
@@ -529,7 +532,7 @@ UsbHcFreeMem (
// Release the current memory block if it is empty and not the head
//
if ((Block != Head) && UsbHcIsMemBlockEmpty (Block)) {
//UsbHcUnlinkMemBlock (Head, Block);
// UsbHcUnlinkMemBlock (Head, Block);
UsbHcFreeMemBlock (Pool, Block);
}
}
@@ -553,11 +556,11 @@ UsbHcFreeMem (
**/
EFI_STATUS
UsbHcAllocateAlignedPages (
IN UINTN Pages,
IN UINTN Alignment,
OUT VOID **HostAddress,
OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
OUT VOID **Mapping
IN UINTN Pages,
IN UINTN Alignment,
OUT VOID **HostAddress,
OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
OUT VOID **Mapping
)
{
EFI_STATUS Status;
@@ -603,7 +606,7 @@ UsbHcAllocateAlignedPages (
}
}
*HostAddress = Memory;
*HostAddress = Memory;
*DeviceAddress = DeviceMemory;
return EFI_SUCCESS;
@@ -619,13 +622,12 @@ UsbHcAllocateAlignedPages (
**/
VOID
UsbHcFreeAlignedPages (
IN VOID *HostAddress,
IN UINTN Pages,
IN VOID *Mapping
IN VOID *HostAddress,
IN UINTN Pages,
IN VOID *Mapping
)
{
ASSERT (Pages != 0);
IoMmuFreeBuffer (Pages, HostAddress, Mapping);
}

58
MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.h
View File

@@ -12,29 +12,29 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Uefi.h>
#define USBHC_MEM_DEFAULT_PAGES 16
#define USBHC_MEM_DEFAULT_PAGES 16
typedef struct _USBHC_MEM_BLOCK USBHC_MEM_BLOCK;
struct _USBHC_MEM_BLOCK {
UINT8 *Bits; // Bit array to record which unit is allocated
UINTN BitsLen;
UINT8 *Buf;
UINT8 *BufHost;
UINTN BufLen; // Memory size in bytes
VOID *Mapping;
USBHC_MEM_BLOCK *Next;
UINT8 *Bits; // Bit array to record which unit is allocated
UINTN BitsLen;
UINT8 *Buf;
UINT8 *BufHost;
UINTN BufLen; // Memory size in bytes
VOID *Mapping;
USBHC_MEM_BLOCK *Next;
};
//
// Memory allocation unit, must be 2^n, n>4
//
#define USBHC_MEM_UNIT 64
#define USBHC_MEM_UNIT 64
#define USBHC_MEM_UNIT_MASK (USBHC_MEM_UNIT - 1)
#define USBHC_MEM_ROUND(Len) (((Len) + USBHC_MEM_UNIT_MASK) & (~USBHC_MEM_UNIT_MASK))
#define USBHC_MEM_UNIT_MASK (USBHC_MEM_UNIT - 1)
#define USBHC_MEM_ROUND(Len) (((Len) + USBHC_MEM_UNIT_MASK) & (~USBHC_MEM_UNIT_MASK))
#define USB_HC_BIT(a) ((UINTN)(1 << (a)))
#define USB_HC_BIT(a) ((UINTN)(1 << (a)))
#define USB_HC_BIT_IS_SET(Data, Bit) \
((BOOLEAN)(((Data) & USB_HC_BIT(Bit)) == USB_HC_BIT(Bit)))
@@ -57,9 +57,9 @@ struct _USBHC_MEM_BLOCK {
// data to be on the same 4G memory.
//
typedef struct _USBHC_MEM_POOL {
BOOLEAN Check4G;
UINT32 Which4G;
USBHC_MEM_BLOCK *Head;
BOOLEAN Check4G;
UINT32 Which4G;
USBHC_MEM_BLOCK *Head;
} USBHC_MEM_POOL;
/**
@@ -74,9 +74,9 @@ typedef struct _USBHC_MEM_POOL {
**/
EFI_PHYSICAL_ADDRESS
UsbHcGetPciAddrForHostAddr (
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
);
/**
@@ -91,9 +91,9 @@ UsbHcGetPciAddrForHostAddr (
**/
EFI_PHYSICAL_ADDRESS
UsbHcGetHostAddrForPciAddr (
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
);
/**
@@ -115,11 +115,11 @@ UsbHcGetHostAddrForPciAddr (
**/
EFI_STATUS
UsbHcAllocateAlignedPages (
IN UINTN Pages,
IN UINTN Alignment,
OUT VOID **HostAddress,
OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
OUT VOID **Mapping
IN UINTN Pages,
IN UINTN Alignment,
OUT VOID **HostAddress,
OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
OUT VOID **Mapping
);
/**
@@ -132,9 +132,9 @@ UsbHcAllocateAlignedPages (
**/
VOID
UsbHcFreeAlignedPages (
IN VOID *HostAddress,
IN UINTN Pages,
IN VOID *Mapping
IN VOID *HostAddress,
IN UINTN Pages,
IN VOID *Mapping
);
#endif

556
MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c
View File

File diff suppressed because it is too large Load Diff

135
MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.h
View File

@@ -25,33 +25,33 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/IoLib.h>
#include <Library/MemoryAllocationLib.h>
typedef struct _PEI_XHC_DEV PEI_XHC_DEV;
typedef struct _USB_DEV_CONTEXT USB_DEV_CONTEXT;
typedef struct _PEI_XHC_DEV PEI_XHC_DEV;
typedef struct _USB_DEV_CONTEXT USB_DEV_CONTEXT;
#include "UsbHcMem.h"
#include "XhciReg.h"
#include "XhciSched.h"
#define CMD_RING_TRB_NUMBER 0x100
#define TR_RING_TRB_NUMBER 0x100
#define ERST_NUMBER 0x01
#define EVENT_RING_TRB_NUMBER 0x200
#define CMD_RING_TRB_NUMBER 0x100
#define TR_RING_TRB_NUMBER 0x100
#define ERST_NUMBER 0x01
#define EVENT_RING_TRB_NUMBER 0x200
#define XHC_1_MICROSECOND 1
#define XHC_1_MILLISECOND (1000 * XHC_1_MICROSECOND)
#define XHC_1_SECOND (1000 * XHC_1_MILLISECOND)
#define XHC_1_MICROSECOND 1
#define XHC_1_MILLISECOND (1000 * XHC_1_MICROSECOND)
#define XHC_1_SECOND (1000 * XHC_1_MILLISECOND)
//
// XHC reset timeout experience values.
// The unit is millisecond, setting it as 1s.
//
#define XHC_RESET_TIMEOUT (1000)
#define XHC_RESET_TIMEOUT (1000)
//
// TRSTRCY delay requirement in usb 2.0 spec chapter 7.1.7.5.
// The unit is microsecond, setting it as 10ms.
//
#define XHC_RESET_RECOVERY_DELAY (10 * 1000)
#define XHC_RESET_RECOVERY_DELAY (10 * 1000)
//
// Wait for root port state stable.
@@ -62,11 +62,11 @@ typedef struct _USB_DEV_CONTEXT USB_DEV_CONTEXT;
// XHC generic timeout experience values.
// The unit is millisecond, setting it as 10s.
//
#define XHC_GENERIC_TIMEOUT (10 * 1000)
#define XHC_GENERIC_TIMEOUT (10 * 1000)
#define XHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0XFFFFFFFF))
#define XHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINTN)(Addr64), 32) & 0XFFFFFFFF))
#define XHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))
#define XHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0XFFFFFFFF))
#define XHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINTN)(Addr64), 32) & 0XFFFFFFFF))
#define XHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))
#define XHC_REG_BIT_IS_SET(XHC, Offset, Bit) \
(XHC_BIT_IS_SET(XhcPeiReadOpReg ((XHC), (Offset)), (Bit)))
@@ -86,23 +86,23 @@ struct _USB_DEV_CONTEXT {
//
// Whether this entry in UsbDevContext array is used or not.
//
BOOLEAN Enabled;
BOOLEAN Enabled;
//
// The slot id assigned to the new device through XHCI's Enable_Slot cmd.
//
UINT8 SlotId;
UINT8 SlotId;
//
// The route string presented an attached usb device.
//
USB_DEV_ROUTE RouteString;
USB_DEV_ROUTE RouteString;
//
// The route string of parent device if it exists. Otherwise it's zero.
//
USB_DEV_ROUTE ParentRouteString;
USB_DEV_ROUTE ParentRouteString;
//
// The actual device address assigned by XHCI through Address_Device command.
//
UINT8 XhciDevAddr;
UINT8 XhciDevAddr;
//
// The requested device address from UsbBus driver through Set_Address standard usb request.
// As XHCI spec replaces this request with Address_Device command, we have to record the
@@ -111,23 +111,23 @@ struct _USB_DEV_CONTEXT {
// through EFI_USB2_HC_PROTOCOL. Xhci driver would be responsible for translating it to actual
// device address and access the actual device.
//
UINT8 BusDevAddr;
UINT8 BusDevAddr;
//
// The pointer to the input device context.
//
VOID *InputContext;
VOID *InputContext;
//
// The pointer to the output device context.
//
VOID *OutputContext;
VOID *OutputContext;
//
// The transfer queue for every endpoint.
//
VOID *EndpointTransferRing[31];
VOID *EndpointTransferRing[31];
//
// The device descriptor which is stored to support XHCI's Evaluate_Context cmd.
//
EFI_USB_DEVICE_DESCRIPTOR DevDesc;
EFI_USB_DEVICE_DESCRIPTOR DevDesc;
//
// As a usb device may include multiple configuration descriptors, we dynamically allocate an array
// to store them.
@@ -135,59 +135,59 @@ struct _USB_DEV_CONTEXT {
// such as Interface descriptor, Endpoint descriptor, and so on.
// These information is used to support XHCI's Config_Endpoint cmd.
//
EFI_USB_CONFIG_DESCRIPTOR **ConfDesc;
EFI_USB_CONFIG_DESCRIPTOR **ConfDesc;
};
#define USB_XHC_DEV_SIGNATURE SIGNATURE_32 ('x', 'h', 'c', 'i')
#define USB_XHC_DEV_SIGNATURE SIGNATURE_32 ('x', 'h', 'c', 'i')
struct _PEI_XHC_DEV {
UINTN Signature;
PEI_USB2_HOST_CONTROLLER_PPI Usb2HostControllerPpi;
EFI_PEI_PPI_DESCRIPTOR PpiDescriptor;
UINT32 UsbHostControllerBaseAddress;
USBHC_MEM_POOL *MemPool;
UINTN Signature;
PEI_USB2_HOST_CONTROLLER_PPI Usb2HostControllerPpi;
EFI_PEI_PPI_DESCRIPTOR PpiDescriptor;
UINT32 UsbHostControllerBaseAddress;
USBHC_MEM_POOL *MemPool;
//
// EndOfPei callback is used to stop the XHC DMA operation
// after exit PEI phase.
//
EFI_PEI_NOTIFY_DESCRIPTOR EndOfPeiNotifyList;
EFI_PEI_NOTIFY_DESCRIPTOR EndOfPeiNotifyList;
//
// XHCI configuration data
//
UINT8 CapLength; ///< Capability Register Length
XHC_HCSPARAMS1 HcSParams1; ///< Structural Parameters 1
XHC_HCSPARAMS2 HcSParams2; ///< Structural Parameters 2
XHC_HCCPARAMS HcCParams; ///< Capability Parameters
UINT32 DBOff; ///< Doorbell Offset
UINT32 RTSOff; ///< Runtime Register Space Offset
UINT32 PageSize;
UINT32 MaxScratchpadBufs;
UINT64 *ScratchBuf;
VOID *ScratchMap;
UINT64 *ScratchEntry;
UINTN *ScratchEntryMap;
UINT64 *DCBAA;
UINT32 MaxSlotsEn;
UINT8 CapLength; ///< Capability Register Length
XHC_HCSPARAMS1 HcSParams1; ///< Structural Parameters 1
XHC_HCSPARAMS2 HcSParams2; ///< Structural Parameters 2
XHC_HCCPARAMS HcCParams; ///< Capability Parameters
UINT32 DBOff; ///< Doorbell Offset
UINT32 RTSOff; ///< Runtime Register Space Offset
UINT32 PageSize;
UINT32 MaxScratchpadBufs;
UINT64 *ScratchBuf;
VOID *ScratchMap;
UINT64 *ScratchEntry;
UINTN *ScratchEntryMap;
UINT64 *DCBAA;
UINT32 MaxSlotsEn;
//
// Cmd Transfer Ring
//
TRANSFER_RING CmdRing;
TRANSFER_RING CmdRing;
//
// EventRing
//
EVENT_RING EventRing;
EVENT_RING EventRing;
//
// Store device contexts managed by XHCI device
// The array supports up to 255 devices, entry 0 is reserved and should not be used.
//
USB_DEV_CONTEXT UsbDevContext[256];
USB_DEV_CONTEXT UsbDevContext[256];
};
#define PEI_RECOVERY_USB_XHC_DEV_FROM_THIS(a) CR (a, PEI_XHC_DEV, Usb2HostControllerPpi, USB_XHC_DEV_SIGNATURE)
#define PEI_RECOVERY_USB_XHC_DEV_FROM_THIS_NOTIFY(a) CR (a, PEI_XHC_DEV, EndOfPeiNotifyList, USB_XHC_DEV_SIGNATURE)
#define PEI_RECOVERY_USB_XHC_DEV_FROM_THIS(a) CR (a, PEI_XHC_DEV, Usb2HostControllerPpi, USB_XHC_DEV_SIGNATURE)
#define PEI_RECOVERY_USB_XHC_DEV_FROM_THIS_NOTIFY(a) CR (a, PEI_XHC_DEV, EndOfPeiNotifyList, USB_XHC_DEV_SIGNATURE)
/**
Initialize the memory management pool for the host controller.
@@ -209,7 +209,7 @@ UsbHcInitMemPool (
**/
VOID
UsbHcFreeMemPool (
IN USBHC_MEM_POOL *Pool
IN USBHC_MEM_POOL *Pool
)
;
@@ -225,8 +225,8 @@ UsbHcFreeMemPool (
**/
VOID *
UsbHcAllocateMem (
IN USBHC_MEM_POOL *Pool,
IN UINTN Size
IN USBHC_MEM_POOL *Pool,
IN UINTN Size
)
;
@@ -240,13 +240,12 @@ UsbHcAllocateMem (
**/
VOID
UsbHcFreeMem (
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
)
;
/**
Initialize IOMMU.
**/
@@ -276,11 +275,11 @@ IoMmuInit (
**/
EFI_STATUS
IoMmuMap (
IN EDKII_IOMMU_OPERATION Operation,
IN VOID *HostAddress,
IN OUT UINTN *NumberOfBytes,
OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
OUT VOID **Mapping
IN EDKII_IOMMU_OPERATION Operation,
IN VOID *HostAddress,
IN OUT UINTN *NumberOfBytes,
OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
OUT VOID **Mapping
);
/**
@@ -294,7 +293,7 @@ IoMmuMap (
**/
EFI_STATUS
IoMmuUnmap (
IN VOID *Mapping
IN VOID *Mapping
);
/**
@@ -337,9 +336,9 @@ IoMmuAllocateBuffer (
**/
EFI_STATUS
IoMmuFreeBuffer (
IN UINTN Pages,
IN VOID *HostAddress,
IN VOID *Mapping
IN UINTN Pages,
IN VOID *HostAddress,
IN VOID *Mapping
);
/**

308
MdeModulePkg/Bus/Pci/XhciPei/XhciReg.h
View File

@@ -13,153 +13,152 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
//
// Capability registers offset
//
#define XHC_CAPLENGTH_OFFSET 0x00 // Capability register length offset
#define XHC_HCIVERSION_OFFSET 0x02 // Interface Version Number 02-03h
#define XHC_HCSPARAMS1_OFFSET 0x04 // Structural Parameters 1
#define XHC_HCSPARAMS2_OFFSET 0x08 // Structural Parameters 2
#define XHC_HCSPARAMS3_OFFSET 0x0c // Structural Parameters 3
#define XHC_HCCPARAMS_OFFSET 0x10 // Capability Parameters
#define XHC_DBOFF_OFFSET 0x14 // Doorbell Offset
#define XHC_RTSOFF_OFFSET 0x18 // Runtime Register Space Offset
#define XHC_CAPLENGTH_OFFSET 0x00 // Capability register length offset
#define XHC_HCIVERSION_OFFSET 0x02 // Interface Version Number 02-03h
#define XHC_HCSPARAMS1_OFFSET 0x04 // Structural Parameters 1
#define XHC_HCSPARAMS2_OFFSET 0x08 // Structural Parameters 2
#define XHC_HCSPARAMS3_OFFSET 0x0c // Structural Parameters 3
#define XHC_HCCPARAMS_OFFSET 0x10 // Capability Parameters
#define XHC_DBOFF_OFFSET 0x14 // Doorbell Offset
#define XHC_RTSOFF_OFFSET 0x18 // Runtime Register Space Offset
//
// Operational registers offset
//
#define XHC_USBCMD_OFFSET 0x0000 // USB Command Register Offset
#define XHC_USBSTS_OFFSET 0x0004 // USB Status Register Offset
#define XHC_PAGESIZE_OFFSET 0x0008 // USB Page Size Register Offset
#define XHC_DNCTRL_OFFSET 0x0014 // Device Notification Control Register Offset
#define XHC_CRCR_OFFSET 0x0018 // Command Ring Control Register Offset
#define XHC_DCBAAP_OFFSET 0x0030 // Device Context Base Address Array Pointer Register Offset
#define XHC_CONFIG_OFFSET 0x0038 // Configure Register Offset
#define XHC_PORTSC_OFFSET 0x0400 // Port Status and Control Register Offset
#define XHC_USBCMD_OFFSET 0x0000 // USB Command Register Offset
#define XHC_USBSTS_OFFSET 0x0004 // USB Status Register Offset
#define XHC_PAGESIZE_OFFSET 0x0008 // USB Page Size Register Offset
#define XHC_DNCTRL_OFFSET 0x0014 // Device Notification Control Register Offset
#define XHC_CRCR_OFFSET 0x0018 // Command Ring Control Register Offset
#define XHC_DCBAAP_OFFSET 0x0030 // Device Context Base Address Array Pointer Register Offset
#define XHC_CONFIG_OFFSET 0x0038 // Configure Register Offset
#define XHC_PORTSC_OFFSET 0x0400 // Port Status and Control Register Offset
//
// Runtime registers offset
//
#define XHC_MFINDEX_OFFSET 0x00 // Microframe Index Register Offset
#define XHC_IMAN_OFFSET 0x20 // Interrupter X Management Register Offset
#define XHC_IMOD_OFFSET 0x24 // Interrupter X Moderation Register Offset
#define XHC_ERSTSZ_OFFSET 0x28 // Event Ring Segment Table Size Register Offset
#define XHC_ERSTBA_OFFSET 0x30 // Event Ring Segment Table Base Address Register Offset
#define XHC_ERDP_OFFSET 0x38 // Event Ring Dequeue Pointer Register Offset
#define XHC_MFINDEX_OFFSET 0x00 // Microframe Index Register Offset
#define XHC_IMAN_OFFSET 0x20 // Interrupter X Management Register Offset
#define XHC_IMOD_OFFSET 0x24 // Interrupter X Moderation Register Offset
#define XHC_ERSTSZ_OFFSET 0x28 // Event Ring Segment Table Size Register Offset
#define XHC_ERSTBA_OFFSET 0x30 // Event Ring Segment Table Base Address Register Offset
#define XHC_ERDP_OFFSET 0x38 // Event Ring Dequeue Pointer Register Offset
//
// Register Bit Definition
//
#define XHC_USBCMD_RUN BIT0 // Run/Stop
#define XHC_USBCMD_RESET BIT1 // Host Controller Reset
#define XHC_USBCMD_INTE BIT2 // Interrupter Enable
#define XHC_USBCMD_HSEE BIT3 // Host System Error Enable
#define XHC_USBCMD_RUN BIT0 // Run/Stop
#define XHC_USBCMD_RESET BIT1 // Host Controller Reset
#define XHC_USBCMD_INTE BIT2 // Interrupter Enable
#define XHC_USBCMD_HSEE BIT3 // Host System Error Enable
#define XHC_USBSTS_HALT BIT0 // Host Controller Halted
#define XHC_USBSTS_HSE BIT2 // Host System Error
#define XHC_USBSTS_EINT BIT3 // Event Interrupt
#define XHC_USBSTS_PCD BIT4 // Port Change Detect
#define XHC_USBSTS_SSS BIT8 // Save State Status
#define XHC_USBSTS_RSS BIT9 // Restore State Status
#define XHC_USBSTS_SRE BIT10 // Save/Restore Error
#define XHC_USBSTS_CNR BIT11 // Host Controller Not Ready
#define XHC_USBSTS_HCE BIT12 // Host Controller Error
#define XHC_USBSTS_HALT BIT0 // Host Controller Halted
#define XHC_USBSTS_HSE BIT2 // Host System Error
#define XHC_USBSTS_EINT BIT3 // Event Interrupt
#define XHC_USBSTS_PCD BIT4 // Port Change Detect
#define XHC_USBSTS_SSS BIT8 // Save State Status
#define XHC_USBSTS_RSS BIT9 // Restore State Status
#define XHC_USBSTS_SRE BIT10 // Save/Restore Error
#define XHC_USBSTS_CNR BIT11 // Host Controller Not Ready
#define XHC_USBSTS_HCE BIT12 // Host Controller Error
#define XHC_PAGESIZE_MASK 0xFFFF // Page Size
#define XHC_PAGESIZE_MASK 0xFFFF // Page Size
#define XHC_CRCR_RCS BIT0 // Ring Cycle State
#define XHC_CRCR_CS BIT1 // Command Stop
#define XHC_CRCR_CA BIT2 // Command Abort
#define XHC_CRCR_CRR BIT3 // Command Ring Running
#define XHC_CRCR_RCS BIT0 // Ring Cycle State
#define XHC_CRCR_CS BIT1 // Command Stop
#define XHC_CRCR_CA BIT2 // Command Abort
#define XHC_CRCR_CRR BIT3 // Command Ring Running
#define XHC_CONFIG_MASK 0xFF // Max Device Slots Enabled
#define XHC_CONFIG_MASK 0xFF // Max Device Slots Enabled
#define XHC_PORTSC_CCS BIT0 // Current Connect Status
#define XHC_PORTSC_PED BIT1 // Port Enabled/Disabled
#define XHC_PORTSC_OCA BIT3 // Over-current Active
#define XHC_PORTSC_RESET BIT4 // Port Reset
#define XHC_PORTSC_PLS (BIT5|BIT6|BIT7|BIT8) // Port Link State
#define XHC_PORTSC_PP BIT9 // Port Power
#define XHC_PORTSC_PS (BIT10|BIT11|BIT12|BIT13) // Port Speed
#define XHC_PORTSC_LWS BIT16 // Port Link State Write Strobe
#define XHC_PORTSC_CSC BIT17 // Connect Status Change
#define XHC_PORTSC_PEC BIT18 // Port Enabled/Disabled Change
#define XHC_PORTSC_WRC BIT19 // Warm Port Reset Change
#define XHC_PORTSC_OCC BIT20 // Over-Current Change
#define XHC_PORTSC_PRC BIT21 // Port Reset Change
#define XHC_PORTSC_PLC BIT22 // Port Link State Change
#define XHC_PORTSC_CEC BIT23 // Port Config Error Change
#define XHC_PORTSC_CAS BIT24 // Cold Attach Status
#define XHC_PORTSC_CCS BIT0 // Current Connect Status
#define XHC_PORTSC_PED BIT1 // Port Enabled/Disabled
#define XHC_PORTSC_OCA BIT3 // Over-current Active
#define XHC_PORTSC_RESET BIT4 // Port Reset
#define XHC_PORTSC_PLS (BIT5|BIT6|BIT7|BIT8) // Port Link State
#define XHC_PORTSC_PP BIT9 // Port Power
#define XHC_PORTSC_PS (BIT10|BIT11|BIT12|BIT13) // Port Speed
#define XHC_PORTSC_LWS BIT16 // Port Link State Write Strobe
#define XHC_PORTSC_CSC BIT17 // Connect Status Change
#define XHC_PORTSC_PEC BIT18 // Port Enabled/Disabled Change
#define XHC_PORTSC_WRC BIT19 // Warm Port Reset Change
#define XHC_PORTSC_OCC BIT20 // Over-Current Change
#define XHC_PORTSC_PRC BIT21 // Port Reset Change
#define XHC_PORTSC_PLC BIT22 // Port Link State Change
#define XHC_PORTSC_CEC BIT23 // Port Config Error Change
#define XHC_PORTSC_CAS BIT24 // Cold Attach Status
#define XHC_HUB_PORTSC_CCS BIT0 // Hub's Current Connect Status
#define XHC_HUB_PORTSC_PED BIT1 // Hub's Port Enabled/Disabled
#define XHC_HUB_PORTSC_OCA BIT3 // Hub's Over-current Active
#define XHC_HUB_PORTSC_RESET BIT4 // Hub's Port Reset
#define XHC_HUB_PORTSC_PP BIT9 // Hub's Port Power
#define XHC_HUB_PORTSC_CSC BIT16 // Hub's Connect Status Change
#define XHC_HUB_PORTSC_PEC BIT17 // Hub's Port Enabled/Disabled Change
#define XHC_HUB_PORTSC_OCC BIT19 // Hub's Over-Current Change
#define XHC_HUB_PORTSC_PRC BIT20 // Hub's Port Reset Change
#define XHC_HUB_PORTSC_BHRC BIT21 // Hub's Port Warm Reset Change
#define XHC_HUB_PORTSC_CCS BIT0 // Hub's Current Connect Status
#define XHC_HUB_PORTSC_PED BIT1 // Hub's Port Enabled/Disabled
#define XHC_HUB_PORTSC_OCA BIT3 // Hub's Over-current Active
#define XHC_HUB_PORTSC_RESET BIT4 // Hub's Port Reset
#define XHC_HUB_PORTSC_PP BIT9 // Hub's Port Power
#define XHC_HUB_PORTSC_CSC BIT16 // Hub's Connect Status Change
#define XHC_HUB_PORTSC_PEC BIT17 // Hub's Port Enabled/Disabled Change
#define XHC_HUB_PORTSC_OCC BIT19 // Hub's Over-Current Change
#define XHC_HUB_PORTSC_PRC BIT20 // Hub's Port Reset Change
#define XHC_HUB_PORTSC_BHRC BIT21 // Hub's Port Warm Reset Change
#define XHC_IMAN_IP BIT0 // Interrupt Pending
#define XHC_IMAN_IE BIT1 // Interrupt Enable
#define XHC_IMODI_MASK 0x0000FFFF // Interrupt Moderation Interval
#define XHC_IMODC_MASK 0xFFFF0000 // Interrupt Moderation Counter
#define XHC_IMAN_IP BIT0 // Interrupt Pending
#define XHC_IMAN_IE BIT1 // Interrupt Enable
#define XHC_IMODI_MASK 0x0000FFFF // Interrupt Moderation Interval
#define XHC_IMODC_MASK 0xFFFF0000 // Interrupt Moderation Counter
#pragma pack (1)
typedef struct {
UINT8 MaxSlots; // Number of Device Slots
UINT16 MaxIntrs:11; // Number of Interrupters
UINT16 Rsvd:5;
UINT8 MaxPorts; // Number of Ports
UINT8 MaxSlots; // Number of Device Slots
UINT16 MaxIntrs : 11; // Number of Interrupters
UINT16 Rsvd : 5;
UINT8 MaxPorts; // Number of Ports
} HCSPARAMS1;
//
// Structural Parameters 1 Register Bitmap Definition
//
typedef union {
UINT32 Dword;
HCSPARAMS1 Data;
UINT32 Dword;
HCSPARAMS1 Data;
} XHC_HCSPARAMS1;
typedef struct {
UINT32 Ist:4; // Isochronous Scheduling Threshold
UINT32 Erst:4; // Event Ring Segment Table Max
UINT32 Rsvd:13;
UINT32 ScratchBufHi:5; // Max Scratchpad Buffers Hi
UINT32 Spr:1; // Scratchpad Restore
UINT32 ScratchBufLo:5; // Max Scratchpad Buffers Lo
UINT32 Ist : 4; // Isochronous Scheduling Threshold
UINT32 Erst : 4; // Event Ring Segment Table Max
UINT32 Rsvd : 13;
UINT32 ScratchBufHi : 5; // Max Scratchpad Buffers Hi
UINT32 Spr : 1; // Scratchpad Restore
UINT32 ScratchBufLo : 5; // Max Scratchpad Buffers Lo
} HCSPARAMS2;
//
// Structural Parameters 2 Register Bitmap Definition
//
typedef union {
UINT32 Dword;
HCSPARAMS2 Data;
UINT32 Dword;
HCSPARAMS2 Data;
} XHC_HCSPARAMS2;
typedef struct {
UINT16 Ac64:1; // 64-bit Addressing Capability
UINT16 Bnc:1; // BW Negotiation Capability
UINT16 Csz:1; // Context Size
UINT16 Ppc:1; // Port Power Control
UINT16 Pind:1; // Port Indicators
UINT16 Lhrc:1; // Light HC Reset Capability
UINT16 Ltc:1; // Latency Tolerance Messaging Capability
UINT16 Nss:1; // No Secondary SID Support
UINT16 Pae:1; // Parse All Event Data
UINT16 Rsvd:3;
UINT16 MaxPsaSize:4; // Maximum Primary Stream Array Size
UINT16 ExtCapReg; // xHCI Extended Capabilities Pointer
UINT16 Ac64 : 1; // 64-bit Addressing Capability
UINT16 Bnc : 1; // BW Negotiation Capability
UINT16 Csz : 1; // Context Size
UINT16 Ppc : 1; // Port Power Control
UINT16 Pind : 1; // Port Indicators
UINT16 Lhrc : 1; // Light HC Reset Capability
UINT16 Ltc : 1; // Latency Tolerance Messaging Capability
UINT16 Nss : 1; // No Secondary SID Support
UINT16 Pae : 1; // Parse All Event Data
UINT16 Rsvd : 3;
UINT16 MaxPsaSize : 4; // Maximum Primary Stream Array Size
UINT16 ExtCapReg; // xHCI Extended Capabilities Pointer
} HCCPARAMS;
//
// Capability Parameters Register Bitmap Definition
//
typedef union {
UINT32 Dword;
HCCPARAMS Data;
UINT32 Dword;
HCCPARAMS Data;
} XHC_HCCPARAMS;
#pragma pack ()
@@ -169,19 +168,19 @@ typedef union {
//
#pragma pack(1)
typedef struct {
UINT8 Pi;
UINT8 SubClassCode;
UINT8 BaseCode;
UINT8 Pi;
UINT8 SubClassCode;
UINT8 BaseCode;
} USB_CLASSC;
typedef struct {
UINT8 Length;
UINT8 DescType;
UINT8 NumPorts;
UINT16 HubCharacter;
UINT8 PwrOn2PwrGood;
UINT8 HubContrCurrent;
UINT8 Filler[16];
UINT8 Length;
UINT8 DescType;
UINT8 NumPorts;
UINT16 HubCharacter;
UINT8 PwrOn2PwrGood;
UINT8 HubContrCurrent;
UINT8 Filler[16];
} EFI_USB_HUB_DESCRIPTOR;
#pragma pack()
@@ -191,8 +190,8 @@ typedef struct {
// For more details, Please refer to USB 3.0 Spec Table 10-7.
//
typedef enum {
Usb3PortBHPortReset = 28,
Usb3PortBHPortResetChange = 29
Usb3PortBHPortReset = 28,
Usb3PortBHPortResetChange = 29
} XHC_PORT_FEATURE;
//
@@ -200,16 +199,16 @@ typedef enum {
// UEFI's port states.
//
typedef struct {
UINT32 HwState;
UINT16 UefiState;
UINT32 HwState;
UINT16 UefiState;
} USB_PORT_STATE_MAP;
//
// Structure to map the hardware port states to feature selector for clear port feature request.
//
typedef struct {
UINT32 HwState;
UINT16 Selector;
UINT32 HwState;
UINT16 Selector;
} USB_CLEAR_PORT_MAP;
/**
@@ -223,8 +222,8 @@ typedef struct {
**/
UINT32
XhcPeiReadOpReg (
IN PEI_XHC_DEV *Xhc,
IN UINT32 Offset
IN PEI_XHC_DEV *Xhc,
IN UINT32 Offset
);
/**
@@ -237,9 +236,9 @@ XhcPeiReadOpReg (
**/
VOID
XhcPeiWriteOpReg (
IN PEI_XHC_DEV *Xhc,
IN UINT32 Offset,
IN UINT32 Data
IN PEI_XHC_DEV *Xhc,
IN UINT32 Offset,
IN UINT32 Data
);
/**
@@ -252,9 +251,9 @@ XhcPeiWriteOpReg (
**/
VOID
XhcPeiSetOpRegBit (
IN PEI_XHC_DEV *Xhc,
IN UINT32 Offset,
IN UINT32 Bit
IN PEI_XHC_DEV *Xhc,
IN UINT32 Offset,
IN UINT32 Bit
);
/**
@@ -267,9 +266,9 @@ XhcPeiSetOpRegBit (
**/
VOID
XhcPeiClearOpRegBit (
IN PEI_XHC_DEV *Xhc,
IN UINT32 Offset,
IN UINT32 Bit
IN PEI_XHC_DEV *Xhc,
IN UINT32 Offset,
IN UINT32 Bit
);
/**
@@ -288,14 +287,13 @@ XhcPeiClearOpRegBit (
**/
EFI_STATUS
XhcPeiWaitOpRegBit (
IN PEI_XHC_DEV *Xhc,
IN UINT32 Offset,
IN UINT32 Bit,
IN BOOLEAN WaitToSet,
IN UINT32 Timeout
IN PEI_XHC_DEV *Xhc,
IN UINT32 Offset,
IN UINT32 Bit,
IN BOOLEAN WaitToSet,
IN UINT32 Timeout
);
/**
Write the data to the XHCI door bell register.
@@ -306,9 +304,9 @@ XhcPeiWaitOpRegBit (
**/
VOID
XhcPeiWriteDoorBellReg (
IN PEI_XHC_DEV *Xhc,
IN UINT32 Offset,
IN UINT32 Data
IN PEI_XHC_DEV *Xhc,
IN UINT32 Offset,
IN UINT32 Data
);
/**
@@ -322,8 +320,8 @@ XhcPeiWriteDoorBellReg (
**/
UINT32
XhcPeiReadRuntimeReg (
IN PEI_XHC_DEV *Xhc,
IN UINT32 Offset
IN PEI_XHC_DEV *Xhc,
IN UINT32 Offset
);
/**
@@ -336,9 +334,9 @@ XhcPeiReadRuntimeReg (
**/
VOID
XhcPeiWriteRuntimeReg (
IN PEI_XHC_DEV *Xhc,
IN UINT32 Offset,
IN UINT32 Data
IN PEI_XHC_DEV *Xhc,
IN UINT32 Offset,
IN UINT32 Data
);
/**
@@ -351,9 +349,9 @@ XhcPeiWriteRuntimeReg (
**/
VOID
XhcPeiSetRuntimeRegBit (
IN PEI_XHC_DEV *Xhc,
IN UINT32 Offset,
IN UINT32 Bit
IN PEI_XHC_DEV *Xhc,
IN UINT32 Offset,
IN UINT32 Bit
);
/**
@@ -366,9 +364,9 @@ XhcPeiSetRuntimeRegBit (
**/
VOID
XhcPeiClearRuntimeRegBit (
IN PEI_XHC_DEV *Xhc,
IN UINT32 Offset,
IN UINT32 Bit
IN PEI_XHC_DEV *Xhc,
IN UINT32 Offset,
IN UINT32 Bit
);
/**
@@ -382,7 +380,7 @@ XhcPeiClearRuntimeRegBit (
**/
BOOLEAN
XhcPeiIsHalt (
IN PEI_XHC_DEV *Xhc
IN PEI_XHC_DEV *Xhc
);
/**
@@ -396,7 +394,7 @@ XhcPeiIsHalt (
**/
BOOLEAN
XhcPeiIsSysError (
IN PEI_XHC_DEV *Xhc
IN PEI_XHC_DEV *Xhc
);
/**
@@ -411,8 +409,8 @@ XhcPeiIsSysError (
**/
EFI_STATUS
XhcPeiResetHC (
IN PEI_XHC_DEV *Xhc,
IN UINT32 Timeout
IN PEI_XHC_DEV *Xhc,
IN UINT32 Timeout
);
/**
@@ -427,8 +425,8 @@ XhcPeiResetHC (
**/
EFI_STATUS
XhcPeiHaltHC (
IN PEI_XHC_DEV *Xhc,
IN UINT32 Timeout
IN PEI_XHC_DEV *Xhc,
IN UINT32 Timeout
);
/**
@@ -443,8 +441,8 @@ XhcPeiHaltHC (
**/
EFI_STATUS
XhcPeiRunHC (
IN PEI_XHC_DEV *Xhc,
IN UINT32 Timeout
IN PEI_XHC_DEV *Xhc,
IN UINT32 Timeout
);
#endif

1034
MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c
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1004
MdeModulePkg/Bus/Pci/XhciPei/XhciSched.h
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File diff suppressed because it is too large Load Diff