MdeModulePkg: Apply uncrustify changes
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737 Apply uncrustify changes to .c/.h files in the MdeModulePkg package Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
This commit is contained in:
Michael Kubacki
committed by
mergify[bot]
mergify[bot]
parent
7c7184e201
commit
1436aea4d5
@@ -61,9 +61,9 @@ typedef enum {
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//
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// The maximum data length of each descriptor line
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//
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#define ADMA_MAX_DATA_PER_LINE 0x10000
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#define EMMC_SDMA_BOUNDARY 512 * 1024
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#define EMMC_SDMA_ROUND_UP(x, n) (((x) + n) & ~(n - 1))
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#define ADMA_MAX_DATA_PER_LINE 0x10000
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#define EMMC_SDMA_BOUNDARY 512 * 1024
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#define EMMC_SDMA_ROUND_UP(x, n) (((x) + n) & ~(n - 1))
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typedef enum {
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EmmcCommandTypeBc, // Broadcast commands, no response
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@@ -85,76 +85,76 @@ typedef enum {
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} EMMC_RESPONSE_TYPE;
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typedef struct _EMMC_COMMAND_BLOCK {
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UINT16 CommandIndex;
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UINT32 CommandArgument;
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UINT32 CommandType; // One of the EMMC_COMMAND_TYPE values
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UINT32 ResponseType; // One of the EMMC_RESPONSE_TYPE values
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UINT16 CommandIndex;
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UINT32 CommandArgument;
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UINT32 CommandType; // One of the EMMC_COMMAND_TYPE values
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UINT32 ResponseType; // One of the EMMC_RESPONSE_TYPE values
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} EMMC_COMMAND_BLOCK;
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typedef struct _EMMC_STATUS_BLOCK {
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UINT32 Resp0;
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UINT32 Resp1;
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UINT32 Resp2;
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UINT32 Resp3;
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UINT32 Resp0;
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UINT32 Resp1;
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UINT32 Resp2;
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UINT32 Resp3;
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} EMMC_STATUS_BLOCK;
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typedef struct _EMMC_COMMAND_PACKET {
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UINT64 Timeout;
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EMMC_COMMAND_BLOCK *EmmcCmdBlk;
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EMMC_STATUS_BLOCK *EmmcStatusBlk;
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VOID *InDataBuffer;
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VOID *OutDataBuffer;
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UINT32 InTransferLength;
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UINT32 OutTransferLength;
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UINT64 Timeout;
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EMMC_COMMAND_BLOCK *EmmcCmdBlk;
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EMMC_STATUS_BLOCK *EmmcStatusBlk;
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VOID *InDataBuffer;
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VOID *OutDataBuffer;
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UINT32 InTransferLength;
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UINT32 OutTransferLength;
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} EMMC_COMMAND_PACKET;
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#pragma pack(1)
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typedef struct {
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UINT32 Valid:1;
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UINT32 End:1;
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UINT32 Int:1;
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UINT32 Reserved:1;
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UINT32 Act:2;
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UINT32 Reserved1:10;
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UINT32 Length:16;
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UINT32 Address;
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UINT32 Valid : 1;
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UINT32 End : 1;
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UINT32 Int : 1;
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UINT32 Reserved : 1;
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UINT32 Act : 2;
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UINT32 Reserved1 : 10;
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UINT32 Length : 16;
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UINT32 Address;
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} EMMC_HC_ADMA_DESC_LINE;
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typedef struct {
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UINT32 TimeoutFreq:6; // bit 0:5
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UINT32 Reserved:1; // bit 6
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UINT32 TimeoutUnit:1; // bit 7
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UINT32 BaseClkFreq:8; // bit 8:15
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UINT32 MaxBlkLen:2; // bit 16:17
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UINT32 BusWidth8:1; // bit 18
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UINT32 Adma2:1; // bit 19
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UINT32 Reserved2:1; // bit 20
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UINT32 HighSpeed:1; // bit 21
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UINT32 Sdma:1; // bit 22
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UINT32 SuspRes:1; // bit 23
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UINT32 Voltage33:1; // bit 24
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UINT32 Voltage30:1; // bit 25
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UINT32 Voltage18:1; // bit 26
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UINT32 Reserved3:1; // bit 27
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UINT32 SysBus64:1; // bit 28
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UINT32 AsyncInt:1; // bit 29
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UINT32 SlotType:2; // bit 30:31
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UINT32 Sdr50:1; // bit 32
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UINT32 Sdr104:1; // bit 33
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UINT32 Ddr50:1; // bit 34
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UINT32 Reserved4:1; // bit 35
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UINT32 DriverTypeA:1; // bit 36
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UINT32 DriverTypeC:1; // bit 37
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UINT32 DriverTypeD:1; // bit 38
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UINT32 DriverType4:1; // bit 39
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UINT32 TimerCount:4; // bit 40:43
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UINT32 Reserved5:1; // bit 44
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UINT32 TuningSDR50:1; // bit 45
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UINT32 RetuningMod:2; // bit 46:47
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UINT32 ClkMultiplier:8; // bit 48:55
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UINT32 Reserved6:7; // bit 56:62
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UINT32 Hs400:1; // bit 63
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UINT32 TimeoutFreq : 6; // bit 0:5
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UINT32 Reserved : 1; // bit 6
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UINT32 TimeoutUnit : 1; // bit 7
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UINT32 BaseClkFreq : 8; // bit 8:15
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UINT32 MaxBlkLen : 2; // bit 16:17
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UINT32 BusWidth8 : 1; // bit 18
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UINT32 Adma2 : 1; // bit 19
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UINT32 Reserved2 : 1; // bit 20
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UINT32 HighSpeed : 1; // bit 21
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UINT32 Sdma : 1; // bit 22
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UINT32 SuspRes : 1; // bit 23
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UINT32 Voltage33 : 1; // bit 24
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UINT32 Voltage30 : 1; // bit 25
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UINT32 Voltage18 : 1; // bit 26
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UINT32 Reserved3 : 1; // bit 27
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UINT32 SysBus64 : 1; // bit 28
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UINT32 AsyncInt : 1; // bit 29
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UINT32 SlotType : 2; // bit 30:31
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UINT32 Sdr50 : 1; // bit 32
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UINT32 Sdr104 : 1; // bit 33
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UINT32 Ddr50 : 1; // bit 34
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UINT32 Reserved4 : 1; // bit 35
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UINT32 DriverTypeA : 1; // bit 36
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UINT32 DriverTypeC : 1; // bit 37
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UINT32 DriverTypeD : 1; // bit 38
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UINT32 DriverType4 : 1; // bit 39
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UINT32 TimerCount : 4; // bit 40:43
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UINT32 Reserved5 : 1; // bit 44
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UINT32 TuningSDR50 : 1; // bit 45
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UINT32 RetuningMod : 2; // bit 46:47
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UINT32 ClkMultiplier : 8; // bit 48:55
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UINT32 Reserved6 : 7; // bit 56:62
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UINT32 Hs400 : 1; // bit 63
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} EMMC_HC_SLOT_CAP;
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#pragma pack()
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@@ -170,7 +170,7 @@ typedef struct {
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**/
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EFI_STATUS
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EmmcPeimHcReset (
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IN UINTN Bar
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IN UINTN Bar
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);
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/**
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@@ -185,7 +185,7 @@ EmmcPeimHcReset (
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**/
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EFI_STATUS
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EmmcPeimHcEnableInterrupt (
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IN UINTN Bar
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IN UINTN Bar
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);
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/**
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@@ -200,8 +200,8 @@ EmmcPeimHcEnableInterrupt (
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**/
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EFI_STATUS
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EmmcPeimHcGetCapability (
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IN UINTN Bar,
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OUT EMMC_HC_SLOT_CAP *Capability
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IN UINTN Bar,
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OUT EMMC_HC_SLOT_CAP *Capability
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);
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/**
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@@ -219,7 +219,7 @@ EmmcPeimHcGetCapability (
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**/
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EFI_STATUS
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EmmcPeimHcCardDetect (
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IN UINTN Bar
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IN UINTN Bar
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);
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/**
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@@ -234,7 +234,7 @@ EmmcPeimHcCardDetect (
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**/
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EFI_STATUS
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EmmcPeimHcInitHost (
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IN UINTN Bar
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IN UINTN Bar
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);
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/**
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@@ -255,11 +255,11 @@ EmmcPeimHcInitHost (
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**/
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EFI_STATUS
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EmmcPeimSwitch (
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IN EMMC_PEIM_HC_SLOT *Slot,
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IN UINT8 Access,
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IN UINT8 Index,
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IN UINT8 Value,
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IN UINT8 CmdSet
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IN EMMC_PEIM_HC_SLOT *Slot,
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IN UINT8 Access,
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IN UINT8 Index,
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IN UINT8 Value,
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IN UINT8 CmdSet
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);
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/**
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@@ -277,8 +277,8 @@ EmmcPeimSwitch (
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**/
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EFI_STATUS
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EmmcPeimSetBlkCount (
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IN EMMC_PEIM_HC_SLOT *Slot,
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IN UINT16 BlockCount
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IN EMMC_PEIM_HC_SLOT *Slot,
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IN UINT16 BlockCount
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);
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/**
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@@ -300,12 +300,12 @@ EmmcPeimSetBlkCount (
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**/
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EFI_STATUS
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EmmcPeimRwMultiBlocks (
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IN EMMC_PEIM_HC_SLOT *Slot,
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IN EFI_LBA Lba,
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IN UINT32 BlockSize,
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IN VOID *Buffer,
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IN UINTN BufferSize,
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IN BOOLEAN IsRead
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IN EMMC_PEIM_HC_SLOT *Slot,
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IN EFI_LBA Lba,
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IN UINT32 BlockSize,
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IN VOID *Buffer,
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IN UINTN BufferSize,
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IN BOOLEAN IsRead
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);
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/**
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@@ -321,7 +321,7 @@ EmmcPeimRwMultiBlocks (
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**/
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EFI_STATUS
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EmmcPeimIdentification (
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IN EMMC_PEIM_HC_SLOT *Slot
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IN EMMC_PEIM_HC_SLOT *Slot
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);
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/**
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@@ -332,8 +332,7 @@ EmmcPeimIdentification (
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**/
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VOID
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EmmcPeimFreeTrb (
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IN EMMC_TRB *Trb
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IN EMMC_TRB *Trb
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);
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#endif
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