MdeModulePkg: Apply uncrustify changes

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737

Apply uncrustify changes to .c/.h files in the MdeModulePkg package

Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
This commit is contained in:
Michael Kubacki
2021-12-05 14:54:02 -08:00
committed by mergify[bot]
parent 7c7184e201
commit 1436aea4d5
994 changed files with 107608 additions and 101311 deletions

View File

@ -30,7 +30,7 @@ typedef struct _PEI_ATA_CONTROLLER_PPI PEI_ATA_CONTROLLER_PPI;
/// This is designed for old generation chipset with PATA/SATA controllers.
/// It may be ignored in PPI implementation for new generation chipset without PATA controller.
///
#define PEI_ICH_IDE_NONE 0x00
#define PEI_ICH_IDE_NONE 0x00
///
/// This bit is used in the ChannelMask parameter of EnableAtaChannel() to
@ -38,7 +38,7 @@ typedef struct _PEI_ATA_CONTROLLER_PPI PEI_ATA_CONTROLLER_PPI;
/// This is designed for old generation chipset with PATA/SATA controllers.
/// It may be ignored in PPI implementation for new generation chipset without PATA controller.
///
#define PEI_ICH_IDE_PRIMARY 0x01
#define PEI_ICH_IDE_PRIMARY 0x01
///
/// This bit is used in the ChannelMask parameter of EnableAtaChannel() to
@ -46,7 +46,7 @@ typedef struct _PEI_ATA_CONTROLLER_PPI PEI_ATA_CONTROLLER_PPI;
/// This is designed for old generation chipset with PATA/SATA controllers.
/// It may be ignored in PPI implementation for new generation chipset without PATA controller.
///
#define PEI_ICH_IDE_SECONDARY 0x02
#define PEI_ICH_IDE_SECONDARY 0x02
///
/// This bit is used in the ChannelMask parameter of EnableAtaChannel() to
@ -54,7 +54,7 @@ typedef struct _PEI_ATA_CONTROLLER_PPI PEI_ATA_CONTROLLER_PPI;
/// This is designed for old generation chipset with PATA/SATA controllers.
/// It may be ignored in PPI implementation for new generation chipset without PATA controller.
///
#define PEI_ICH_SATA_NONE 0x04
#define PEI_ICH_SATA_NONE 0x04
///
/// This bit is used in the ChannelMask parameter of EnableAtaChannel() to
@ -62,7 +62,7 @@ typedef struct _PEI_ATA_CONTROLLER_PPI PEI_ATA_CONTROLLER_PPI;
/// This is designed for old generation chipset with PATA/SATA controllers.
/// It may be ignored in PPI implementation for new generation chipset without PATA controller.
///
#define PEI_ICH_SATA_PRIMARY 0x08
#define PEI_ICH_SATA_PRIMARY 0x08
///
/// This bit is used in the ChannelMask parameter of EnableAtaChannel() to
@ -79,11 +79,11 @@ typedef struct {
///
/// Base I/O port address of the IDE controller's command block
///
UINT16 CommandBlockBaseAddr;
UINT16 CommandBlockBaseAddr;
///
/// Base I/O port address of the IDE controller's control block
///
UINT16 ControlBlockBaseAddr;
UINT16 ControlBlockBaseAddr;
} IDE_REGS_BASE_ADDR;
/**
@ -144,12 +144,10 @@ UINT32
/// retrieves the base I/O port addresses to the enabled IDE and SATA channels.
///
struct _PEI_ATA_CONTROLLER_PPI {
PEI_ENABLE_ATA EnableAtaChannel;
GET_IDE_REGS_BASE_ADDR GetIdeRegsBaseAddr;
PEI_ENABLE_ATA EnableAtaChannel;
GET_IDE_REGS_BASE_ADDR GetIdeRegsBaseAddr;
};
extern EFI_GUID gPeiAtaControllerPpiGuid;
extern EFI_GUID gPeiAtaControllerPpiGuid;
#endif