UefiCpuPkg/Cpuid.h: Update CPUID definitions with SDM (Sep.2016)
https://bugzilla.tianocore.org/show_bug.cgi?id=176 Update CPUID leaf and sub-leaf indexes and structures as described by Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 2A, September 2016, CPUID instruction. Summary of incompatible changes: 1. Field name changes in CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Bit 12 has been renamed from 'PQM' to 'RDT_M' and bit 15 has been renamed from 'PQE' to 'RDT_A'. 2. Stucture and filed name changes for 'CPUID Platform QoS Monitoring Information' related definitions Definition 'CPUID_PLATFORM_QOS_MONITORING' has been renamed to 'CPUID_INTEL_RDT_MONITORING'. Definition 'CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF' has been renamed to 'CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF'. Definition 'CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF' has been renamed to 'CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF'. 3. Stucture and filed name changes for 'CPUID Platform QoS Enforcement Information' related definitions Definition 'CPUID_PLATFORM_QOS_ENFORCEMENT' has been renamed to 'CPUID_INTEL_RDT_ALLOCATION'. Definition 'CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF' has been renamed to 'CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF'. Definition 'CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF' has been renamed to 'CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF'. This commit also updates the relating codes in UefiCpuPkg/Application/Cpuid to reflect the changes. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
This commit is contained in:
Hao Wu
@@ -88,13 +88,14 @@ CPUID_CACHE_INFO_DESCRIPTION mCpuidCacheInfoDescription[] = {
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{ 0x56 , "TLB" , "Data TLB0: 4 MByte pages, 4-way set associative, 16 entries" },
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{ 0x57 , "TLB" , "Data TLB0: 4 KByte pages, 4-way associative, 16 entries" },
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{ 0x59 , "TLB" , "Data TLB0: 4 KByte pages, fully associative, 16 entries" },
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{ 0x5A , "TLB" , "Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries" },
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{ 0x5A , "TLB" , "Data TLB0: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries" },
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{ 0x5B , "TLB" , "Data TLB: 4 KByte and 4 MByte pages, 64 entries" },
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{ 0x5C , "TLB" , "Data TLB: 4 KByte and 4 MByte pages,128 entries" },
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{ 0x5D , "TLB" , "Data TLB: 4 KByte and 4 MByte pages,256 entries" },
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{ 0x60 , "Cache" , "1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size" },
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{ 0x61 , "TLB" , "Instruction TLB: 4 KByte pages, fully associative, 48 entries" },
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{ 0x63 , "TLB" , "Data TLB: 1 GByte pages, 4-way set associative, 4 entries" },
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{ 0x63 , "TLB" , "Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries" },
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{ 0x64 , "TLB" , "Data TLB: 4 KByte pages, 4-way set associative, 512 entries" },
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{ 0x66 , "Cache" , "1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size" },
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{ 0x67 , "Cache" , "1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size" },
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{ 0x68 , "Cache" , "1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size" },
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@@ -133,6 +134,7 @@ CPUID_CACHE_INFO_DESCRIPTION mCpuidCacheInfoDescription[] = {
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{ 0xC1 , "STLB" , "Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries" },
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{ 0xC2 , "DTLB" , "DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries" },
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{ 0xC3 , "STLB" , "Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries." },
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{ 0xC4 , "DTLB" , "DTLB: 2M/4M Byte pages, 4-way associative, 32 entries" },
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{ 0xCA , "STLB" , "Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries" },
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{ 0xD0 , "Cache" , "3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size" },
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{ 0xD1 , "Cache" , "3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size" },
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@@ -604,18 +606,24 @@ CpuidStructuredExtendedFeatureFlags (
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PRINT_BIT_FIELD (Ebx, EnhancedRepMovsbStosb);
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PRINT_BIT_FIELD (Ebx, INVPCID);
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PRINT_BIT_FIELD (Ebx, RTM);
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PRINT_BIT_FIELD (Ebx, PQM);
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PRINT_BIT_FIELD (Ebx, RDT_M);
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PRINT_BIT_FIELD (Ebx, DeprecateFpuCsDs);
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PRINT_BIT_FIELD (Ebx, MPX);
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PRINT_BIT_FIELD (Ebx, PQE);
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PRINT_BIT_FIELD (Ebx, RDT_A);
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PRINT_BIT_FIELD (Ebx, RDSEED);
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PRINT_BIT_FIELD (Ebx, ADX);
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PRINT_BIT_FIELD (Ebx, SMAP);
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PRINT_BIT_FIELD (Ebx, CLFLUSHOPT);
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PRINT_BIT_FIELD (Ebx, CLWB);
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PRINT_BIT_FIELD (Ebx, IntelProcessorTrace);
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PRINT_BIT_FIELD (Ebx, SHA);
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PRINT_BIT_FIELD (Ecx, PREFETCHWT1);
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PRINT_BIT_FIELD (Ecx, UMIP);
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PRINT_BIT_FIELD (Ecx, PKU);
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PRINT_BIT_FIELD (Ecx, OSPKE);
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PRINT_BIT_FIELD (Ecx, MAWAU);
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PRINT_BIT_FIELD (Ecx, RDPID);
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PRINT_BIT_FIELD (Ecx, SGX_LC);
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}
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}
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}
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@@ -815,78 +823,81 @@ CpuidExtendedStateMainLeaf (
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}
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/**
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Display CPUID_PLATFORM_QOS_MONITORING enumeration sub-leaf.
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Display CPUID_INTEL_RDT_MONITORING enumeration sub-leaf.
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**/
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VOID
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CpuidPlatformQosMonitoringEnumerationSubLeaf (
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CpuidIntelRdtMonitoringEnumerationSubLeaf (
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VOID
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)
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{
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UINT32 Ebx;
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CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF_EDX Edx;
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CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX Edx;
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if (CPUID_PLATFORM_QOS_MONITORING > gMaximumBasicFunction) {
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if (CPUID_INTEL_RDT_MONITORING > gMaximumBasicFunction) {
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return;
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}
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AsmCpuidEx (
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CPUID_PLATFORM_QOS_MONITORING, CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF,
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CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF,
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NULL, &Ebx, NULL, &Edx.Uint32
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);
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Print (L"CPUID_PLATFORM_QOS_MONITORING (Leaf %08x, Sub-Leaf %08x)\n", CPUID_PLATFORM_QOS_MONITORING, CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF);
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Print (L"CPUID_INTEL_RDT_MONITORING (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF);
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Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, Ebx, 0, Edx.Uint32);
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PRINT_VALUE (Ebx, Maximum_RMID_Range);
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PRINT_BIT_FIELD (Edx, L3CacheQosEnforcement);
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PRINT_BIT_FIELD (Edx, L3CacheRDT_M);
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}
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/**
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Display CPUID_PLATFORM_QOS_MONITORING capability sub-leaf.
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Display CPUID_INTEL_RDT_MONITORING L3 cache capability sub-leaf.
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**/
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VOID
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CpuidPlatformQosMonitoringCapabilitySubLeaf (
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CpuidIntelRdtMonitoringL3CacheCapabilitySubLeaf (
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VOID
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)
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{
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UINT32 Ebx;
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UINT32 Ecx;
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CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF_EDX Edx;
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CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX Edx;
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if (CPUID_PLATFORM_QOS_MONITORING > gMaximumBasicFunction) {
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if (CPUID_INTEL_RDT_MONITORING > gMaximumBasicFunction) {
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return;
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}
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AsmCpuidEx (
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CPUID_PLATFORM_QOS_MONITORING, CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF,
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CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF,
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NULL, &Ebx, &Ecx, &Edx.Uint32
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);
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Print (L"CPUID_PLATFORM_QOS_MONITORING (Leaf %08x, Sub-Leaf %08x)\n", CPUID_PLATFORM_QOS_MONITORING, CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF);
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Print (L"CPUID_INTEL_RDT_MONITORING (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF);
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Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, Ebx, Ecx, Edx.Uint32);
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PRINT_VALUE (Ebx, OccupancyConversionFactor);
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PRINT_VALUE (Ecx, Maximum_RMID_Range);
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PRINT_BIT_FIELD (Edx, L3CacheOccupancyMonitoring);
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PRINT_BIT_FIELD (Edx, L3CacheTotalBandwidthMonitoring);
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PRINT_BIT_FIELD (Edx, L3CacheLocalBandwidthMonitoring);
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}
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/**
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Display CPUID_PLATFORM_QOS_ENFORCEMENT sub-leaf.
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Display CPUID_INTEL_RDT_ALLOCATION L3 cache allocation technology enumeration
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sub-leaf.
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**/
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VOID
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CpuidPlatformQosEnforcementResidSubLeaf (
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CpuidIntelRdtAllocationL3CacheSubLeaf (
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VOID
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)
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{
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CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EAX Eax;
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CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX Eax;
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UINT32 Ebx;
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CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_ECX Ecx;
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CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EDX Edx;
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CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX Ecx;
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CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX Edx;
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AsmCpuidEx (
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CPUID_PLATFORM_QOS_ENFORCEMENT, CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF,
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CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF,
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&Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx.Uint32
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);
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Print (L"CPUID_PLATFORM_QOS_ENFORCEMENT (Leaf %08x, Sub-Leaf %08x)\n", CPUID_PLATFORM_QOS_ENFORCEMENT, CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF);
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Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF);
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Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, Ecx.Uint32, Edx.Uint32);
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PRINT_BIT_FIELD (Eax, CapacityLength);
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PRINT_VALUE (Ebx, AllocationUnitBitMap);
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@@ -896,29 +907,56 @@ CpuidPlatformQosEnforcementResidSubLeaf (
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}
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/**
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Display CPUID_PLATFORM_QOS_ENFORCEMENT main leaf and sub-leaf.
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Display CPUID_INTEL_RDT_ALLOCATION L2 cache allocation technology enumeration
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sub-leaf.
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**/
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VOID
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CpuidPlatformQosEnforcementMainLeaf (
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CpuidIntelRdtAllocationL2CacheSubLeaf (
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VOID
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)
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{
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CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF_EBX Ebx;
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CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX Eax;
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UINT32 Ebx;
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CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX Edx;
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if (CPUID_PLATFORM_QOS_ENFORCEMENT > gMaximumBasicFunction) {
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AsmCpuidEx (
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CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF,
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&Eax.Uint32, &Ebx, NULL, &Edx.Uint32
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);
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Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF);
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Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, 0, Edx.Uint32);
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PRINT_BIT_FIELD (Eax, CapacityLength);
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PRINT_VALUE (Ebx, AllocationUnitBitMap);
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PRINT_BIT_FIELD (Edx, HighestCosNumber);
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}
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/**
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Display CPUID_INTEL_RDT_ALLOCATION main leaf and sub-leaves.
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**/
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VOID
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CpuidIntelRdtAllocationMainLeaf (
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VOID
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)
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{
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CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX Ebx;
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if (CPUID_INTEL_RDT_ALLOCATION > gMaximumBasicFunction) {
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return;
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}
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AsmCpuidEx (
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CPUID_PLATFORM_QOS_ENFORCEMENT, CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF,
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CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF,
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NULL, &Ebx.Uint32, NULL, NULL
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);
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Print (L"CPUID_PLATFORM_QOS_ENFORCEMENT (Leaf %08x, Sub-Leaf %08x)\n", CPUID_PLATFORM_QOS_ENFORCEMENT, CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF);
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Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF);
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Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, Ebx.Uint32, 0, 0);
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PRINT_BIT_FIELD (Ebx, L3CacheQosEnforcement);
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PRINT_BIT_FIELD (Ebx, L3CacheAllocation);
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PRINT_BIT_FIELD (Ebx, L2CacheAllocation);
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CpuidPlatformQosEnforcementResidSubLeaf ();
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CpuidIntelRdtAllocationL3CacheSubLeaf ();
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CpuidIntelRdtAllocationL2CacheSubLeaf ();
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}
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/**
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@@ -1093,6 +1131,8 @@ CpuidIntelProcessorTraceMainLeaf (
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PRINT_BIT_FIELD (Ebx, ConfigurablePsb);
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PRINT_BIT_FIELD (Ebx, IpTraceStopFiltering);
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PRINT_BIT_FIELD (Ebx, Mtc);
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PRINT_BIT_FIELD (Ebx, PTWrite);
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PRINT_BIT_FIELD (Ebx, PowerEventTrace);
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PRINT_BIT_FIELD (Ecx, RTIT);
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PRINT_BIT_FIELD (Ecx, ToPA);
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PRINT_BIT_FIELD (Ecx, SingleRangeOutput);
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@@ -1113,14 +1153,15 @@ CpuidTimeStampCounter (
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{
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UINT32 Eax;
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UINT32 Ebx;
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UINT32 Ecx;
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if (CPUID_TIME_STAMP_COUNTER > gMaximumBasicFunction) {
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return;
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}
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AsmCpuid (CPUID_TIME_STAMP_COUNTER, &Eax, &Ebx, NULL, NULL);
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AsmCpuid (CPUID_TIME_STAMP_COUNTER, &Eax, &Ebx, &Ecx, NULL);
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Print (L"CPUID_TIME_STAMP_COUNTER (Leaf %08x)\n", CPUID_TIME_STAMP_COUNTER);
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Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx, 0, 0);
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Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx, Ecx, 0);
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}
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/**
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@@ -1446,9 +1487,9 @@ UefiMain (
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CpuidArchitecturalPerformanceMonitoring ();
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CpuidExtendedTopology ();
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CpuidExtendedStateMainLeaf ();
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CpuidPlatformQosMonitoringEnumerationSubLeaf ();
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CpuidPlatformQosMonitoringCapabilitySubLeaf ();
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CpuidPlatformQosEnforcementMainLeaf ();
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CpuidIntelRdtMonitoringEnumerationSubLeaf ();
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CpuidIntelRdtMonitoringL3CacheCapabilitySubLeaf ();
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CpuidIntelRdtAllocationMainLeaf ();
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CpuidEnumerationOfIntelSgx ();
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CpuidIntelProcessorTraceMainLeaf ();
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CpuidTimeStampCounter ();
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