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ArmPlatformPkg/ArmJuno: fix Juno PIO host bridge mapping

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The Juno PIO mapping is 8M, so it should be using a 32-bit
PIO address translation. Further, PIO addresses should start
at 0 and be translated to/from the ARM MMIO region.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
This commit is contained in:
Jeremy Linton
2016-07-14 08:58:29 -05:00
committed by Leif Lindholm
parent e39d0569a6
commit 162e789178
1 changed files with 6 additions and 3 deletions
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9
ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.c
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@@ -72,7 +72,9 @@ HWPciRbInit (
PCI_TRACE ("PCIe Setting up Address Translation"); PCI_TRACE ("PCIe Setting up Address Translation");
PCIE_ROOTPORT_WRITE32 (PCIE_BAR_WIN, PCIE_BAR_WIN_SUPPORT_IO | PCIE_BAR_WIN_SUPPORT_MEM | PCIE_BAR_WIN_SUPPORT_MEM64); // The Juno PIO window is 8M, so we need full 32-bit PIO decoding.
PCIE_ROOTPORT_WRITE32 (PCIE_BAR_WIN, PCIE_BAR_WIN_SUPPORT_IO | PCIE_BAR_WIN_SUPPORT_IO32 |
PCIE_BAR_WIN_SUPPORT_MEM | PCIE_BAR_WIN_SUPPORT_MEM64);
// Setup the PCI Configuration Registers // Setup the PCI Configuration Registers
// Offset 0a: SubClass 04 PCI-PCI Bridge // Offset 0a: SubClass 04 PCI-PCI Bridge
@@ -107,8 +109,9 @@ HWPciRbInit (
SetTranslationAddressEntry (CpuIo, TranslationTable, PCI_ECAM_BASE, PCI_ECAM_BASE, PCI_ECAM_SIZE, PCI_ATR_TRSLID_PCIE_CONF); SetTranslationAddressEntry (CpuIo, TranslationTable, PCI_ECAM_BASE, PCI_ECAM_BASE, PCI_ECAM_SIZE, PCI_ATR_TRSLID_PCIE_CONF);
TranslationTable += PCI_ATR_ENTRY_SIZE; TranslationTable += PCI_ATR_ENTRY_SIZE;
// PCI IO Support // PCI IO Support, the PIO space is translated from the arm MMIO PCI_IO_BASE address to the PIO base address of 0
SetTranslationAddressEntry (CpuIo, TranslationTable, PCI_IO_BASE, PCI_IO_BASE, PCI_IO_SIZE, PCI_ATR_TRSLID_PCIE_IO); // AKA, PIO addresses used by endpoints are generally in the range of 0-64K.
SetTranslationAddressEntry (CpuIo, TranslationTable, PCI_IO_BASE, 0, PCI_IO_SIZE, PCI_ATR_TRSLID_PCIE_IO);
TranslationTable += PCI_ATR_ENTRY_SIZE; TranslationTable += PCI_ATR_ENTRY_SIZE;
// PCI MEM32 Support // PCI MEM32 Support