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Update XHCI driver to use PCI IO AllocateBuffer/Map/Unmap to do DMA operation.

Browse Source 
Signed-off-by: Elvin Li <elvin.li@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>


git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14546 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Elvin Li
2013-08-12 08:51:55 +00:00
committed by li-elvin
parent eb290d0257
commit 1847ed0bfd
7 changed files with 1358 additions and 124 deletions
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758
MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.c Normal file
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@ -0,0 +1,758 @@
/** @file
Routine procedures for memory allocate/free.
Copyright (c) 2013, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "Xhci.h"
/**
Allocate a block of memory to be used by the buffer pool.
@param Pool The buffer pool to allocate memory for.
@param Pages How many pages to allocate.
@return The allocated memory block or NULL if failed.
**/
USBHC_MEM_BLOCK *
UsbHcAllocMemBlock (
IN USBHC_MEM_POOL *Pool,
IN UINTN Pages
)
{
USBHC_MEM_BLOCK *Block;
EFI_PCI_IO_PROTOCOL *PciIo;
VOID *BufHost;
VOID *Mapping;
EFI_PHYSICAL_ADDRESS MappedAddr;
UINTN Bytes;
EFI_STATUS Status;
PciIo = Pool->PciIo;
Block = AllocateZeroPool (sizeof (USBHC_MEM_BLOCK));
if (Block == NULL) {
return NULL;
}
//
// each bit in the bit array represents USBHC_MEM_UNIT
// bytes of memory in the memory block.
//
ASSERT (USBHC_MEM_UNIT * 8 <= EFI_PAGE_SIZE);
Block->BufLen = EFI_PAGES_TO_SIZE (Pages);
Block->BitsLen = Block->BufLen / (USBHC_MEM_UNIT * 8);
Block->Bits = AllocateZeroPool (Block->BitsLen);
if (Block->Bits == NULL) {
gBS->FreePool (Block);
return NULL;
}
//
// Allocate the number of Pages of memory, then map it for
// bus master read and write.
//
Status = PciIo->AllocateBuffer (
PciIo,
AllocateAnyPages,
EfiBootServicesData,
Pages,
&BufHost,
0
);
if (EFI_ERROR (Status)) {
goto FREE_BITARRAY;
}
Bytes = EFI_PAGES_TO_SIZE (Pages);
Status = PciIo->Map (
PciIo,
EfiPciIoOperationBusMasterCommonBuffer,
BufHost,
&Bytes,
&MappedAddr,
&Mapping
);
if (EFI_ERROR (Status) || (Bytes != EFI_PAGES_TO_SIZE (Pages))) {
goto FREE_BUFFER;
}
Block->BufHost = BufHost;
Block->Buf = (UINT8 *) ((UINTN) MappedAddr);
Block->Mapping = Mapping;
return Block;
FREE_BUFFER:
PciIo->FreeBuffer (PciIo, Pages, BufHost);
FREE_BITARRAY:
gBS->FreePool (Block->Bits);
gBS->FreePool (Block);
return NULL;
}
/**
Free the memory block from the memory pool.
@param Pool The memory pool to free the block from.
@param Block The memory block to free.
**/
VOID
UsbHcFreeMemBlock (
IN USBHC_MEM_POOL *Pool,
IN USBHC_MEM_BLOCK *Block
)
{
EFI_PCI_IO_PROTOCOL *PciIo;
ASSERT ((Pool != NULL) && (Block != NULL));
PciIo = Pool->PciIo;
//
// Unmap the common buffer then free the structures
//
PciIo->Unmap (PciIo, Block->Mapping);
PciIo->FreeBuffer (PciIo, EFI_SIZE_TO_PAGES (Block->BufLen), Block->BufHost);
gBS->FreePool (Block->Bits);
gBS->FreePool (Block);
}
/**
Alloc some memory from the block.
@param Block The memory block to allocate memory from.
@param Units Number of memory units to allocate.
@return The pointer to the allocated memory. If couldn't allocate the needed memory,
the return value is NULL.
**/
VOID *
UsbHcAllocMemFromBlock (
IN USBHC_MEM_BLOCK *Block,
IN UINTN Units
)
{
UINTN Byte;
UINT8 Bit;
UINTN StartByte;
UINT8 StartBit;
UINTN Available;
UINTN Count;
ASSERT ((Block != 0) && (Units != 0));
StartByte = 0;
StartBit = 0;
Available = 0;
for (Byte = 0, Bit = 0; Byte < Block->BitsLen;) {
//
// If current bit is zero, the corresponding memory unit is
// available, otherwise we need to restart our searching.
// Available counts the consective number of zero bit.
//
if (!USB_HC_BIT_IS_SET (Block->Bits[Byte], Bit)) {
Available++;
if (Available >= Units) {
break;
}
NEXT_BIT (Byte, Bit);
} else {
NEXT_BIT (Byte, Bit);
Available = 0;
StartByte = Byte;
StartBit = Bit;
}
}
if (Available < Units) {
return NULL;
}
//
// Mark the memory as allocated
//
Byte = StartByte;
Bit = StartBit;
for (Count = 0; Count < Units; Count++) {
ASSERT (!USB_HC_BIT_IS_SET (Block->Bits[Byte], Bit));
Block->Bits[Byte] = (UINT8) (Block->Bits[Byte] | USB_HC_BIT (Bit));
NEXT_BIT (Byte, Bit);
}
return Block->BufHost + (StartByte * 8 + StartBit) * USBHC_MEM_UNIT;
}
/**
Calculate the corresponding pci bus address according to the Mem parameter.
@param Pool The memory pool of the host controller.
@param Mem The pointer to host memory.
@param Size The size of the memory region.
@return The pci memory address
**/
EFI_PHYSICAL_ADDRESS
UsbHcGetPciAddrForHostAddr (
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
)
{
USBHC_MEM_BLOCK *Head;
USBHC_MEM_BLOCK *Block;
UINTN AllocSize;
EFI_PHYSICAL_ADDRESS PhyAddr;
UINTN Offset;
Head = Pool->Head;
AllocSize = USBHC_MEM_ROUND (Size);
if (Mem == NULL) {
return 0;
}
for (Block = Head; Block != NULL; Block = Block->Next) {
//
// scan the memory block list for the memory block that
// completely contains the allocated memory.
//
if ((Block->BufHost <= (UINT8 *) Mem) && (((UINT8 *) Mem + AllocSize) <= (Block->BufHost + Block->BufLen))) {
break;
}
}
ASSERT ((Block != NULL));
//
// calculate the pci memory address for host memory address.
//
Offset = (UINT8 *)Mem - Block->BufHost;
PhyAddr = (EFI_PHYSICAL_ADDRESS)(UINTN) (Block->Buf + Offset);
return PhyAddr;
}
/**
Calculate the corresponding host address according to the pci address.
@param Pool The memory pool of the host controller.
@param Mem The pointer to pci memory.
@param Size The size of the memory region.
@return The host memory address
**/
EFI_PHYSICAL_ADDRESS
UsbHcGetHostAddrForPciAddr (
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
)
{
USBHC_MEM_BLOCK *Head;
USBHC_MEM_BLOCK *Block;
UINTN AllocSize;
EFI_PHYSICAL_ADDRESS HostAddr;
UINTN Offset;
Head = Pool->Head;
AllocSize = USBHC_MEM_ROUND (Size);
if (Mem == NULL) {
return 0;
}
for (Block = Head; Block != NULL; Block = Block->Next) {
//
// scan the memory block list for the memory block that
// completely contains the allocated memory.
//
if ((Block->Buf <= (UINT8 *) Mem) && (((UINT8 *) Mem + AllocSize) <= (Block->Buf + Block->BufLen))) {
break;
}
}
ASSERT ((Block != NULL));
//
// calculate the pci memory address for host memory address.
//
Offset = (UINT8 *)Mem - Block->Buf;
HostAddr = (EFI_PHYSICAL_ADDRESS)(UINTN) (Block->BufHost + Offset);
return HostAddr;
}
/**
Insert the memory block to the pool's list of the blocks.
@param Head The head of the memory pool's block list.
@param Block The memory block to insert.
**/
VOID
UsbHcInsertMemBlockToPool (
IN USBHC_MEM_BLOCK *Head,
IN USBHC_MEM_BLOCK *Block
)
{
ASSERT ((Head != NULL) && (Block != NULL));
Block->Next = Head->Next;
Head->Next = Block;
}
/**
Is the memory block empty?
@param Block The memory block to check.
@retval TRUE The memory block is empty.
@retval FALSE The memory block isn't empty.
**/
BOOLEAN
UsbHcIsMemBlockEmpty (
IN USBHC_MEM_BLOCK *Block
)
{
UINTN Index;
for (Index = 0; Index < Block->BitsLen; Index++) {
if (Block->Bits[Index] != 0) {
return FALSE;
}
}
return TRUE;
}
/**
Unlink the memory block from the pool's list.
@param Head The block list head of the memory's pool.
@param BlockToUnlink The memory block to unlink.
**/
VOID
UsbHcUnlinkMemBlock (
IN USBHC_MEM_BLOCK *Head,
IN USBHC_MEM_BLOCK *BlockToUnlink
)
{
USBHC_MEM_BLOCK *Block;
ASSERT ((Head != NULL) && (BlockToUnlink != NULL));
for (Block = Head; Block != NULL; Block = Block->Next) {
if (Block->Next == BlockToUnlink) {
Block->Next = BlockToUnlink->Next;
BlockToUnlink->Next = NULL;
break;
}
}
}
/**
Initialize the memory management pool for the host controller.
@param PciIo The PciIo that can be used to access the host controller.
@retval EFI_SUCCESS The memory pool is initialized.
@retval EFI_OUT_OF_RESOURCE Fail to init the memory pool.
**/
USBHC_MEM_POOL *
UsbHcInitMemPool (
IN EFI_PCI_IO_PROTOCOL *PciIo
)
{
USBHC_MEM_POOL *Pool;
Pool = AllocatePool (sizeof (USBHC_MEM_POOL));
if (Pool == NULL) {
return Pool;
}
Pool->PciIo = PciIo;
Pool->Head = UsbHcAllocMemBlock (Pool, USBHC_MEM_DEFAULT_PAGES);
if (Pool->Head == NULL) {
gBS->FreePool (Pool);
Pool = NULL;
}
return Pool;
}
/**
Release the memory management pool.
@param Pool The USB memory pool to free.
@retval EFI_SUCCESS The memory pool is freed.
@retval EFI_DEVICE_ERROR Failed to free the memory pool.
**/
EFI_STATUS
UsbHcFreeMemPool (
IN USBHC_MEM_POOL *Pool
)
{
USBHC_MEM_BLOCK *Block;
ASSERT (Pool->Head != NULL);
//
// Unlink all the memory blocks from the pool, then free them.
// UsbHcUnlinkMemBlock can't be used to unlink and free the
// first block.
//
for (Block = Pool->Head->Next; Block != NULL; Block = Pool->Head->Next) {
UsbHcUnlinkMemBlock (Pool->Head, Block);
UsbHcFreeMemBlock (Pool, Block);
}
UsbHcFreeMemBlock (Pool, Pool->Head);
gBS->FreePool (Pool);
return EFI_SUCCESS;
}
/**
Allocate some memory from the host controller's memory pool
which can be used to communicate with host controller.
@param Pool The host controller's memory pool.
@param Size Size of the memory to allocate.
@return The allocated memory or NULL.
**/
VOID *
UsbHcAllocateMem (
IN USBHC_MEM_POOL *Pool,
IN UINTN Size
)
{
USBHC_MEM_BLOCK *Head;
USBHC_MEM_BLOCK *Block;
USBHC_MEM_BLOCK *NewBlock;
VOID *Mem;
UINTN AllocSize;
UINTN Pages;
Mem = NULL;
AllocSize = USBHC_MEM_ROUND (Size);
Head = Pool->Head;
ASSERT (Head != NULL);
//
// First check whether current memory blocks can satisfy the allocation.
//
for (Block = Head; Block != NULL; Block = Block->Next) {
Mem = UsbHcAllocMemFromBlock (Block, AllocSize / USBHC_MEM_UNIT);
if (Mem != NULL) {
ZeroMem (Mem, Size);
break;
}
}
if (Mem != NULL) {
return Mem;
}
//
// Create a new memory block if there is not enough memory
// in the pool. If the allocation size is larger than the
// default page number, just allocate a large enough memory
// block. Otherwise allocate default pages.
//
if (AllocSize > EFI_PAGES_TO_SIZE (USBHC_MEM_DEFAULT_PAGES)) {
Pages = EFI_SIZE_TO_PAGES (AllocSize) + 1;
} else {
Pages = USBHC_MEM_DEFAULT_PAGES;
}
NewBlock = UsbHcAllocMemBlock (Pool, Pages);
if (NewBlock == NULL) {
DEBUG ((EFI_D_ERROR, "UsbHcAllocateMem: failed to allocate block\n"));
return NULL;
}
//
// Add the new memory block to the pool, then allocate memory from it
//
UsbHcInsertMemBlockToPool (Head, NewBlock);
Mem = UsbHcAllocMemFromBlock (NewBlock, AllocSize / USBHC_MEM_UNIT);
if (Mem != NULL) {
ZeroMem (Mem, Size);
}
return Mem;
}
/**
Free the allocated memory back to the memory pool.
@param Pool The memory pool of the host controller.
@param Mem The memory to free.
@param Size The size of the memory to free.
**/
VOID
UsbHcFreeMem (
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
)
{
USBHC_MEM_BLOCK *Head;
USBHC_MEM_BLOCK *Block;
UINT8 *ToFree;
UINTN AllocSize;
UINTN Byte;
UINTN Bit;
UINTN Count;
Head = Pool->Head;
AllocSize = USBHC_MEM_ROUND (Size);
ToFree = (UINT8 *) Mem;
for (Block = Head; Block != NULL; Block = Block->Next) {
//
// scan the memory block list for the memory block that
// completely contains the memory to free.
//
if ((Block->BufHost <= ToFree) && ((ToFree + AllocSize) <= (Block->BufHost + Block->BufLen))) {
//
// compute the start byte and bit in the bit array
//
Byte = ((ToFree - Block->BufHost) / USBHC_MEM_UNIT) / 8;
Bit = ((ToFree - Block->BufHost) / USBHC_MEM_UNIT) % 8;
//
// reset associated bits in bit arry
//
for (Count = 0; Count < (AllocSize / USBHC_MEM_UNIT); Count++) {
ASSERT (USB_HC_BIT_IS_SET (Block->Bits[Byte], Bit));
Block->Bits[Byte] = (UINT8) (Block->Bits[Byte] ^ USB_HC_BIT (Bit));
NEXT_BIT (Byte, Bit);
}
break;
}
}
//
// If Block == NULL, it means that the current memory isn't
// in the host controller's pool. This is critical because
// the caller has passed in a wrong memory point
//
ASSERT (Block != NULL);
//
// Release the current memory block if it is empty and not the head
//
if ((Block != Head) && UsbHcIsMemBlockEmpty (Block)) {
UsbHcUnlinkMemBlock (Head, Block);
UsbHcFreeMemBlock (Pool, Block);
}
return ;
}
/**
Allocates pages at a specified alignment that are suitable for an EfiPciIoOperationBusMasterCommonBuffer mapping.
If Alignment is not a power of two and Alignment is not zero, then ASSERT().
@param PciIo The PciIo that can be used to access the host controller.
@param Pages The number of pages to allocate.
@param Alignment The requested alignment of the allocation. Must be a power of two.
@param HostAddress The system memory address to map to the PCI controller.
@param DeviceAddress The resulting map address for the bus master PCI controller to
use to access the hosts HostAddress.
@param Mapping A resulting value to pass to Unmap().
@retval EFI_SUCCESS Success to allocate aligned pages.
@retval EFI_INVALID_PARAMETER Pages or Alignment is not valid.
@retval EFI_OUT_OF_RESOURCES Do not have enough resources to allocate memory.
**/
EFI_STATUS
UsbHcAllocateAlignedPages (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINTN Pages,
IN UINTN Alignment,
OUT VOID **HostAddress,
OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
OUT VOID **Mapping
)
{
EFI_STATUS Status;
VOID *Memory;
UINTN AlignedMemory;
UINTN AlignmentMask;
UINTN UnalignedPages;
UINTN RealPages;
UINTN Bytes;
//
// Alignment must be a power of two or zero.
//
ASSERT ((Alignment & (Alignment - 1)) == 0);
if ((Alignment & (Alignment - 1)) != 0) {
return EFI_INVALID_PARAMETER;
}
if (Pages == 0) {
return EFI_INVALID_PARAMETER;
}
if (Alignment > EFI_PAGE_SIZE) {
//
// Caculate the total number of pages since alignment is larger than page size.
//
AlignmentMask = Alignment - 1;
RealPages = Pages + EFI_SIZE_TO_PAGES (Alignment);
//
// Make sure that Pages plus EFI_SIZE_TO_PAGES (Alignment) does not overflow.
//
ASSERT (RealPages > Pages);
Status = PciIo->AllocateBuffer (
PciIo,
AllocateAnyPages,
EfiBootServicesData,
Pages,
&Memory,
0
);
if (EFI_ERROR (Status)) {
return EFI_OUT_OF_RESOURCES;
}
AlignedMemory = ((UINTN) Memory + AlignmentMask) & ~AlignmentMask;
UnalignedPages = EFI_SIZE_TO_PAGES (AlignedMemory - (UINTN) Memory);
if (UnalignedPages > 0) {
//
// Free first unaligned page(s).
//
Status = PciIo->FreeBuffer (PciIo, UnalignedPages, Memory);
ASSERT_EFI_ERROR (Status);
}
Memory = (VOID *)(UINTN)(AlignedMemory + EFI_PAGES_TO_SIZE (Pages));
UnalignedPages = RealPages - Pages - UnalignedPages;
if (UnalignedPages > 0) {
//
// Free last unaligned page(s).
//
Status = PciIo->FreeBuffer (PciIo, UnalignedPages, Memory);
ASSERT_EFI_ERROR (Status);
}
} else {
//
// Do not over-allocate pages in this case.
//
Status = PciIo->AllocateBuffer (
PciIo,
AllocateAnyPages,
EfiBootServicesData,
Pages,
&Memory,
0
);
if (EFI_ERROR (Status)) {
return EFI_OUT_OF_RESOURCES;
}
AlignedMemory = (UINTN) Memory;
}
Bytes = EFI_PAGES_TO_SIZE (Pages);
Status = PciIo->Map (
PciIo,
EfiPciIoOperationBusMasterCommonBuffer,
(VOID *) AlignedMemory,
&Bytes,
DeviceAddress,
Mapping
);
if (EFI_ERROR (Status) || (Bytes != EFI_PAGES_TO_SIZE (Pages))) {
Status = PciIo->FreeBuffer (PciIo, Pages, (VOID *) AlignedMemory);
return EFI_OUT_OF_RESOURCES;
}
*HostAddress = (VOID *) AlignedMemory;
return EFI_SUCCESS;
}
/**
Frees memory that was allocated with UsbHcAllocateAlignedPages().
@param PciIo The PciIo that can be used to access the host controller.
@param HostAddress The system memory address to map to the PCI controller.
@param Pages The number of 4 KB pages to free.
@param Mapping The mapping value returned from Map().
**/
VOID
UsbHcFreeAlignedPages (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN VOID *HostAddress,
IN UINTN Pages,
VOID *Mapping
)
{
EFI_STATUS Status;
ASSERT (Pages != 0);
Status = PciIo->Unmap (PciIo, Mapping);
ASSERT_EFI_ERROR (Status);
Status = PciIo->FreeBuffer (
PciIo,
Pages,
HostAddress
);
ASSERT_EFI_ERROR (Status);
}

213
MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.h Normal file
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@ -0,0 +1,213 @@
/** @file
This file contains the definination for host controller memory management routines.
Copyright (c) 2013, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _EFI_XHCI_MEM_H_
#define _EFI_XHCI_MEM_H_
#define USB_HC_BIT(a) ((UINTN)(1 << (a)))
#define USB_HC_BIT_IS_SET(Data, Bit) \
((BOOLEAN)(((Data) & USB_HC_BIT(Bit)) == USB_HC_BIT(Bit)))
typedef struct _USBHC_MEM_BLOCK USBHC_MEM_BLOCK;
struct _USBHC_MEM_BLOCK {
UINT8 *Bits; // Bit array to record which unit is allocated
UINTN BitsLen;
UINT8 *Buf;
UINT8 *BufHost;
UINTN BufLen; // Memory size in bytes
VOID *Mapping;
USBHC_MEM_BLOCK *Next;
};
//
// USBHC_MEM_POOL is used to manage the memory used by USB
// host controller. XHCI requires the control memory and transfer
// data to be on the same 4G memory.
//
typedef struct _USBHC_MEM_POOL {
EFI_PCI_IO_PROTOCOL *PciIo;
BOOLEAN Check4G;
UINT32 Which4G;
USBHC_MEM_BLOCK *Head;
} USBHC_MEM_POOL;
//
// Memory allocation unit, must be 2^n, n>4
//
#define USBHC_MEM_UNIT 64
#define USBHC_MEM_UNIT_MASK (USBHC_MEM_UNIT - 1)
#define USBHC_MEM_DEFAULT_PAGES 16
#define USBHC_MEM_ROUND(Len) (((Len) + USBHC_MEM_UNIT_MASK) & (~USBHC_MEM_UNIT_MASK))
//
// Advance the byte and bit to the next bit, adjust byte accordingly.
//
#define NEXT_BIT(Byte, Bit) \
do { \
(Bit)++; \
if ((Bit) > 7) { \
(Byte)++; \
(Bit) = 0; \
} \
} while (0)
/**
Initialize the memory management pool for the host controller.
@param PciIo The PciIo that can be used to access the host controller.
@retval EFI_SUCCESS The memory pool is initialized.
@retval EFI_OUT_OF_RESOURCE Fail to init the memory pool.
**/
USBHC_MEM_POOL *
UsbHcInitMemPool (
IN EFI_PCI_IO_PROTOCOL *PciIo
);
/**
Release the memory management pool.
@param Pool The USB memory pool to free.
@retval EFI_SUCCESS The memory pool is freed.
@retval EFI_DEVICE_ERROR Failed to free the memory pool.
**/
EFI_STATUS
UsbHcFreeMemPool (
IN USBHC_MEM_POOL *Pool
);
/**
Allocate some memory from the host controller's memory pool
which can be used to communicate with host controller.
@param Pool The host controller's memory pool.
@param Size Size of the memory to allocate.
@return The allocated memory or NULL.
**/
VOID *
UsbHcAllocateMem (
IN USBHC_MEM_POOL *Pool,
IN UINTN Size
);
/**
Free the allocated memory back to the memory pool.
@param Pool The memory pool of the host controller.
@param Mem The memory to free.
@param Size The size of the memory to free.
**/
VOID
UsbHcFreeMem (
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
);
/**
Calculate the corresponding pci bus address according to the Mem parameter.
@param Pool The memory pool of the host controller.
@param Mem The pointer to host memory.
@param Size The size of the memory region.
@return The pci memory address
**/
EFI_PHYSICAL_ADDRESS
UsbHcGetPciAddrForHostAddr (
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
);
/**
Calculate the corresponding host address according to the pci address.
@param Pool The memory pool of the host controller.
@param Mem The pointer to pci memory.
@param Size The size of the memory region.
@return The host memory address
**/
EFI_PHYSICAL_ADDRESS
UsbHcGetHostAddrForPciAddr (
IN USBHC_MEM_POOL *Pool,
IN VOID *Mem,
IN UINTN Size
);
/**
Allocates pages at a specified alignment that are suitable for an EfiPciIoOperationBusMasterCommonBuffer mapping.
If Alignment is not a power of two and Alignment is not zero, then ASSERT().
@param PciIo The PciIo that can be used to access the host controller.
@param Pages The number of pages to allocate.
@param Alignment The requested alignment of the allocation. Must be a power of two.
@param HostAddress The system memory address to map to the PCI controller.
@param DeviceAddress The resulting map address for the bus master PCI controller to
use to access the hosts HostAddress.
@param Mapping A resulting value to pass to Unmap().
@retval EFI_SUCCESS Success to allocate aligned pages.
@retval EFI_INVALID_PARAMETER Pages or Alignment is not valid.
@retval EFI_OUT_OF_RESOURCES Do not have enough resources to allocate memory.
**/
EFI_STATUS
UsbHcAllocateAlignedPages (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINTN Pages,
IN UINTN Alignment,
OUT VOID **HostAddress,
OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
OUT VOID **Mapping
);
/**
Frees memory that was allocated with UsbHcAllocateAlignedPages().
@param PciIo The PciIo that can be used to access the host controller.
@param HostAddress The system memory address to map to the PCI controller.
@param Pages The number of pages to free.
@param Mapping The mapping value returned from Map().
**/
VOID
UsbHcFreeAlignedPages (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN VOID *HostAddress,
IN UINTN Pages,
VOID *Mapping
);
#endif

18
MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c
View File

@ -907,6 +907,17 @@ XhcControlTransfer (
goto FREE_URB; goto FREE_URB;
} }
Xhc->PciIo->Flush (Xhc->PciIo);
if (Urb->DataMap != NULL) {
Status = Xhc->PciIo->Unmap (Xhc->PciIo, Urb->DataMap);
ASSERT_EFI_ERROR (Status);
if (EFI_ERROR (Status)) {
Status = EFI_DEVICE_ERROR;
goto FREE_URB;
}
}
// //
// Hook Get_Descriptor request from UsbBus as we need evaluate context and configure endpoint. // Hook Get_Descriptor request from UsbBus as we need evaluate context and configure endpoint.
// Hook Get_Status request form UsbBus as we need trace device attach/detach event happened at hub. // Hook Get_Status request form UsbBus as we need trace device attach/detach event happened at hub.
@ -1185,7 +1196,8 @@ XhcBulkTransfer (
Status = EFI_DEVICE_ERROR; Status = EFI_DEVICE_ERROR;
} }
FreePool (Urb); Xhc->PciIo->Flush (Xhc->PciIo);
XhcFreeUrb (Xhc, Urb);
ON_EXIT: ON_EXIT:
@ -1351,6 +1363,7 @@ XhcAsyncInterruptTransfer (
Status = RingIntTransferDoorBell (Xhc, Urb); Status = RingIntTransferDoorBell (Xhc, Urb);
ON_EXIT: ON_EXIT:
Xhc->PciIo->Flush (Xhc->PciIo);
gBS->RestoreTPL (OldTpl); gBS->RestoreTPL (OldTpl);
return Status; return Status;
@ -1482,7 +1495,8 @@ XhcSyncInterruptTransfer (
Status = EFI_DEVICE_ERROR; Status = EFI_DEVICE_ERROR;
} }
FreePool (Urb); Xhc->PciIo->Flush (Xhc->PciIo);
XhcFreeUrb (Xhc, Urb);
ON_EXIT: ON_EXIT:
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {

6
MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h
View File

@ -40,6 +40,7 @@ typedef struct _USB_DEV_CONTEXT USB_DEV_CONTEXT;
#include "XhciReg.h" #include "XhciReg.h"
#include "XhciSched.h" #include "XhciSched.h"
#include "ComponentName.h" #include "ComponentName.h"
#include "UsbHcMem.h"
// //
// The unit is microsecond, setting it as 1us. // The unit is microsecond, setting it as 1us.
@ -201,6 +202,7 @@ struct _USB_XHCI_INSTANCE {
UINT32 Signature; UINT32 Signature;
EFI_PCI_IO_PROTOCOL *PciIo; EFI_PCI_IO_PROTOCOL *PciIo;
UINT64 OriginalPciAttributes; UINT64 OriginalPciAttributes;
USBHC_MEM_POOL *MemPool;
EFI_USB2_HC_PROTOCOL Usb2Hc; EFI_USB2_HC_PROTOCOL Usb2Hc;
@ -223,10 +225,14 @@ struct _USB_XHCI_INSTANCE {
UINT16 MaxInterrupt; UINT16 MaxInterrupt;
UINT32 PageSize; UINT32 PageSize;
UINT64 *ScratchBuf; UINT64 *ScratchBuf;
VOID *ScratchMap;
UINT32 MaxScratchpadBufs; UINT32 MaxScratchpadBufs;
UINT64 *ScratchEntry;
UINTN *ScratchEntryMap;
UINT32 ExtCapRegBase; UINT32 ExtCapRegBase;
UINT32 UsbLegSupOffset; UINT32 UsbLegSupOffset;
UINT64 *DCBAA; UINT64 *DCBAA;
VOID *DCBAAMap;
UINT32 MaxSlotsEn; UINT32 MaxSlotsEn;
// //
// Cmd Transfer Ring // Cmd Transfer Ring

4
MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
View File

@ -6,7 +6,7 @@
# It implements the interfaces of monitoring the status of all ports and transferring # It implements the interfaces of monitoring the status of all ports and transferring
# Control, Bulk, Interrupt and Isochronous requests to those attached usb LS/FS/HS/SS devices. # Control, Bulk, Interrupt and Isochronous requests to those attached usb LS/FS/HS/SS devices.
# #
# Copyright (c) 2011 - 2012, Intel Corporation. All rights reserved.<BR> # Copyright (c) 2011 - 2013, Intel Corporation. All rights reserved.<BR>
# #
# This program and the accompanying materials # This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License # are licensed and made available under the terms and conditions of the BSD License
@ -42,6 +42,8 @@
Xhci.c Xhci.c
XhciReg.c XhciReg.c
XhciSched.c XhciSched.c
UsbHcMem.c
UsbHcMem.h
ComponentName.c ComponentName.c
ComponentName.h ComponentName.h
Xhci.h Xhci.h

466
MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
View File

@ -109,7 +109,7 @@ XhcCmdTransfer (
Status = EFI_SUCCESS; Status = EFI_SUCCESS;
} }
FreePool (Urb); XhcFreeUrb (Xhc, Urb);
ON_EXIT: ON_EXIT:
return Status; return Status;
@ -180,6 +180,30 @@ XhcCreateUrb (
return Urb; return Urb;
} }
/**
Free an allocated URB.
@param Xhc The XHCI device.
@param Urb The URB to free.
**/
VOID
XhcFreeUrb (
IN USB_XHCI_INSTANCE *Xhc,
IN URB *Urb
)
{
if ((Xhc == NULL) || (Urb == NULL)) {
return;
}
if (Urb->DataMap != NULL) {
Xhc->PciIo->Unmap (Xhc->PciIo, Urb->DataMap);
}
FreePool (Urb);
}
/** /**
Create a transfer TRB. Create a transfer TRB.
@ -204,6 +228,10 @@ XhcCreateTransferTrb (
UINTN TotalLen; UINTN TotalLen;
UINTN Len; UINTN Len;
UINTN TrbNum; UINTN TrbNum;
EFI_PCI_IO_PROTOCOL_OPERATION MapOp;
EFI_PHYSICAL_ADDRESS PhyAddr;
VOID *Map;
EFI_STATUS Status;
SlotId = XhcBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr); SlotId = XhcBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);
if (SlotId == 0) { if (SlotId == 0) {
@ -220,12 +248,31 @@ XhcCreateTransferTrb (
ASSERT (Dci < 32); ASSERT (Dci < 32);
EPRing = (TRANSFER_RING *)(UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]; EPRing = (TRANSFER_RING *)(UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1];
Urb->Ring = EPRing; Urb->Ring = EPRing;
OutputContext = (VOID *)(UINTN)Xhc->DCBAA[SlotId]; OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;
if (Xhc->HcCParams.Data.Csz == 0) { if (Xhc->HcCParams.Data.Csz == 0) {
EPType = (UINT8) ((DEVICE_CONTEXT *)OutputContext)->EP[Dci-1].EPType; EPType = (UINT8) ((DEVICE_CONTEXT *)OutputContext)->EP[Dci-1].EPType;
} else { } else {
EPType = (UINT8) ((DEVICE_CONTEXT_64 *)OutputContext)->EP[Dci-1].EPType; EPType = (UINT8) ((DEVICE_CONTEXT_64 *)OutputContext)->EP[Dci-1].EPType;
} }
if (Urb->Data != NULL) {
if (((UINT8) (Urb->Ep.Direction)) == EfiUsbDataIn) {
MapOp = EfiPciIoOperationBusMasterWrite;
} else {
MapOp = EfiPciIoOperationBusMasterRead;
}
Len = Urb->DataLen;
Status = Xhc->PciIo->Map (Xhc->PciIo, MapOp, Urb->Data, &Len, &PhyAddr, &Map);
if (EFI_ERROR (Status) || (Len != Urb->DataLen)) {
DEBUG ((EFI_D_ERROR, "XhcCreateTransferTrb: Fail to map Urb->Data.\n"));
return EFI_OUT_OF_RESOURCES;
}
Urb->DataPhy = (VOID *) ((UINTN) PhyAddr);
Urb->DataMap = Map;
}
// //
// Construct the TRB // Construct the TRB
@ -267,8 +314,8 @@ XhcCreateTransferTrb (
if (Urb->DataLen > 0) { if (Urb->DataLen > 0) {
XhcSyncTrsRing (Xhc, EPRing); XhcSyncTrsRing (Xhc, EPRing);
TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue; TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
TrbStart->TrbCtrData.TRBPtrLo = XHC_LOW_32BIT(Urb->Data); TrbStart->TrbCtrData.TRBPtrLo = XHC_LOW_32BIT(Urb->DataPhy);
TrbStart->TrbCtrData.TRBPtrHi = XHC_HIGH_32BIT(Urb->Data); TrbStart->TrbCtrData.TRBPtrHi = XHC_HIGH_32BIT(Urb->DataPhy);
TrbStart->TrbCtrData.Lenth = (UINT32) Urb->DataLen; TrbStart->TrbCtrData.Lenth = (UINT32) Urb->DataLen;
TrbStart->TrbCtrData.TDSize = 0; TrbStart->TrbCtrData.TDSize = 0;
TrbStart->TrbCtrData.IntTarget = 0; TrbStart->TrbCtrData.IntTarget = 0;
@ -333,8 +380,8 @@ XhcCreateTransferTrb (
Len = 0x10000; Len = 0x10000;
} }
TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue; TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
TrbStart->TrbNormal.TRBPtrLo = XHC_LOW_32BIT((UINT8 *) Urb->Data + TotalLen); TrbStart->TrbNormal.TRBPtrLo = XHC_LOW_32BIT((UINT8 *) Urb->DataPhy + TotalLen);
TrbStart->TrbNormal.TRBPtrHi = XHC_HIGH_32BIT((UINT8 *) Urb->Data + TotalLen); TrbStart->TrbNormal.TRBPtrHi = XHC_HIGH_32BIT((UINT8 *) Urb->DataPhy + TotalLen);
TrbStart->TrbNormal.Lenth = (UINT32) Len; TrbStart->TrbNormal.Lenth = (UINT32) Len;
TrbStart->TrbNormal.TDSize = 0; TrbStart->TrbNormal.TDSize = 0;
TrbStart->TrbNormal.IntTarget = 0; TrbStart->TrbNormal.IntTarget = 0;
@ -368,8 +415,8 @@ XhcCreateTransferTrb (
Len = 0x10000; Len = 0x10000;
} }
TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue; TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
TrbStart->TrbNormal.TRBPtrLo = XHC_LOW_32BIT((UINT8 *) Urb->Data + TotalLen); TrbStart->TrbNormal.TRBPtrLo = XHC_LOW_32BIT((UINT8 *) Urb->DataPhy + TotalLen);
TrbStart->TrbNormal.TRBPtrHi = XHC_HIGH_32BIT((UINT8 *) Urb->Data + TotalLen); TrbStart->TrbNormal.TRBPtrHi = XHC_HIGH_32BIT((UINT8 *) Urb->DataPhy + TotalLen);
TrbStart->TrbNormal.Lenth = (UINT32) Len; TrbStart->TrbNormal.Lenth = (UINT32) Len;
TrbStart->TrbNormal.TDSize = 0; TrbStart->TrbNormal.TDSize = 0;
TrbStart->TrbNormal.IntTarget = 0; TrbStart->TrbNormal.IntTarget = 0;
@ -412,12 +459,24 @@ XhcInitSched (
) )
{ {
VOID *Dcbaa; VOID *Dcbaa;
EFI_PHYSICAL_ADDRESS DcbaaPhy;
UINT64 CmdRing; UINT64 CmdRing;
EFI_PHYSICAL_ADDRESS CmdRingPhy;
UINTN Entries; UINTN Entries;
UINT32 MaxScratchpadBufs; UINT32 MaxScratchpadBufs;
UINT64 *ScratchBuf; UINT64 *ScratchBuf;
UINT64 *ScratchEntryBuf; EFI_PHYSICAL_ADDRESS ScratchPhy;
UINT64 *ScratchEntry;
EFI_PHYSICAL_ADDRESS ScratchEntryPhy;
UINT32 Index; UINT32 Index;
UINTN *ScratchEntryMap;
EFI_STATUS Status;
//
// Initialize memory management.
//
Xhc->MemPool = UsbHcInitMemPool (Xhc->PciIo);
ASSERT (Xhc->MemPool != NULL);
// //
// Program the Max Device Slots Enabled (MaxSlotsEn) field in the CONFIG register (5.4.7) // Program the Max Device Slots Enabled (MaxSlotsEn) field in the CONFIG register (5.4.7)
@ -434,7 +493,7 @@ XhcInitSched (
// Software shall set Device Context Base Address Array entries for unallocated Device Slots to '0'. // Software shall set Device Context Base Address Array entries for unallocated Device Slots to '0'.
// //
Entries = (Xhc->MaxSlotsEn + 1) * sizeof(UINT64); Entries = (Xhc->MaxSlotsEn + 1) * sizeof(UINT64);
Dcbaa = AllocatePages (EFI_SIZE_TO_PAGES (Entries)); Dcbaa = UsbHcAllocateMem (Xhc->MemPool, Entries);
ASSERT (Dcbaa != NULL); ASSERT (Dcbaa != NULL);
ZeroMem (Dcbaa, Entries); ZeroMem (Dcbaa, Entries);
@ -447,23 +506,57 @@ XhcInitSched (
Xhc->MaxScratchpadBufs = MaxScratchpadBufs; Xhc->MaxScratchpadBufs = MaxScratchpadBufs;
ASSERT (MaxScratchpadBufs <= 1023); ASSERT (MaxScratchpadBufs <= 1023);
if (MaxScratchpadBufs != 0) { if (MaxScratchpadBufs != 0) {
ScratchBuf = AllocateAlignedPages (EFI_SIZE_TO_PAGES (MaxScratchpadBufs * sizeof (UINT64)), Xhc->PageSize); //
ASSERT (ScratchBuf != NULL); // Allocate the buffer to record the Mapping for each scratch buffer in order to Unmap them
//
ScratchEntryMap = AllocateZeroPool (sizeof (UINTN) * MaxScratchpadBufs);
ASSERT (ScratchEntryMap != NULL);
Xhc->ScratchEntryMap = ScratchEntryMap;
//
// Allocate the buffer to record the host address for each entry
//
ScratchEntry = AllocateZeroPool (sizeof (UINT64) * MaxScratchpadBufs);
ASSERT (ScratchEntry != NULL);
Xhc->ScratchEntry = ScratchEntry;
Status = UsbHcAllocateAlignedPages (
Xhc->PciIo,
EFI_SIZE_TO_PAGES (MaxScratchpadBufs * sizeof (UINT64)),
Xhc->PageSize,
(VOID **) &ScratchBuf,
&ScratchPhy,
&Xhc->ScratchMap
);
ASSERT_EFI_ERROR (Status);
ZeroMem (ScratchBuf, MaxScratchpadBufs * sizeof (UINT64)); ZeroMem (ScratchBuf, MaxScratchpadBufs * sizeof (UINT64));
Xhc->ScratchBuf = ScratchBuf; Xhc->ScratchBuf = ScratchBuf;
//
// Allocate each scratch buffer
//
for (Index = 0; Index < MaxScratchpadBufs; Index++) { for (Index = 0; Index < MaxScratchpadBufs; Index++) {
ScratchEntryBuf = AllocateAlignedPages (EFI_SIZE_TO_PAGES (Xhc->PageSize), Xhc->PageSize); Status = UsbHcAllocateAlignedPages (
ASSERT (ScratchEntryBuf != NULL); Xhc->PciIo,
ZeroMem (ScratchEntryBuf, Xhc->PageSize); EFI_SIZE_TO_PAGES (Xhc->PageSize),
*ScratchBuf++ = (UINT64)(UINTN)ScratchEntryBuf; Xhc->PageSize,
(VOID **) &ScratchEntry[Index],
&ScratchEntryPhy,
(VOID **) &ScratchEntryMap[Index]
);
ASSERT_EFI_ERROR (Status);
ZeroMem ((VOID *)(UINTN)ScratchEntry[Index], Xhc->PageSize);
//
// Fill with the PCI device address
//
*ScratchBuf++ = ScratchEntryPhy;
} }
// //
// The Scratchpad Buffer Array contains pointers to the Scratchpad Buffers. Entry 0 of the // The Scratchpad Buffer Array contains pointers to the Scratchpad Buffers. Entry 0 of the
// Device Context Base Address Array points to the Scratchpad Buffer Array. // Device Context Base Address Array points to the Scratchpad Buffer Array.
// //
*(UINT64 *)Dcbaa = (UINT64)(UINTN)Xhc->ScratchBuf; *(UINT64 *)Dcbaa = (UINT64)(UINTN) ScratchPhy;
} }
// //
@ -475,8 +568,10 @@ XhcInitSched (
// Some 3rd party XHCI external cards don't support single 64-bytes width register access, // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
// So divide it to two 32-bytes width register access. // So divide it to two 32-bytes width register access.
// //
XhcWriteOpReg (Xhc, XHC_DCBAAP_OFFSET, XHC_LOW_32BIT(Xhc->DCBAA)); DcbaaPhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Dcbaa, Entries);
XhcWriteOpReg (Xhc, XHC_DCBAAP_OFFSET + 4, XHC_HIGH_32BIT (Xhc->DCBAA)); XhcWriteOpReg (Xhc, XHC_DCBAAP_OFFSET, XHC_LOW_32BIT(DcbaaPhy));
XhcWriteOpReg (Xhc, XHC_DCBAAP_OFFSET + 4, XHC_HIGH_32BIT (DcbaaPhy));
DEBUG ((EFI_D_INFO, "XhcInitSched:DCBAA=0x%x\n", (UINT64)(UINTN)Xhc->DCBAA)); DEBUG ((EFI_D_INFO, "XhcInitSched:DCBAA=0x%x\n", (UINT64)(UINTN)Xhc->DCBAA));
// //
@ -492,14 +587,15 @@ XhcInitSched (
// So we set RCS as inverted PCS init value to let Command Ring empty // So we set RCS as inverted PCS init value to let Command Ring empty
// //
CmdRing = (UINT64)(UINTN)Xhc->CmdRing.RingSeg0; CmdRing = (UINT64)(UINTN)Xhc->CmdRing.RingSeg0;
ASSERT ((CmdRing & 0x3F) == 0); CmdRingPhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, (VOID *)(UINTN) CmdRing, sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER);
CmdRing |= XHC_CRCR_RCS; ASSERT ((CmdRingPhy & 0x3F) == 0);
CmdRingPhy |= XHC_CRCR_RCS;
// //
// Some 3rd party XHCI external cards don't support single 64-bytes width register access, // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
// So divide it to two 32-bytes width register access. // So divide it to two 32-bytes width register access.
// //
XhcWriteOpReg (Xhc, XHC_CRCR_OFFSET, XHC_LOW_32BIT(CmdRing)); XhcWriteOpReg (Xhc, XHC_CRCR_OFFSET, XHC_LOW_32BIT(CmdRingPhy));
XhcWriteOpReg (Xhc, XHC_CRCR_OFFSET + 4, XHC_HIGH_32BIT (CmdRing)); XhcWriteOpReg (Xhc, XHC_CRCR_OFFSET + 4, XHC_HIGH_32BIT (CmdRingPhy));
DEBUG ((EFI_D_INFO, "XhcInitSched:XHC_CRCR=0x%x\n", Xhc->CmdRing.RingSeg0)); DEBUG ((EFI_D_INFO, "XhcInitSched:XHC_CRCR=0x%x\n", Xhc->CmdRing.RingSeg0));
@ -547,6 +643,7 @@ XhcRecoverHaltedEndpoint (
CMD_SET_TR_DEQ_POINTER CmdSetTRDeq; CMD_SET_TR_DEQ_POINTER CmdSetTRDeq;
UINT8 Dci; UINT8 Dci;
UINT8 SlotId; UINT8 SlotId;
EFI_PHYSICAL_ADDRESS PhyAddr;
Status = EFI_SUCCESS; Status = EFI_SUCCESS;
SlotId = XhcBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr); SlotId = XhcBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);
@ -578,8 +675,9 @@ XhcRecoverHaltedEndpoint (
// 2)Set dequeue pointer // 2)Set dequeue pointer
// //
ZeroMem (&CmdSetTRDeq, sizeof (CmdSetTRDeq)); ZeroMem (&CmdSetTRDeq, sizeof (CmdSetTRDeq));
CmdSetTRDeq.PtrLo = XHC_LOW_32BIT (Urb->Ring->RingEnqueue) | Urb->Ring->RingPCS; PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Urb->Ring->RingEnqueue, sizeof (CMD_SET_TR_DEQ_POINTER));
CmdSetTRDeq.PtrHi = XHC_HIGH_32BIT (Urb->Ring->RingEnqueue); CmdSetTRDeq.PtrLo = XHC_LOW_32BIT (PhyAddr) | Urb->Ring->RingPCS;
CmdSetTRDeq.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdSetTRDeq.CycleBit = 1; CmdSetTRDeq.CycleBit = 1;
CmdSetTRDeq.Type = TRB_TYPE_SET_TR_DEQUE; CmdSetTRDeq.Type = TRB_TYPE_SET_TR_DEQUE;
CmdSetTRDeq.Endpoint = Dci; CmdSetTRDeq.Endpoint = Dci;
@ -615,35 +713,45 @@ CreateEventRing (
{ {
VOID *Buf; VOID *Buf;
EVENT_RING_SEG_TABLE_ENTRY *ERSTBase; EVENT_RING_SEG_TABLE_ENTRY *ERSTBase;
UINTN Size;
EFI_PHYSICAL_ADDRESS ERSTPhy;
EFI_PHYSICAL_ADDRESS DequeuePhy;
ASSERT (EventRing != NULL); ASSERT (EventRing != NULL);
Buf = AllocatePages (EFI_SIZE_TO_PAGES (sizeof (TRB_TEMPLATE) * EVENT_RING_TRB_NUMBER)); Size = sizeof (TRB_TEMPLATE) * EVENT_RING_TRB_NUMBER;
Buf = UsbHcAllocateMem (Xhc->MemPool, Size);
ASSERT (Buf != NULL); ASSERT (Buf != NULL);
ASSERT (((UINTN) Buf & 0x3F) == 0); ASSERT (((UINTN) Buf & 0x3F) == 0);
ZeroMem (Buf, sizeof (TRB_TEMPLATE) * EVENT_RING_TRB_NUMBER); ZeroMem (Buf, Size);
EventRing->EventRingSeg0 = Buf; EventRing->EventRingSeg0 = Buf;
EventRing->TrbNumber = EVENT_RING_TRB_NUMBER; EventRing->TrbNumber = EVENT_RING_TRB_NUMBER;
EventRing->EventRingDequeue = (TRB_TEMPLATE *) EventRing->EventRingSeg0; EventRing->EventRingDequeue = (TRB_TEMPLATE *) EventRing->EventRingSeg0;
EventRing->EventRingEnqueue = (TRB_TEMPLATE *) EventRing->EventRingSeg0; EventRing->EventRingEnqueue = (TRB_TEMPLATE *) EventRing->EventRingSeg0;
DequeuePhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, Size);
// //
// Software maintains an Event Ring Consumer Cycle State (CCS) bit, initializing it to '1' // Software maintains an Event Ring Consumer Cycle State (CCS) bit, initializing it to '1'
// and toggling it every time the Event Ring Dequeue Pointer wraps back to the beginning of the Event Ring. // and toggling it every time the Event Ring Dequeue Pointer wraps back to the beginning of the Event Ring.
// //
EventRing->EventRingCCS = 1; EventRing->EventRingCCS = 1;
Buf = AllocatePages (EFI_SIZE_TO_PAGES (sizeof (EVENT_RING_SEG_TABLE_ENTRY) * ERST_NUMBER)); Size = EFI_SIZE_TO_PAGES (sizeof (EVENT_RING_SEG_TABLE_ENTRY) * ERST_NUMBER);
Buf = UsbHcAllocateMem (Xhc->MemPool, Size);
ASSERT (Buf != NULL); ASSERT (Buf != NULL);
ASSERT (((UINTN) Buf & 0x3F) == 0); ASSERT (((UINTN) Buf & 0x3F) == 0);
ZeroMem (Buf, sizeof (EVENT_RING_SEG_TABLE_ENTRY) * ERST_NUMBER); ZeroMem (Buf, Size);
ERSTBase = (EVENT_RING_SEG_TABLE_ENTRY *) Buf; ERSTBase = (EVENT_RING_SEG_TABLE_ENTRY *) Buf;
EventRing->ERSTBase = ERSTBase; EventRing->ERSTBase = ERSTBase;
ERSTBase->PtrLo = XHC_LOW_32BIT (EventRing->EventRingSeg0); ERSTBase->PtrLo = XHC_LOW_32BIT (DequeuePhy);
ERSTBase->PtrHi = XHC_HIGH_32BIT (EventRing->EventRingSeg0); ERSTBase->PtrHi = XHC_HIGH_32BIT (DequeuePhy);
ERSTBase->RingTrbSize = EVENT_RING_TRB_NUMBER; ERSTBase->RingTrbSize = EVENT_RING_TRB_NUMBER;
ERSTPhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, ERSTBase, Size);
// //
// Program the Interrupter Event Ring Segment Table Size (ERSTSZ) register (5.5.2.3.1) // Program the Interrupter Event Ring Segment Table Size (ERSTSZ) register (5.5.2.3.1)
// //
@ -661,12 +769,12 @@ CreateEventRing (
XhcWriteRuntimeReg ( XhcWriteRuntimeReg (
Xhc, Xhc,
XHC_ERDP_OFFSET, XHC_ERDP_OFFSET,
XHC_LOW_32BIT((UINT64)(UINTN)EventRing->EventRingDequeue) XHC_LOW_32BIT((UINT64)(UINTN)DequeuePhy)
); );
XhcWriteRuntimeReg ( XhcWriteRuntimeReg (
Xhc, Xhc,
XHC_ERDP_OFFSET + 4, XHC_ERDP_OFFSET + 4,
XHC_HIGH_32BIT((UINT64)(UINTN)EventRing->EventRingDequeue) XHC_HIGH_32BIT((UINT64)(UINTN)DequeuePhy)
); );
// //
// Program the Interrupter Event Ring Segment Table Base Address (ERSTBA) register(5.5.2.3.2) // Program the Interrupter Event Ring Segment Table Base Address (ERSTBA) register(5.5.2.3.2)
@ -677,12 +785,12 @@ CreateEventRing (
XhcWriteRuntimeReg ( XhcWriteRuntimeReg (
Xhc, Xhc,
XHC_ERSTBA_OFFSET, XHC_ERSTBA_OFFSET,
XHC_LOW_32BIT((UINT64)(UINTN)ERSTBase) XHC_LOW_32BIT((UINT64)(UINTN)ERSTPhy)
); );
XhcWriteRuntimeReg ( XhcWriteRuntimeReg (
Xhc, Xhc,
XHC_ERSTBA_OFFSET + 4, XHC_ERSTBA_OFFSET + 4,
XHC_HIGH_32BIT((UINT64)(UINTN)ERSTBase) XHC_HIGH_32BIT((UINT64)(UINTN)ERSTPhy)
); );
// //
// Need set IMAN IE bit to enble the ring interrupt // Need set IMAN IE bit to enble the ring interrupt
@ -707,8 +815,9 @@ CreateTransferRing (
{ {
VOID *Buf; VOID *Buf;
LINK_TRB *EndTrb; LINK_TRB *EndTrb;
EFI_PHYSICAL_ADDRESS PhyAddr;
Buf = AllocatePages (EFI_SIZE_TO_PAGES (sizeof (TRB_TEMPLATE) * TrbNum)); Buf = UsbHcAllocateMem (Xhc->MemPool, sizeof (TRB_TEMPLATE) * TrbNum);
ASSERT (Buf != NULL); ASSERT (Buf != NULL);
ASSERT (((UINTN) Buf & 0x3F) == 0); ASSERT (((UINTN) Buf & 0x3F) == 0);
ZeroMem (Buf, sizeof (TRB_TEMPLATE) * TrbNum); ZeroMem (Buf, sizeof (TRB_TEMPLATE) * TrbNum);
@ -725,8 +834,9 @@ CreateTransferRing (
// //
EndTrb = (LINK_TRB *) ((UINTN)Buf + sizeof (TRB_TEMPLATE) * (TrbNum - 1)); EndTrb = (LINK_TRB *) ((UINTN)Buf + sizeof (TRB_TEMPLATE) * (TrbNum - 1));
EndTrb->Type = TRB_TYPE_LINK; EndTrb->Type = TRB_TYPE_LINK;
EndTrb->PtrLo = XHC_LOW_32BIT (Buf); PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, sizeof (TRB_TEMPLATE) * TrbNum);
EndTrb->PtrHi = XHC_HIGH_32BIT (Buf); EndTrb->PtrLo = XHC_LOW_32BIT (PhyAddr);
EndTrb->PtrHi = XHC_HIGH_32BIT (PhyAddr);
// //
// Toggle Cycle (TC). When set to '1', the xHC shall toggle its interpretation of the Cycle bit. // Toggle Cycle (TC). When set to '1', the xHC shall toggle its interpretation of the Cycle bit.
// //
@ -751,34 +861,19 @@ XhcFreeEventRing (
IN EVENT_RING *EventRing IN EVENT_RING *EventRing
) )
{ {
UINT8 Index;
EVENT_RING_SEG_TABLE_ENTRY *TablePtr;
VOID *RingBuf;
EVENT_RING_SEG_TABLE_ENTRY *EventRingPtr;
if(EventRing->EventRingSeg0 == NULL) { if(EventRing->EventRingSeg0 == NULL) {
return EFI_SUCCESS; return EFI_SUCCESS;
} }
// //
// Get the Event Ring Segment Table base address // Free EventRing Segment 0
// //
TablePtr = (EVENT_RING_SEG_TABLE_ENTRY *)(EventRing->ERSTBase); UsbHcFreeMem (Xhc->MemPool, EventRing->EventRingSeg0, sizeof (TRB_TEMPLATE) * EVENT_RING_TRB_NUMBER);
// //
// Get all the TRBs Ring and release // Free ESRT table
// //
for (Index = 0; Index < ERST_NUMBER; Index++) { UsbHcFreeMem (Xhc->MemPool, EventRing->ERSTBase, sizeof (EVENT_RING_SEG_TABLE_ENTRY) * ERST_NUMBER);
EventRingPtr = TablePtr + Index;
RingBuf = (VOID *)(UINTN)(EventRingPtr->PtrLo | LShiftU64 ((UINT64)EventRingPtr->PtrHi, 32));
if(RingBuf != NULL) {
FreePages (RingBuf, EFI_SIZE_TO_PAGES (sizeof (TRB_TEMPLATE) * EVENT_RING_TRB_NUMBER));
ZeroMem (EventRingPtr, sizeof (EVENT_RING_SEG_TABLE_ENTRY));
}
}
FreePages (TablePtr, EFI_SIZE_TO_PAGES (sizeof (EVENT_RING_SEG_TABLE_ENTRY) * ERST_NUMBER));
return EFI_SUCCESS; return EFI_SUCCESS;
} }
@ -793,28 +888,44 @@ XhcFreeSched (
IN USB_XHCI_INSTANCE *Xhc IN USB_XHCI_INSTANCE *Xhc
) )
{ {
UINT32 Index; UINT32 Index;
UINT64 *ScratchBuf; UINT64 *ScratchEntry;
if (Xhc->ScratchBuf != NULL) { if (Xhc->ScratchBuf != NULL) {
ScratchBuf = Xhc->ScratchBuf; ScratchEntry = Xhc->ScratchEntry;
for (Index = 0; Index < Xhc->MaxScratchpadBufs; Index++) { for (Index = 0; Index < Xhc->MaxScratchpadBufs; Index++) {
FreeAlignedPages ((VOID*)(UINTN)*ScratchBuf++, EFI_SIZE_TO_PAGES (Xhc->PageSize)); //
// Free Scratchpad Buffers
//
UsbHcFreeAlignedPages (Xhc->PciIo, (VOID*)(UINTN)ScratchEntry[Index], EFI_SIZE_TO_PAGES (Xhc->PageSize), (VOID *) Xhc->ScratchEntryMap[Index]);
} }
FreeAlignedPages (Xhc->ScratchBuf, EFI_SIZE_TO_PAGES (Xhc->MaxScratchpadBufs * sizeof (UINT64))); //
// Free Scratchpad Buffer Array
//
UsbHcFreeAlignedPages (Xhc->PciIo, Xhc->ScratchBuf, EFI_SIZE_TO_PAGES (Xhc->MaxScratchpadBufs * sizeof (UINT64)), Xhc->ScratchMap);
FreePool (Xhc->ScratchEntryMap);
FreePool (Xhc->ScratchEntry);
} }
if (Xhc->DCBAA != NULL) { if (Xhc->CmdRing.RingSeg0 != NULL) {
FreePages (Xhc->DCBAA, EFI_SIZE_TO_PAGES((Xhc->MaxSlotsEn + 1) * sizeof(UINT64))); UsbHcFreeMem (Xhc->MemPool, Xhc->CmdRing.RingSeg0, sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER);
Xhc->DCBAA = NULL;
}
if (Xhc->CmdRing.RingSeg0 != NULL){
FreePages (Xhc->CmdRing.RingSeg0, EFI_SIZE_TO_PAGES (sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER));
Xhc->CmdRing.RingSeg0 = NULL; Xhc->CmdRing.RingSeg0 = NULL;
} }
XhcFreeEventRing (Xhc,&Xhc->EventRing); XhcFreeEventRing (Xhc,&Xhc->EventRing);
if (Xhc->DCBAA != NULL) {
UsbHcFreeMem (Xhc->MemPool, Xhc->DCBAA, (Xhc->MaxSlotsEn + 1) * sizeof(UINT64));
Xhc->DCBAA = NULL;
}
//
// Free memory pool at last
//
if (Xhc->MemPool != NULL) {
UsbHcFreeMemPool (Xhc->MemPool);
Xhc->MemPool = NULL;
}
} }
/** /**
@ -918,6 +1029,7 @@ XhcCheckUrbResult (
UINT64 XhcDequeue; UINT64 XhcDequeue;
UINT32 High; UINT32 High;
UINT32 Low; UINT32 Low;
EFI_PHYSICAL_ADDRESS PhyAddr;
ASSERT ((Xhc != NULL) && (Urb != NULL)); ASSERT ((Xhc != NULL) && (Urb != NULL));
@ -955,8 +1067,12 @@ XhcCheckUrbResult (
if ((EvtTrb->Type != TRB_TYPE_COMMAND_COMPLT_EVENT) && (EvtTrb->Type != TRB_TYPE_TRANS_EVENT)) { if ((EvtTrb->Type != TRB_TYPE_COMMAND_COMPLT_EVENT) && (EvtTrb->Type != TRB_TYPE_TRANS_EVENT)) {
continue; continue;
} }
TRBPtr = (TRB_TEMPLATE *)(UINTN)(EvtTrb->TRBPtrLo | LShiftU64 ((UINT64) EvtTrb->TRBPtrHi, 32)); //
// Need convert pci device address to host address
//
PhyAddr = (EFI_PHYSICAL_ADDRESS)(EvtTrb->TRBPtrLo | LShiftU64 ((UINT64) EvtTrb->TRBPtrHi, 32));
TRBPtr = (TRB_TEMPLATE *)(UINTN) UsbHcGetHostAddrForPciAddr (Xhc->MemPool, (VOID *)(UINTN) PhyAddr, sizeof (TRB_TEMPLATE));
// //
// Update the status of Urb according to the finished event regardless of whether // Update the status of Urb according to the finished event regardless of whether
@ -1048,13 +1164,15 @@ EXIT:
High = XhcReadRuntimeReg (Xhc, XHC_ERDP_OFFSET + 4); High = XhcReadRuntimeReg (Xhc, XHC_ERDP_OFFSET + 4);
XhcDequeue = (UINT64)(LShiftU64((UINT64)High, 32) | Low); XhcDequeue = (UINT64)(LShiftU64((UINT64)High, 32) | Low);
if ((XhcDequeue & (~0x0F)) != ((UINT64)(UINTN)Xhc->EventRing.EventRingDequeue & (~0x0F))) { PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->EventRing.EventRingDequeue, sizeof (TRB_TEMPLATE));
if ((XhcDequeue & (~0x0F)) != (PhyAddr & (~0x0F))) {
// //
// Some 3rd party XHCI external cards don't support single 64-bytes width register access, // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
// So divide it to two 32-bytes width register access. // So divide it to two 32-bytes width register access.
// //
XhcWriteRuntimeReg (Xhc, XHC_ERDP_OFFSET, XHC_LOW_32BIT (Xhc->EventRing.EventRingDequeue) | BIT3); XhcWriteRuntimeReg (Xhc, XHC_ERDP_OFFSET, XHC_LOW_32BIT (PhyAddr) | BIT3);
XhcWriteRuntimeReg (Xhc, XHC_ERDP_OFFSET + 4, XHC_HIGH_32BIT (Xhc->EventRing.EventRingDequeue)); XhcWriteRuntimeReg (Xhc, XHC_ERDP_OFFSET + 4, XHC_HIGH_32BIT (PhyAddr));
} }
return Status; return Status;
@ -1159,7 +1277,7 @@ XhciDelAsyncIntTransfer (
(Urb->Ep.Direction == Direction)) { (Urb->Ep.Direction == Direction)) {
RemoveEntryList (&Urb->UrbList); RemoveEntryList (&Urb->UrbList);
FreePool (Urb->Data); FreePool (Urb->Data);
FreePool (Urb); XhcFreeUrb (Xhc, Urb);
return EFI_SUCCESS; return EFI_SUCCESS;
} }
} }
@ -1186,7 +1304,7 @@ XhciDelAllAsyncIntTransfers (
Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList); Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);
RemoveEntryList (&Urb->UrbList); RemoveEntryList (&Urb->UrbList);
FreePool (Urb->Data); FreePool (Urb->Data);
FreePool (Urb); XhcFreeUrb (Xhc, Urb);
} }
} }
@ -1217,6 +1335,60 @@ XhcUpdateAsyncRequest (
} }
} }
/**
Flush data from PCI controller specific address to mapped system
memory address.
@param Xhc The XHCI device.
@param Urb The URB to unmap.
@retval EFI_SUCCESS Success to flush data to mapped system memory.
@retval EFI_DEVICE_ERROR Fail to flush data to mapped system memory.
**/
EFI_STATUS
XhcFlushAsyncIntMap (
IN USB_XHCI_INSTANCE *Xhc,
IN URB *Urb
)
{
EFI_STATUS Status;
EFI_PHYSICAL_ADDRESS PhyAddr;
EFI_PCI_IO_PROTOCOL_OPERATION MapOp;
EFI_PCI_IO_PROTOCOL *PciIo;
UINTN Len;
VOID *Map;
PciIo = Xhc->PciIo;
Len = Urb->DataLen;
if (Urb->Ep.Direction == EfiUsbDataIn) {
MapOp = EfiPciIoOperationBusMasterWrite;
} else {
MapOp = EfiPciIoOperationBusMasterRead;
}
if (Urb->DataMap != NULL) {
Status = PciIo->Unmap (PciIo, Urb->DataMap);
if (EFI_ERROR (Status)) {
goto ON_ERROR;
}
}
Urb->DataMap = NULL;
Status = PciIo->Map (PciIo, MapOp, Urb->Data, &Len, &PhyAddr, &Map);
if (EFI_ERROR (Status) || (Len != Urb->DataLen)) {
goto ON_ERROR;
}
Urb->DataPhy = (VOID *) ((UINTN) PhyAddr);
Urb->DataMap = Map;
return EFI_SUCCESS;
ON_ERROR:
return EFI_DEVICE_ERROR;
}
/** /**
Interrupt transfer periodic check handler. Interrupt transfer periodic check handler.
@ -1238,6 +1410,7 @@ XhcMonitorAsyncRequests (
UINT8 *ProcBuf; UINT8 *ProcBuf;
URB *Urb; URB *Urb;
UINT8 SlotId; UINT8 SlotId;
EFI_STATUS Status;
EFI_TPL OldTpl; EFI_TPL OldTpl;
OldTpl = gBS->RaiseTPL (XHC_TPL); OldTpl = gBS->RaiseTPL (XHC_TPL);
@ -1265,6 +1438,15 @@ XhcMonitorAsyncRequests (
continue; continue;
} }
//
// Flush any PCI posted write transactions from a PCI host
// bridge to system memory.
//
Status = XhcFlushAsyncIntMap (Xhc, Urb);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcMonitorAsyncRequests: Fail to Flush AsyncInt Mapped Memeory\n"));
}
// //
// Allocate a buffer then copy the transferred data for user. // Allocate a buffer then copy the transferred data for user.
// If failed to allocate the buffer, update the URB for next // If failed to allocate the buffer, update the URB for next
@ -1582,7 +1764,7 @@ XhcSyncTrsRing (
// Toggle PCS maintained by software // Toggle PCS maintained by software
// //
TrsRing->RingPCS = (TrsRing->RingPCS & BIT0) ? 0 : 1; TrsRing->RingPCS = (TrsRing->RingPCS & BIT0) ? 0 : 1;
TrsTrb = (TRB_TEMPLATE *)(UINTN)((TrsTrb->Parameter1 | LShiftU64 ((UINT64)TrsTrb->Parameter2, 32)) & ~0x0F); TrsTrb = (TRB_TEMPLATE *) TrsRing->RingSeg0; // Use host address
} }
} }
@ -1727,6 +1909,7 @@ XhcInitializeDeviceSlot (
UINT8 SlotId; UINT8 SlotId;
UINT8 ParentSlotId; UINT8 ParentSlotId;
DEVICE_CONTEXT *ParentDeviceContext; DEVICE_CONTEXT *ParentDeviceContext;
EFI_PHYSICAL_ADDRESS PhyAddr;
ZeroMem (&CmdTrb, sizeof (CMD_TRB_ENABLE_SLOT)); ZeroMem (&CmdTrb, sizeof (CMD_TRB_ENABLE_SLOT));
CmdTrb.CycleBit = 1; CmdTrb.CycleBit = 1;
@ -1754,7 +1937,7 @@ XhcInitializeDeviceSlot (
// 4.3.3 Device Slot Initialization // 4.3.3 Device Slot Initialization
// 1) Allocate an Input Context data structure (6.2.5) and initialize all fields to '0'. // 1) Allocate an Input Context data structure (6.2.5) and initialize all fields to '0'.
// //
InputContext = AllocatePages (EFI_SIZE_TO_PAGES (sizeof (INPUT_CONTEXT))); InputContext = UsbHcAllocateMem (Xhc->MemPool, sizeof (INPUT_CONTEXT));
ASSERT (InputContext != NULL); ASSERT (InputContext != NULL);
ASSERT (((UINTN) InputContext & 0x3F) == 0); ASSERT (((UINTN) InputContext & 0x3F) == 0);
ZeroMem (InputContext, sizeof (INPUT_CONTEXT)); ZeroMem (InputContext, sizeof (INPUT_CONTEXT));
@ -1843,13 +2026,18 @@ XhcInitializeDeviceSlot (
// //
// Init the DCS(dequeue cycle state) as the transfer ring's CCS // Init the DCS(dequeue cycle state) as the transfer ring's CCS
// //
InputContext->EP[0].PtrLo = XHC_LOW_32BIT (((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0) | BIT0; PhyAddr = UsbHcGetPciAddrForHostAddr (
InputContext->EP[0].PtrHi = XHC_HIGH_32BIT (((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0); Xhc->MemPool,
((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0,
sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER
);
InputContext->EP[0].PtrLo = XHC_LOW_32BIT (PhyAddr) | BIT0;
InputContext->EP[0].PtrHi = XHC_HIGH_32BIT (PhyAddr);
// //
// 6) Allocate the Output Device Context data structure (6.2.1) and initialize it to '0'. // 6) Allocate the Output Device Context data structure (6.2.1) and initialize it to '0'.
// //
OutputContext = AllocatePages (EFI_SIZE_TO_PAGES (sizeof (DEVICE_CONTEXT))); OutputContext = UsbHcAllocateMem (Xhc->MemPool, sizeof (DEVICE_CONTEXT));
ASSERT (OutputContext != NULL); ASSERT (OutputContext != NULL);
ASSERT (((UINTN) OutputContext & 0x3F) == 0); ASSERT (((UINTN) OutputContext & 0x3F) == 0);
ZeroMem (OutputContext, sizeof (DEVICE_CONTEXT)); ZeroMem (OutputContext, sizeof (DEVICE_CONTEXT));
@ -1859,15 +2047,20 @@ XhcInitializeDeviceSlot (
// 7) Load the appropriate (Device Slot ID) entry in the Device Context Base Address Array (5.4.6) with // 7) Load the appropriate (Device Slot ID) entry in the Device Context Base Address Array (5.4.6) with
// a pointer to the Output Device Context data structure (6.2.1). // a pointer to the Output Device Context data structure (6.2.1).
// //
Xhc->DCBAA[SlotId] = (UINT64) (UINTN) OutputContext; PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, OutputContext, sizeof (DEVICE_CONTEXT));
//
// Fill DCBAA with PCI device address
//
Xhc->DCBAA[SlotId] = (UINT64) (UINTN) PhyAddr;
// //
// 8) Issue an Address Device Command for the Device Slot, where the command points to the Input // 8) Issue an Address Device Command for the Device Slot, where the command points to the Input
// Context data structure described above. // Context data structure described above.
// //
ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr)); ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr));
CmdTrbAddr.PtrLo = XHC_LOW_32BIT (Xhc->UsbDevContext[SlotId].InputContext); PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT));
CmdTrbAddr.PtrHi = XHC_HIGH_32BIT (Xhc->UsbDevContext[SlotId].InputContext); CmdTrbAddr.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbAddr.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbAddr.CycleBit = 1; CmdTrbAddr.CycleBit = 1;
CmdTrbAddr.Type = TRB_TYPE_ADDRESS_DEV; CmdTrbAddr.Type = TRB_TYPE_ADDRESS_DEV;
CmdTrbAddr.SlotId = Xhc->UsbDevContext[SlotId].SlotId; CmdTrbAddr.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
@ -1920,6 +2113,7 @@ XhcInitializeDeviceSlot64 (
UINT8 SlotId; UINT8 SlotId;
UINT8 ParentSlotId; UINT8 ParentSlotId;
DEVICE_CONTEXT_64 *ParentDeviceContext; DEVICE_CONTEXT_64 *ParentDeviceContext;
EFI_PHYSICAL_ADDRESS PhyAddr;
ZeroMem (&CmdTrb, sizeof (CMD_TRB_ENABLE_SLOT)); ZeroMem (&CmdTrb, sizeof (CMD_TRB_ENABLE_SLOT));
CmdTrb.CycleBit = 1; CmdTrb.CycleBit = 1;
@ -1947,7 +2141,7 @@ XhcInitializeDeviceSlot64 (
// 4.3.3 Device Slot Initialization // 4.3.3 Device Slot Initialization
// 1) Allocate an Input Context data structure (6.2.5) and initialize all fields to '0'. // 1) Allocate an Input Context data structure (6.2.5) and initialize all fields to '0'.
// //
InputContext = AllocatePages (EFI_SIZE_TO_PAGES (sizeof (INPUT_CONTEXT_64))); InputContext = UsbHcAllocateMem (Xhc->MemPool, sizeof (INPUT_CONTEXT_64));
ASSERT (InputContext != NULL); ASSERT (InputContext != NULL);
ASSERT (((UINTN) InputContext & 0x3F) == 0); ASSERT (((UINTN) InputContext & 0x3F) == 0);
ZeroMem (InputContext, sizeof (INPUT_CONTEXT_64)); ZeroMem (InputContext, sizeof (INPUT_CONTEXT_64));
@ -2036,13 +2230,18 @@ XhcInitializeDeviceSlot64 (
// //
// Init the DCS(dequeue cycle state) as the transfer ring's CCS // Init the DCS(dequeue cycle state) as the transfer ring's CCS
// //
InputContext->EP[0].PtrLo = XHC_LOW_32BIT (((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0) | BIT0; PhyAddr = UsbHcGetPciAddrForHostAddr (
InputContext->EP[0].PtrHi = XHC_HIGH_32BIT (((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0); Xhc->MemPool,
((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0,
sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER
);
InputContext->EP[0].PtrLo = XHC_LOW_32BIT (PhyAddr) | BIT0;
InputContext->EP[0].PtrHi = XHC_HIGH_32BIT (PhyAddr);
// //
// 6) Allocate the Output Device Context data structure (6.2.1) and initialize it to '0'. // 6) Allocate the Output Device Context data structure (6.2.1) and initialize it to '0'.
// //
OutputContext = AllocatePages (EFI_SIZE_TO_PAGES (sizeof (DEVICE_CONTEXT_64))); OutputContext = UsbHcAllocateMem (Xhc->MemPool, sizeof (DEVICE_CONTEXT_64));
ASSERT (OutputContext != NULL); ASSERT (OutputContext != NULL);
ASSERT (((UINTN) OutputContext & 0x3F) == 0); ASSERT (((UINTN) OutputContext & 0x3F) == 0);
ZeroMem (OutputContext, sizeof (DEVICE_CONTEXT_64)); ZeroMem (OutputContext, sizeof (DEVICE_CONTEXT_64));
@ -2052,15 +2251,20 @@ XhcInitializeDeviceSlot64 (
// 7) Load the appropriate (Device Slot ID) entry in the Device Context Base Address Array (5.4.6) with // 7) Load the appropriate (Device Slot ID) entry in the Device Context Base Address Array (5.4.6) with
// a pointer to the Output Device Context data structure (6.2.1). // a pointer to the Output Device Context data structure (6.2.1).
// //
Xhc->DCBAA[SlotId] = (UINT64) (UINTN) OutputContext; PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, OutputContext, sizeof (DEVICE_CONTEXT_64));
//
// Fill DCBAA with PCI device address
//
Xhc->DCBAA[SlotId] = (UINT64) (UINTN) PhyAddr;
// //
// 8) Issue an Address Device Command for the Device Slot, where the command points to the Input // 8) Issue an Address Device Command for the Device Slot, where the command points to the Input
// Context data structure described above. // Context data structure described above.
// //
ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr)); ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr));
CmdTrbAddr.PtrLo = XHC_LOW_32BIT (Xhc->UsbDevContext[SlotId].InputContext); PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT_64));
CmdTrbAddr.PtrHi = XHC_HIGH_32BIT (Xhc->UsbDevContext[SlotId].InputContext); CmdTrbAddr.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbAddr.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbAddr.CycleBit = 1; CmdTrbAddr.CycleBit = 1;
CmdTrbAddr.Type = TRB_TYPE_ADDRESS_DEV; CmdTrbAddr.Type = TRB_TYPE_ADDRESS_DEV;
CmdTrbAddr.SlotId = Xhc->UsbDevContext[SlotId].SlotId; CmdTrbAddr.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
@ -2150,9 +2354,10 @@ XhcDisableSlotCmd (
if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index] != NULL) { if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index] != NULL) {
RingSeg = ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index])->RingSeg0; RingSeg = ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index])->RingSeg0;
if (RingSeg != NULL) { if (RingSeg != NULL) {
FreePages (RingSeg, EFI_SIZE_TO_PAGES (sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER)); UsbHcFreeMem (Xhc->MemPool, RingSeg, sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER);
} }
FreePool (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index]); FreePool (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index]);
Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index] = NULL;
} }
} }
@ -2163,11 +2368,11 @@ XhcDisableSlotCmd (
} }
if (Xhc->UsbDevContext[SlotId].InputContext != NULL) { if (Xhc->UsbDevContext[SlotId].InputContext != NULL) {
FreePages (Xhc->UsbDevContext[SlotId].InputContext, EFI_SIZE_TO_PAGES (sizeof (INPUT_CONTEXT))); UsbHcFreeMem (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT));
} }
if (Xhc->UsbDevContext[SlotId].OutputContext != NULL) { if (Xhc->UsbDevContext[SlotId].OutputContext != NULL) {
FreePages (Xhc->UsbDevContext[SlotId].OutputContext, EFI_SIZE_TO_PAGES (sizeof (DEVICE_CONTEXT))); UsbHcFreeMem (Xhc->MemPool, Xhc->UsbDevContext[SlotId].OutputContext, sizeof (DEVICE_CONTEXT));
} }
// //
// Doesn't zero the entry because XhcAsyncInterruptTransfer() may be invoked to remove the established // Doesn't zero the entry because XhcAsyncInterruptTransfer() may be invoked to remove the established
@ -2249,9 +2454,10 @@ XhcDisableSlotCmd64 (
if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index] != NULL) { if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index] != NULL) {
RingSeg = ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index])->RingSeg0; RingSeg = ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index])->RingSeg0;
if (RingSeg != NULL) { if (RingSeg != NULL) {
FreePages (RingSeg, EFI_SIZE_TO_PAGES (sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER)); UsbHcFreeMem (Xhc->MemPool, RingSeg, sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER);
} }
FreePool (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index]); FreePool (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index]);
Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index] = NULL;
} }
} }
@ -2262,11 +2468,11 @@ XhcDisableSlotCmd64 (
} }
if (Xhc->UsbDevContext[SlotId].InputContext != NULL) { if (Xhc->UsbDevContext[SlotId].InputContext != NULL) {
FreePages (Xhc->UsbDevContext[SlotId].InputContext, EFI_SIZE_TO_PAGES (sizeof (INPUT_CONTEXT_64))); UsbHcFreeMem (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT_64));
} }
if (Xhc->UsbDevContext[SlotId].OutputContext != NULL) { if (Xhc->UsbDevContext[SlotId].OutputContext != NULL) {
FreePages (Xhc->UsbDevContext[SlotId].OutputContext, EFI_SIZE_TO_PAGES (sizeof (DEVICE_CONTEXT_64))); UsbHcFreeMem (Xhc->MemPool, Xhc->UsbDevContext[SlotId].OutputContext, sizeof (DEVICE_CONTEXT_64));
} }
// //
// Doesn't zero the entry because XhcAsyncInterruptTransfer() may be invoked to remove the established // Doesn't zero the entry because XhcAsyncInterruptTransfer() may be invoked to remove the established
@ -2311,7 +2517,7 @@ XhcSetConfigCmd (
UINT8 Direction; UINT8 Direction;
UINT8 Dci; UINT8 Dci;
UINT8 MaxDci; UINT8 MaxDci;
UINT32 PhyAddr; EFI_PHYSICAL_ADDRESS PhyAddr;
UINT8 Interval; UINT8 Interval;
TRANSFER_RING *EndpointTransferRing; TRANSFER_RING *EndpointTransferRing;
@ -2438,11 +2644,15 @@ XhcSetConfigCmd (
break; break;
} }
PhyAddr = XHC_LOW_32BIT (((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0); PhyAddr = UsbHcGetPciAddrForHostAddr (
Xhc->MemPool,
((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0,
sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER
);
PhyAddr &= ~(0x0F); PhyAddr &= ~(0x0F);
PhyAddr |= ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS; PhyAddr |= ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS;
InputContext->EP[Dci-1].PtrLo = PhyAddr; InputContext->EP[Dci-1].PtrLo = XHC_LOW_32BIT (PhyAddr);
InputContext->EP[Dci-1].PtrHi = XHC_HIGH_32BIT (((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0); InputContext->EP[Dci-1].PtrHi = XHC_HIGH_32BIT (PhyAddr);
EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length); EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
} }
@ -2455,8 +2665,9 @@ XhcSetConfigCmd (
// configure endpoint // configure endpoint
// //
ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP)); ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (InputContext); PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));
CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (InputContext); CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbCfgEP.CycleBit = 1; CmdTrbCfgEP.CycleBit = 1;
CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT; CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;
CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId; CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
@ -2503,7 +2714,7 @@ XhcSetConfigCmd64 (
UINT8 Direction; UINT8 Direction;
UINT8 Dci; UINT8 Dci;
UINT8 MaxDci; UINT8 MaxDci;
UINT32 PhyAddr; EFI_PHYSICAL_ADDRESS PhyAddr;
UINT8 Interval; UINT8 Interval;
TRANSFER_RING *EndpointTransferRing; TRANSFER_RING *EndpointTransferRing;
@ -2630,11 +2841,17 @@ XhcSetConfigCmd64 (
break; break;
} }
PhyAddr = XHC_LOW_32BIT (((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0); PhyAddr = UsbHcGetPciAddrForHostAddr (
Xhc->MemPool,
((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0,
sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER
);
PhyAddr &= ~(0x0F); PhyAddr &= ~(0x0F);
PhyAddr |= ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS; PhyAddr |= ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS;
InputContext->EP[Dci-1].PtrLo = PhyAddr;
InputContext->EP[Dci-1].PtrHi = XHC_HIGH_32BIT (((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0); InputContext->EP[Dci-1].PtrLo = XHC_LOW_32BIT (PhyAddr);
InputContext->EP[Dci-1].PtrHi = XHC_HIGH_32BIT (PhyAddr);
EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length); EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
} }
@ -2647,8 +2864,9 @@ XhcSetConfigCmd64 (
// configure endpoint // configure endpoint
// //
ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP)); ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (InputContext); PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));
CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (InputContext); CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbCfgEP.CycleBit = 1; CmdTrbCfgEP.CycleBit = 1;
CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT; CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;
CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId; CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
@ -2687,6 +2905,7 @@ XhcEvaluateContext (
CMD_TRB_EVALUATE_CONTEXT CmdTrbEvalu; CMD_TRB_EVALUATE_CONTEXT CmdTrbEvalu;
EVT_TRB_COMMAND_COMPLETION *EvtTrb; EVT_TRB_COMMAND_COMPLETION *EvtTrb;
INPUT_CONTEXT *InputContext; INPUT_CONTEXT *InputContext;
EFI_PHYSICAL_ADDRESS PhyAddr;
ASSERT (Xhc->UsbDevContext[SlotId].SlotId != 0); ASSERT (Xhc->UsbDevContext[SlotId].SlotId != 0);
@ -2700,8 +2919,9 @@ XhcEvaluateContext (
InputContext->EP[0].MaxPacketSize = MaxPacketSize; InputContext->EP[0].MaxPacketSize = MaxPacketSize;
ZeroMem (&CmdTrbEvalu, sizeof (CmdTrbEvalu)); ZeroMem (&CmdTrbEvalu, sizeof (CmdTrbEvalu));
CmdTrbEvalu.PtrLo = XHC_LOW_32BIT (InputContext); PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));
CmdTrbEvalu.PtrHi = XHC_HIGH_32BIT (InputContext); CmdTrbEvalu.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbEvalu.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbEvalu.CycleBit = 1; CmdTrbEvalu.CycleBit = 1;
CmdTrbEvalu.Type = TRB_TYPE_EVALU_CONTXT; CmdTrbEvalu.Type = TRB_TYPE_EVALU_CONTXT;
CmdTrbEvalu.SlotId = Xhc->UsbDevContext[SlotId].SlotId; CmdTrbEvalu.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
@ -2739,6 +2959,7 @@ XhcEvaluateContext64 (
CMD_TRB_EVALUATE_CONTEXT CmdTrbEvalu; CMD_TRB_EVALUATE_CONTEXT CmdTrbEvalu;
EVT_TRB_COMMAND_COMPLETION *EvtTrb; EVT_TRB_COMMAND_COMPLETION *EvtTrb;
INPUT_CONTEXT_64 *InputContext; INPUT_CONTEXT_64 *InputContext;
EFI_PHYSICAL_ADDRESS PhyAddr;
ASSERT (Xhc->UsbDevContext[SlotId].SlotId != 0); ASSERT (Xhc->UsbDevContext[SlotId].SlotId != 0);
@ -2752,8 +2973,9 @@ XhcEvaluateContext64 (
InputContext->EP[0].MaxPacketSize = MaxPacketSize; InputContext->EP[0].MaxPacketSize = MaxPacketSize;
ZeroMem (&CmdTrbEvalu, sizeof (CmdTrbEvalu)); ZeroMem (&CmdTrbEvalu, sizeof (CmdTrbEvalu));
CmdTrbEvalu.PtrLo = XHC_LOW_32BIT (InputContext); PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));
CmdTrbEvalu.PtrHi = XHC_HIGH_32BIT (InputContext); CmdTrbEvalu.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbEvalu.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbEvalu.CycleBit = 1; CmdTrbEvalu.CycleBit = 1;
CmdTrbEvalu.Type = TRB_TYPE_EVALU_CONTXT; CmdTrbEvalu.Type = TRB_TYPE_EVALU_CONTXT;
CmdTrbEvalu.SlotId = Xhc->UsbDevContext[SlotId].SlotId; CmdTrbEvalu.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
@ -2797,6 +3019,7 @@ XhcConfigHubContext (
INPUT_CONTEXT *InputContext; INPUT_CONTEXT *InputContext;
DEVICE_CONTEXT *OutputContext; DEVICE_CONTEXT *OutputContext;
CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP; CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;
EFI_PHYSICAL_ADDRESS PhyAddr;
ASSERT (Xhc->UsbDevContext[SlotId].SlotId != 0); ASSERT (Xhc->UsbDevContext[SlotId].SlotId != 0);
InputContext = Xhc->UsbDevContext[SlotId].InputContext; InputContext = Xhc->UsbDevContext[SlotId].InputContext;
@ -2819,8 +3042,9 @@ XhcConfigHubContext (
InputContext->Slot.MTT = MTT; InputContext->Slot.MTT = MTT;
ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP)); ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (InputContext); PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));
CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (InputContext); CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbCfgEP.CycleBit = 1; CmdTrbCfgEP.CycleBit = 1;
CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT; CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;
CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId; CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
@ -2863,6 +3087,7 @@ XhcConfigHubContext64 (
INPUT_CONTEXT_64 *InputContext; INPUT_CONTEXT_64 *InputContext;
DEVICE_CONTEXT_64 *OutputContext; DEVICE_CONTEXT_64 *OutputContext;
CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP; CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;
EFI_PHYSICAL_ADDRESS PhyAddr;
ASSERT (Xhc->UsbDevContext[SlotId].SlotId != 0); ASSERT (Xhc->UsbDevContext[SlotId].SlotId != 0);
InputContext = Xhc->UsbDevContext[SlotId].InputContext; InputContext = Xhc->UsbDevContext[SlotId].InputContext;
@ -2885,8 +3110,9 @@ XhcConfigHubContext64 (
InputContext->Slot.MTT = MTT; InputContext->Slot.MTT = MTT;
ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP)); ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (InputContext); PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));
CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (InputContext); CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbCfgEP.CycleBit = 1; CmdTrbCfgEP.CycleBit = 1;
CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT; CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;
CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId; CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;

17
MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.h
View File

@ -2,7 +2,7 @@
This file contains the definition for XHCI host controller schedule routines. This file contains the definition for XHCI host controller schedule routines.
Copyright (c) 2011 - 2012, Intel Corporation. All rights reserved.<BR> Copyright (c) 2011 - 2013, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at which accompanies this distribution. The full text of the license may be found at
@ -172,6 +172,8 @@ typedef struct _URB {
EFI_USB_DEVICE_REQUEST *Request; EFI_USB_DEVICE_REQUEST *Request;
VOID *Data; VOID *Data;
UINTN DataLen; UINTN DataLen;
VOID *DataPhy;
VOID *DataMap;
EFI_ASYNC_USB_TRANSFER_CALLBACK Callback; EFI_ASYNC_USB_TRANSFER_CALLBACK Callback;
VOID *Context; VOID *Context;
// //
@ -1305,6 +1307,19 @@ XhcCreateUrb (
IN VOID *Context IN VOID *Context
); );
/**
Free an allocated URB.
@param Xhc The XHCI device.
@param Urb The URB to free.
**/
VOID
XhcFreeUrb (
IN USB_XHCI_INSTANCE *Xhc,
IN URB *Urb
);
/** /**
Create a transfer TRB. Create a transfer TRB.