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ArmPlatformPkg/PL031RealTimeClock: Fixed driver to support UEFI Runtime Services

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- Removed PCD base address from the macro definition. The base address needs to be fixup when the driver runs in UEFI Runtime mode
- Added the PL031 controller memory region to the Runtime UEFI Memory Mapped IO
- Caught the gEfiEventVirtualAddressChangeGuid event to fixup the PL031 Base address

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15435 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Olivier Martin
2014-04-08 17:59:00 +00:00
committed by oliviermartin
parent 9d34cac819
commit 18ee5b6d78
3 changed files with 119 additions and 76 deletions
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34
ArmPlatformPkg/Include/Drivers/PL031RealTimeClock.h
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@@ -1,6 +1,6 @@
/** @file
*
* Copyright (c) 2011, ARM Limited. All rights reserved.
* Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
@@ -17,22 +17,22 @@
#define __PL031_REAL_TIME_CLOCK_H__
// PL031 Registers
#define PL031_RTC_DR_DATA_REGISTER ((UINT32)PcdGet32(PcdPL031RtcBase) + 0x000)
#define PL031_RTC_MR_MATCH_REGISTER ((UINT32)PcdGet32(PcdPL031RtcBase) + 0x004)
#define PL031_RTC_LR_LOAD_REGISTER ((UINT32)PcdGet32(PcdPL031RtcBase) + 0x008)
#define PL031_RTC_CR_CONTROL_REGISTER ((UINT32)PcdGet32(PcdPL031RtcBase) + 0x00C)
#define PL031_RTC_IMSC_IRQ_MASK_SET_CLEAR_REGISTER ((UINT32)PcdGet32(PcdPL031RtcBase) + 0x010)
#define PL031_RTC_RIS_RAW_IRQ_STATUS_REGISTER ((UINT32)PcdGet32(PcdPL031RtcBase) + 0x014)
#define PL031_RTC_MIS_MASKED_IRQ_STATUS_REGISTER ((UINT32)PcdGet32(PcdPL031RtcBase) + 0x018)
#define PL031_RTC_ICR_IRQ_CLEAR_REGISTER ((UINT32)PcdGet32(PcdPL031RtcBase) + 0x01C)
#define PL031_RTC_PERIPH_ID0 ((UINT32)PcdGet32(PcdPL031RtcBase) + 0xFE0)
#define PL031_RTC_PERIPH_ID1 ((UINT32)PcdGet32(PcdPL031RtcBase) + 0xFE4)
#define PL031_RTC_PERIPH_ID2 ((UINT32)PcdGet32(PcdPL031RtcBase) + 0xFE8)
#define PL031_RTC_PERIPH_ID3 ((UINT32)PcdGet32(PcdPL031RtcBase) + 0xFEC)
#define PL031_RTC_PCELL_ID0 ((UINT32)PcdGet32(PcdPL031RtcBase) + 0xFF0)
#define PL031_RTC_PCELL_ID1 ((UINT32)PcdGet32(PcdPL031RtcBase) + 0xFF4)
#define PL031_RTC_PCELL_ID2 ((UINT32)PcdGet32(PcdPL031RtcBase) + 0xFF8)
#define PL031_RTC_PCELL_ID3 ((UINT32)PcdGet32(PcdPL031RtcBase) + 0xFFC)
#define PL031_RTC_DR_DATA_REGISTER 0x000
#define PL031_RTC_MR_MATCH_REGISTER 0x004
#define PL031_RTC_LR_LOAD_REGISTER 0x008
#define PL031_RTC_CR_CONTROL_REGISTER 0x00C
#define PL031_RTC_IMSC_IRQ_MASK_SET_CLEAR_REGISTER 0x010
#define PL031_RTC_RIS_RAW_IRQ_STATUS_REGISTER 0x014
#define PL031_RTC_MIS_MASKED_IRQ_STATUS_REGISTER 0x018
#define PL031_RTC_ICR_IRQ_CLEAR_REGISTER 0x01C
#define PL031_RTC_PERIPH_ID0 0xFE0
#define PL031_RTC_PERIPH_ID1 0xFE4
#define PL031_RTC_PERIPH_ID2 0xFE8
#define PL031_RTC_PERIPH_ID3 0xFEC
#define PL031_RTC_PCELL_ID0 0xFF0
#define PL031_RTC_PCELL_ID1 0xFF4
#define PL031_RTC_PCELL_ID2 0xFF8
#define PL031_RTC_PCELL_ID3 0xFFC
// PL031 Values
#define PL031_RTC_ENABLED 0x00000001