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Hack in some DSB, ISB syncronization primatives. Need to do it a little cleaner.

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git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10023 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
andrewfish
2010-02-18 04:25:31 +00:00
parent 5dea9bd6e6
commit 1a27eb4887
5 changed files with 307 additions and 5 deletions
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68
ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm
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@@ -40,59 +40,101 @@ XP_ON EQU ( 0x1:SHL:23 )
ArmInvalidateDataCacheEntryByMVA
DSB
ISB
MCR p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
DSB
ISB
BX lr
ArmCleanDataCacheEntryByMVA
DSB
ISB
MCR p15, 0, r0, c7, c10, 1 ; clean single data cache line
DSB
ISB
BX lr
ArmCleanInvalidateDataCacheEntryByMVA
DSB
ISB
MCR p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
DSB
ISB
BX lr
ArmInvalidateDataCacheEntryBySetWay
DSB
ISB
mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line
DSB
ISB
bx lr
ArmCleanInvalidateDataCacheEntryBySetWay
DSB
ISB
mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line
DSB
ISB
bx lr
ArmCleanDataCacheEntryBySetWay
DSB
ISB
mcr p15, 0, r0, c7, c10, 2 ; Clean this line
DSB
ISB
bx lr
ArmDrainWriteBuffer
DSB
ISB
mcr p15, 0, r0, c7, c10, 4 ; Drain write buffer for sync
DSB
ISB
bx lr
ArmInvalidateInstructionCache
DSB
ISB
MOV R0,#0
MCR p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache
MOV R0,#0
MCR p15,0,R0,c7,c5,4 ;Instruction synchronization barrier
DSB
ISB
BX LR
ArmEnableMmu
DSB
ISB
mrc p15,0,R0,c1,c0,0
orr R0,R0,#1
mcr p15,0,R0,c1,c0,0
DSB
ISB
bx LR
ArmMmuEnabled
DSB
ISB
mrc p15,0,R0,c1,c0,0
and R0,R0,#1
DSB
ISB
bx LR
ArmDisableMmu
DSB
ISB
mov R0,#0
mcr p15,0,R0,c13,c0,0 ;FCSE PID register must be cleared before disabling MMU
mrc p15,0,R0,c1,c0,0
@@ -102,46 +144,72 @@ ArmDisableMmu
mcr p15,0,R0,c7,c10,4 ;Data synchronization barrier
mov R0,#0
mcr p15,0,R0,c7,c5,4 ;Instruction synchronization barrier
DSB
ISB
bx LR
ArmEnableDataCache
DSB
ISB
LDR R1,=DC_ON
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
ORR R0,R0,R1 ;Set C bit
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
DSB
ISB
BX LR
ArmDisableDataCache
DSB
ISB
LDR R1,=DC_ON
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
BIC R0,R0,R1 ;Clear C bit
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
DSB
ISB
BX LR
ArmEnableInstructionCache
DSB
ISB
LDR R1,=IC_ON
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
ORR R0,R0,R1 ;Set I bit
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
DSB
ISB
BX LR
ArmDisableInstructionCache
DSB
ISB
LDR R1,=IC_ON
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
BIC R0,R0,R1 ;Clear I bit.
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
DSB
ISB
BX LR
ArmEnableBranchPrediction
DSB
ISB
mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #0x00000800
mcr p15, 0, r0, c1, c0, 0
DSB
ISB
bx LR
ArmDisableBranchPrediction
DSB
ISB
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x00000800
mcr p15, 0, r0, c1, c0, 0
DSB
ISB
bx LR
END