Second set of changes based on a review of the code comments in the Include directory for typos, grammar issues, and language clarity.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@8467 6f19259b-4bc3-4df7-8a09-765794883524
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@@ -39,7 +39,7 @@ InvalidateInstructionCache (
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aligned on a cache line boundary, then the entire instruction cache line
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containing Address + Length -1 is invalidated. This function may choose to
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invalidate the entire instruction cache if that is more efficient than
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invalidating the specified range. If Length is 0, the no instruction cache
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invalidating the specified range. If Length is 0, then no instruction cache
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lines are invalidated. Address is returned.
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If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
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@@ -88,7 +88,7 @@ WriteBackInvalidateDataCache (
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line containing Address + Length -1 is written back and invalidated. This
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function may choose to write back and invalidate the entire data cache if
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that is more efficient than writing back and invalidating the specified
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range. If Length is 0, the no data cache lines are written back and
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range. If Length is 0, then no data cache lines are written back and
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invalidated. Address is returned.
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If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
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@@ -136,7 +136,7 @@ WriteBackDataCache (
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cache line boundary, then the entire data cache line containing Address +
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Length -1 is written back. This function may choose to write back the entire
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data cache if that is more efficient than writing back the specified range.
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If Length is 0, the no data cache lines are written back. This function may
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If Length is 0, then no data cache lines are written back. This function may
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also invalidate all the data cache lines in the specified range of the cache
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coherency domain of the calling CPU. Address is returned.
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