Sync up ArmPkg with patch from mailing list. Changed name of BdsLib.h to BdsUnixLib.h and fixed a lot of issues with Xcode building.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11293 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
andrewfish
@@ -86,22 +86,22 @@
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#define TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK (0xFFF00000)
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#define TT_DESCRIPTOR_SECTION_BASE_ADDRESS(a) (a & TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK)
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#define TT_DESCRIPTOR_SECTION_WRITE_BACK (TT_DESCRIPTOR_TYPE_SECTION | \
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TT_DESCRIPTOR_SECTION_NS_NON_SECURE | \
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#define TT_DESCRIPTOR_SECTION_WRITE_BACK(Secure) (TT_DESCRIPTOR_TYPE_SECTION | \
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(Secure ? TT_DESCRIPTOR_SECTION_NS_SECURE : TT_DESCRIPTOR_SECTION_NS_NON_SECURE ) | \
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TT_DESCRIPTOR_SECTION_NG_GLOBAL | \
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TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \
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TT_DESCRIPTOR_SECTION_DOMAIN(0) | \
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TT_DESCRIPTOR_SECTION_AP_RW_RW | \
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TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC)
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#define TT_DESCRIPTOR_SECTION_WRITE_THROUGH (TT_DESCRIPTOR_TYPE_SECTION | \
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TT_DESCRIPTOR_SECTION_NS_NON_SECURE | \
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#define TT_DESCRIPTOR_SECTION_WRITE_THROUGH(Secure) (TT_DESCRIPTOR_TYPE_SECTION | \
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(Secure ? TT_DESCRIPTOR_SECTION_NS_SECURE : TT_DESCRIPTOR_SECTION_NS_NON_SECURE ) | \
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TT_DESCRIPTOR_SECTION_NG_GLOBAL | \
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TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \
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TT_DESCRIPTOR_SECTION_DOMAIN(0) | \
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TT_DESCRIPTOR_SECTION_AP_RW_RW | \
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TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC)
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#define TT_DESCRIPTOR_SECTION_UNCACHED (TT_DESCRIPTOR_TYPE_SECTION | \
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TT_DESCRIPTOR_SECTION_NS_NON_SECURE | \
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#define TT_DESCRIPTOR_SECTION_UNCACHED(Secure) (TT_DESCRIPTOR_TYPE_SECTION | \
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(Secure ? TT_DESCRIPTOR_SECTION_NS_SECURE : TT_DESCRIPTOR_SECTION_NS_NON_SECURE ) | \
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TT_DESCRIPTOR_SECTION_NG_GLOBAL | \
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TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \
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TT_DESCRIPTOR_SECTION_DOMAIN(0) | \
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@@ -22,17 +22,52 @@
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#define DOMAIN_ACCESS_CONTROL_RESERVED(a) (2UL << (2 * (a)))
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#define DOMAIN_ACCESS_CONTROL_MANAGER(a) (3UL << (2 * (a)))
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#define TRANSLATION_TABLE_SIZE (16 * 1024)
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#define TRANSLATION_TABLE_ALIGNMENT (16 * 1024)
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#define TRANSLATION_TABLE_ALIGNMENT_MASK (TRANSLATION_TABLE_ALIGNMENT - 1)
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#define TTBR_NOT_OUTER_SHAREABLE BIT5
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#define TTBR_RGN_OUTER_NON_CACHEABLE 0
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#define TTBR_RGN_OUTER_WRITE_BACK_ALLOC BIT3
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#define TTBR_RGN_OUTER_WRITE_THROUGH BIT4
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#define TTBR_RGN_OUTER_WRITE_BACK_NO_ALLOC (BIT3|BIT4)
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#define TTBR_SHAREABLE BIT1
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#define TTBR_NON_SHAREABLE 0
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#define TTBR_INNER_CACHEABLE BIT0
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#define TTBR_NON_INNER_CACHEABLE BIT0
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#define TTBR_RGN_INNER_NON_CACHEABLE 0
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#define TTBR_RGN_INNER_WRITE_BACK_ALLOC BIT6
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#define TTBR_RGN_INNER_WRITE_THROUGH BIT0
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#define TTBR_RGN_INNER_WRITE_BACK_NO_ALLOC (BIT0|BIT6)
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#define TTBR_WRITE_THROUGH_NO_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_ALLOC | TTBR_RGN_INNER_WRITE_BACK_ALLOC )
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#define TTBR_WRITE_BACK_NO_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_NO_ALLOC | TTBR_RGN_INNER_WRITE_BACK_NO_ALLOC )
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#define TTBR_NON_CACHEABLE ( TTBR_RGN_OUTER_NON_CACHEABLE | TTBR_RGN_INNER_NON_CACHEABLE )
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#define TTBR_WRITE_BACK_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_ALLOC | TTBR_RGN_INNER_WRITE_BACK_ALLOC )
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#define TRANSLATION_TABLE_SECTION_COUNT 4096
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#define TRANSLATION_TABLE_SECTION_SIZE (sizeof(UINT32) * TRANSLATION_TABLE_SECTION_COUNT)
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#define TRANSLATION_TABLE_SECTION_ALIGNMENT (sizeof(UINT32) * TRANSLATION_TABLE_SECTION_COUNT)
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#define TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK (TRANSLATION_TABLE_SECTION_ALIGNMENT - 1)
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#define TRANSLATION_TABLE_PAGE_COUNT 256
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#define TRANSLATION_TABLE_PAGE_SIZE (sizeof(UINT32) * TRANSLATION_TABLE_PAGE_COUNT)
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#define TRANSLATION_TABLE_PAGE_ALIGNMENT (sizeof(UINT32) * TRANSLATION_TABLE_PAGE_COUNT)
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#define TRANSLATION_TABLE_PAGE_ALIGNMENT_MASK (TRANSLATION_TABLE_PAGE_ALIGNMENT - 1)
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#define TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(table, address) ((UINT32 *)(table) + (((UINTN)(address)) >> 20))
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// Translation table descriptor types
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#define TT_DESCRIPTOR_TYPE_MASK ((1UL << 18) | (3UL << 0))
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#define TT_DESCRIPTOR_TYPE_PAGE_TABLE ((0UL << 18) | (1UL << 0))
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#define TT_DESCRIPTOR_TYPE_SECTION ((0UL << 18) | (2UL << 0))
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#define TT_DESCRIPTOR_TYPE_SUPERSECTION ((1UL << 18) | (2UL << 0))
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#define TT_DESCRIPTOR_SECTION_TYPE_MASK ((1UL << 18) | (3UL << 0))
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#define TT_DESCRIPTOR_SECTION_TYPE_FAULT (0UL << 0)
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#define TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE (1UL << 0)
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#define TT_DESCRIPTOR_SECTION_TYPE_SECTION ((0UL << 18) | (2UL << 0))
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#define TT_DESCRIPTOR_SECTION_TYPE_SUPERSECTION ((1UL << 18) | (2UL << 0))
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#define TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(Desc) (((Desc) & 3UL) == TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE)
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// Translation table descriptor types
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#define TT_DESCRIPTOR_PAGE_TYPE_MASK (3UL << 0)
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#define TT_DESCRIPTOR_PAGE_TYPE_FAULT (0UL << 0)
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#define TT_DESCRIPTOR_PAGE_TYPE_PAGE (2UL << 0)
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#define TT_DESCRIPTOR_PAGE_TYPE_PAGE_XN (3UL << 0)
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#define TT_DESCRIPTOR_PAGE_TYPE_LARGEPAGE (1UL << 0)
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// Section descriptor definitions
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#define TT_DESCRIPTOR_SECTION_SIZE (0x00100000)
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@@ -45,10 +80,18 @@
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#define TT_DESCRIPTOR_SECTION_NG_GLOBAL (0UL << 17)
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#define TT_DESCRIPTOR_SECTION_NG_LOCAL (1UL << 17)
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#define TT_DESCRIPTOR_PAGE_NG_MASK (1UL << 11)
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#define TT_DESCRIPTOR_PAGE_NG_GLOBAL (0UL << 11)
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#define TT_DESCRIPTOR_PAGE_NG_LOCAL (1UL << 11)
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#define TT_DESCRIPTOR_SECTION_S_MASK (1UL << 16)
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#define TT_DESCRIPTOR_SECTION_S_NOT_SHARED (0UL << 16)
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#define TT_DESCRIPTOR_SECTION_S_SHARED (1UL << 16)
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#define TT_DESCRIPTOR_PAGE_S_MASK (1UL << 10)
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#define TT_DESCRIPTOR_PAGE_S_NOT_SHARED (0UL << 10)
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#define TT_DESCRIPTOR_PAGE_S_SHARED (1UL << 10)
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#define TT_DESCRIPTOR_SECTION_AP_MASK ((1UL << 15) | (3UL << 10))
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#define TT_DESCRIPTOR_SECTION_AP_NO_NO ((0UL << 15) | (0UL << 10))
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#define TT_DESCRIPTOR_SECTION_AP_RW_NO ((0UL << 15) | (1UL << 10))
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@@ -57,7 +100,20 @@
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#define TT_DESCRIPTOR_SECTION_AP_RO_NO ((1UL << 15) | (1UL << 10))
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#define TT_DESCRIPTOR_SECTION_AP_RO_RO ((1UL << 15) | (3UL << 10))
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#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK ((3UL << 12) | (0UL << 3) | (0UL << 2))
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#define TT_DESCRIPTOR_PAGE_AP_MASK ((1UL << 9) | (3UL << 4))
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#define TT_DESCRIPTOR_PAGE_AP_NO_NO ((0UL << 9) | (0UL << 4))
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#define TT_DESCRIPTOR_PAGE_AP_RW_NO ((0UL << 9) | (1UL << 4))
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#define TT_DESCRIPTOR_PAGE_AP_RW_RO ((0UL << 9) | (2UL << 4))
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#define TT_DESCRIPTOR_PAGE_AP_RW_RW ((0UL << 9) | (3UL << 4))
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#define TT_DESCRIPTOR_PAGE_AP_RO_NO ((1UL << 9) | (1UL << 4))
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#define TT_DESCRIPTOR_PAGE_AP_RO_RO ((1UL << 9) | (3UL << 4))
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#define TT_DESCRIPTOR_SECTION_XN_MASK (0x1UL << 4)
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#define TT_DESCRIPTOR_PAGE_XN_MASK (0x1UL << 0)
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#define TT_DESCRIPTOR_LARGEPAGE_XN_MASK (0x1UL << 15)
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#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK ((3UL << 12) | (1UL << 3) | (1UL << 2))
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#define TT_DESCRIPTOR_SECTION_CACHEABLE_MASK (1UL << 3)
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#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED ((0UL << 12) | (0UL << 3) | (0UL << 2))
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#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_SHAREABLE_DEVICE ((0UL << 12) | (0UL << 3) | (1UL << 2))
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#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC ((0UL << 12) | (1UL << 3) | (0UL << 2))
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@@ -66,39 +122,240 @@
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#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC ((1UL << 12) | (1UL << 3) | (1UL << 2))
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#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_SHAREABLE_DEVICE ((2UL << 12) | (0UL << 3) | (0UL << 2))
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#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK ((3UL << 6) | (1UL << 3) | (1UL << 2))
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#define TT_DESCRIPTOR_PAGE_CACHEABLE_MASK (1UL << 3)
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#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED ((0UL << 6) | (0UL << 3) | (0UL << 2))
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#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_SHAREABLE_DEVICE ((0UL << 6) | (0UL << 3) | (1UL << 2))
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#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC ((0UL << 6) | (1UL << 3) | (0UL << 2))
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#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_NO_ALLOC ((0UL << 6) | (1UL << 3) | (1UL << 2))
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#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE ((1UL << 6) | (0UL << 3) | (0UL << 2))
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#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC ((1UL << 6) | (1UL << 3) | (1UL << 2))
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#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_SHAREABLE_DEVICE ((2UL << 6) | (0UL << 3) | (0UL << 2))
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#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_MASK ((3UL << 12) | (0UL << 3) | (0UL << 2))
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#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_STRONGLY_ORDERED ((0UL << 12) | (0UL << 3) | (0UL << 2))
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#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_SHAREABLE_DEVICE ((0UL << 12) | (0UL << 3) | (1UL << 2))
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#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC ((0UL << 12) | (1UL << 3) | (0UL << 2))
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#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_WRITE_BACK_NO_ALLOC ((0UL << 12) | (1UL << 3) | (1UL << 2))
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#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_NON_CACHEABLE ((1UL << 12) | (0UL << 3) | (0UL << 2))
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#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_WRITE_BACK_ALLOC ((1UL << 12) | (1UL << 3) | (1UL << 2))
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#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_NON_SHAREABLE_DEVICE ((2UL << 12) | (0UL << 3) | (0UL << 2))
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#define TT_DESCRIPTOR_CONVERT_TO_PAGE_AP(Desc) ((((Desc) & TT_DESCRIPTOR_SECTION_AP_MASK) >> 6) & TT_DESCRIPTOR_PAGE_AP_MASK)
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#define TT_DESCRIPTOR_CONVERT_TO_PAGE_NG(Desc) ((((Desc) & TT_DESCRIPTOR_SECTION_NG_MASK) >> 6) & TT_DESCRIPTOR_PAGE_NG_MASK)
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#define TT_DESCRIPTOR_CONVERT_TO_PAGE_S(Desc) ((((Desc) & TT_DESCRIPTOR_SECTION_S_MASK) >> 6) & TT_DESCRIPTOR_PAGE_S_MASK)
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#define TT_DESCRIPTOR_CONVERT_TO_PAGE_XN(Desc,IsLargePage) ((IsLargePage)? \
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((((Desc) & TT_DESCRIPTOR_SECTION_XN_MASK) >> 4) & TT_DESCRIPTOR_LARGEPAGE_XN_MASK): \
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((((Desc) & TT_DESCRIPTOR_SECTION_XN_MASK) << 11) & TT_DESCRIPTOR_PAGE_XN_MASK))
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#define TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY(Desc,IsLargePage) (IsLargePage? \
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(((Desc) & TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK) & TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_MASK): \
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(((((Desc) & (0x3 << 12)) >> 6) | (Desc & (0x3 << 2)))))
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#define TT_DESCRIPTOR_SECTION_DOMAIN_MASK (0x0FUL << 5)
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#define TT_DESCRIPTOR_SECTION_DOMAIN(a) (((a) & 0x0FUL) << 5)
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#define TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK (0xFFF00000)
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#define TT_DESCRIPTOR_SECTION_BASE_ADDRESS(a) (a & TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK)
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#define TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK (0xFFFFFC00)
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#define TT_DESCRIPTOR_SECTION_BASE_ADDRESS(a) ((a) & TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK)
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#define TT_DESCRIPTOR_SECTION_BASE_SHIFT 20
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#define TT_DESCRIPTOR_PAGE_BASE_ADDRESS_MASK (0xFFFFF000)
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#define TT_DESCRIPTOR_PAGE_INDEX_MASK (0x000FF000)
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#define TT_DESCRIPTOR_PAGE_BASE_ADDRESS(a) ((a) & TT_DESCRIPTOR_PAGE_BASE_ADDRESS_MASK)
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#define TT_DESCRIPTOR_PAGE_BASE_SHIFT 12
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#define TT_DESCRIPTOR_SECTION_WRITE_BACK(Secure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \
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((Secure) ? TT_DESCRIPTOR_SECTION_NS_SECURE : TT_DESCRIPTOR_SECTION_NS_NON_SECURE ) | \
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TT_DESCRIPTOR_SECTION_NG_GLOBAL | \
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TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \
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TT_DESCRIPTOR_SECTION_DOMAIN(0) | \
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TT_DESCRIPTOR_SECTION_AP_RW_RW | \
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TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC)
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#define TT_DESCRIPTOR_SECTION_WRITE_THROUGH(Secure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \
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((Secure) ? TT_DESCRIPTOR_SECTION_NS_SECURE : TT_DESCRIPTOR_SECTION_NS_NON_SECURE ) | \
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TT_DESCRIPTOR_SECTION_NG_GLOBAL | \
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TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \
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TT_DESCRIPTOR_SECTION_DOMAIN(0) | \
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TT_DESCRIPTOR_SECTION_AP_RW_RW | \
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TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC)
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#define TT_DESCRIPTOR_SECTION_DEVICE(Secure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \
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((Secure) ? TT_DESCRIPTOR_SECTION_NS_SECURE : TT_DESCRIPTOR_SECTION_NS_NON_SECURE ) | \
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TT_DESCRIPTOR_SECTION_NG_GLOBAL | \
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TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \
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TT_DESCRIPTOR_SECTION_DOMAIN(0) | \
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TT_DESCRIPTOR_SECTION_AP_RW_RW | \
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TT_DESCRIPTOR_SECTION_CACHE_POLICY_SHAREABLE_DEVICE)
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#define TT_DESCRIPTOR_SECTION_UNCACHED(Secure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \
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((Secure) ? TT_DESCRIPTOR_SECTION_NS_SECURE : TT_DESCRIPTOR_SECTION_NS_NON_SECURE ) | \
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TT_DESCRIPTOR_SECTION_NG_GLOBAL | \
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TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \
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TT_DESCRIPTOR_SECTION_DOMAIN(0) | \
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TT_DESCRIPTOR_SECTION_AP_RW_RW | \
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TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE)
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// Cortex A9 feature bit definitions
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#define A9_FEATURE_PARITY (1<<9)
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#define A9_FEATURE_AOW (1<<8)
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#define A9_FEATURE_EXCL (1<<7)
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#define A9_FEATURE_SMP (1<<6)
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#define A9_FEATURE_FOZ (1<<3)
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#define A9_FEATURE_DPREF (1<<2)
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#define A9_FEATURE_HINT (1<<1)
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#define A9_FEATURE_FWD (1<<0)
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// SCU register offsets & masks
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#define SCU_CONTROL_OFFSET 0x0
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#define SCU_CONFIG_OFFSET 0x4
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#define SCU_INVALL_OFFSET 0xC
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#define SCU_FILT_START_OFFSET 0x40
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#define SCU_FILT_END_OFFSET 0x44
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#define SCU_SACR_OFFSET 0x50
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#define SCU_SSACR_OFFSET 0x54
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#define SMP_GIC_CPUIF_BASE 0x100
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#define SMP_GIC_DIST_BASE 0x1000
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// CPACR - Coprocessor Access Control Register defintions
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#define CPACR_CP_DENIED(cp) 0x00
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#define CPACR_CP_PRIV(cp) ((0x1 << ((cp) << 1)) & 0x0FFFFFFF)
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#define CPACR_CP_FULL(cp) ((0x3 << ((cp) << 1)) & 0x0FFFFFFF)
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#define CPACR_ASEDIS (1 << 31)
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#define CPACR_D32DIS (1 << 30)
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#define CPACR_CP_FULL_ACCESS 0x0FFFFFFF
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// NSACR - Non-Secure Access Control Register defintions
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#define NSACR_CP(cp) ((1 << (cp)) & 0x3FFF)
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#define NSACR_NSD32DIS (1 << 14)
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#define NSACR_NSASEDIS (1 << 15)
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#define NSACR_PLE (1 << 16)
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#define NSACR_TL (1 << 17)
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#define NSACR_NS_SMP (1 << 18)
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#define NSACR_RFR (1 << 19)
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// SCR - Secure Configuration Register defintions
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#define SCR_NS (1 << 0)
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#define SCR_IRQ (1 << 1)
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#define SCR_FIQ (1 << 2)
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#define SCR_EA (1 << 3)
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#define SCR_FW (1 << 4)
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#define SCR_AW (1 << 5)
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VOID
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EFIAPI
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ArmEnableSWPInstruction (
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VOID
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);
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VOID
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EFIAPI
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ArmWriteNsacr (
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IN UINT32 SetWayFormat
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);
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VOID
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EFIAPI
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ArmWriteScr (
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IN UINT32 SetWayFormat
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);
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VOID
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EFIAPI
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ArmWriteVMBar (
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IN UINT32 SetWayFormat
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);
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VOID
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EFIAPI
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ArmWriteVBar (
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IN UINT32 SetWayFormat
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);
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UINT32
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EFIAPI
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ArmReadVBar (
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VOID
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);
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VOID
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EFIAPI
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ArmWriteCPACR (
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IN UINT32 SetWayFormat
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);
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VOID
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EFIAPI
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ArmEnableVFP (
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VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmCallWFI (
|
||||
VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmInvalidScu (
|
||||
VOID
|
||||
);
|
||||
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmGetScuBaseAddress (
|
||||
VOID
|
||||
);
|
||||
|
||||
UINT32
|
||||
EFIAPI
|
||||
ArmIsScuEnable(
|
||||
VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmWriteAuxCr (
|
||||
IN UINT32 Bit
|
||||
);
|
||||
|
||||
UINT32
|
||||
EFIAPI
|
||||
ArmReadAuxCr (
|
||||
VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmSetAuxCrBit (
|
||||
IN UINT32 Bits
|
||||
);
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmSetupSmpNonSecure (
|
||||
IN UINTN CoreId
|
||||
);
|
||||
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmReadCbar(
|
||||
VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmInvalidateInstructionAndDataTlb(
|
||||
VOID
|
||||
);
|
||||
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmReadMpidr(
|
||||
VOID
|
||||
);
|
||||
|
||||
#define TT_DESCRIPTOR_SECTION_WRITE_BACK (TT_DESCRIPTOR_TYPE_SECTION | \
|
||||
TT_DESCRIPTOR_SECTION_NS_NON_SECURE | \
|
||||
TT_DESCRIPTOR_SECTION_NG_GLOBAL | \
|
||||
TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \
|
||||
TT_DESCRIPTOR_SECTION_DOMAIN(0) | \
|
||||
TT_DESCRIPTOR_SECTION_AP_RW_RW | \
|
||||
TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC)
|
||||
#define TT_DESCRIPTOR_SECTION_WRITE_THROUGH (TT_DESCRIPTOR_TYPE_SECTION | \
|
||||
TT_DESCRIPTOR_SECTION_NS_NON_SECURE | \
|
||||
TT_DESCRIPTOR_SECTION_NG_GLOBAL | \
|
||||
TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \
|
||||
TT_DESCRIPTOR_SECTION_DOMAIN(0) | \
|
||||
TT_DESCRIPTOR_SECTION_AP_RW_RW | \
|
||||
TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC)
|
||||
#define TT_DESCRIPTOR_SECTION_DEVICE (TT_DESCRIPTOR_TYPE_SECTION | \
|
||||
TT_DESCRIPTOR_SECTION_NS_NON_SECURE | \
|
||||
TT_DESCRIPTOR_SECTION_NG_GLOBAL | \
|
||||
TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \
|
||||
TT_DESCRIPTOR_SECTION_DOMAIN(0) | \
|
||||
TT_DESCRIPTOR_SECTION_AP_RW_RW | \
|
||||
TT_DESCRIPTOR_SECTION_CACHE_POLICY_SHAREABLE_DEVICE)
|
||||
#define TT_DESCRIPTOR_SECTION_UNCACHED (TT_DESCRIPTOR_TYPE_SECTION | \
|
||||
TT_DESCRIPTOR_SECTION_NS_NON_SECURE | \
|
||||
TT_DESCRIPTOR_SECTION_NG_GLOBAL | \
|
||||
TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \
|
||||
TT_DESCRIPTOR_SECTION_DOMAIN(0) | \
|
||||
TT_DESCRIPTOR_SECTION_AP_RW_RW | \
|
||||
TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE)
|
||||
|
||||
#endif // __ARM_V7_H__
|
||||
|
||||
84
ArmPkg/Include/Drivers/PL341Dmc.h
Normal file
84
ArmPkg/Include/Drivers/PL341Dmc.h
Normal file
@@ -0,0 +1,84 @@
|
||||
/** @file
|
||||
*
|
||||
* Copyright (c) 2011, ARM Limited. All rights reserved.
|
||||
*
|
||||
* This program and the accompanying materials
|
||||
* are licensed and made available under the terms and conditions of the BSD License
|
||||
* which accompanies this distribution. The full text of the license may be found at
|
||||
* http://opensource.org/licenses/bsd-license.php
|
||||
*
|
||||
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
*
|
||||
**/
|
||||
|
||||
#ifndef PL341DMC_H_
|
||||
#define PL341DMC_H_
|
||||
|
||||
|
||||
struct pl341_dmc_config {
|
||||
UINTN base; // base address for the controller
|
||||
UINTN has_qos; // has QoS registers
|
||||
UINTN max_chip; // number of memory chips accessible
|
||||
UINT32 refresh_prd;
|
||||
UINT32 cas_latency;
|
||||
UINT32 write_latency;
|
||||
UINT32 t_mrd;
|
||||
UINT32 t_ras;
|
||||
UINT32 t_rc;
|
||||
UINT32 t_rcd;
|
||||
UINT32 t_rfc;
|
||||
UINT32 t_rp;
|
||||
UINT32 t_rrd;
|
||||
UINT32 t_wr;
|
||||
UINT32 t_wtr;
|
||||
UINT32 t_xp;
|
||||
UINT32 t_xsr;
|
||||
UINT32 t_esr;
|
||||
UINT32 memory_cfg;
|
||||
UINT32 memory_cfg2;
|
||||
UINT32 memory_cfg3;
|
||||
UINT32 chip_cfg0;
|
||||
UINT32 chip_cfg1;
|
||||
UINT32 chip_cfg2;
|
||||
UINT32 chip_cfg3;
|
||||
UINT32 t_faw;
|
||||
};
|
||||
|
||||
/* Memory config bit fields */
|
||||
#define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_9 0x1
|
||||
#define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_10 0x2
|
||||
#define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_11 0x3
|
||||
#define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_12 0x4
|
||||
#define DMC_MEMORY_CONFIG_ROW_ADDRESS_11 (0x0 << 3)
|
||||
#define DMC_MEMORY_CONFIG_ROW_ADDRESS_12 (0x1 << 3)
|
||||
#define DMC_MEMORY_CONFIG_ROW_ADDRESS_13 (0x2 << 3)
|
||||
#define DMC_MEMORY_CONFIG_ROW_ADDRESS_14 (0x3 << 3)
|
||||
#define DMC_MEMORY_CONFIG_ROW_ADDRESS_15 (0x4 << 3)
|
||||
#define DMC_MEMORY_CONFIG_ROW_ADDRESS_16 (0x5 << 3)
|
||||
#define DMC_MEMORY_CONFIG_BURST_2 (0x1 << 15)
|
||||
#define DMC_MEMORY_CONFIG_BURST_4 (0x2 << 15)
|
||||
#define DMC_MEMORY_CONFIG_BURST_8 (0x3 << 15)
|
||||
#define DMC_MEMORY_CONFIG_BURST_16 (0x4 << 15)
|
||||
#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_1 (0x0 << 21)
|
||||
#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_2 (0x1 << 21)
|
||||
#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_3 (0x2 << 21)
|
||||
#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_4 (0x3 << 21)
|
||||
|
||||
#define DMC_MEMORY_CFG2_CLK_ASYNC (0x0 << 0)
|
||||
#define DMC_MEMORY_CFG2_CLK_SYNC (0x1 << 0)
|
||||
#define DMC_MEMORY_CFG2_DQM_INIT (0x1 << 2)
|
||||
#define DMC_MEMORY_CFG2_CKE_INIT (0x1 << 3)
|
||||
#define DMC_MEMORY_CFG2_BANK_BITS_2 (0x0 << 4)
|
||||
#define DMC_MEMORY_CFG2_BANK_BITS_3 (0x3 << 4)
|
||||
#define DMC_MEMORY_CFG2_MEM_WIDTH_16 (0x0 << 6)
|
||||
#define DMC_MEMORY_CFG2_MEM_WIDTH_32 (0x1 << 6)
|
||||
#define DMC_MEMORY_CFG2_MEM_WIDTH_64 (0x2 << 6)
|
||||
#define DMC_MEMORY_CFG2_MEM_WIDTH_RESERVED (0x3 << 6)
|
||||
|
||||
|
||||
|
||||
VOID PL341DmcInit(struct pl341_dmc_config *config);
|
||||
|
||||
|
||||
#endif /* PL341DMC_H_ */
|
||||
120
ArmPkg/Include/Drivers/PL390Gic.h
Normal file
120
ArmPkg/Include/Drivers/PL390Gic.h
Normal file
@@ -0,0 +1,120 @@
|
||||
/** @file
|
||||
*
|
||||
* Copyright (c) 2011, ARM Limited. All rights reserved.
|
||||
*
|
||||
* This program and the accompanying materials
|
||||
* are licensed and made available under the terms and conditions of the BSD License
|
||||
* which accompanies this distribution. The full text of the license may be found at
|
||||
* http://opensource.org/licenses/bsd-license.php
|
||||
*
|
||||
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
*
|
||||
**/
|
||||
|
||||
#ifndef __PL390GIC_H
|
||||
#define __PL390GIC_H
|
||||
|
||||
//
|
||||
// GIC definitions
|
||||
//
|
||||
|
||||
// Distributor
|
||||
#define GIC_ICDDCR 0x000 // Distributor Control Register
|
||||
#define GIC_ICDICTR 0x004 // Interrupt Controller Type Register
|
||||
#define GIC_ICDIIDR 0x008 // Implementer Identification Register
|
||||
|
||||
// each reg base below repeats for VE_NUM_GIC_REG_PER_INT_BITS (see GIC spec)
|
||||
#define GIC_ICDISR 0x080 // Interrupt Security Registers
|
||||
#define GIC_ICDISER 0x100 // Interrupt Set-Enable Registers
|
||||
#define GIC_ICDICER 0x180 // Interrupt Clear-Enable Registers
|
||||
#define GIC_ICDSPR 0x200 // Interrupt Set-Pending Registers
|
||||
#define GIC_ICDICPR 0x280 // Interrupt Clear-Pending Registers
|
||||
#define GIC_ICDABR 0x300 // Active Bit Registers
|
||||
|
||||
// each reg base below repeats for VE_NUM_GIC_REG_PER_INT_BYTES
|
||||
#define GIC_ICDIPR 0x400 // Interrupt Priority Registers
|
||||
|
||||
// each reg base below repeats for VE_NUM_GIC_INTERRUPTS
|
||||
#define GIC_ICDIPTR 0x800 // Interrupt Processor Target Registers
|
||||
#define GIC_ICDICFR 0xC00 // Interrupt Configuration Registers
|
||||
|
||||
// just one of these
|
||||
#define GIC_ICDSGIR 0xF00 // Software Generated Interrupt Register
|
||||
|
||||
// Cpu interface
|
||||
#define GIC_ICCICR 0x00 // CPU Interface Control Register
|
||||
#define GIC_ICCPMR 0x04 // Interrupt Priority Mask Register
|
||||
#define GIC_ICCBPR 0x08 // Binary Point Register
|
||||
#define GIC_ICCIAR 0x0C // Interrupt Acknowledge Register
|
||||
#define GIC_ICCEIOR 0x10 // End Of Interrupt Register
|
||||
#define GIC_ICCRPR 0x14 // Running Priority Register
|
||||
#define GIC_ICCPIR 0x18 // Highest Pending Interrupt Register
|
||||
#define GIC_ICCABPR 0x1C // Aliased Binary Point Register
|
||||
#define GIC_ICCIDR 0xFC // Identification Register
|
||||
|
||||
#define GIC_ICDSGIR_FILTER_TARGETLIST 0x0
|
||||
#define GIC_ICDSGIR_FILTER_EVERYONEELSE 0x1
|
||||
#define GIC_ICDSGIR_FILTER_ITSELF 0x2
|
||||
|
||||
//Bit-masks to configure the CPU Interface Control register
|
||||
#define GIC_ICCICR_ENABLE_SECURE(a) ((a << 0) & 0x01)
|
||||
#define GIC_ICCICR_ENABLE_NS(a) ((a << 1) & 0x02)
|
||||
#define GIC_ICCICR_ACK_CTL(a) ((a << 2) & 0x04)
|
||||
#define GIC_ICCICR_SIGNAL_SECURE_TO_FIQ(a)((a << 3) & 0x08)
|
||||
#define GIC_ICCICR_USE_SBPR(a) ((a << 4) & 0x10)
|
||||
|
||||
|
||||
//
|
||||
// GIC SEC interfaces
|
||||
//
|
||||
VOID
|
||||
EFIAPI
|
||||
PL390GicSetupNonSecure (
|
||||
IN INTN GicDistributorBase,
|
||||
IN INTN GicInterruptInterfaceBase
|
||||
);
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
PL390GicEnableInterruptInterface (
|
||||
IN INTN GicInterruptInterfaceBase
|
||||
);
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
PL390GicEnableDistributor (
|
||||
IN INTN GicDistributorBase
|
||||
);
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
PL390GicSendSgiTo (
|
||||
IN INTN GicDistributorBase,
|
||||
IN INTN TargetListFilter,
|
||||
IN INTN CPUTargetList
|
||||
);
|
||||
|
||||
UINT32
|
||||
EFIAPI
|
||||
PL390GicAcknowledgeSgiFrom (
|
||||
IN INTN GicInterruptInterfaceBase,
|
||||
IN INTN CoreId
|
||||
);
|
||||
|
||||
UINT32
|
||||
EFIAPI
|
||||
PL390GicAcknowledgeSgi2From (
|
||||
IN INTN GicInterruptInterfaceBase,
|
||||
IN INTN CoreId,
|
||||
IN INTN SgiId
|
||||
);
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
PL390GicSetPriorityMask (
|
||||
IN INTN GicInterruptInterfaceBase,
|
||||
IN INTN PriorityMask
|
||||
);
|
||||
|
||||
#endif
|
||||
@@ -43,7 +43,11 @@ typedef enum {
|
||||
ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED,
|
||||
ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,
|
||||
ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,
|
||||
ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
|
||||
ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,
|
||||
ARM_MEMORY_REGION_ATTRIBUTE_SECURE_UNCACHED_UNBUFFERED,
|
||||
ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_BACK,
|
||||
ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_THROUGH,
|
||||
ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE
|
||||
} ARM_MEMORY_REGION_ATTRIBUTES;
|
||||
|
||||
typedef struct {
|
||||
@@ -145,6 +149,12 @@ Cp15CacheInfo (
|
||||
VOID
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
EFIAPI
|
||||
ArmIsMPCore (
|
||||
VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmInvalidateDataCache (
|
||||
@@ -224,6 +234,12 @@ ArmDisableMmu (
|
||||
VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmDisableCachesAndMmu (
|
||||
VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmEnableInterrupts (
|
||||
@@ -241,6 +257,7 @@ EFIAPI
|
||||
ArmGetInterruptState (
|
||||
VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmEnableFiq (
|
||||
@@ -280,13 +297,13 @@ ArmSetDomainAccessControl (
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmSetTranslationTableBaseAddress (
|
||||
ArmSetTTBR0 (
|
||||
IN VOID *TranslationTableBase
|
||||
);
|
||||
|
||||
VOID *
|
||||
EFIAPI
|
||||
ArmGetTranslationTableBaseAddress (
|
||||
ArmGetTTBR0BaseAddress (
|
||||
VOID
|
||||
);
|
||||
|
||||
|
||||
22
ArmPkg/Include/Library/ArmMPCoreMailBoxLib.h
Normal file
22
ArmPkg/Include/Library/ArmMPCoreMailBoxLib.h
Normal file
@@ -0,0 +1,22 @@
|
||||
/** @file
|
||||
*
|
||||
* Copyright (c) 2011, ARM Limited. All rights reserved.
|
||||
*
|
||||
* This program and the accompanying materials
|
||||
* are licensed and made available under the terms and conditions of the BSD License
|
||||
* which accompanies this distribution. The full text of the license may be found at
|
||||
* http://opensource.org/licenses/bsd-license.php
|
||||
*
|
||||
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
*
|
||||
**/
|
||||
|
||||
#ifndef _ARM_MPCORE_MAILBOX_LIB_H_
|
||||
#define _ARM_MPCORE_MAILBOX_LIB_H_
|
||||
|
||||
VOID ArmClearMPCoreMailbox(VOID);
|
||||
|
||||
UINTN ArmGetMPCoreMailbox(VOID);
|
||||
|
||||
#endif
|
||||
69
ArmPkg/Include/Library/ArmTrustZoneLib.h
Normal file
69
ArmPkg/Include/Library/ArmTrustZoneLib.h
Normal file
@@ -0,0 +1,69 @@
|
||||
/** @file
|
||||
*
|
||||
* Copyright (c) 2011, ARM Limited. All rights reserved.
|
||||
*
|
||||
* This program and the accompanying materials
|
||||
* are licensed and made available under the terms and conditions of the BSD License
|
||||
* which accompanies this distribution. The full text of the license may be found at
|
||||
* http://opensource.org/licenses/bsd-license.php
|
||||
*
|
||||
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
*
|
||||
**/
|
||||
|
||||
#ifndef __ARM_TRUSTZONE_LIB_H__
|
||||
#define __ARM_TRUSTZONE_LIB_H__
|
||||
|
||||
#include <Uefi.h>
|
||||
|
||||
// Setup TZ Protection Controller
|
||||
#define TZPC_DECPROT_0 0
|
||||
#define TZPC_DECPROT_1 1
|
||||
#define TZPC_DECPROT_2 2
|
||||
#define TZPC_DECPROT_MAX 2
|
||||
|
||||
/**
|
||||
FIXME: Need documentation
|
||||
**/
|
||||
EFI_STATUS TZPCSetDecProtBits(UINTN tzpc_base, UINTN tzpc_id, UINTN bits);
|
||||
|
||||
/**
|
||||
FIXME: Need documentation
|
||||
**/
|
||||
EFI_STATUS TZPCClearDecProtBits(UINTN tzpc_base, UINTN tzpc_id, UINTN bits);
|
||||
|
||||
// Setup TZ Address Space Controller
|
||||
#define TZASC_REGION_ENABLED 1
|
||||
#define TZASC_REGION_DISABLED 0
|
||||
#define TZASC_REGION_SIZE_32KB 0xE
|
||||
#define TZASC_REGION_SIZE_64KB 0xF
|
||||
#define TZASC_REGION_SIZE_128KB 0x10
|
||||
#define TZASC_REGION_SIZE_256KB 0x11
|
||||
#define TZASC_REGION_SIZE_512KB 0x12
|
||||
#define TZASC_REGION_SIZE_1MB 0x13
|
||||
#define TZASC_REGION_SIZE_2MB 0x14
|
||||
#define TZASC_REGION_SIZE_4MB 0x15
|
||||
#define TZASC_REGION_SIZE_8MB 0x16
|
||||
#define TZASC_REGION_SIZE_16MB 0x17
|
||||
#define TZASC_REGION_SIZE_32MB 0x18
|
||||
#define TZASC_REGION_SIZE_64MB 0x19
|
||||
#define TZASC_REGION_SIZE_128MB 0x1A
|
||||
#define TZASC_REGION_SIZE_256MB 0x1B
|
||||
#define TZASC_REGION_SIZE_512MB 0x1C
|
||||
#define TZASC_REGION_SIZE_1GB 0x1D
|
||||
#define TZASC_REGION_SIZE_2GB 0x1E
|
||||
#define TZASC_REGION_SIZE_4GB 0x1F
|
||||
#define TZASC_REGION_SECURITY_SR (1 << 3)
|
||||
#define TZASC_REGION_SECURITY_SW (1 << 2)
|
||||
#define TZASC_REGION_SECURITY_SRW (TZASC_REGION_SECURITY_SR|TZASC_REGION_SECURITY_SW)
|
||||
#define TZASC_REGION_SECURITY_NSR (1 << 1)
|
||||
#define TZASC_REGION_SECURITY_NSW 1
|
||||
#define TZASC_REGION_SECURITY_NSRW (TZASC_REGION_SECURITY_NSR|TZASC_REGION_SECURITY_NSW)
|
||||
|
||||
/**
|
||||
FIXME: Need documentation
|
||||
**/
|
||||
EFI_STATUS TZASCSetRegion(UINTN tzasc_base, UINTN region_id, UINTN enabled, UINTN low_address, UINTN high_address, UINTN size, UINTN security);
|
||||
|
||||
#endif
|
||||
38
ArmPkg/Include/Library/BdsUnixLib.h
Normal file
38
ArmPkg/Include/Library/BdsUnixLib.h
Normal file
@@ -0,0 +1,38 @@
|
||||
/** @file
|
||||
*
|
||||
* Copyright (c) 2011, ARM Limited. All rights reserved.
|
||||
*
|
||||
* This program and the accompanying materials
|
||||
* are licensed and made available under the terms and conditions of the BSD License
|
||||
* which accompanies this distribution. The full text of the license may be found at
|
||||
* http://opensource.org/licenses/bsd-license.php
|
||||
*
|
||||
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
*
|
||||
**/
|
||||
|
||||
#ifndef __BDS_ENTRY_H__
|
||||
#define __BDS_ENTRY_H__
|
||||
|
||||
EFI_STATUS
|
||||
BdsConnectAllDrivers ( VOID );
|
||||
|
||||
EFI_STATUS
|
||||
BdsBootLinux (
|
||||
IN CONST CHAR16* LinuxKernel,
|
||||
IN CONST CHAR8* ATag,
|
||||
IN CONST CHAR16* Fdt
|
||||
);
|
||||
|
||||
EFI_STATUS
|
||||
BdsLoadApplication (
|
||||
IN CHAR16* EfiApp
|
||||
);
|
||||
|
||||
EFI_STATUS
|
||||
BdsLoadApplicationFromPath (
|
||||
IN CHAR16* EfiAppPath
|
||||
);
|
||||
|
||||
#endif
|
||||
62
ArmPkg/Include/Library/L2X0CacheLib.h
Normal file
62
ArmPkg/Include/Library/L2X0CacheLib.h
Normal file
@@ -0,0 +1,62 @@
|
||||
/** @file
|
||||
*
|
||||
* Copyright (c) 2011, ARM Limited. All rights reserved.
|
||||
*
|
||||
* This program and the accompanying materials
|
||||
* are licensed and made available under the terms and conditions of the BSD License
|
||||
* which accompanies this distribution. The full text of the license may be found at
|
||||
* http://opensource.org/licenses/bsd-license.php
|
||||
*
|
||||
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
*
|
||||
**/
|
||||
|
||||
#ifndef L2CACHELIB_H_
|
||||
#define L2CACHELIB_H_
|
||||
|
||||
#define L2_LATENCY 7
|
||||
|
||||
#define L2_TAG_ACCESS_LATENCY L2_LATENCY
|
||||
#define L2_TAG_SETUP_LATENCY L2_LATENCY
|
||||
#define L2_DATA_ACCESS_LATENCY L2_LATENCY
|
||||
#define L2_DATA_SETUP_LATENCY L2_LATENCY
|
||||
|
||||
|
||||
#define L2X0_CACHEID 0x000
|
||||
#define L2X0_CTRL 0x100
|
||||
#define L2X0_AUXCTRL 0x104
|
||||
#define L230_TAG_LATENCY 0x108
|
||||
#define L230_DATA_LATENCY 0x10C
|
||||
#define L2X0_INTCLEAR 0x220
|
||||
#define L2X0_CACHE_SYNC 0x730
|
||||
#define L2X0_INVWAY 0x77C
|
||||
#define L2X0_CLEAN_WAY 0x7BC
|
||||
#define L2X0_PFCTRL 0xF60
|
||||
#define L2X0_PWRCTRL 0xF80
|
||||
|
||||
#define L2X0_CACHEID_IMPLEMENTER_ARM 0x41
|
||||
#define L2X0_CACHEID_PARTNUM_PL310 0x03
|
||||
|
||||
#define L2X0_CTRL_ENABLED 0x1
|
||||
#define L2X0_CTRL_DISABLED 0x0
|
||||
|
||||
#define L2X0_AUXCTRL_EXCLUSIVE (1<<12)
|
||||
#define L2X0_AUXCTRL_WAYSIZE_16KB (0x001 << 17)
|
||||
#define L2X0_AUXCTRL_WAYSIZE_32KB (0x010 << 17)
|
||||
#define L2X0_AUXCTRL_WAYSIZE_64KB (0x011 << 17)
|
||||
#define L2X0_AUXCTRL_WAYSIZE_128KB (0x100 << 17)
|
||||
#define L2X0_AUXCTRL_WAYSIZE_256KB (0x101 << 17)
|
||||
#define L2X0_AUXCTRL_WAYSIZE_512KB (0x110 << 17)
|
||||
#define L2X0_AUXCTRL_EM (1 << 20)
|
||||
#define L2x0_AUXCTRL_AW_AWCACHE (0x00 << 23)
|
||||
#define L2x0_AUXCTRL_AW_NOALLOC (0x01 << 23)
|
||||
#define L2x0_AUXCTRL_AW_OVERRIDE (0x10 << 23)
|
||||
#define L2X0_AUXCTRL_SBO (1 << 25)
|
||||
#define L2X0_AUXCTRL_NSAC (1 << 27)
|
||||
#define L2x0_AUXCTRL_DPREFETCH (1 << 28)
|
||||
#define L2x0_AUXCTRL_IPREFETCH (1 << 29)
|
||||
|
||||
VOID L2x0CacheInit(UINTN L2x0Base, BOOLEAN CacheEnabled);
|
||||
|
||||
#endif /* L2CACHELIB_H_ */
|
||||
112
ArmPkg/Include/Protocol/MmcHost.h
Normal file
112
ArmPkg/Include/Protocol/MmcHost.h
Normal file
@@ -0,0 +1,112 @@
|
||||
/** @file
|
||||
Definition of the MMC Host Protocol
|
||||
|
||||
Copyright (c) 2011, ARM Limited. All rights reserved.
|
||||
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __MMC_HOST_H__
|
||||
#define __MMC_HOST_H__
|
||||
|
||||
///
|
||||
/// Global ID for the MMC Host Protocol
|
||||
///
|
||||
#define EFI_MMC_HOST_PROTOCOL_GUID \
|
||||
{ 0x3e591c00, 0x9e4a, 0x11df, {0x92, 0x44, 0x00, 0x02, 0xA5, 0xD5, 0xC5, 0x1B } }
|
||||
|
||||
#define MMC_RESPONSE_TYPE_R1 0
|
||||
#define MMC_RESPONSE_TYPE_R1b 0
|
||||
#define MMC_RESPONSE_TYPE_R2 1
|
||||
#define MMC_RESPONSE_TYPE_R3 0
|
||||
#define MMC_RESPONSE_TYPE_R6 0
|
||||
#define MMC_RESPONSE_TYPE_R7 0
|
||||
#define MMC_RESPONSE_TYPE_OCR 0
|
||||
#define MMC_RESPONSE_TYPE_CID 1
|
||||
#define MMC_RESPONSE_TYPE_CSD 1
|
||||
#define MMC_RESPONSE_TYPE_RCA 0
|
||||
|
||||
typedef UINT32 MMC_RESPONSE_TYPE;
|
||||
|
||||
typedef UINT32 MMC_CMD;
|
||||
|
||||
#define MMC_CMD_WAIT_RESPONSE (1 << 16)
|
||||
#define MMC_CMD_LONG_RESPONSE (1 << 17)
|
||||
|
||||
#define MMC_INDX(CMD_INDX) (CMD_INDX & 0xFFFF)
|
||||
|
||||
#define MMC_CMD0 MMC_INDX(0)
|
||||
#define MMC_CMD1 (MMC_INDX(1) | MMC_CMD_WAIT_RESPONSE)
|
||||
#define MMC_CMD2 (MMC_INDX(2) | MMC_CMD_WAIT_RESPONSE | MMC_CMD_LONG_RESPONSE)
|
||||
#define MMC_CMD3 (MMC_INDX(3) | MMC_CMD_WAIT_RESPONSE)
|
||||
#define MMC_CMD5 (MMC_INDX(5) | MMC_CMD_WAIT_RESPONSE)
|
||||
#define MMC_CMD7 (MMC_INDX(7) | MMC_CMD_WAIT_RESPONSE)
|
||||
#define MMC_CMD8 (MMC_INDX(8) | MMC_CMD_WAIT_RESPONSE)
|
||||
#define MMC_CMD9 (MMC_INDX(9) | MMC_CMD_WAIT_RESPONSE | MMC_CMD_LONG_RESPONSE)
|
||||
#define MMC_CMD11 (MMC_INDX(11) | MMC_CMD_WAIT_RESPONSE)
|
||||
#define MMC_CMD12 (MMC_INDX(12) | MMC_CMD_WAIT_RESPONSE)
|
||||
#define MMC_CMD13 (MMC_INDX(13) | MMC_CMD_WAIT_RESPONSE)
|
||||
#define MMC_CMD16 (MMC_INDX(16) | MMC_CMD_WAIT_RESPONSE)
|
||||
#define MMC_CMD17 (MMC_INDX(17) | MMC_CMD_WAIT_RESPONSE)
|
||||
#define MMC_CMD18 (MMC_INDX(18) | MMC_CMD_WAIT_RESPONSE)
|
||||
#define MMC_CMD20 (MMC_INDX(20) | MMC_CMD_WAIT_RESPONSE)
|
||||
#define MMC_CMD23 (MMC_INDX(23) | MMC_CMD_WAIT_RESPONSE)
|
||||
#define MMC_CMD24 (MMC_INDX(24) | MMC_CMD_WAIT_RESPONSE)
|
||||
#define MMC_CMD55 (MMC_INDX(55) | MMC_CMD_WAIT_RESPONSE)
|
||||
#define MMC_ACMD41 (MMC_INDX(41) | MMC_CMD_WAIT_RESPONSE)
|
||||
|
||||
typedef enum _MMC_STATE {
|
||||
MmcInvalidState = 0,
|
||||
MmcHwInitializationState,
|
||||
MmcIdleState,
|
||||
MmcReadyState,
|
||||
MmcIdentificationState,
|
||||
MmcStandByState,
|
||||
MmcTransferState,
|
||||
MmcSendingDataState,
|
||||
MmcReceiveDataState,
|
||||
MmcProgrammingState,
|
||||
MmcDisconnectState,
|
||||
} MMC_STATE;
|
||||
|
||||
typedef BOOLEAN (*MMC_ISCARDPRESENT)();
|
||||
|
||||
typedef BOOLEAN (*MMC_ISREADONLY)();
|
||||
|
||||
typedef EFI_STATUS (*MMC_BUILDDEVICEPATH)(EFI_DEVICE_PATH_PROTOCOL **DevicePath);
|
||||
|
||||
typedef EFI_STATUS (*MMC_NOTIFYSTATE)(MMC_STATE State);
|
||||
|
||||
typedef EFI_STATUS (*MMC_SENDCOMMAND)(MMC_CMD Cmd, UINT32 Argument);
|
||||
|
||||
typedef EFI_STATUS (*MMC_RECEIVERESPONSE)(MMC_RESPONSE_TYPE Type, UINT32* Buffer);
|
||||
|
||||
typedef EFI_STATUS (*MMC_READBLOCKDATA)(EFI_LBA Lba, UINTN Length, UINT32* Buffer);
|
||||
|
||||
typedef EFI_STATUS (*MMC_WRITEBLOCKDATA)(EFI_LBA Lba, UINTN Length, UINT32* Buffer);
|
||||
|
||||
typedef struct _EFI_MMC_HOST_PROTOCOL {
|
||||
MMC_ISCARDPRESENT IsCardPresent;
|
||||
MMC_ISREADONLY IsReadOnly;
|
||||
MMC_BUILDDEVICEPATH BuildDevicePath;
|
||||
|
||||
MMC_NOTIFYSTATE NotifyState;
|
||||
|
||||
MMC_SENDCOMMAND SendCommand;
|
||||
MMC_RECEIVERESPONSE ReceiveResponse;
|
||||
|
||||
MMC_READBLOCKDATA ReadBlockData;
|
||||
MMC_WRITEBLOCKDATA WriteBlockData;
|
||||
} EFI_MMC_HOST_PROTOCOL;
|
||||
|
||||
extern EFI_GUID gEfiMmcHostProtocolGuid;
|
||||
|
||||
#endif
|
||||
|
||||
Reference in New Issue
Block a user