sravan/system76-edk2
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Sync up ArmPkg with patch from mailing list. Changed name of BdsLib.h to BdsUnixLib.h and fixed a lot of issues with Xcode building.

Browse Source 
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11293 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
andrewfish
2011-02-02 22:35:30 +00:00
parent 7373d15a98
commit 1bfda055df
113 changed files with 7979 additions and 964 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
ArmPkg/Library/ArmDmaLib/ArmDmaLib.c
View File

@@ -215,7 +215,7 @@ DmaAllocateBuffer (
//
if (MemoryType == EfiBootServicesData) {
*HostAddress = UncachedAllocatePages (Pages);
} else if (MemoryType != EfiRuntimeServicesData) {
} else if (MemoryType == EfiRuntimeServicesData) {
*HostAddress = UncachedAllocateRuntimePages (Pages);
} else {
return EFI_INVALID_PARAMETER;

19
ArmPkg/Library/ArmLib/Arm11/Arm11Lib.c
View File

@@ -31,14 +31,25 @@ FillTranslationTable (
switch (MemoryRegion->Attributes) {
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK;
Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(0);
break;
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH;
Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0);
break;
case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);
break;
case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_BACK:
Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(1);
break;
case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_THROUGH:
Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(1);
break;
case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_UNCACHED_UNBUFFERED:
Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(1);
break;
default:
Attributes = TT_DESCRIPTOR_SECTION_UNCACHED;
Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);
break;
}
@@ -93,7 +104,7 @@ ArmConfigureMmu (
MemoryTable++;
}
ArmSetTranslationTableBaseAddress(TranslationTable);
ArmSetTTBR0(TranslationTable);
ArmSetDomainAccessControl(DOMAIN_ACCESS_CONTROL_NONE(15) |
DOMAIN_ACCESS_CONTROL_NONE(14) |

63
ArmPkg/Library/ArmLib/Arm11/Arm11Support.S
View File

@@ -12,46 +12,29 @@
#
#------------------------------------------------------------------------------
#include <AsmMacroIoLib.h>
.text
.align 2
.globl ASM_PFX(ArmCleanInvalidateDataCache)
INTERWORK_FUNC(ArmCleanInvalidateDataCache)
.globl ASM_PFX(ArmCleanDataCache)
INTERWORK_FUNC(ArmCleanDataCache)
.globl ASM_PFX(ArmInvalidateDataCache)
INTERWORK_FUNC(ArmInvalidateDataCache)
.globl ASM_PFX(ArmInvalidateInstructionCache)
INTERWORK_FUNC(ArmInvalidateInstructionCache)
.globl ASM_PFX(ArmInvalidateDataCacheEntryByMVA)
INTERWORK_FUNC(ArmInvalidateDataCacheEntryByMVA)
.globl ASM_PFX(ArmCleanDataCacheEntryByMVA)
INTERWORK_FUNC(ArmCleanDataCacheEntryByMVA)
.globl ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA)
INTERWORK_FUNC(ArmCleanInvalidateDataCacheEntryByMVA)
.globl ASM_PFX(ArmEnableMmu)
INTERWORK_FUNC(ArmEnableMmu)
.globl ASM_PFX(ArmDisableMmu)
INTERWORK_FUNC(ArmDisableMmu)
.globl ASM_PFX(ArmMmuEnabled)
INTERWORK_FUNC(ArmMmuEnabled)
.globl ASM_PFX(ArmEnableDataCache)
INTERWORK_FUNC(ArmEnableDataCache)
.globl ASM_PFX(ArmDisableDataCache)
INTERWORK_FUNC(ArmDisableDataCache)
.globl ASM_PFX(ArmEnableInstructionCache)
INTERWORK_FUNC(ArmEnableInstructionCache)
.globl ASM_PFX(ArmDisableInstructionCache)
INTERWORK_FUNC(ArmDisableInstructionCache)
.globl ASM_PFX(ArmEnableBranchPrediction)
INTERWORK_FUNC(ArmEnableBranchPrediction)
.globl ASM_PFX(ArmDisableBranchPrediction)
INTERWORK_FUNC(ArmDisableBranchPrediction)
.globl ASM_PFX(ArmDataMemoryBarrier)
INTERWORK_FUNC(ArmDataMemoryBarrier)
.globl ASM_PFX(ArmDataSyncronizationBarrier)
INTERWORK_FUNC(ArmDataSyncronizationBarrier)
.globl ASM_PFX(ArmInstructionSynchronizationBarrier)
INTERWORK_FUNC(ArmInstructionSynchronizationBarrier)
GCC_ASM_EXPORT(ArmCleanInvalidateDataCache)
GCC_ASM_EXPORT(ArmCleanDataCache)
GCC_ASM_EXPORT(ArmInvalidateDataCache)
GCC_ASM_EXPORT(ArmInvalidateInstructionCache)
GCC_ASM_EXPORT(ArmInvalidateDataCacheEntryByMVA)
GCC_ASM_EXPORT(ArmCleanDataCacheEntryByMVA)
GCC_ASM_EXPORT(ArmCleanInvalidateDataCacheEntryByMVA)
GCC_ASM_EXPORT(ArmEnableMmu)
GCC_ASM_EXPORT(ArmDisableMmu)
GCC_ASM_EXPORT(ArmMmuEnabled)
GCC_ASM_EXPORT(ArmEnableDataCache)
GCC_ASM_EXPORT(ArmDisableDataCache)
GCC_ASM_EXPORT(ArmEnableInstructionCache)
GCC_ASM_EXPORT(ArmDisableInstructionCache)
GCC_ASM_EXPORT(ArmEnableBranchPrediction)
GCC_ASM_EXPORT(ArmDisableBranchPrediction)
GCC_ASM_EXPORT(ArmDataMemoryBarrier)
GCC_ASM_EXPORT(ArmDataSyncronizationBarrier)
GCC_ASM_EXPORT(ArmInstructionSynchronizationBarrier)
.set DC_ON, (0x1<<2)
@@ -116,14 +99,14 @@ ASM_PFX(ArmDisableMmu):
bx LR
ASM_PFX(ArmEnableDataCache):
ldr R1,=DC_ON
LoadConstantToReg(DC_ON, R1) @ldr R1,=DC_ON
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
orr R0,R0,R1 @Set C bit
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
bx LR
ASM_PFX(ArmDisableDataCache):
ldr R1,=DC_ON
LoadConstantToReg(DC_ON, R1) @ldr R1,=DC_ON
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
bic R0,R0,R1 @Clear C bit
mcr p15,0,r0,c1,c0,0 @Write control register configuration data

9
ArmPkg/Library/ArmLib/Arm9/Arm9Lib.c
View File

@@ -16,6 +16,7 @@
#include <Library/ArmLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/DebugLib.h>
VOID
FillTranslationTable (
@@ -37,6 +38,12 @@ FillTranslationTable (
Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH;
break;
case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
Attributes = TT_DESCRIPTOR_SECTION_UNCACHED_UNBUFFERED;
break;
case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_BACK:
case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_THROUGH:
case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_UNCACHED_UNBUFFERED:
ASSERT(0); // Trustzone is not supported on ARMv5
default:
Attributes = TT_DESCRIPTOR_SECTION_UNCACHED_UNBUFFERED;
break;
@@ -93,7 +100,7 @@ ArmConfigureMmu (
MemoryTable++;
}
ArmSetTranslationTableBaseAddress(TranslationTable);
ArmSetTTBR0(TranslationTable);
ArmSetDomainAccessControl(DOMAIN_ACCESS_CONTROL_NONE(15) |
DOMAIN_ACCESS_CONTROL_NONE(14) |

57
ArmPkg/Library/ArmLib/Arm9/Arm9Support.S
View File

@@ -14,44 +14,25 @@
.text
.align 2
.globl ASM_PFX(ArmCleanInvalidateDataCache)
INTERWORK_FUNC(ArmCleanInvalidateDataCache)
.globl ASM_PFX(ArmCleanDataCache)
INTERWORK_FUNC(ArmCleanDataCache)
.globl ASM_PFX(ArmInvalidateDataCache)
INTERWORK_FUNC(ArmInvalidateDataCache)
.globl ASM_PFX(ArmInvalidateInstructionCache)
INTERWORK_FUNC(ArmInvalidateInstructionCache)
.globl ASM_PFX(ArmInvalidateDataCacheEntryByMVA)
INTERWORK_FUNC(ArmInvalidateDataCacheEntryByMVA)
.globl ASM_PFX(ArmCleanDataCacheEntryByMVA)
INTERWORK_FUNC(ArmCleanDataCacheEntryByMVA)
.globl ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA)
INTERWORK_FUNC(ArmCleanInvalidateDataCacheEntryByMVA)
.globl ASM_PFX(ArmEnableMmu)
INTERWORK_FUNC(ArmEnableMmu)
.globl ASM_PFX(ArmDisableMmu)
INTERWORK_FUNC(ArmDisableMmu)
.globl ASM_PFX(ArmMmuEnabled)
INTERWORK_FUNC(ArmMmuEnabled)
.globl ASM_PFX(ArmEnableDataCache)
INTERWORK_FUNC(ArmEnableDataCache)
.globl ASM_PFX(ArmDisableDataCache)
INTERWORK_FUNC(ArmDisableDataCache)
.globl ASM_PFX(ArmEnableInstructionCache)
INTERWORK_FUNC(ArmEnableInstructionCache)
.globl ASM_PFX(ArmDisableInstructionCache)
INTERWORK_FUNC(ArmDisableInstructionCache)
.globl ASM_PFX(ArmEnableBranchPrediction)
INTERWORK_FUNC(ArmEnableBranchPrediction)
.globl ASM_PFX(ArmDisableBranchPrediction)
INTERWORK_FUNC(ArmDisableBranchPrediction)
.globl ASM_PFX(ArmDataMemoryBarrier)
INTERWORK_FUNC(ArmDataMemoryBarrier)
.globl ASM_PFX(ArmDataSyncronizationBarrier)
INTERWORK_FUNC(ArmDataSyncronizationBarrier)
.globl ASM_PFX(ArmInstructionSynchronizationBarrier)
INTERWORK_FUNC(ArmInstructionSynchronizationBarrier)
GCC_ASM_EXPORT(ArmCleanInvalidateDataCache)
GCC_ASM_EXPORT(ArmCleanDataCache)
GCC_ASM_EXPORT(ArmInvalidateDataCache)
GCC_ASM_EXPORT(ArmInvalidateInstructionCache)
GCC_ASM_EXPORT(ArmInvalidateDataCacheEntryByMVA)
GCC_ASM_EXPORT(ArmCleanDataCacheEntryByMVA)
GCC_ASM_EXPORT(ArmCleanInvalidateDataCacheEntryByMVA)
GCC_ASM_EXPORT(ArmEnableMmu)
GCC_ASM_EXPORT(ArmDisableMmu)
GCC_ASM_EXPORT(ArmMmuEnabled)
GCC_ASM_EXPORT(ArmEnableDataCache)
GCC_ASM_EXPORT(ArmDisableDataCache)
GCC_ASM_EXPORT(ArmEnableInstructionCache)
GCC_ASM_EXPORT(ArmDisableInstructionCache)
GCC_ASM_EXPORT(ArmEnableBranchPrediction)
GCC_ASM_EXPORT(ArmDisableBranchPrediction)
GCC_ASM_EXPORT(ArmDataMemoryBarrier)
GCC_ASM_EXPORT(ArmDataSyncronizationBarrier)
GCC_ASM_EXPORT(ArmInstructionSynchronizationBarrier)
.set DC_ON, (1<<2)

132
ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.S
View File

@@ -12,44 +12,36 @@
#
#------------------------------------------------------------------------------
.globl ASM_PFX(Cp15IdCode)
INTERWORK_FUNC(Cp15IdCode)
.globl ASM_PFX(Cp15CacheInfo)
INTERWORK_FUNC(Cp15CacheInfo)
.globl ASM_PFX(ArmEnableInterrupts)
INTERWORK_FUNC(ArmEnableInterrupts)
.globl ASM_PFX(ArmDisableInterrupts)
INTERWORK_FUNC(ArmDisableInterrupts)
.globl ASM_PFX(ArmGetInterruptState)
INTERWORK_FUNC(ArmGetInterruptState)
.globl ASM_PFX(ArmEnableFiq)
INTERWORK_FUNC(ArmEnableFiq)
.globl ASM_PFX(ArmDisableFiq)
INTERWORK_FUNC(ArmDisableFiq)
.globl ASM_PFX(ArmGetFiqState)
INTERWORK_FUNC(ArmGetFiqState)
.globl ASM_PFX(ArmInvalidateTlb)
INTERWORK_FUNC(ArmInvalidateTlb)
.globl ASM_PFX(ArmSetTranslationTableBaseAddress)
INTERWORK_FUNC(ArmSetTranslationTableBaseAddress)
.globl ASM_PFX(ArmGetTranslationTableBaseAddress)
INTERWORK_FUNC(ArmGetTranslationTableBaseAddress)
.globl ASM_PFX(ArmSetDomainAccessControl)
INTERWORK_FUNC(ArmSetDomainAccessControl)
.globl ASM_PFX(ArmUpdateTranslationTableEntry)
INTERWORK_FUNC(ArmUpdateTranslationTableEntry)
.globl ASM_PFX(CPSRMaskInsert)
INTERWORK_FUNC(CPSRMaskInsert)
.globl ASM_PFX(CPSRRead)
INTERWORK_FUNC(CPSRRead)
.globl ASM_PFX(ReadCCSIDR)
INTERWORK_FUNC(ReadCCSIDR)
.globl ASM_PFX(ReadCLIDR)
INTERWORK_FUNC(ReadCLIDR)
#include <AsmMacroIoLib.h>
.text
.align 2
GCC_ASM_EXPORT(Cp15IdCode)
GCC_ASM_EXPORT(Cp15CacheInfo)
GCC_ASM_EXPORT(ArmIsMPCore)
GCC_ASM_EXPORT(ArmEnableAsynchronousAbort)
GCC_ASM_EXPORT(ArmDisableAsynchronousAbort)
GCC_ASM_EXPORT(ArmEnableIrq)
GCC_ASM_EXPORT(ArmDisableIrq)
GCC_ASM_EXPORT(ArmGetInterruptState)
GCC_ASM_EXPORT(ArmEnableFiq)
GCC_ASM_EXPORT(ArmDisableFiq)
GCC_ASM_EXPORT(ArmEnableInterrupts)
GCC_ASM_EXPORT(ArmDisableInterrupts)
GCC_ASM_EXPORT(ArmGetFiqState)
GCC_ASM_EXPORT(ArmInvalidateTlb)
GCC_ASM_EXPORT(ArmSetTTBR0)
GCC_ASM_EXPORT(ArmGetTTBR0BaseAddress)
GCC_ASM_EXPORT(ArmSetDomainAccessControl)
GCC_ASM_EXPORT(ArmUpdateTranslationTableEntry)
GCC_ASM_EXPORT(CPSRMaskInsert)
GCC_ASM_EXPORT(CPSRRead)
GCC_ASM_EXPORT(ReadCCSIDR)
GCC_ASM_EXPORT(ReadCLIDR)
#------------------------------------------------------------------------------
ASM_PFX(Cp15IdCode):
@@ -60,35 +52,67 @@ ASM_PFX(Cp15CacheInfo):
mrc p15,0,R0,c0,c0,1
bx LR
ASM_PFX(ArmEnableInterrupts):
cpsie i
bx LR
ASM_PFX(ArmIsMPCore):
mrc p15,0,R0,c0,c0,5
// Get Multiprocessing extension (bit31) & U bit (bit30)
and R0, R0, #0xC0000000
// if bit30 == 0 then the processor is part of a multiprocessor system)
and R0, R0, #0x80000000
bx LR
ASM_PFX(ArmDisableInterrupts):
ASM_PFX(ArmEnableAsynchronousAbort):
cpsie a
isb
bx LR
ASM_PFX(ArmDisableAsynchronousAbort):
cpsid a
isb
bx LR
ASM_PFX(ArmEnableIrq):
cpsie i
isb
bx LR
ASM_PFX(ArmDisableIrq):
cpsid i
bx LR
isb
bx LR
ASM_PFX(ArmGetInterruptState):
mrs R0,CPSR
tst R0,#0x80 @Check if IRQ is enabled.
moveq R0,#1
movne R0,#0
bx LR
mrs R0,CPSR
tst R0,#0x80 @Check if IRQ is enabled.
moveq R0,#1
movne R0,#0
bx LR
ASM_PFX(ArmEnableFiq):
cpsie f
bx LR
isb
bx LR
ASM_PFX(ArmDisableFiq):
cpsid f
bx LR
isb
bx LR
ASM_PFX(ArmEnableInterrupts):
cpsie if
isb
bx LR
ASM_PFX(ArmDisableInterrupts):
cpsid if
isb
bx LR
ASM_PFX(ArmGetFiqState):
mrs R0,CPSR
tst R0,#0x40 @Check if FIQ is enabled.
moveq R0,#1
movne R0,#0
bx LR
mrs R0,CPSR
tst R0,#0x40 @Check if FIQ is enabled.
moveq R0,#1
movne R0,#0
bx LR
ASM_PFX(ArmInvalidateTlb):
mov r0,#0
@@ -98,13 +122,15 @@ ASM_PFX(ArmInvalidateTlb):
isb
bx lr
ASM_PFX(ArmSetTranslationTableBaseAddress):
ASM_PFX(ArmSetTTBR0):
mcr p15,0,r0,c2,c0,0
isb
bx lr
ASM_PFX(ArmGetTranslationTableBaseAddress):
ASM_PFX(ArmGetTTBR0BaseAddress):
mrc p15,0,r0,c2,c0,0
LoadConstantToReg(0xFFFFC000, r1)
and r0, r0, r1
isb
bx lr

72
ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.asm
View File

@@ -15,15 +15,20 @@
EXPORT Cp15IdCode
EXPORT Cp15CacheInfo
EXPORT ArmEnableInterrupts
EXPORT ArmDisableInterrupts
EXPORT ArmIsMPCore
EXPORT ArmEnableAsynchronousAbort
EXPORT ArmDisableAsynchronousAbort
EXPORT ArmEnableIrq
EXPORT ArmDisableIrq
EXPORT ArmGetInterruptState
EXPORT ArmEnableFiq
EXPORT ArmDisableFiq
EXPORT ArmEnableInterrupts
EXPORT ArmDisableInterrupts
EXPORT ArmGetFiqState
EXPORT ArmInvalidateTlb
EXPORT ArmSetTranslationTableBaseAddress
EXPORT ArmGetTranslationTableBaseAddress
EXPORT ArmSetTTBR0
EXPORT ArmGetTTBR0BaseAddress
EXPORT ArmSetDomainAccessControl
EXPORT ArmUpdateTranslationTableEntry
EXPORT CPSRMaskInsert
@@ -44,27 +49,59 @@ Cp15CacheInfo
mrc p15,0,R0,c0,c0,1
bx LR
ArmEnableInterrupts
ArmIsMPCore
mrc p15,0,R0,c0,c0,5
// Get Multiprocessing extension (bit31) & U bit (bit30)
and R0, R0, #0xC0000000
// if bit30 == 0 then the processor is part of a multiprocessor system)
and R0, R0, #0x80000000
bx LR
ArmEnableAsynchronousAbort
cpsie a
isb
bx LR
ArmDisableAsynchronousAbort
cpsid a
isb
bx LR
ArmEnableIrq
cpsie i
isb
bx LR
ArmDisableInterrupts
ArmDisableIrq
cpsid i
bx LR
ArmGetInterruptState
mrs R0,CPSR
tst R0,#0x80 ;Check if IRQ is enabled.
moveq R0,#1
movne R0,#0
isb
bx LR
ArmEnableFiq
cpsie f
isb
bx LR
ArmDisableFiq
cpsid f
isb
bx LR
ArmEnableInterrupts
cpsie if
isb
bx LR
ArmDisableInterrupts
cpsid if
isb
bx LR
ArmGetInterruptState
mrs R0,CPSR
tst R0,#0x80 ;Check if IRQ is enabled.
moveq R0,#1
movne R0,#0
bx LR
ArmGetFiqState
@@ -82,13 +119,15 @@ ArmInvalidateTlb
isb
bx lr
ArmSetTranslationTableBaseAddress
ArmSetTTBR0
mcr p15,0,r0,c2,c0,0
isb
bx lr
ArmGetTranslationTableBaseAddress
ArmGetTTBR0BaseAddress
mrc p15,0,r0,c2,c0,0
ldr r1, = 0xFFFFC000
and r0, r0, r1
isb
bx lr
@@ -150,7 +189,4 @@ ReadCLIDR
mrc p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register
bx lr
END

124
ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.c
View File

@@ -15,113 +15,10 @@
#include <Chipset/ArmV7.h>
#include <Library/ArmLib.h>
#include <Library/BaseLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/IoLib.h>
#include "ArmV7Lib.h"
#include "ArmLibPrivate.h"
VOID
FillTranslationTable (
IN UINT32 *TranslationTable,
IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryRegion
)
{
UINT32 *Entry;
UINTN Sections;
UINTN Index;
UINT32 Attributes;
UINT32 PhysicalBase = MemoryRegion->PhysicalBase;
switch (MemoryRegion->Attributes) {
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK;
break;
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH;
break;
case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:
Attributes = TT_DESCRIPTOR_SECTION_DEVICE;
break;
case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
default:
Attributes = TT_DESCRIPTOR_SECTION_UNCACHED;
break;
}
Entry = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);
Sections = MemoryRegion->Length / TT_DESCRIPTOR_SECTION_SIZE;
for (Index = 0; Index < Sections; Index++) {
*Entry++ = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;
PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;
}
}
VOID
EFIAPI
ArmConfigureMmu (
IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,
OUT VOID **TranslationTableBase OPTIONAL,
OUT UINTN *TranslationTableSize OPTIONAL
)
{
VOID *TranslationTable;
// Allocate pages for translation table.
TranslationTable = AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_SIZE + TRANSLATION_TABLE_ALIGNMENT));
TranslationTable = (VOID *)(((UINTN)TranslationTable + TRANSLATION_TABLE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_ALIGNMENT_MASK);
if (TranslationTableBase != NULL) {
*TranslationTableBase = TranslationTable;
}
if (TranslationTableBase != NULL) {
*TranslationTableSize = TRANSLATION_TABLE_SIZE;
}
ZeroMem(TranslationTable, TRANSLATION_TABLE_SIZE);
ArmCleanInvalidateDataCache();
ArmInvalidateInstructionCache();
ArmInvalidateTlb();
ArmDisableDataCache();
ArmDisableInstructionCache();
ArmDisableMmu();
// Make sure nothing sneaked into the cache
ArmCleanInvalidateDataCache();
ArmInvalidateInstructionCache();
while (MemoryTable->Length != 0) {
FillTranslationTable(TranslationTable, MemoryTable);
MemoryTable++;
}
ArmSetTranslationTableBaseAddress(TranslationTable);
ArmSetDomainAccessControl(DOMAIN_ACCESS_CONTROL_NONE(15) |
DOMAIN_ACCESS_CONTROL_NONE(14) |
DOMAIN_ACCESS_CONTROL_NONE(13) |
DOMAIN_ACCESS_CONTROL_NONE(12) |
DOMAIN_ACCESS_CONTROL_NONE(11) |
DOMAIN_ACCESS_CONTROL_NONE(10) |
DOMAIN_ACCESS_CONTROL_NONE( 9) |
DOMAIN_ACCESS_CONTROL_NONE( 8) |
DOMAIN_ACCESS_CONTROL_NONE( 7) |
DOMAIN_ACCESS_CONTROL_NONE( 6) |
DOMAIN_ACCESS_CONTROL_NONE( 5) |
DOMAIN_ACCESS_CONTROL_NONE( 4) |
DOMAIN_ACCESS_CONTROL_NONE( 3) |
DOMAIN_ACCESS_CONTROL_NONE( 2) |
DOMAIN_ACCESS_CONTROL_NONE( 1) |
DOMAIN_ACCESS_CONTROL_MANAGER(0));
ArmEnableInstructionCache();
ArmEnableDataCache();
ArmEnableMmu();
}
ARM_CACHE_TYPE
EFIAPI
ArmCacheType (
@@ -139,7 +36,7 @@ ArmCacheArchitecture (
{
UINT32 CLIDR = ReadCLIDR ();
return CLIDR; // BugBug Fix Me
return (ARM_CACHE_ARCHITECTURE)CLIDR; // BugBug Fix Me
}
BOOLEAN
@@ -173,7 +70,7 @@ ArmDataCacheSize (
UINT32 LineSize;
UINT32 CCSIDR = ReadCCSIDR (0);
LineSize = (1 << (CCSIDR + 2));
LineSize = (1 << ((CCSIDR & 0x7) + 2));
Associativity = ((CCSIDR >> 3) & 0x3ff) + 1;
NumSets = ((CCSIDR >> 13) & 0x7fff) + 1;
@@ -245,7 +142,7 @@ ArmInstructionCacheSize (
UINT32 LineSize;
UINT32 CCSIDR = ReadCCSIDR (1);
LineSize = (1 << (CCSIDR + 2));
LineSize = (1 << ((CCSIDR & 0x7) + 2));
Associativity = ((CCSIDR >> 3) & 0x3ff) + 1;
NumSets = ((CCSIDR >> 13) & 0x7fff) + 1;
@@ -299,6 +196,8 @@ ArmV7DataCacheOperation (
UINTN SavedInterruptState;
SavedInterruptState = ArmGetInterruptState ();
ArmDisableInterrupts();
ArmV7AllDataCachesOperation (DataCacheOperation);
@@ -335,3 +234,14 @@ ArmCleanDataCache (
{
ArmV7DataCacheOperation (ArmCleanDataCacheEntryBySetWay);
}
VOID
EFIAPI
ArmSetAuxCrBit (
IN UINT32 Bits
)
{
UINT32 val = ArmReadAuxCr();
val |= Bits;
ArmWriteAuxCr(val);
}

36
ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.h
View File

@@ -40,5 +40,41 @@ ArmCleanInvalidateDataCacheEntryBySetWay (
IN UINT32 SetWayFormat
);
VOID
EFIAPI
ArmEnableAsynchronousAbort (
VOID
);
UINTN
EFIAPI
ArmDisableAsynchronousAbort (
VOID
);
VOID
EFIAPI
ArmEnableIrq (
VOID
);
UINTN
EFIAPI
ArmDisableIrq (
VOID
);
VOID
EFIAPI
ArmEnableFiq (
VOID
);
UINTN
EFIAPI
ArmDisableFiq (
VOID
);
#endif // __ARM_V7_LIB_H__

1
ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf
View File

@@ -30,6 +30,7 @@
ArmV7Support.asm | RVCT
ArmV7Lib.c
ArmV7Mmu.c
[Packages]
ArmPkg/ArmPkg.dec

1
ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf
View File

@@ -30,6 +30,7 @@
ArmV7Support.asm | RVCT
ArmV7Lib.c
ArmV7Mmu.c
[Packages]
ArmPkg/ArmPkg.dec

40
ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf Normal file
View File

@@ -0,0 +1,40 @@
#/* @file
# Copyright (c) 2011, ARM Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#*/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = ArmV7Lib
FILE_GUID = 411cdfd8-f964-4b9d-a3e3-1719a9c15559
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = ArmLib
[Sources.common]
ArmLibSupport.S | GCC
ArmLibSupport.asm | RVCT
../Common/ArmLib.c
ArmV7Support.S | GCC
ArmV7Support.asm | RVCT
ArmV7Lib.c
[Packages]
ArmPkg/ArmPkg.dec
MdePkg/MdePkg.dec
[Protocols]
gEfiCpuArchProtocolGuid
[FixedPcd]
gArmTokenSpaceGuid.PcdArmCacheOperationThreshold

57
ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCore.c Normal file
View File

@@ -0,0 +1,57 @@
/** @file
*
* Copyright (c) 2011, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
* which accompanies this distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#include <Uefi.h>
#include <Chipset/ArmV7.h>
#include <Library/ArmLib.h>
#include <Library/BaseLib.h>
#include <Library/IoLib.h>
#include "ArmV7Lib.h"
#include "ArmLibPrivate.h"
VOID
EFIAPI
ArmSetupSmpNonSecure (
IN UINTN CoreId
)
{
INTN scu_base;
ArmSetAuxCrBit (A9_FEATURE_SMP);
if (CoreId == 0) {
scu_base = ArmGetScuBaseAddress();
// Allow NS access to SCU register
MmioOr32(scu_base + SCU_SACR_OFFSET, 0xf);
// Allow NS access to Private Peripherals
MmioOr32(scu_base + SCU_SSACR_OFFSET, 0xfff);
}
}
VOID
EFIAPI
ArmInvalidScu (
VOID
)
{
INTN scu_base;
scu_base = ArmGetScuBaseAddress();
/* Invalidate all: write -1 to SCU Invalidate All register */
MmioWrite32(scu_base + SCU_INVALL_OFFSET, 0xffffffff);
/* Enable SCU */
MmioWrite32(scu_base + SCU_CONTROL_OFFSET, 0x1);
}

48
ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreHelper.S Normal file
View File

@@ -0,0 +1,48 @@
#
# Copyright (c) 2011, ARM Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http:#opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#
#include <AsmMacroIoLib.h>
#include <Base.h>
#include <Library/PcdLib.h>
#include <Chipset/ArmV7.h>
#include <AutoGen.h>
#.include AsmMacroIoLib.inc
.text
.align 2
GCC_ASM_EXPORT(ArmIsScuEnable)
GCC_ASM_EXPORT(ArmGetScuBaseAddress)
# IN None
# OUT r0 = SCU Base Address
ASM_PFX(ArmGetScuBaseAddress):
# Read Configuration Base Address Register. ArmCBar cannot be called to get
# the Configuration BAR as a stack is not necessary setup. The SCU is at the
# offset 0x0000 from the Private Memory Region.
mrc p15, 4, r0, c15, c0, 0
bx lr
# IN None
# OUT r1 = SCU enabled (boolean)
ASM_PFX(ArmIsScuEnable):
# Read Configuration Base Address Register. ArmCBar cannot be called to get
# the Configuration BAR as a stack is not necessary setup. The SCU is at the
# offset 0x0000 from the Private Memory Region.
mrc p15, 4, r0, c15, c0, 0
add r1, r0, #SCU_CONTROL_OFFSET
ldr r1, [r1]
and r1, r1, #1
bx lr
ASM_FUNCTION_REMOVE_IF_UNREFERENCED

48
ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreHelper.asm Normal file
View File

@@ -0,0 +1,48 @@
//
// Copyright (c) 2011, ARM Limited. All rights reserved.
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
//
#include <AsmMacroIoLib.h>
#include <Base.h>
#include <Library/PcdLib.h>
#include <Chipset/ArmV7.h>
#include <AutoGen.h>
INCLUDE AsmMacroIoLib.inc
EXPORT ArmIsScuEnable
EXPORT ArmGetScuBaseAddress
AREA ArmV7MPCore, CODE, READONLY
// IN None
// OUT r0 = SCU Base Address
ArmGetScuBaseAddress
// Read Configuration Base Address Register. ArmCBar cannot be called to get
// the Configuration BAR as a stack is not necessary setup. The SCU is at the
// offset 0x0000 from the Private Memory Region.
mrc p15, 4, r0, c15, c0, 0
bx lr
// IN None
// OUT r1 = SCU enabled (boolean)
ArmIsScuEnable
// Read Configuration Base Address Register. ArmCBar cannot be called to get
// the Configuration BAR as a stack is not necessary setup. The SCU is at the
// offset 0x0000 from the Private Memory Region.
mrc p15, 4, r0, c15, c0, 0
add r1, r0, #SCU_CONTROL_OFFSET
ldr r1, [r1]
and r1, r1, #1
bx lr
END

51
ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLib.inf Normal file
View File

@@ -0,0 +1,51 @@
#/** @file
# Helper Library for ARMv7 MPCore architecture
# Copyright (c) 2011, ARM Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = ArmV7Lib
FILE_GUID = 411cdfd8-f964-4b9d-a3e3-1719a9c15559
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
LIBRARY_CLASS = ArmLib
[Sources.common]
ArmLibSupport.S | GCC
ArmLibSupport.asm | RVCT
../Common/ArmLib.c
ArmV7Support.S | GCC
ArmV7Support.asm | RVCT
ArmV7Lib.c
ArmV7Mmu.c
ArmV7MPCore.c
ArmV7MPCoreHelper.S | GCC
ArmV7MPCoreHelper.asm | RVCT
[Packages]
ArmPkg/ArmPkg.dec
MdePkg/MdePkg.dec
[LibraryClasses]
MemoryAllocationLib
[Protocols]
gEfiCpuArchProtocolGuid
[FixedPcd]
gArmTokenSpaceGuid.PcdArmCacheOperationThreshold

49
ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLibPrePi.inf Normal file
View File

@@ -0,0 +1,49 @@
#/** @file
#
# Copyright (c) 2011, ARM Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = ArmV7LibPrePi
FILE_GUID = A150FA0C-F4E8-4207-9BEB-CD6DFB430D73
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = ArmLib
[Sources.common]
ArmLibSupport.S | GCC
ArmLibSupport.asm | RVCT
../Common/ArmLib.c
ArmV7Support.S | GCC
ArmV7Support.asm | RVCT
ArmV7Lib.c
ArmV7Mmu.c
ArmV7MPCore.c
ArmV7MPCoreHelper.S | GCC
ArmV7MPCoreHelper.asm | RVCT
[Packages]
ArmPkg/ArmPkg.dec
MdePkg/MdePkg.dec
[LibraryClasses]
PrePiLib
[Protocols]
gEfiCpuArchProtocolGuid
[FixedPcd]
gArmTokenSpaceGuid.PcdArmCacheOperationThreshold

43
ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLibSec.inf Normal file
View File

@@ -0,0 +1,43 @@
#/* @file
# Copyright (c) 2011, ARM Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#*/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = ArmV7Lib
FILE_GUID = 411cdfd8-f964-4b9d-a3e3-1719a9c15559
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = ArmLib
[Sources.common]
ArmLibSupport.S | GCC
ArmLibSupport.asm | RVCT
../Common/ArmLib.c
ArmV7Support.S | GCC
ArmV7Support.asm | RVCT
ArmV7Lib.c
ArmV7MPCore.c
ArmV7MPCoreHelper.S | GCC
ArmV7MPCoreHelper.asm | RVCT
[Packages]
ArmPkg/ArmPkg.dec
MdePkg/MdePkg.dec
[Protocols]
gEfiCpuArchProtocolGuid
[FixedPcd]
gArmTokenSpaceGuid.PcdArmCacheOperationThreshold

162
ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c Normal file
View File

@@ -0,0 +1,162 @@
/** @file
* File managing the MMU for ARMv7 architecture
*
* Copyright (c) 2011, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
* which accompanies this distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#include <Uefi.h>
#include <Chipset/ArmV7.h>
#include <Library/BaseMemoryLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/ArmLib.h>
#include <Library/BaseLib.h>
#include "ArmV7Lib.h"
#include "ArmLibPrivate.h"
VOID
FillTranslationTable (
IN UINT32 *TranslationTable,
IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryRegion
)
{
UINT32 *Entry;
UINTN Sections;
UINTN Index;
UINT32 Attributes;
UINT32 PhysicalBase = MemoryRegion->PhysicalBase;
switch (MemoryRegion->Attributes) {
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(0);
break;
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0);
break;
case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:
Attributes = TT_DESCRIPTOR_SECTION_DEVICE(0);
break;
case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);
break;
case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_BACK:
Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(1);
break;
case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_THROUGH:
Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(1);
break;
case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE:
Attributes = TT_DESCRIPTOR_SECTION_DEVICE(1);
break;
case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_UNCACHED_UNBUFFERED:
Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(1);
break;
default:
Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);
break;
}
Entry = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);
Sections = MemoryRegion->Length / TT_DESCRIPTOR_SECTION_SIZE;
for (Index = 0; Index < Sections; Index++) {
*Entry++ = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;
PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;
}
}
VOID
EFIAPI
ArmConfigureMmu (
IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,
OUT VOID **TranslationTableBase OPTIONAL,
OUT UINTN *TranslationTableSize OPTIONAL
)
{
UINTN TranslationTable;
ARM_MEMORY_REGION_ATTRIBUTES TranslationTableAttribute;
UINT32 TTBRAttributes;
// Allocate pages for translation table.
TranslationTable = (UINTN)AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_SECTION_SIZE + TRANSLATION_TABLE_SECTION_ALIGNMENT));
TranslationTable = ((UINTN)TranslationTable + TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK;
if (TranslationTableBase != NULL) {
*TranslationTableBase = (VOID *)TranslationTable;
}
if (TranslationTableBase != NULL) {
*TranslationTableSize = TRANSLATION_TABLE_SECTION_SIZE;
}
ZeroMem ((VOID *)TranslationTable, TRANSLATION_TABLE_SECTION_SIZE);
ArmCleanInvalidateDataCache();
ArmInvalidateInstructionCache();
ArmInvalidateTlb();
ArmDisableDataCache();
ArmDisableInstructionCache();
ArmDisableMmu();
// Make sure nothing sneaked into the cache
ArmCleanInvalidateDataCache();
ArmInvalidateInstructionCache();
TranslationTableAttribute = 0;
while (MemoryTable->Length != 0) {
// Find the memory attribute for the Translation Table
if ((TranslationTable >= MemoryTable->PhysicalBase) && (TranslationTable < MemoryTable->PhysicalBase + MemoryTable->Length)) {
TranslationTableAttribute = MemoryTable->Attributes;
}
FillTranslationTable ((VOID *)TranslationTable, MemoryTable);
MemoryTable++;
}
// Translate the Memory Attributes into Translation Table Register Attributes
if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED) ||
(TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_SECURE_UNCACHED_UNBUFFERED)) {
TTBRAttributes = TTBR_NON_CACHEABLE;
} else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK) ||
(TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_BACK)) {
TTBRAttributes = TTBR_WRITE_BACK_ALLOC;
} else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH) ||
(TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_THROUGH)) {
TTBRAttributes = TTBR_WRITE_THROUGH_NO_ALLOC;
} else {
//TODO: We should raise an error here
TTBRAttributes = TTBR_NON_CACHEABLE;
}
ArmSetTTBR0 ((VOID *)(UINTN)((TranslationTable & 0xFFFFC000) | (TTBRAttributes & 0x7F)));
ArmSetDomainAccessControl (DOMAIN_ACCESS_CONTROL_NONE(15) |
DOMAIN_ACCESS_CONTROL_NONE(14) |
DOMAIN_ACCESS_CONTROL_NONE(13) |
DOMAIN_ACCESS_CONTROL_NONE(12) |
DOMAIN_ACCESS_CONTROL_NONE(11) |
DOMAIN_ACCESS_CONTROL_NONE(10) |
DOMAIN_ACCESS_CONTROL_NONE( 9) |
DOMAIN_ACCESS_CONTROL_NONE( 8) |
DOMAIN_ACCESS_CONTROL_NONE( 7) |
DOMAIN_ACCESS_CONTROL_NONE( 6) |
DOMAIN_ACCESS_CONTROL_NONE( 5) |
DOMAIN_ACCESS_CONTROL_NONE( 4) |
DOMAIN_ACCESS_CONTROL_NONE( 3) |
DOMAIN_ACCESS_CONTROL_NONE( 2) |
DOMAIN_ACCESS_CONTROL_NONE( 1) |
DOMAIN_ACCESS_CONTROL_MANAGER(0));
ArmEnableInstructionCache();
ArmEnableDataCache();
ArmEnableMmu();
}

166
ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S
View File

@@ -12,55 +12,51 @@
#
#------------------------------------------------------------------------------
.globl ASM_PFX(ArmInvalidateInstructionCache)
INTERWORK_FUNC(ArmInvalidateInstructionCache)
.globl ASM_PFX(ArmInvalidateDataCacheEntryByMVA)
INTERWORK_FUNC(ArmInvalidateDataCacheEntryByMVA)
.globl ASM_PFX(ArmCleanDataCacheEntryByMVA)
INTERWORK_FUNC(ArmCleanDataCacheEntryByMVA)
.globl ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA)
INTERWORK_FUNC(ArmCleanInvalidateDataCacheEntryByMVA)
.globl ASM_PFX(ArmInvalidateDataCacheEntryBySetWay)
INTERWORK_FUNC(ArmInvalidateDataCacheEntryBySetWay)
.globl ASM_PFX(ArmCleanDataCacheEntryBySetWay)
INTERWORK_FUNC(ArmCleanDataCacheEntryBySetWay)
.globl ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay)
INTERWORK_FUNC(ArmCleanInvalidateDataCacheEntryBySetWay)
.globl ASM_PFX(ArmDrainWriteBuffer)
INTERWORK_FUNC(ArmDrainWriteBuffer)
.globl ASM_PFX(ArmEnableMmu)
INTERWORK_FUNC(ArmEnableMmu)
.globl ASM_PFX(ArmDisableMmu)
INTERWORK_FUNC(ArmDisableMmu)
.globl ASM_PFX(ArmMmuEnabled)
INTERWORK_FUNC(ArmMmuEnabled)
.globl ASM_PFX(ArmEnableDataCache)
INTERWORK_FUNC(ArmEnableDataCache)
.globl ASM_PFX(ArmDisableDataCache)
INTERWORK_FUNC(ArmDisableDataCache)
.globl ASM_PFX(ArmEnableInstructionCache)
INTERWORK_FUNC(ArmEnableInstructionCache)
.globl ASM_PFX(ArmDisableInstructionCache)
INTERWORK_FUNC(ArmDisableInstructionCache)
.globl ASM_PFX(ArmEnableBranchPrediction)
INTERWORK_FUNC(ArmEnableBranchPrediction)
.globl ASM_PFX(ArmDisableBranchPrediction)
INTERWORK_FUNC(ArmDisableBranchPrediction)
.globl ASM_PFX(ArmV7AllDataCachesOperation)
INTERWORK_FUNC(ArmV7AllDataCachesOperation)
.globl ASM_PFX(ArmDataMemoryBarrier)
INTERWORK_FUNC(ArmDataMemoryBarrier)
.globl ASM_PFX(ArmDataSyncronizationBarrier)
INTERWORK_FUNC(ArmDataSyncronizationBarrier)
.globl ASM_PFX(ArmInstructionSynchronizationBarrier)
INTERWORK_FUNC(ArmInstructionSynchronizationBarrier)
.text
.align 2
GCC_ASM_EXPORT (ArmInvalidateInstructionCache)
GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryByMVA)
GCC_ASM_EXPORT (ArmCleanDataCacheEntryByMVA)
GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryByMVA)
GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryBySetWay)
GCC_ASM_EXPORT (ArmCleanDataCacheEntryBySetWay)
GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryBySetWay)
GCC_ASM_EXPORT (ArmDrainWriteBuffer)
GCC_ASM_EXPORT (ArmEnableMmu)
GCC_ASM_EXPORT (ArmDisableMmu)
GCC_ASM_EXPORT (ArmDisableCachesAndMmu)
GCC_ASM_EXPORT (ArmMmuEnabled)
GCC_ASM_EXPORT (ArmEnableDataCache)
GCC_ASM_EXPORT (ArmDisableDataCache)
GCC_ASM_EXPORT (ArmEnableInstructionCache)
GCC_ASM_EXPORT (ArmDisableInstructionCache)
GCC_ASM_EXPORT (ArmEnableSWPInstruction)
GCC_ASM_EXPORT (ArmEnableBranchPrediction)
GCC_ASM_EXPORT (ArmDisableBranchPrediction)
GCC_ASM_EXPORT (ArmV7AllDataCachesOperation)
GCC_ASM_EXPORT (ArmDataMemoryBarrier)
GCC_ASM_EXPORT (ArmDataSyncronizationBarrier)
GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier)
GCC_ASM_EXPORT (ArmWriteNsacr)
GCC_ASM_EXPORT (ArmWriteScr)
GCC_ASM_EXPORT (ArmWriteVMBar)
GCC_ASM_EXPORT (ArmWriteVBar)
GCC_ASM_EXPORT (ArmWriteCPACR)
GCC_ASM_EXPORT (ArmEnableVFP)
GCC_ASM_EXPORT (ArmCallWFI)
GCC_ASM_EXPORT (ArmWriteAuxCr)
GCC_ASM_EXPORT (ArmReadAuxCr)
GCC_ASM_EXPORT (ArmReadCbar)
GCC_ASM_EXPORT (ArmInvalidateInstructionAndDataTlb)
GCC_ASM_EXPORT (ArmReadMpidr)
.set DC_ON, (0x1<<2)
.set IC_ON, (0x1<<12)
.set CTRL_M_BIT, (1 << 0)
.set CTRL_C_BIT, (1 << 2)
.set CTRL_B_BIT, (1 << 7)
.set CTRL_I_BIT, (1 << 12)
ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
@@ -69,7 +65,6 @@ ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
isb
bx lr
ASM_PFX(ArmCleanDataCacheEntryByMVA):
mcr p15, 0, r0, c7, c10, 1 @clean single data cache line
dsb
@@ -104,7 +99,6 @@ ASM_PFX(ArmCleanDataCacheEntryBySetWay):
isb
bx lr
ASM_PFX(ArmInvalidateInstructionCache):
mcr p15,0,R0,c7,c5,0 @Invalidate entire instruction cache
dsb
@@ -119,10 +113,6 @@ ASM_PFX(ArmEnableMmu):
isb
bx LR
ASM_PFX(ArmMmuEnabled):
mrc p15,0,R0,c1,c0,0
and R0,R0,#1
bx LR
ASM_PFX(ArmDisableMmu):
mrc p15,0,R0,c1,c0,0
@@ -135,6 +125,21 @@ ASM_PFX(ArmDisableMmu):
isb
bx LR
ASM_PFX(ArmDisableCachesAndMmu):
mrc p15, 0, r0, c1, c0, 0 @ Get control register
bic r0, r0, #CTRL_M_BIT @ Disable MMU
bic r0, r0, #CTRL_C_BIT @ Disable D Cache
bic r0, r0, #CTRL_I_BIT @ Disable I Cache
mcr p15, 0, r0, c1, c0, 0 @ Write control register
dsb
isb
bx LR
ASM_PFX(ArmMmuEnabled):
mrc p15,0,R0,c1,c0,0
and R0,R0,#1
bx LR
ASM_PFX(ArmEnableDataCache):
ldr R1,=DC_ON
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
@@ -171,6 +176,13 @@ ASM_PFX(ArmDisableInstructionCache):
isb
bx LR
ASM_PFX(ArmEnableSWPInstruction):
mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #0x00000400
mcr p15, 0, r0, c1, c0, 0
isb
bx LR
ASM_PFX(ArmEnableBranchPrediction):
mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #0x00000800
@@ -254,5 +266,59 @@ ASM_PFX(ArmInstructionSynchronizationBarrier):
isb
bx LR
ASM_PFX(ArmWriteNsacr):
mcr p15, 0, r0, c1, c1, 2
bx lr
ASM_PFX(ArmWriteScr):
mcr p15, 0, r0, c1, c1, 0
bx lr
ASM_PFX(ArmWriteAuxCr):
mcr p15, 0, r0, c1, c0, 1
bx lr
ASM_PFX(ArmReadAuxCr):
mrc p15, 0, r0, c1, c0, 1
bx lr
ASM_PFX(ArmWriteVMBar):
mcr p15, 0, r0, c12, c0, 1
bx lr
ASM_PFX(ArmWriteVBar):
mcr p15, 0, r0, c12, c0, 0
bx lr
ASM_PFX(ArmWriteCPACR):
mcr p15, 0, r0, c1, c0, 2
bx lr
ASM_PFX(ArmEnableVFP):
// Enable VFP registers
mrc p15, 0, r0, c1, c0, 2
orr r0, r0, #0x00f00000 // Enable VPF access (V* instructions)
mcr p15, 0, r0, c1, c0, 2
mov r0, #0x40000000 // Set EN bit in FPEXC
mcr p10,#0x7,r0,c8,c0,#0 // msr FPEXC,r0 in ARM assembly
bx lr
ASM_PFX(ArmCallWFI):
wfi
bx lr
//Note: Return 0 in Uniprocessor implementation
ASM_PFX(ArmReadCbar):
mrc p15, 4, r0, c15, c0, 0 //Read Configuration Base Address Register
bx lr
ASM_PFX(ArmInvalidateInstructionAndDataTlb):
mcr p15, 0, r0, c8, c7, 0 @ Invalidate Inst TLB and Data TLB
dsb
bx lr
ASM_PFX(ArmReadMpidr):
mrc p15, 0, r0, c0, c0, 5 @ read MPIDR
bx lr
ASM_FUNCTION_REMOVE_IF_UNREFERENCED

169
ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm
View File

@@ -22,24 +22,42 @@
EXPORT ArmDrainWriteBuffer
EXPORT ArmEnableMmu
EXPORT ArmDisableMmu
EXPORT ArmDisableCachesAndMmu
EXPORT ArmMmuEnabled
EXPORT ArmEnableDataCache
EXPORT ArmDisableDataCache
EXPORT ArmEnableInstructionCache
EXPORT ArmDisableInstructionCache
EXPORT ArmEnableSWPInstruction
EXPORT ArmEnableBranchPrediction
EXPORT ArmDisableBranchPrediction
EXPORT ArmV7AllDataCachesOperation
EXPORT ArmDataMemoryBarrier
EXPORT ArmDataSyncronizationBarrier
EXPORT ArmInstructionSynchronizationBarrier
EXPORT ArmWriteNsacr
EXPORT ArmWriteScr
EXPORT ArmWriteVMBar
EXPORT ArmWriteVBar
EXPORT ArmReadVBar
EXPORT ArmWriteCPACR
EXPORT ArmEnableVFP
EXPORT ArmCallWFI
EXPORT ArmWriteAuxCr
EXPORT ArmReadAuxCr
EXPORT ArmReadCbar
EXPORT ArmInvalidateInstructionAndDataTlb
EXPORT ArmReadMpidr
AREA ArmCacheLib, CODE, READONLY
PRESERVE8
DC_ON EQU ( 0x1:SHL:2 )
IC_ON EQU ( 0x1:SHL:12 )
DC_ON EQU ( 0x1:SHL:2 )
IC_ON EQU ( 0x1:SHL:12 )
CTRL_M_BIT EQU (1 << 0)
CTRL_C_BIT EQU (1 << 2)
CTRL_B_BIT EQU (1 << 7)
CTRL_I_BIT EQU (1 << 12)
ArmInvalidateDataCacheEntryByMVA
@@ -90,75 +108,91 @@ ArmInvalidateInstructionCache
bx LR
ArmEnableMmu
mrc p15,0,R0,c1,c0,0
orr R0,R0,#1
mcr p15,0,R0,c1,c0,0
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
orr R0,R0,#1 ; Set SCTLR.M bit : Enable MMU
mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
dsb
isb
bx LR
ArmMmuEnabled
mrc p15,0,R0,c1,c0,0
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
and R0,R0,#1
bx LR
ArmDisableMmu
mrc p15,0,R0,c1,c0,0
bic R0,R0,#1
mcr p15,0,R0,c1,c0,0 ;Disable MMU
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
bic R0,R0,#1 ; Clear SCTLR.M bit : Disable MMU
mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
mcr p15,0,R0,c8,c7,0 ;Invalidate TLB
mcr p15,0,R0,c7,c5,6 ;Invalidate Branch predictor array
mcr p15,0,R0,c8,c7,0 ; TLBIALL : Invalidate unified TLB
mcr p15,0,R0,c7,c5,6 ; BPIALL : Invalidate entire branch predictor array
dsb
isb
bx LR
ArmDisableCachesAndMmu
mrc p15, 0, r0, c1, c0, 0 ; Get control register
bic r0, r0, #CTRL_M_BIT ; Disable MMU
bic r0, r0, #CTRL_C_BIT ; Disable D Cache
bic r0, r0, #CTRL_I_BIT ; Disable I Cache
mcr p15, 0, r0, c1, c0, 0 ; Write control register
dsb
isb
bx LR
ArmEnableDataCache
ldr R1,=DC_ON
mrc p15,0,R0,c1,c0,0 ;Read control register configuration data
orr R0,R0,R1 ;Set C bit
mcr p15,0,R0,c1,c0,0 ;Write control register configuration data
ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
orr R0,R0,R1 ; Set SCTLR.C bit : Data and unified caches enabled
mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
dsb
isb
bx LR
ArmDisableDataCache
ldr R1,=DC_ON
mrc p15,0,R0,c1,c0,0 ;Read control register configuration data
bic R0,R0,R1 ;Clear C bit
mcr p15,0,R0,c1,c0,0 ;Write control register configuration data
ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
bic R0,R0,R1 ; Clear SCTLR.C bit : Data and unified caches disabled
mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
isb
bx LR
ArmEnableInstructionCache
ldr R1,=IC_ON
mrc p15,0,R0,c1,c0,0 ;Read control register configuration data
orr R0,R0,R1 ;Set I bit
mcr p15,0,R0,c1,c0,0 ;Write control register configuration data
ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
orr R0,R0,R1 ; Set SCTLR.I bit : Instruction caches enabled
mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
dsb
isb
bx LR
ArmDisableInstructionCache
ldr R1,=IC_ON
mrc p15,0,R0,c1,c0,0 ;Read control register configuration data
BIC R0,R0,R1 ;Clear I bit.
mcr p15,0,R0,c1,c0,0 ;Write control register configuration data
ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
BIC R0,R0,R1 ; Clear SCTLR.I bit : Instruction caches disabled
mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
isb
bx LR
ArmEnableSWPInstruction
mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #0x00000400
mcr p15, 0, r0, c1, c0, 0
isb
bx LR
ArmEnableBranchPrediction
mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #0x00000800
mcr p15, 0, r0, c1, c0, 0
mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
orr r0, r0, #0x00000800 ;
mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
isb
bx LR
ArmDisableBranchPrediction
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x00000800
mcr p15, 0, r0, c1, c0, 0
mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
bic r0, r0, #0x00000800 ;
mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
isb
bx LR
@@ -173,9 +207,9 @@ ArmV7AllDataCachesOperation
mov R10, #0
Loop1
add R2, R10, R10, LSR #1 ; Work out 3xcachelevel
mov R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level
and R12, R12, #7 ; get those 3 bits alone
add R2, R10, R10, LSR #1 ; Work out 3xcachelevel
mov R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level
and R12, R12, #7 ; get those 3 bits alone
cmp R12, #2
blt Skip ; no cache or only instruction cache at this level
mcr p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
@@ -226,5 +260,64 @@ ArmInstructionSynchronizationBarrier
isb
bx LR
END
ArmWriteNsacr
mcr p15, 0, r0, c1, c1, 2
bx lr
ArmWriteScr
mcr p15, 0, r0, c1, c1, 0
bx lr
ArmWriteAuxCr
mcr p15, 0, r0, c1, c0, 1
bx lr
ArmReadAuxCr
mrc p15, 0, r0, c1, c0, 1
bx lr
ArmWriteVMBar
mcr p15, 0, r0, c12, c0, 1
bx lr
ArmWriteVBar
mcr p15, 0, r0, c12, c0, 0
bx lr
ArmReadVBar
mrc p15, 0, r0, c12, c0, 0
bx lr
ArmWriteCPACR
mcr p15, 0, r0, c1, c0, 2
bx lr
ArmEnableVFP
// Enable VFP registers
mrc p15, 0, r0, c1, c0, 2
orr r0, r0, #0x00f00000 // Enable VPF access (V* instructions)
mcr p15, 0, r0, c1, c0, 2
mov r0, #0x40000000 // Set EN bit in FPEXC
mcr p10,#0x7,r0,c8,c0,#0 // msr FPEXC,r0 in ARM assembly
bx lr
ArmCallWFI
wfi
bx lr
//Note: Return 0 in Uniprocessor implementation
ArmReadCbar
mrc p15, 4, r0, c15, c0, 0 //Read Configuration Base Address Register
bx lr
ArmInvalidateInstructionAndDataTlb
mcr p15, 0, r0, c8, c7, 0 ; Invalidate Inst TLB and Data TLB
dsb
bx lr
ArmReadMpidr
mrc p15, 0, r0, c0, c0, 5 ; read MPIDR
bx lr
END

51
ArmPkg/Library/ArmLib/Common/ArmLibSupport.S
View File

@@ -12,37 +12,24 @@
#
#------------------------------------------------------------------------------
#include <AsmMacroIoLib.h>
.text
.align 2
.globl ASM_PFX(Cp15IdCode)
INTERWORK_FUNC(Cp15IdCode)
.globl ASM_PFX(Cp15CacheInfo)
INTERWORK_FUNC(Cp15CacheInfo)
.globl ASM_PFX(ArmEnableInterrupts)
INTERWORK_FUNC(ArmEnableInterrupts)
.globl ASM_PFX(ArmDisableInterrupts)
INTERWORK_FUNC(ArmDisableInterrupts)
.globl ASM_PFX(ArmGetInterruptState)
INTERWORK_FUNC(ArmGetInterruptState)
.globl ASM_PFX(ArmEnableFiq)
INTERWORK_FUNC(ArmEnableFiq)
.globl ASM_PFX(ArmDisableFiq)
INTERWORK_FUNC(ArmDisableFiq)
.globl ASM_PFX(ArmGetFiqState)
INTERWORK_FUNC(ArmGetFiqState)
.globl ASM_PFX(ArmInvalidateTlb)
INTERWORK_FUNC(ArmInvalidateTlb)
.globl ASM_PFX(ArmSetTranslationTableBaseAddress)
INTERWORK_FUNC(ArmSetTranslationTableBaseAddress)
.globl ASM_PFX(ArmGetTranslationTableBaseAddress)
INTERWORK_FUNC(ArmGetTranslationTableBaseAddress)
.globl ASM_PFX(ArmSetDomainAccessControl)
INTERWORK_FUNC(ArmSetDomainAccessControl)
.globl ASM_PFX(CPSRMaskInsert)
INTERWORK_FUNC(CPSRMaskInsert)
.globl ASM_PFX(CPSRRead)
INTERWORK_FUNC(CPSRRead)
GCC_ASM_EXPORT(Cp15IdCode)
GCC_ASM_EXPORT(Cp15CacheInfo)
GCC_ASM_EXPORT(ArmEnableInterrupts)
GCC_ASM_EXPORT(ArmDisableInterrupts)
GCC_ASM_EXPORT(ArmGetInterruptState)
GCC_ASM_EXPORT(ArmEnableFiq)
GCC_ASM_EXPORT(ArmDisableFiq)
GCC_ASM_EXPORT(ArmGetFiqState)
GCC_ASM_EXPORT(ArmInvalidateTlb)
GCC_ASM_EXPORT(ArmSetTTBR0)
GCC_ASM_EXPORT(ArmGetTTBR0BaseAddress)
GCC_ASM_EXPORT(ArmSetDomainAccessControl)
GCC_ASM_EXPORT(CPSRMaskInsert)
GCC_ASM_EXPORT(CPSRRead)
#------------------------------------------------------------------------------
@@ -103,12 +90,14 @@ ASM_PFX(ArmInvalidateTlb):
mcr p15,0,r0,c8,c7,0
bx lr
ASM_PFX(ArmSetTranslationTableBaseAddress):
ASM_PFX(ArmSetTTBR0):
mcr p15,0,r0,c2,c0,0
bx lr
ASM_PFX(ArmGetTranslationTableBaseAddress):
ASM_PFX(ArmGetTTBR0BaseAddress):
mrc p15,0,r0,c2,c0,0
LoadConstantToReg(0xFFFFC000, r1) @ and r0, r0, #0xFFFFC000
and r0, r0, r1
bx lr

18
ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm
View File

@@ -15,6 +15,7 @@
EXPORT Cp15IdCode
EXPORT Cp15CacheInfo
EXPORT ArmIsMPCore
EXPORT ArmEnableInterrupts
EXPORT ArmDisableInterrupts
EXPORT ArmGetInterruptState
@@ -22,8 +23,8 @@
EXPORT ArmDisableFiq
EXPORT ArmGetFiqState
EXPORT ArmInvalidateTlb
EXPORT ArmSetTranslationTableBaseAddress
EXPORT ArmGetTranslationTableBaseAddress
EXPORT ArmSetTTBR0
EXPORT ArmGetTTBR0BaseAddress
EXPORT ArmSetDomainAccessControl
EXPORT CPSRMaskInsert
EXPORT CPSRRead
@@ -38,6 +39,14 @@ Cp15CacheInfo
mrc p15,0,R0,c0,c0,1
bx LR
ArmIsMPCore
mrc p15,0,R0,c0,c0,5
# Get Multiprocessing extension (bit31) & U bit (bit30)
and R0, R0, #0xC0000000
# if bit30 == 0 then the processor is part of a multiprocessor system)
and R0, R0, #0x80000000
bx LR
ArmEnableInterrupts
mrs R0,CPSR
bic R0,R0,#0x80 ;Enable IRQ interrupts
@@ -87,12 +96,13 @@ ArmInvalidateTlb
mcr p15,0,r0,c8,c7,0
bx lr
ArmSetTranslationTableBaseAddress
ArmSetTTBR0
mcr p15,0,r0,c2,c0,0
bx lr
ArmGetTranslationTableBaseAddress
ArmGetTTBR0BaseAddress
mrc p15,0,r0,c2,c0,0
and r0, r0, #0xFFFFC000
bx lr
ArmSetDomainAccessControl

25
ArmPkg/Library/ArmMPCoreMailBoxLib/ArmMPCoreMailBox.c Normal file
View File

@@ -0,0 +1,25 @@
/** @file
*
* Copyright (c) 2011, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
* which accompanies this distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#include <Library/ArmMPCoreMailBoxLib.h>
#include <Library/PcdLib.h>
#include <Library/IoLib.h>
VOID ArmClearMPCoreMailbox() {
MmioWrite32(PcdGet32(PcdMPCoreMailboxClearAddress),PcdGet32(PcdMPCoreMailboxClearValue));
}
UINTN ArmGetMPCoreMailbox() {
return MmioRead32(PcdGet32(PcdMPCoreMailboxGetAddress));
}

37
ArmPkg/Library/ArmMPCoreMailBoxLib/ArmMPCoreMailBoxLib.inf Normal file
View File

@@ -0,0 +1,37 @@
#/* @file
# Copyright (c) 2011, ARM Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#*/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = ArmMPCoreMailBoxLib
FILE_GUID = de76d780-f422-11df-967a-0002a5d5c51b
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = ArmMPCoreMailBoxLib
[Packages]
MdePkg/MdePkg.dec
ArmPkg/ArmPkg.dec
[LibraryClasses]
IoLib
[Sources.common]
ArmMPCoreMailBox.c
[Protocols]
[FixedPcd]
gArmTokenSpaceGuid.PcdMPCoreMailboxGetAddress
gArmTokenSpaceGuid.PcdMPCoreMailboxClearAddress
gArmTokenSpaceGuid.PcdMPCoreMailboxClearValue

79
ArmPkg/Library/ArmTrustZoneLib/ArmTrustZone.c Normal file
View File

@@ -0,0 +1,79 @@
/** @file
*
* Copyright (c) 2011, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
* which accompanies this distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#include <Library/BaseLib.h>
#include <Library/IoLib.h>
#include <Library/ArmTrustZoneLib.h>
#define TZPC_DECPROT0_STATUS_REG 0x800
#define TZPC_DECPROT0_SET_REG 0x804
#define TZPC_DECPROT0_CLEAR_REG 0x808
#define TZASC_CONFIGURATION_REG 0x000
#define TZASC_REGIONS_REG 0x100
#define TZASC_REGION0_LOW_ADDRESS_REG 0x100
#define TZASC_REGION0_HIGH_ADDRESS_REG 0x104
#define TZASC_REGION0_ATTRIBUTES 0x108
/**
FIXME: Need documentation
**/
EFI_STATUS TZPCSetDecProtBits(UINTN TzpcBase, UINTN TzpcId, UINTN Bits) {
if (TzpcId > TZPC_DECPROT_MAX) {
return EFI_INVALID_PARAMETER;
}
MmioWrite32((UINTN)TzpcBase + TZPC_DECPROT0_SET_REG + (TzpcId * 0x0C), Bits);
return EFI_SUCCESS;
}
/**
FIXME: Need documentation
**/
EFI_STATUS TZPCClearDecProtBits(UINTN TzpcBase, UINTN TzpcId, UINTN Bits) {
if (TzpcId> TZPC_DECPROT_MAX) {
return EFI_INVALID_PARAMETER;
}
MmioWrite32((UINTN)TzpcBase + TZPC_DECPROT0_CLEAR_REG + (TzpcId * 0x0C), Bits);
return EFI_SUCCESS;
}
/**
FIXME: Need documentation
**/
UINT32 TZASCGetNumRegions(UINTN TzascBase) {
return (MmioRead32((UINTN)TzascBase + TZASC_CONFIGURATION_REG) & 0xF);
}
/**
FIXME: Need documentation
**/
EFI_STATUS TZASCSetRegion(UINTN TzascBase, UINTN RegionId, UINTN Enabled, UINTN LowAddress, UINTN HighAddress, UINTN Size, UINTN Security) {
UINT32* Region;
if (RegionId > TZASCGetNumRegions(TzascBase)) {
return EFI_INVALID_PARAMETER;
}
Region = (UINT32*)((UINTN)TzascBase + TZASC_REGIONS_REG + (RegionId * 0x10));
MmioWrite32((UINTN)(Region), LowAddress&0xFFFF8000);
MmioWrite32((UINTN)(Region+1), HighAddress);
MmioWrite32((UINTN)(Region+2), ((Security & 0xF) <<28) | ((Size & 0x3F) << 1) | (Enabled & 0x1));
return EFI_SUCCESS;
}

32
ArmPkg/Library/ArmTrustZoneLib/ArmTrustZoneLib.inf Normal file
View File

@@ -0,0 +1,32 @@
#/* @file
# Copyright (c) 2011, ARM Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#*/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = ArmTrustZoneLib
FILE_GUID = 5962d040-8b8a-11df-9a71-0002a5d5c51b
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = ArmTrustZoneLib
[Sources.common]
ArmTrustZone.c
[Packages]
MdePkg/MdePkg.dec
ArmPkg/ArmPkg.dec
[LibraryClasses]
BaseLib
IoLib

3
ArmPkg/Library/BaseMemoryLibStm/Arm/CopyMem.S
View File

@@ -39,8 +39,7 @@ InternalMemCopyMem (
**/
.text
.align 2
.globl ASM_PFX(InternalMemCopyMem)
INTERWORK_FUNC(InternalMemCopyMem)
GCC_ASM_EXPORT(InternalMemCopyMem)
ASM_PFX(InternalMemCopyMem):
stmfd sp!, {r4-r11, lr}

3
ArmPkg/Library/BaseMemoryLibStm/Arm/SetMem.S
View File

@@ -37,8 +37,7 @@ InternalMemSetMem (
.text
.align 2
.globl ASM_PFX(InternalMemSetMem)
INTERWORK_FUNC(InternalMemSetMem)
GCC_ASM_EXPORT(InternalMemSetMem)
ASM_PFX(InternalMemSetMem):
stmfd sp!, {r4-r11, lr}

3
ArmPkg/Library/BaseMemoryLibVstm/Arm/CopyMem.S
View File

@@ -39,8 +39,7 @@ InternalMemCopyMem (
**/
.text
.align 2
.globl ASM_PFX(InternalMemCopyMem)
INTERWORK_FUNC(InternalMemCopyMem)
GCC_ASM_EXPORT(InternalMemCopyMem)
ASM_PFX(InternalMemCopyMem):
stmfd sp!, {r4, r9, lr}

3
ArmPkg/Library/BaseMemoryLibVstm/Arm/SetMem.S
View File

@@ -37,8 +37,7 @@ InternalMemSetMem (
.text
.align 2
.globl ASM_PFX(InternalMemSetMem)
INTERWORK_FUNC(InternalMemSetMem)
GCC_ASM_EXPORT(InternalMemSetMem)
ASM_PFX(InternalMemSetMem):
stmfd sp!, {r4-r7, lr}

2
ArmPkg/Library/BasePeCoffLib/BasePeCoff.c
View File

@@ -913,7 +913,7 @@ PeCoffLoaderLoadImage (
ImageContext->Handle,
0,
&ImageContext->SizeOfHeaders,
(void *)(UINTN)ImageContext->ImageAddress
(VOID*)(UINTN)ImageContext->ImageAddress
);
Hdr.Te = (EFI_TE_IMAGE_HEADER *)(UINTN)(ImageContext->ImageAddress);

102
ArmPkg/Library/BdsLib/BdsAppLoader.c Normal file
View File

@@ -0,0 +1,102 @@
/** @file
*
* Copyright (c) 2011, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
* which accompanies this distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#include "BdsInternal.h"
EFI_STATUS
BdsLoadPeCoff (
IN BDS_FILE *EfiAppFile
)
{
EFI_STATUS Status;
EFI_HANDLE ImageHandle;
MEDIA_FW_VOL_FILEPATH_DEVICE_PATH NewNode;
EFI_DEVICE_PATH_PROTOCOL *DevicePath;
// Only support loading from FV right now
ASSERT(EfiAppFile->Type == BDS_FILETYPE_FV);
// Generate the Device Path for the file
DevicePath = DuplicateDevicePath(EfiAppFile->DevicePath);
EfiInitializeFwVolDevicepathNode (&NewNode, &(EfiAppFile->File.Fv.Guid));
DevicePath = AppendDevicePathNode (DevicePath, (EFI_DEVICE_PATH_PROTOCOL *)&NewNode);
Status = gBS->LoadImage (TRUE, gImageHandle, DevicePath, NULL, 0, &ImageHandle);
if (!EFI_ERROR (Status)) {
Status = gBS->StartImage (ImageHandle, NULL, NULL);
}
return Status;
}
EFI_STATUS BdsLoadApplicationFromPath(
IN CHAR16* EfiAppPath
) {
EFI_STATUS Status;
BDS_FILE EfiAppFile;
// Need to connect every drivers to ensure no dependencies are missing for the application
Status = BdsConnectAllDrivers();
if (EFI_ERROR(Status)) {
DEBUG ((EFI_D_ERROR, "FAIL to connect all drivers\n"));
return Status;
}
// Locate the application from a device path
Status = BdsLoadFilePath(EfiAppPath, &EfiAppFile);
if (EFI_ERROR(Status)) {
DEBUG ((EFI_D_ERROR, "ERROR: Do not find EFI application %s\n",EfiAppPath));
return Status;
}
// Start the application
Status = BdsLoadPeCoff(&EfiAppFile);
return Status;
}
EFI_STATUS BdsLoadApplication(
IN CHAR16* EfiApp
) {
EFI_STATUS Status;
UINTN NoHandles, HandleIndex;
EFI_HANDLE *Handles;
BDS_FILE EfiAppFile;
// Need to connect every drivers to ensure no dependencies are missing for the application
Status = BdsConnectAllDrivers();
if (EFI_ERROR(Status)) {
DEBUG ((EFI_D_ERROR, "FAIL to connect all drivers\n"));
return Status;
}
// Search the application in any Firmware Volume
Status = gBS->LocateHandleBuffer (ByProtocol, &gEfiFirmwareVolume2ProtocolGuid, NULL, &NoHandles, &Handles);
if (EFI_ERROR (Status) || (NoHandles == 0)) {
DEBUG ((EFI_D_ERROR, "FAIL to find Firmware Volume\n"));
return Status;
}
// Search in all Firmware Volume for the EFI Application
for (HandleIndex = 0; HandleIndex < NoHandles; HandleIndex++) {
Status = BdsLoadFileFromFirmwareVolume(Handles[HandleIndex],EfiApp,EFI_FV_FILETYPE_APPLICATION,&EfiAppFile);
if (!EFI_ERROR (Status)) {
// Start the application
Status = BdsLoadPeCoff(&EfiAppFile);
return Status;
}
}
return Status;
}

182
ArmPkg/Library/BdsLib/BdsFilePath.c Normal file
View File

@@ -0,0 +1,182 @@
/** @file
*
* Copyright (c) 2011, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
* which accompanies this distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#include "BdsInternal.h"
// Count the number of DevicePath Node
static UINTN NumberNodeFromDevicePath(
IN EFI_DEVICE_PATH_PROTOCOL* DevicePath
) {
UINTN NumberDevicePathNode = 0;
while (!IsDevicePathEnd (DevicePath)) {
NumberDevicePathNode++;
DevicePath = NextDevicePathNode(DevicePath);
}
return NumberDevicePathNode;
}
// Extract the FilePath from the Device Path
CHAR16* BdsExtractFilePathFromDevicePath(
IN CONST CHAR16 *StrDevicePath,
IN UINTN NumberDevicePathNode
) {
UINTN Node;
CHAR16 *Str;
Str = (CHAR16*)StrDevicePath;
Node = 0;
while ((Str != NULL) && (*Str != L'\0') && (Node < NumberDevicePathNode)) {
if ((*Str == L'/') || (*Str == L'\\')) {
Node++;
}
Str++;
}
if (*Str == L'\0') {
return NULL;
} else {
return Str;
}
}
EFI_STATUS
BdsLoadDevicePath(
IN EFI_DEVICE_PATH_PROTOCOL* DevicePath,
OUT EFI_HANDLE *Handle
) {
EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath;
EFI_STATUS Status;
if ((DevicePath == NULL) || (Handle == NULL)) {
return EFI_INVALID_PARAMETER;
}
do {
RemainingDevicePath = DevicePath;
// The LocateDevicePath() function locates all devices on DevicePath that support Protocol and returns
// the handle to the device that is closest to DevicePath. On output, the device path pointer is modified
// to point to the remaining part of the device path
Status = gBS->LocateDevicePath(&gEfiDevicePathProtocolGuid,&RemainingDevicePath,Handle);
if (!EFI_ERROR (Status)) {
// Recursive = FALSE: We do not want to start all the device tree
Status = gBS->ConnectController (*Handle, NULL, RemainingDevicePath, FALSE);
}
// We need to check if RemainingDevicePath does not point on the last node. Otherwise, calling
// NextDevicePathNode() will return an undetermined Device Path Node
if (!IsDevicePathEnd (RemainingDevicePath)) {
RemainingDevicePath = NextDevicePathNode (RemainingDevicePath);
}
} while (!EFI_ERROR (Status) && !IsDevicePathEnd (RemainingDevicePath));
if (!EFI_ERROR (Status)) {
// Now, we have got the whole Device Path connected, call again ConnectController to ensure all the supported Driver
// Binding Protocol are connected (such as DiskIo and SimpleFileSystem)
RemainingDevicePath = DevicePath;
Status = gBS->LocateDevicePath(&gEfiDevicePathProtocolGuid,&RemainingDevicePath,Handle);
if (!EFI_ERROR (Status)) {
Status = gBS->ConnectController (*Handle, NULL, RemainingDevicePath, FALSE);
if (EFI_ERROR (Status)) {
// If the last node is a Memory Map Device Path just return EFI_SUCCESS.
if ((RemainingDevicePath->Type == HARDWARE_DEVICE_PATH) && (RemainingDevicePath->SubType == HW_MEMMAP_DP)) {
Status = EFI_SUCCESS;
}
}
}
} else if (IsDevicePathEnd (RemainingDevicePath)) {
// Case when the DevicePath contains a MemoryMap Device Path Node and all drivers are connected.
// Ensure the Device Path exists
RemainingDevicePath = DevicePath;
Status = gBS->LocateDevicePath(&gEfiDevicePathProtocolGuid,&RemainingDevicePath,Handle);
}
return Status;
}
EFI_STATUS
BdsLoadFilePath (
IN CONST CHAR16 *DeviceFilePath,
OUT BDS_FILE *File
) {
EFI_DEVICE_PATH_PROTOCOL *DevicePath;
EFI_DEVICE_PATH_FROM_TEXT_PROTOCOL *EfiDevicePathFromTextProtocol;
EFI_STATUS Status;
EFI_HANDLE Handle;
UINTN NumberDevicePathNode;
CHAR16 *FilePath;
//Do a sanity check on the Device file path
if (DeviceFilePath == NULL) {
return EFI_INVALID_PARAMETER;
}
// Convert the Device Path String into Device Path Protocol
Status = gBS->LocateProtocol(&gEfiDevicePathFromTextProtocolGuid, NULL, (VOID **)&EfiDevicePathFromTextProtocol);
ASSERT_EFI_ERROR(Status);
DevicePath = EfiDevicePathFromTextProtocol->ConvertTextToDevicePath(DeviceFilePath);
//Do a sanity check on the Device Path
if (DevicePath == NULL) {
return EFI_INVALID_PARAMETER;
}
// Count the number of DevicePath Node
NumberDevicePathNode = NumberNodeFromDevicePath(DevicePath);
// Extract the FilePath from the Device Path
FilePath = BdsExtractFilePathFromDevicePath(DeviceFilePath,NumberDevicePathNode);
Status = BdsLoadDevicePath(DevicePath,&Handle);
if (EFI_ERROR (Status)) {
return Status;
}
//If FilePath == NULL then let consider if a MemoryMap Device Path
if (FilePath == NULL) {
// Check if the Node is a MemoryMap Device Path
Status = BdsLoadFileFromMemMap(Handle,DevicePath,File);
} else {
Status = BdsLoadFileFromSimpleFileSystem(Handle,FilePath,File);
if (EFI_ERROR (Status)) {
Status = BdsLoadFileFromFirmwareVolume(Handle,FilePath,EFI_FV_FILETYPE_ALL,File);
}
}
if (!EFI_ERROR (Status)) {
File->DevicePath = DevicePath;
}
return Status;
}
EFI_STATUS BdsCopyRawFileToRuntimeMemory(
IN BDS_FILE *File,
OUT VOID **FileImage,
OUT UINTN *FileSize
) {
if (File == NULL) {
return EFI_INVALID_PARAMETER;
}
if (File->Type == BDS_FILETYPE_FS) {
return BdsCopyRawFileToRuntimeMemoryFS(File->File.Fs.Handle,FileImage,FileSize);
} else if (File->Type == BDS_FILETYPE_FV) {
return BdsCopyRawFileToRuntimeMemoryFV(&(File->File.Fv),FileImage,FileSize);
} else if (File->Type == BDS_FILETYPE_MEM) {
return BdsCopyRawFileToRuntimeMemoryMemMap(&(File->File.Mem),FileImage,FileSize);
} else {
return EFI_INVALID_PARAMETER;
}
}

86
ArmPkg/Library/BdsLib/BdsFilePathFs.c Normal file
View File

@@ -0,0 +1,86 @@
/** @file
*
* Copyright (c) 2011, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
* which accompanies this distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#include "BdsInternal.h"
EFI_STATUS BdsLoadFileFromSimpleFileSystem(
IN EFI_HANDLE Handle,
IN CHAR16 *FilePath,
OUT BDS_FILE *File
) {
EFI_SIMPLE_FILE_SYSTEM_PROTOCOL *FsProtocol;
EFI_FILE_PROTOCOL *Fs;
EFI_STATUS Status;
EFI_FILE_PROTOCOL *FileHandle = NULL;
if (File == NULL) {
return EFI_INVALID_PARAMETER;
}
Status = gBS->HandleProtocol(Handle,&gEfiSimpleFileSystemProtocolGuid, (VOID **)&FsProtocol);
if (EFI_ERROR(Status)) {
return Status;
}
//Try to Open the volume and get root directory
Status = FsProtocol->OpenVolume(FsProtocol, &Fs);
if (EFI_ERROR(Status)) {
return Status;
}
Status = Fs->Open(Fs, &FileHandle, FilePath, EFI_FILE_MODE_READ, 0);
File->Type = BDS_FILETYPE_FS;
File->FilePath = FilePath;
File->File.Fs.Handle = FileHandle;
return Status;
}
EFI_STATUS BdsCopyRawFileToRuntimeMemoryFS(
IN EFI_FILE_PROTOCOL *File,
OUT VOID **FileImage,
OUT UINTN *FileSize
) {
EFI_FILE_INFO *FileInfo;
UINTN Size;
VOID* Image;
EFI_STATUS Status;
Size = 0;
File->GetInfo(File, &gEfiFileInfoGuid, &Size, NULL);
FileInfo = AllocatePool (Size);
Status = File->GetInfo(File, &gEfiFileInfoGuid, &Size, FileInfo);
if (EFI_ERROR(Status)) {
return Status;
}
// Get the file size
Size = FileInfo->FileSize;
if (FileSize) {
*FileSize = Size;
}
FreePool(FileInfo);
Image = AllocateRuntimePool(Size);
if (Image == NULL) {
return EFI_OUT_OF_RESOURCES;
}
Status = File->Read(File, &Size, Image);
if (!EFI_ERROR(Status)) {
*FileImage = Image;
}
return Status;
}

136
ArmPkg/Library/BdsLib/BdsFilePathFv.c Normal file
View File

@@ -0,0 +1,136 @@
/** @file
*
* Copyright (c) 2011, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
* which accompanies this distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#include "BdsInternal.h"
EFI_STATUS BdsLoadFileFromFirmwareVolume(
IN EFI_HANDLE FvHandle,
IN CHAR16 *FilePath,
IN EFI_FV_FILETYPE FileTypeFilter,
OUT BDS_FILE *File
) {
EFI_FIRMWARE_VOLUME2_PROTOCOL *FvProtocol;
VOID *Key;
EFI_STATUS Status, FileStatus;
EFI_GUID NameGuid;
EFI_FV_FILETYPE FileType;
EFI_FV_FILE_ATTRIBUTES Attributes;
UINTN Size;
UINTN UiStringLen;
CHAR16 *UiSection;
UINT32 Authentication;
if (File == NULL) {
return EFI_INVALID_PARAMETER;
}
Status = gBS->HandleProtocol(FvHandle,&gEfiFirmwareVolume2ProtocolGuid, (VOID **)&FvProtocol);
if (EFI_ERROR(Status)) {
return Status;
}
// Length of FilePath
UiStringLen = StrLen (FilePath);
// Allocate Key
Key = AllocatePool (FvProtocol->KeySize);
ASSERT (Key != NULL);
ZeroMem (Key, FvProtocol->KeySize);
do {
// Search in all files
FileType = FileTypeFilter;
Status = FvProtocol->GetNextFile (FvProtocol, Key, &FileType, &NameGuid, &Attributes, &Size);
if (!EFI_ERROR (Status)) {
UiSection = NULL;
FileStatus = FvProtocol->ReadSection (
FvProtocol,
&NameGuid,
EFI_SECTION_USER_INTERFACE,
0,
(VOID **)&UiSection,
&Size,
&Authentication
);
if (!EFI_ERROR (FileStatus)) {
if (StrnCmp (FilePath, UiSection, UiStringLen) == 0) {
//
// We found a UiString match.
//
//*FileGuid = NameGuid;
File->Type = BDS_FILETYPE_FV;
File->FilePath = FilePath;
CopyGuid (&(File->File.Fv.Guid),&NameGuid);
File->File.Fv.FvProtocol = FvProtocol;
File->File.Fv.FileType = FileType;
Status = gBS->HandleProtocol(FvHandle,&gEfiDevicePathProtocolGuid, (VOID **)&(File->DevicePath));
FreePool (Key);
FreePool (UiSection);
return FileStatus;
}
FreePool (UiSection);
}
}
} while (!EFI_ERROR (Status));
FreePool(Key);
return Status;
}
EFI_STATUS BdsCopyRawFileToRuntimeMemoryFV(
IN BDS_FV_FILE *FvFile,
OUT VOID **FileImage,
OUT UINTN *FileSize
) {
EFI_STATUS Status = EFI_INVALID_PARAMETER;
EFI_FIRMWARE_VOLUME2_PROTOCOL *FvProtocol;
EFI_FV_FILETYPE FileType;
EFI_GUID* NameGuid;
EFI_FV_FILE_ATTRIBUTES Attributes;
UINT32 Authentication;
FvProtocol = FvFile->FvProtocol;
FileType = FvFile->FileType;
NameGuid = &(FvFile->Guid);
if (FileType == EFI_FV_FILETYPE_RAW) {
*FileImage = NULL;
*FileSize = 0;
Status = FvProtocol->ReadFile(
FvProtocol,NameGuid, // IN
FileImage,FileSize, // IN OUT
&FileType,&Attributes,&Authentication // OUT
);
ASSERT_EFI_ERROR(Status);
// This raw file also contains a header
*FileSize = *FileSize - 4;
*FileImage = (UINT8*)FileImage + 4;
} else if (FileType == EFI_FV_FILETYPE_FREEFORM) {
Status = FvProtocol->ReadSection (
FvProtocol,NameGuid,EFI_SECTION_RAW,0, // IN
FileImage,FileSize, // IN OUT
&Authentication // OUT
);
ASSERT_EFI_ERROR(Status);
} else {
ASSERT(0); //Maybe support application as well ???
}
return Status;
}

73
ArmPkg/Library/BdsLib/BdsFilePathMem.c Normal file
View File

@@ -0,0 +1,73 @@
/** @file
*
* Copyright (c) 2011, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
* which accompanies this distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#include "BdsInternal.h"
EFI_STATUS BdsLoadFileFromMemMap (
IN EFI_HANDLE Handle,
IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
OUT BDS_FILE *File
) {
EFI_DEVICE_PATH_PROTOCOL *LastDevicePath;
if ((File == NULL) || (DevicePath == NULL) || (IsDevicePathEnd (DevicePath))) {
return EFI_INVALID_PARAMETER;
}
// Check if the last node of the device Path is a Memory Map Device Node
LastDevicePath = DevicePath;
DevicePath = NextDevicePathNode(DevicePath);
while (!IsDevicePathEnd (DevicePath)) {
LastDevicePath = DevicePath;
DevicePath = NextDevicePathNode(DevicePath);
}
if ((LastDevicePath->Type != HARDWARE_DEVICE_PATH) || (LastDevicePath->SubType != HW_MEMMAP_DP)) {
return EFI_UNSUPPORTED;
}
File->Type = BDS_FILETYPE_MEM;
File->File.Mem.MemoryType = ((MEMMAP_DEVICE_PATH*)LastDevicePath)->MemoryType;
File->File.Mem.StartingAddress = ((MEMMAP_DEVICE_PATH*)LastDevicePath)->StartingAddress;
File->File.Mem.EndingAddress = ((MEMMAP_DEVICE_PATH*)LastDevicePath)->EndingAddress;
return EFI_SUCCESS;
}
EFI_STATUS BdsCopyRawFileToRuntimeMemoryMemMap(
IN BDS_MEM_FILE *MemFile,
OUT VOID **FileImage,
OUT UINTN *FileSize
) {
UINTN Size;
VOID* Image;
Size = MemFile->EndingAddress - MemFile->StartingAddress;
if ((Size == 0) || (FileImage == NULL)) {
return EFI_INVALID_PARAMETER;
}
if (FileSize != NULL) {
*FileSize = Size;
}
Image = AllocateRuntimePool(Size);
if (Image == NULL) {
return EFI_OUT_OF_RESOURCES;
}
*FileImage = CopyMem(Image,(CONST VOID*)(UINTN)MemFile->StartingAddress,Size);
return EFI_SUCCESS;
}

183
ArmPkg/Library/BdsLib/BdsHelper.c Normal file
View File

@@ -0,0 +1,183 @@
/** @file
*
* Copyright (c) 2011, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
* which accompanies this distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#include "BdsInternal.h"
#include <Library/DxeServicesTableLib.h>
#include <Library/HobLib.h>
EFI_STATUS
ShutdownUefiBootServices( VOID )
{
EFI_STATUS Status;
UINTN MemoryMapSize;
EFI_MEMORY_DESCRIPTOR *MemoryMap;
UINTN MapKey;
UINTN DescriptorSize;
UINT32 DescriptorVersion;
UINTN Pages;
MemoryMap = NULL;
MemoryMapSize = 0;
do {
Status = gBS->GetMemoryMap (
&MemoryMapSize,
MemoryMap,
&MapKey,
&DescriptorSize,
&DescriptorVersion
);
if (Status == EFI_BUFFER_TOO_SMALL) {
Pages = EFI_SIZE_TO_PAGES (MemoryMapSize) + 1;
MemoryMap = AllocatePages (Pages);
//
// Get System MemoryMap
//
Status = gBS->GetMemoryMap (
&MemoryMapSize,
MemoryMap,
&MapKey,
&DescriptorSize,
&DescriptorVersion
);
// Don't do anything between the GetMemoryMap() and ExitBootServices()
if (!EFI_ERROR (Status)) {
Status = gBS->ExitBootServices (gImageHandle, MapKey);
if (EFI_ERROR (Status)) {
FreePages (MemoryMap, Pages);
MemoryMap = NULL;
MemoryMapSize = 0;
}
}
}
} while (EFI_ERROR (Status));
return Status;
}
EFI_STATUS
BdsConnectAllDrivers( VOID ) {
UINTN HandleCount, Index;
EFI_HANDLE *HandleBuffer;
EFI_STATUS Status;
do {
// Locate all the driver handles
Status = gBS->LocateHandleBuffer (
AllHandles,
NULL,
NULL,
&HandleCount,
&HandleBuffer
);
if (EFI_ERROR (Status)) {
break;
}
// Connect every handles
for (Index = 0; Index < HandleCount; Index++) {
gBS->ConnectController(HandleBuffer[Index], NULL, NULL, TRUE);
}
if (HandleBuffer != NULL) {
FreePool (HandleBuffer);
}
// Check if new handles have been created after the start of the previous handles
Status = gDS->Dispatch ();
} while (!EFI_ERROR(Status));
return EFI_SUCCESS;
}
STATIC EFI_STATUS InsertSystemMemoryResources(LIST_ENTRY *ResourceList, EFI_HOB_RESOURCE_DESCRIPTOR *ResHob) {
BDS_SYSTEM_MEMORY_RESOURCE NewResource;
LIST_ENTRY *Link;
BDS_SYSTEM_MEMORY_RESOURCE *Resource;
//DEBUG ((EFI_D_ERROR, "** InsertSystemMemoryResources(0x%X,0x%X)\n",(UINT32)ResHob->PhysicalStart,(UINT32)ResHob->ResourceLength));
if (IsListEmpty (ResourceList)) {
ZeroMem(&NewResource,sizeof(BDS_SYSTEM_MEMORY_RESOURCE));
NewResource.PhysicalStart = ResHob->PhysicalStart;
NewResource.ResourceLength = ResHob->ResourceLength;
InsertTailList (ResourceList, &NewResource.Link);
return EFI_SUCCESS;
}
//for (Link = GetFirstNode (ResourceList); !IsNull (ResourceList,Link); Link = GetNextNode (ResourceList,Link)) {
Link = ResourceList->ForwardLink;
while (Link != NULL && Link != ResourceList) {
Resource = (BDS_SYSTEM_MEMORY_RESOURCE*)Link;
//DEBUG ((EFI_D_ERROR, " - (0x%X,0x%X)\n",(UINT32)Resource->PhysicalStart,(UINT32)Resource->ResourceLength));
// Sanity Check. The resources should not overlapped.
ASSERT(!((ResHob->PhysicalStart >= Resource->PhysicalStart) && (ResHob->PhysicalStart < (Resource->PhysicalStart + Resource->ResourceLength))));
ASSERT(!((ResHob->PhysicalStart + ResHob->ResourceLength >= Resource->PhysicalStart) &&
((ResHob->PhysicalStart + ResHob->ResourceLength) < (Resource->PhysicalStart + Resource->ResourceLength))));
// The new resource is attached after this resource descriptor
if (ResHob->PhysicalStart == Resource->PhysicalStart + Resource->ResourceLength) {
Resource->ResourceLength = Resource->ResourceLength + ResHob->ResourceLength;
//DEBUG ((EFI_D_ERROR, "** Attached new Length:0x%X\n",(UINT32)Resource->ResourceLength));
return EFI_SUCCESS;
}
// The new resource is attached before this resource descriptor
else if (ResHob->PhysicalStart + ResHob->ResourceLength == Resource->PhysicalStart) {
Resource->PhysicalStart = ResHob->PhysicalStart;
Resource->ResourceLength = Resource->ResourceLength + ResHob->ResourceLength;
//DEBUG ((EFI_D_ERROR, "** Attached2 new Length:0x%X\n",(UINT32)Resource->ResourceLength));
return EFI_SUCCESS;
}
Link = Link->ForwardLink;
}
// None of the Resource of the list is attached to this ResHob. Create a new entry for it
ZeroMem(&NewResource,sizeof(BDS_SYSTEM_MEMORY_RESOURCE));
NewResource.PhysicalStart = ResHob->PhysicalStart;
NewResource.ResourceLength = ResHob->ResourceLength;
InsertTailList (ResourceList, &NewResource.Link);
return EFI_SUCCESS;
}
EFI_STATUS GetSystemMemoryResources(LIST_ENTRY *ResourceList) {
EFI_HOB_RESOURCE_DESCRIPTOR *ResHob;
InitializeListHead (ResourceList);
// Find the first System Memory Resource Descriptor
ResHob = (EFI_HOB_RESOURCE_DESCRIPTOR *)GetFirstHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR);
while ((ResHob != NULL) && (ResHob->ResourceType != EFI_RESOURCE_SYSTEM_MEMORY)) {
ResHob = (EFI_HOB_RESOURCE_DESCRIPTOR *)GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR,(VOID *)((UINTN)ResHob + ResHob->Header.HobLength));
}
// Did not find any
if (ResHob == NULL) {
return EFI_NOT_FOUND;
} else {
InsertSystemMemoryResources(ResourceList, ResHob);
}
ResHob = (EFI_HOB_RESOURCE_DESCRIPTOR *)GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR,(VOID *)((UINTN)ResHob + ResHob->Header.HobLength));
while (ResHob != NULL) {
if (ResHob->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) {
InsertSystemMemoryResources(ResourceList, ResHob);
}
ResHob = (EFI_HOB_RESOURCE_DESCRIPTOR *)GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR,(VOID *)((UINTN)ResHob + ResHob->Header.HobLength));
}
return EFI_SUCCESS;
}

136
ArmPkg/Library/BdsLib/BdsInternal.h Normal file
View File

@@ -0,0 +1,136 @@
/** @file
*
* Copyright (c) 2011, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
* which accompanies this distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#ifndef __BDS_INTERNAL_H__
#define __BDS_INTERNAL_H__
#include <PiDxe.h>
#include <Library/BaseLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiLib.h>
#include <Library/DevicePathLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/DebugLib.h>
#include <Library/BdsUnixLib.h>
#include <Guid/FileInfo.h>
#include <Protocol/DevicePath.h>
#include <Protocol/DevicePathFromText.h>
#include <Protocol/SimpleFileSystem.h>
#include <Protocol/FirmwareVolume2.h>
typedef enum { BDS_FILETYPE_MEM, BDS_FILETYPE_FS, BDS_FILETYPE_FV } BDS_FILE_TYPE;
typedef struct {
UINT32 MemoryType;
EFI_PHYSICAL_ADDRESS StartingAddress;
EFI_PHYSICAL_ADDRESS EndingAddress;
} BDS_MEM_FILE;
typedef struct {
EFI_FILE_PROTOCOL *Handle;
} BDS_FS_FILE;
typedef struct {
EFI_FIRMWARE_VOLUME2_PROTOCOL *FvProtocol;
EFI_FV_FILETYPE FileType;
EFI_GUID Guid;
} BDS_FV_FILE;
typedef struct _BDS_FILE {
CHAR16* FilePath;
EFI_DEVICE_PATH_PROTOCOL *DevicePath;
BDS_FILE_TYPE Type;
union {
BDS_MEM_FILE Mem;
BDS_FS_FILE Fs;
BDS_FV_FILE Fv;
} File;
} BDS_FILE;
typedef struct _BDS_SYSTEM_MEMORY_RESOURCE {
LIST_ENTRY Link; // This attribute must be the first entry of this structure (to avoid pointer computation)
EFI_PHYSICAL_ADDRESS PhysicalStart;
UINT64 ResourceLength;
} BDS_SYSTEM_MEMORY_RESOURCE;
// BdsHelper.c
EFI_STATUS
ShutdownUefiBootServices( VOID );
EFI_STATUS
GetSystemMemoryResources (LIST_ENTRY *ResourceList);
// BdsFilePath.c
EFI_STATUS BdsLoadDevicePath(
IN EFI_DEVICE_PATH_PROTOCOL* DevicePath,
OUT EFI_HANDLE *Handle
);
EFI_STATUS BdsLoadFilePath(
IN CONST CHAR16 *DeviceFilePath,
OUT BDS_FILE *File
);
EFI_STATUS BdsCopyRawFileToRuntimeMemory(
IN BDS_FILE *File,
OUT VOID **FileImage,
OUT UINTN *FileSize
);
// BdsFilePathFs.c
EFI_STATUS BdsLoadFileFromSimpleFileSystem(
IN EFI_HANDLE Handle,
IN CHAR16 *FilePath,
OUT BDS_FILE *File
);
EFI_STATUS BdsCopyRawFileToRuntimeMemoryFS(
IN EFI_FILE_PROTOCOL *File,
OUT VOID **FileImage,
OUT UINTN *FileSize
);
// BdsFilePathFv.c
EFI_STATUS BdsLoadFileFromFirmwareVolume(
IN EFI_HANDLE FvHandle,
IN CHAR16 *FilePath,
IN EFI_FV_FILETYPE FileTypeFilter,
OUT BDS_FILE *File
);
EFI_STATUS BdsCopyRawFileToRuntimeMemoryFV(
IN BDS_FV_FILE *FvFile,
OUT VOID **FileImage,
OUT UINTN *FileSize
);
// BdsFilePathMem.c
EFI_STATUS BdsLoadFileFromMemMap (
IN EFI_HANDLE Handle,
IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
OUT BDS_FILE *File
);
EFI_STATUS BdsCopyRawFileToRuntimeMemoryMemMap(
IN BDS_MEM_FILE *MemFile,
OUT VOID **FileImage,
OUT UINTN *FileSize
);
#endif

63
ArmPkg/Library/BdsLib/BdsLib.inf Normal file
View File

@@ -0,0 +1,63 @@
#/* @file
# Copyright (c) 2011, ARM Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#*/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = BdsLib
FILE_GUID = ddbf73a0-bb25-11df-8e4e-0002a5d5c51b
MODULE_TYPE = UEFI_DRIVER
VERSION_STRING = 1.0
LIBRARY_CLASS = BdsLib
[Sources.common]
BdsFilePath.c
BdsFilePathFs.c
BdsFilePathFv.c
BdsFilePathMem.c
BdsLinuxLoader.c
BdsAppLoader.c
BdsHelper.c
[Packages]
MdePkg/MdePkg.dec
EmbeddedPkg/EmbeddedPkg.dec
ArmPkg/ArmPkg.dec
[LibraryClasses]
DevicePathLib
BaseLib
HobLib
DebugLib
UefiDriverEntryPoint
DxeServicesTableLib
ArmLib
[Guids]
gEfiFileInfoGuid
[Protocols]
gEfiBdsArchProtocolGuid
gEfiDevicePathProtocolGuid
gEfiDevicePathFromTextProtocolGuid
gEfiSimpleFileSystemProtocolGuid
gEfiFirmwareVolume2ProtocolGuid
[FeaturePcd]
[FixedPcd]
gArmTokenSpaceGuid.PcdArmMachineType
[Pcd]
[Depex]
TRUE

337
ArmPkg/Library/BdsLib/BdsLinuxLoader.c Normal file
View File

@@ -0,0 +1,337 @@
/** @file
*
* Copyright (c) 2011, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
* which accompanies this distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#include "BdsInternal.h"
#include "BdsLinuxLoader.h"
#include <Library/PcdLib.h>
#include <Library/ArmLib.h>
#include <Library/HobLib.h>
STATIC
EFI_STATUS
GetARMLinuxMachineType (
IN BOOLEAN FdtSupported,
OUT UINT32 *MachineType
) {
if (FdtSupported)
{
// FDT requires that the machine type is set to the maximum 32-bit number.
*MachineType = 0xFFFFFFFF;
}
else
{
// Non-FDT requires a specific machine type.
// This OS Boot loader supports just one machine type,
// but that could change in the future.
*MachineType = PcdGet32(PcdArmMachineType);
}
return EFI_SUCCESS;
}
STATIC
VOID
SetupCoreTag( IN UINT32 PageSize )
{
Params->header.size = tag_size(atag_core);
Params->header.type = ATAG_CORE;
Params->body.core_tag.flags = 1; /* ensure read-only */
Params->body.core_tag.pagesize = PageSize; /* systems PageSize (4k) */
Params->body.core_tag.rootdev = 0; /* zero root device (typically overridden from kernel command line )*/
Params = next_tag_address(Params); /* move pointer to next tag */
}
STATIC
VOID
SetupMemTag( IN UINTN StartAddress, IN UINT32 Size )
{
Params->header.size = tag_size(atag_mem);
Params->header.type = ATAG_MEM;
Params->body.mem_tag.start = StartAddress; /* Start of memory chunk for AtagMem */
Params->body.mem_tag.size = Size; /* Size of memory chunk for AtagMem */
Params = next_tag_address(Params); /* move pointer to next tag */
}
STATIC
VOID
SetupCmdlineTag( IN CONST CHAR8 *CmdLine )
{
UINT32 LineLength;
// Increment the line length by 1 to account for the null string terminator character
LineLength = AsciiStrLen(CmdLine) + 1;
/* Check for NULL strings.
* Do not insert a tag for an empty CommandLine, don't even modify the tag address pointer.
* Remember, you have at least one null string terminator character.
*/
if( LineLength > 1 )
{
Params->header.size = ((UINT32)sizeof(struct atag_header) + LineLength + (UINT32)3) >> 2;
Params->header.type = ATAG_CMDLINE;
/* place CommandLine into tag */
AsciiStrCpy(Params->body.cmdline_tag.cmdline, CmdLine);
Params = next_tag_address(Params); /* move pointer to next tag */
}
}
STATIC
VOID
SetupEndTag( VOID )
{
// Empty tag ends list; this has zero length and no body
Params->header.type = ATAG_NONE;
Params->header.size = 0;
/* We can not calculate the next address by using the standard macro:
* Params = next_tag_address(Params);
* because it relies on the header.size, which here it is 0 (zero).
* The easiest way is to add the sizeof(Params->header).
*/
Params = (struct atag *)((UINT32)Params + sizeof(Params->header));
}
STATIC
EFI_STATUS
PrepareAtagList(
IN OUT struct atag **AtagStartAddress,
IN CONST CHAR8* CommandLineString,
OUT UINT32 *AtagSize
) {
LIST_ENTRY *ResourceLink;
LIST_ENTRY ResourceList;
BDS_SYSTEM_MEMORY_RESOURCE *Resource;
// If no address supplied then this function will decide where to put it
if( *AtagStartAddress == 0 )
{
/* WARNING: At the time of writing (2010-July-30) the linux kernel expects
* the atag list it in the first 1MB of memory and preferably at address 0x100.
* This has a very high risk of overwriting UEFI code, but as
* the linux kernel does not expect any runtime services from uefi
* and there is no afterlife section following the linux kernel termination,
* it does not matter if we stamp over that memory area.
*
* The proposed workaround is to create the atag list somewhere in boot services memory
* and then transfer it to address 0x100 (or to runtime services memory) immediately
* before starting the kernel.
* An additional benefit of this is that when we copy the ATAG list to it's final place,
* we can trim down the memory allocation size. Before we create the list we don't know
* how much space it is going to take, so we are over-allocating space.
*/
*AtagStartAddress = (struct atag *) AllocatePool(ATAG_MAX_SIZE);
}
// Ensure the pointer is not NULL.
ASSERT( *AtagStartAddress != (struct atag *)NULL );
// Ready to setup the atag list
Params = *AtagStartAddress;
// Standard core tag 4k PageSize
SetupCoreTag( (UINT32)SIZE_4KB );
// Physical memory setup
GetSystemMemoryResources(&ResourceList);
ResourceLink = ResourceList.ForwardLink;
while (ResourceLink != NULL && ResourceLink != &ResourceList) {
Resource = (BDS_SYSTEM_MEMORY_RESOURCE*)ResourceList.ForwardLink;
SetupMemTag( (UINT32)Resource->PhysicalStart, (UINT32)Resource->ResourceLength );
ResourceLink = ResourceLink->ForwardLink;
}
// CommandLine setting root device
SetupCmdlineTag( CommandLineString );
// end of tags
SetupEndTag();
// Calculate atag list size
*AtagSize = (UINT32)Params - (UINT32)*AtagStartAddress + 1;
return EFI_SUCCESS;
}
STATIC
EFI_STATUS
PreparePlatformHardware( VOID )
{
//Note: Interrupts will be disabled by the GIC driver when ExitBootServices() will be called.
// clean, invalidate, disable data cache
ArmCleanInvalidateDataCache();
ArmDisableDataCache();
// Invalidate and disable the Instruction cache
ArmInvalidateInstructionCache ();
ArmDisableInstructionCache ();
// turn off MMU
ArmInvalidateTlb();
ArmDisableMmu();
return EFI_SUCCESS;
}
/*************************************************
* R0, R1, R2 correspond to registers R0, R1, R2
*************************************************/
//STATIC
EFI_STATUS
StartLinuxKernel( IN VOID* KernelAddress, IN UINTN R0, IN UINTN R1, IN UINTN R2 )
{
VOID (*Kernel)(UINT32 Zero, UINT32 Arch, UINTN AtagListParams);
// set the kernel address
Kernel = (VOID (*)(UINT32, UINT32, UINTN)) KernelAddress;
// Outside BootServices, so can't use Print();
DEBUG((EFI_D_ERROR, "\nStarting the kernel:\n\n"));
// jump to kernel with register set
Kernel( R0, R1, R2 );
// Kernel should never exit
// After Life services are not provided
ASSERT( FALSE );
return EFI_SUCCESS;
}
EFI_STATUS BdsBootLinux(
IN CONST CHAR16* LinuxKernel,
IN CONST CHAR8* ATag,
IN CONST CHAR16* Fdt
) {
BDS_FILE LinuxKernelFile;
BDS_FILE FdtFile;
EFI_STATUS Status;
VOID* LinuxImage;
UINT32 KernelParamsSize;
VOID* KernelParamsAddress = NULL;
UINTN KernelParamsNewAddress;
UINTN *AtagAddress;
UINT32 MachineType;
BOOLEAN FdtSupported = FALSE;
EFI_HOB_RESOURCE_DESCRIPTOR *ResHob;
// Load the Linux kernel from a device path
Status = BdsLoadFilePath(LinuxKernel, &LinuxKernelFile);
if (EFI_ERROR(Status)) {
DEBUG ((EFI_D_ERROR, "ERROR: Do not find Linux kernel %s\n",LinuxKernel));
return Status;
}
// Copy the Linux Kernel from the raw file to Runtime memory
Status = BdsCopyRawFileToRuntimeMemory(&LinuxKernelFile,&LinuxImage,NULL);
if (EFI_ERROR(Status)) {
goto Exit;
}
// Load the FDT binary from a device path
Status = BdsLoadFilePath(Fdt, &FdtFile);
if (!EFI_ERROR(Status)) {
// Copy the FDT binary from the raw file to Runtime memory
Status = BdsCopyRawFileToRuntimeMemory(&FdtFile,&KernelParamsAddress,&KernelParamsSize);
if (EFI_ERROR(Status)) {
goto Exit;
} else {
FdtSupported = TRUE;
}
}
/**********************************************************
* Setup the platform type
**********************************************************/
Status = GetARMLinuxMachineType(FdtSupported, &MachineType);
if(EFI_ERROR(Status))
{
Print(L"ERROR : Can not prepare ARM Linux machine type. Status=0x%X\n", Status);
goto Exit;
}
if (!FdtSupported) {
/**********************************************************
* Setup the ATAG list
**********************************************************/
// By setting address=0 we leave the memory allocation to the function
AtagAddress = 0;
Status = PrepareAtagList( (struct atag **)&AtagAddress, ATag, &KernelParamsSize );
KernelParamsAddress = (VOID*)AtagAddress;
if(EFI_ERROR(Status))
{
Print(L"ERROR : Can not prepare ATAG list. Status=0x%X\n", Status);
goto Exit;
}
}
/**********************************************************
* Switch off interrupts, caches, mmu, etc
**********************************************************/
Status = PreparePlatformHardware();
if(EFI_ERROR(Status))
{
Print(L"ERROR : Can not prepare platform hardware. Status=0x%X\n", Status);
goto Exit;
}
// Initialize the ATag destination
KernelParamsNewAddress = 0x100;
// Update the ATag destination by finding the start address of the first System Memory Resource Descriptor Hob
ResHob = (EFI_HOB_RESOURCE_DESCRIPTOR *)GetFirstHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR);
while (ResHob != NULL) {
if (ResHob->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) {
KernelParamsNewAddress = (UINTN)ResHob->PhysicalStart + 0x100;
break;
}
ResHob = (EFI_HOB_RESOURCE_DESCRIPTOR *)GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, (VOID *)((UINTN)ResHob + ResHob->Header.HobLength));
}
// Shut down UEFI boot services. ExitBootServices() will notify every driver that created an event on
// ExitBootServices event. Example the Interrupt DXE driver will disable the interrupts on this event.
Status = ShutdownUefiBootServices();
if(EFI_ERROR(Status))
{
Print(L"ERROR : Can not shutdown UEFI boot services. Status=0x%X\n", Status);
goto Exit;
}
// Move the kernel parameters to any address inside the first 1MB.
// This is necessary because the ARM Linux kernel requires
// the FTD / ATAG List to reside entirely inside the first 1MB of
// physical memory.
CopyMem((VOID*)KernelParamsNewAddress, KernelParamsAddress, KernelParamsSize);
//**********************************************************
// * Start the Linux Kernel
// **********************************************************
// Lift off ...
Status = StartLinuxKernel(LinuxImage, (UINTN)0, (UINTN)MachineType, KernelParamsNewAddress );
// Only be here if we fail to start Linux
DEBUG((EFI_D_ERROR, "ERROR : Can not start the kernel. Status=0x%X\n", Status));
Exit:
// Free Runtimee Memory (kernel and FDT)
return Status;
}

165
ArmPkg/Library/BdsLib/BdsLinuxLoader.h Normal file
View File

@@ -0,0 +1,165 @@
/** @file
*
* Copyright (c) 2011, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
* which accompanies this distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#ifndef __BDSLINUXLOADER_H
#define __BDSLINUXLOADER_H
#define ATAG_MAX_SIZE 0x4000
//PcdKernelParamsMaxMemorySize
/* ATAG : list of possible tags */
#define ATAG_NONE 0x00000000
#define ATAG_CORE 0x54410001
#define ATAG_MEM 0x54410002
#define ATAG_VIDEOTEXT 0x54410003
#define ATAG_RAMDISK 0x54410004
#define ATAG_INITRD2 0x54420005
#define ATAG_SERIAL 0x54410006
#define ATAG_REVISION 0x54410007
#define ATAG_VIDEOLFB 0x54410008
#define ATAG_CMDLINE 0x54410009
#define ATAG_ARM_MP_CORE 0x5441000A
// Some system addresses
// These should probably come from the platform header file or from pcd values
#define DRAM_BASE 0x10000000
#define ZIMAGE_LOAD_ADDRESS (DRAM_BASE + 0x8000)
#define INITRD_LOAD_ADDRESS (DRAM_BASE + 0x800000)
#define SIZE_1B 0x00000001
#define SIZE_2B 0x00000002
#define SIZE_4B 0x00000004
#define SIZE_8B 0x00000008
#define SIZE_16B 0x00000010
#define SIZE_32B 0x00000020
#define SIZE_64B 0x00000040
#define SIZE_128B 0x00000080
#define SIZE_256B 0x00000100
#define SIZE_512B 0x00000200
#define SIZE_1KB 0x00000400
#define SIZE_2KB 0x00000800
#define SIZE_4KB 0x00001000
#define SIZE_8KB 0x00002000
#define SIZE_16KB 0x00004000
#define SIZE_32KB 0x00008000
#define SIZE_64KB 0x00010000
#define SIZE_128KB 0x00020000
#define SIZE_256KB 0x00040000
#define SIZE_512KB 0x00080000
#define SIZE_1MB 0x00100000
#define SIZE_2MB 0x00200000
#define SIZE_4MB 0x00400000
#define SIZE_8MB 0x00800000
#define SIZE_16MB 0x01000000
#define SIZE_32MB 0x02000000
#define SIZE_64MB 0x04000000
#define SIZE_100MB 0x06400000
#define SIZE_128MB 0x08000000
#define SIZE_256MB 0x10000000
#define SIZE_512MB 0x20000000
#define SIZE_1GB 0x40000000
#define SIZE_2GB 0x80000000
/* structures for each atag */
struct atag_header {
UINT32 size; /* length of tag in words including this header */
UINT32 type; /* tag type */
};
struct atag_core {
UINT32 flags;
UINT32 pagesize;
UINT32 rootdev;
};
struct atag_mem {
UINT32 size;
UINTN start;
};
struct atag_videotext {
UINT8 x;
UINT8 y;
UINT16 video_page;
UINT8 video_mode;
UINT8 video_cols;
UINT16 video_ega_bx;
UINT8 video_lines;
UINT8 video_isvga;
UINT16 video_points;
};
struct atag_ramdisk {
UINT32 flags;
UINT32 size;
UINTN start;
};
struct atag_initrd2 {
UINT32 start;
UINT32 size;
};
struct atag_serialnr {
UINT32 low;
UINT32 high;
};
struct atag_revision {
UINT32 rev;
};
struct atag_videolfb {
UINT16 lfb_width;
UINT16 lfb_height;
UINT16 lfb_depth;
UINT16 lfb_linelength;
UINT32 lfb_base;
UINT32 lfb_size;
UINT8 red_size;
UINT8 red_pos;
UINT8 green_size;
UINT8 green_pos;
UINT8 blue_size;
UINT8 blue_pos;
UINT8 rsvd_size;
UINT8 rsvd_pos;
};
struct atag_cmdline {
CHAR8 cmdline[1];
};
struct atag {
struct atag_header header;
union {
struct atag_core core_tag;
struct atag_mem mem_tag;
struct atag_videotext videotext_tag;
struct atag_ramdisk ramdisk_tag;
struct atag_initrd2 initrd2_tag;
struct atag_serialnr serialnr_tag;
struct atag_revision revision_tag;
struct atag_videolfb videolfb_tag;
struct atag_cmdline cmdline_tag;
} body;
};
#define next_tag_address(t) ((struct atag *)((UINT32)(t) + (((t)->header.size) << 2) ))
#define tag_size(type) ((UINT32)((sizeof(struct atag_header) + sizeof(struct type)) >> 2))
STATIC struct atag *Params; /* used to point at the current tag */
#endif

3
ArmPkg/Library/CompilerIntrinsicsLib/Arm/ashldi3.S
View File

@@ -14,8 +14,7 @@
.text
.align 2
.globl ASM_PFX(__ashldi3)
INTERWORK_FUNC(__ashldi3)
GCC_ASM_EXPORT(__ashldi3)
ASM_PFX(__ashldi3):
cmp r2, #31

3
ArmPkg/Library/CompilerIntrinsicsLib/Arm/ashrdi3.S
View File

@@ -14,8 +14,7 @@
.text
.align 2
.globl ASM_PFX(__ashrdi3)
INTERWORK_FUNC(__ashrdi3)
GCC_ASM_EXPORT(__ashrdi3)
ASM_PFX(__ashrdi3):
cmp r2, #31

3
ArmPkg/Library/CompilerIntrinsicsLib/Arm/clzsi2.S
View File

@@ -14,8 +14,7 @@
.text
.align 2
.globl ASM_PFX(__clzsi2)
INTERWORK_FUNC(__clzsi2)
GCC_ASM_EXPORT(__clzsi2)
ASM_PFX(__clzsi2):
@ frame_needed = 1, uses_anonymous_args = 0

3
ArmPkg/Library/CompilerIntrinsicsLib/Arm/ctzsi2.S
View File

@@ -14,8 +14,7 @@
.text
.align 2
.globl ASM_PFX(__ctzsi2)
INTERWORK_FUNC(__ctzsi2)
GCC_ASM_EXPORT(__ctzsi2)
ASM_PFX(__ctzsi2):
uxth r3, r0

3
ArmPkg/Library/CompilerIntrinsicsLib/Arm/divdi3.S
View File

@@ -14,8 +14,7 @@
.text
.align 2
.globl ASM_PFX(__divdi3)
INTERWORK_FUNC(__divdi3)
GCC_ASM_EXPORT(__divdi3)
ASM_PFX(__divdi3):
@ args = 0, pretend = 0, frame = 0

3
ArmPkg/Library/CompilerIntrinsicsLib/Arm/divsi3.S
View File

@@ -14,8 +14,7 @@
.text
.align 2
.globl ASM_PFX(__divsi3)
INTERWORK_FUNC(__divsi3)
GCC_ASM_EXPORT(__divsi3)
ASM_PFX(__divsi3):
eor r3, r0, r0, asr #31

3
ArmPkg/Library/CompilerIntrinsicsLib/Arm/ldivmod.S
View File

@@ -15,8 +15,7 @@
.text
.align 2
.globl ASM_PFX(__aeabi_ldivmod)
INTERWORK_FUNC(__aeabi_ldivmod)
GCC_ASM_EXPORT(__aeabi_ldivmod)
//
// A pair of (unsigned) long longs is returned in {{r0, r1}, {r2, r3}},

3
ArmPkg/Library/CompilerIntrinsicsLib/Arm/lshrdi3.S
View File

@@ -14,8 +14,7 @@
.text
.align 2
.globl ASM_PFX(__lshrdi3)
INTERWORK_FUNC(__lshrdi3)
GCC_ASM_EXPORT(__lshrdi3)
ASM_PFX(__lshrdi3):
cmp r2, #31

3
ArmPkg/Library/CompilerIntrinsicsLib/Arm/memcpy.S
View File

@@ -14,8 +14,7 @@
.text
.align 2
.globl ASM_PFX(memcpy)
INTERWORK_FUNC(memcpy)
GCC_ASM_EXPORT(memcpy)
ASM_PFX(memcpy):
stmfd sp!, {r7, lr}

3
ArmPkg/Library/CompilerIntrinsicsLib/Arm/memset.S
View File

@@ -15,8 +15,7 @@
.text
.align 2
.globl ASM_PFX(memset)
INTERWORK_FUNC(memset)
GCC_ASM_EXPORT (memset)
ASM_PFX(memset):
@ args = 0, pretend = 0, frame = 0

3
ArmPkg/Library/CompilerIntrinsicsLib/Arm/moddi3.S
View File

@@ -14,8 +14,7 @@
.text
.align 2
.globl ASM_PFX(__moddi3)
INTERWORK_FUNC(__moddi3)
GCC_ASM_EXPORT(__moddi3)
ASM_PFX(__moddi3):
stmfd sp!, {r4, r5, r7, lr}

3
ArmPkg/Library/CompilerIntrinsicsLib/Arm/modsi3.S
View File

@@ -14,8 +14,7 @@
.text
.align 2
.globl ASM_PFX(__modsi3)
INTERWORK_FUNC(__modsi3)
GCC_ASM_EXPORT(__modsi3)
ASM_PFX(__modsi3):
stmfd sp!, {r4, r5, r7, lr}

3
ArmPkg/Library/CompilerIntrinsicsLib/Arm/muldi3.S
View File

@@ -14,8 +14,7 @@
.text
.align 2
.globl ASM_PFX(__muldi3)
INTERWORK_FUNC(__muldi3)
GCC_ASM_EXPORT(__muldi3)
ASM_PFX(__muldi3):
stmfd sp!, {r4, r5, r6, r7, lr}

3
ArmPkg/Library/CompilerIntrinsicsLib/Arm/sourcery.S
View File

@@ -15,8 +15,7 @@
.text
.align 2
.globl ASM_PFX(__aeabi_ulcmp)
INTERWORK_FUNC(__aeabi_ulcmp)
GCC_ASM_EXPORT(__aeabi_ulcmp)
ASM_PFX(__aeabi_ulcmp):
stmfd sp!, {r4, r5, r8}

3
ArmPkg/Library/CompilerIntrinsicsLib/Arm/switch16.S
View File

@@ -16,8 +16,7 @@
.text
.p2align 2
.globl ASM_PFX(__switch16)
INTERWORK_FUNC(__switch16)
GCC_ASM_EXPORT(__switch16)
ASM_PFX(__switch16):
ldrh ip, [lr, #-1]

3
ArmPkg/Library/CompilerIntrinsicsLib/Arm/switch32.S
View File

@@ -16,8 +16,7 @@
.text
.p2align 2
.globl ASM_PFX(__switch32)
INTERWORK_FUNC(__switch32)
GCC_ASM_EXPORT(__switch32)
ASM_PFX(__switch32):
ldr ip, [lr, #-1]

4
ArmPkg/Library/CompilerIntrinsicsLib/Arm/switch8.S
View File

@@ -16,9 +16,7 @@
.text
.p2align 2
.globl ASM_PFX(__switch8)
INTERWORK_FUNC(__switch8)
GCC_ASM_EXPORT(__switch8)
ASM_PFX(__switch8):
ldrb ip, [lr, #-1]

3
ArmPkg/Library/CompilerIntrinsicsLib/Arm/switchu8.S
View File

@@ -16,8 +16,7 @@
.text
.p2align 2
.globl ASM_PFX(__switchu8)
INTERWORK_FUNC(__switchu8)
GCC_ASM_EXPORT(__switchu8)
ASM_PFX(__switchu8):

3
ArmPkg/Library/CompilerIntrinsicsLib/Arm/ucmpdi2.S
View File

@@ -14,8 +14,7 @@
.text
.align 2
.globl ASM_PFX(__ucmpdi2)
INTERWORK_FUNC(__ucmpdi2)
GCC_ASM_EXPORT(__ucmpdi2)
ASM_PFX(__ucmpdi2):
stmfd sp!, {r4, r5, r8, lr}

3
ArmPkg/Library/CompilerIntrinsicsLib/Arm/udivdi3.S
View File

@@ -14,8 +14,7 @@
.text
.align 2
.globl ASM_PFX(__udivdi3)
INTERWORK_FUNC(__udivdi3)
GCC_ASM_EXPORT(__udivdi3)
ASM_PFX(__udivdi3):
stmfd sp!, {r7, lr}

5
ArmPkg/Library/CompilerIntrinsicsLib/Arm/udivmoddi4.S
View File

@@ -14,9 +14,8 @@
.text
.align 2
.globl ASM_PFX(__udivmoddi4)
INTERWORK_FUNC(__udivmoddi4)
GCC_ASM_EXPORT(__udivmoddi4)
ASM_PFX(__udivmoddi4):
stmfd sp!, {r4, r5, r6, r7, lr}
add r7, sp, #12

3
ArmPkg/Library/CompilerIntrinsicsLib/Arm/udivsi3.S
View File

@@ -14,8 +14,7 @@
.text
.align 2
.globl ASM_PFX(__udivsi3)
INTERWORK_FUNC(__udivsi3)
GCC_ASM_EXPORT(__udivsi3)
ASM_PFX(__udivsi3):
cmp r1, #0

3
ArmPkg/Library/CompilerIntrinsicsLib/Arm/uldiv.S
View File

@@ -16,8 +16,7 @@
.text
.align 2
.globl ASM_PFX(__aeabi_uldivmod)
INTERWORK_FUNC(__aeabi_uldivmod)
GCC_ASM_EXPORT(__aeabi_uldivmod)
//
//UINT64

3
ArmPkg/Library/CompilerIntrinsicsLib/Arm/umoddi3.S
View File

@@ -14,8 +14,7 @@
.text
.align 2
.globl ASM_PFX(__umoddi3)
INTERWORK_FUNC(__umoddi3)
GCC_ASM_EXPORT(__umoddi3)
ASM_PFX(__umoddi3):
stmfd sp!, {r7, lr}

3
ArmPkg/Library/CompilerIntrinsicsLib/Arm/umodsi3.S
View File

@@ -14,8 +14,7 @@
.text
.align 2
.globl ASM_PFX(__umodsi3)
INTERWORK_FUNC(__umodsi3)
GCC_ASM_EXPORT(__umodsi3)
ASM_PFX(__umodsi3):
stmfd sp!, {r4, r5, r7, lr}

42
ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.c
View File

@@ -32,37 +32,33 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
CHAR8 *
DeCygwinPathIfNeeded (
IN CHAR8 *Name
IN CHAR8 *Name,
IN CHAR8 *Temp,
IN UINTN Size
)
{
CHAR8 *Ptr;
UINTN Index;
UINTN Len;
UINTN Index2;
Ptr = AsciiStrStr (Name, "/cygdrive/");
if (Ptr == NULL) {
return Name;
}
Len = AsciiStrLen (Ptr);
// convert "/cygdrive" to spaces
for (Index = 0; Index < 9; Index++) {
Ptr[Index] = ' ';
for (Index = 9, Index2 = 0; (Index < (Size + 9)) && (Ptr[Index] != '\0'); Index++, Index2++) {
Temp[Index2] = Ptr[Index];
if (Temp[Index2] == '/') {
Temp[Index2] = '\\' ;
}
// convert /c to c:
Ptr[9] = Ptr[10];
Ptr[10] = ':';
// switch path seperators
for (Index = 11; Index < Len; Index++) {
if (Ptr[Index] == '/') {
Ptr[Index] = '\\' ;
if (Index2 == 1) {
Temp[Index2 - 1] = Ptr[Index];
Temp[Index2] = ':';
}
}
return Name;
return Temp;
}
@@ -81,12 +77,14 @@ PeCoffLoaderRelocateImageExtraAction (
IN OUT PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext
)
{
CHAR8 Temp[512];
#ifdef __CC_ARM
// Print out the command for the RVD debugger to load symbols for this image
DEBUG ((EFI_D_ERROR, "load /a /ni /np %a &0x%08x\n", DeCygwinPathIfNeeded (ImageContext->PdbPointer), (UINTN)(ImageContext->ImageAddress + ImageContext->SizeOfHeaders)));
DEBUG ((EFI_D_ERROR, "load /a /ni /np %a &0x%08x\n", DeCygwinPathIfNeeded (ImageContext->PdbPointer, Temp, sizeof (Temp)), (UINTN)(ImageContext->ImageAddress + ImageContext->SizeOfHeaders)));
#elif __GNUC__
// This may not work correctly if you generate PE/COFF directlyas then the Offset would not be required
DEBUG ((EFI_D_ERROR, "add-symbol-file %a 0x%08x\n", DeCygwinPathIfNeeded (ImageContext->PdbPointer), (UINTN)(ImageContext->ImageAddress + ImageContext->SizeOfHeaders)));
DEBUG ((EFI_D_ERROR, "add-symbol-file %a 0x%08x\n", DeCygwinPathIfNeeded (ImageContext->PdbPointer, Temp, sizeof (Temp)), (UINTN)(ImageContext->ImageAddress + ImageContext->SizeOfHeaders)));
#else
DEBUG ((EFI_D_ERROR, "Loading driver at 0x%11p EntryPoint=0x%11p ", (VOID *)(UINTN) ImageContext->ImageAddress, FUNCTION_ENTRY_POINT (ImageContext->EntryPoint)));
#endif
@@ -110,12 +108,16 @@ PeCoffLoaderUnloadImageExtraAction (
IN OUT PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext
)
{
CHAR8 Temp[512];
#ifdef __CC_ARM
{
// Print out the command for the RVD debugger to load symbols for this image
DEBUG ((EFI_D_ERROR, "unload symbols_only %a", DeCygwinPathIfNeeded (ImageContext->PdbPointer)));
DEBUG ((EFI_D_ERROR, "unload symbols_only %a", DeCygwinPathIfNeeded (ImageContext->PdbPointer, Temp, sizeof (Temp))));
}
#elif __GNUC__
// This may not work correctly if you generate PE/COFF directlyas then the Offset would not be required
DEBUG ((EFI_D_ERROR, "remove-symbol-file %a 0x%08x\n", DeCygwinPathIfNeeded (ImageContext->PdbPointer), (UINTN)(ImageContext->ImageAddress + ImageContext->SizeOfHeaders)));
DEBUG ((EFI_D_ERROR, "remove-symbol-file %a 0x%08x\n", DeCygwinPathIfNeeded (ImageContext->PdbPointer, Temp, sizeof (Temp)), (UINTN)(ImageContext->ImageAddress + ImageContext->SizeOfHeaders)));
#else
DEBUG ((EFI_D_ERROR, "Unloading %a", ImageContext->PdbPointer));
#endif

20
ArmPkg/Library/L2X0CacheLibNull/L2X0Cache.c Normal file
View File

@@ -0,0 +1,20 @@
/** @file
*
* Copyright (c) 2011, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
* which accompanies this distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#include <Library/L2X0CacheLib.h>
// Initialize L2X0 Cache Controller
VOID L2x0CacheInit(UINTN L2x0Base, BOOLEAN CacheEnabled) {
//No implementation
}

27
ArmPkg/Library/L2X0CacheLibNull/L2X0CacheLibNull.inf Normal file
View File

@@ -0,0 +1,27 @@
#/* @file
# Copyright (c) 2011, ARM Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#*/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = L2X0CacheLibNull
FILE_GUID = 9c76c900-1e8c-11e0-8766-0002a5d5c51b
MODULE_TYPE = SEC
VERSION_STRING = 1.0
LIBRARY_CLASS = L2X0CacheLib
[Sources]
L2X0Cache.c
[Packages]
MdePkg/MdePkg.dec
ArmPkg/ArmPkg.dec