Sync up ArmPkg with patch from mailing list. Changed name of BdsLib.h to BdsUnixLib.h and fixed a lot of issues with Xcode building.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11293 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
andrewfish
@@ -22,24 +22,42 @@
|
||||
EXPORT ArmDrainWriteBuffer
|
||||
EXPORT ArmEnableMmu
|
||||
EXPORT ArmDisableMmu
|
||||
EXPORT ArmDisableCachesAndMmu
|
||||
EXPORT ArmMmuEnabled
|
||||
EXPORT ArmEnableDataCache
|
||||
EXPORT ArmDisableDataCache
|
||||
EXPORT ArmEnableInstructionCache
|
||||
EXPORT ArmDisableInstructionCache
|
||||
EXPORT ArmEnableSWPInstruction
|
||||
EXPORT ArmEnableBranchPrediction
|
||||
EXPORT ArmDisableBranchPrediction
|
||||
EXPORT ArmV7AllDataCachesOperation
|
||||
EXPORT ArmDataMemoryBarrier
|
||||
EXPORT ArmDataSyncronizationBarrier
|
||||
EXPORT ArmInstructionSynchronizationBarrier
|
||||
EXPORT ArmWriteNsacr
|
||||
EXPORT ArmWriteScr
|
||||
EXPORT ArmWriteVMBar
|
||||
EXPORT ArmWriteVBar
|
||||
EXPORT ArmReadVBar
|
||||
EXPORT ArmWriteCPACR
|
||||
EXPORT ArmEnableVFP
|
||||
EXPORT ArmCallWFI
|
||||
EXPORT ArmWriteAuxCr
|
||||
EXPORT ArmReadAuxCr
|
||||
EXPORT ArmReadCbar
|
||||
EXPORT ArmInvalidateInstructionAndDataTlb
|
||||
EXPORT ArmReadMpidr
|
||||
|
||||
AREA ArmCacheLib, CODE, READONLY
|
||||
PRESERVE8
|
||||
|
||||
DC_ON EQU ( 0x1:SHL:2 )
|
||||
IC_ON EQU ( 0x1:SHL:12 )
|
||||
|
||||
DC_ON EQU ( 0x1:SHL:2 )
|
||||
IC_ON EQU ( 0x1:SHL:12 )
|
||||
CTRL_M_BIT EQU (1 << 0)
|
||||
CTRL_C_BIT EQU (1 << 2)
|
||||
CTRL_B_BIT EQU (1 << 7)
|
||||
CTRL_I_BIT EQU (1 << 12)
|
||||
|
||||
|
||||
ArmInvalidateDataCacheEntryByMVA
|
||||
@@ -90,75 +108,91 @@ ArmInvalidateInstructionCache
|
||||
bx LR
|
||||
|
||||
ArmEnableMmu
|
||||
mrc p15,0,R0,c1,c0,0
|
||||
orr R0,R0,#1
|
||||
mcr p15,0,R0,c1,c0,0
|
||||
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
|
||||
orr R0,R0,#1 ; Set SCTLR.M bit : Enable MMU
|
||||
mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
|
||||
dsb
|
||||
isb
|
||||
bx LR
|
||||
|
||||
ArmMmuEnabled
|
||||
mrc p15,0,R0,c1,c0,0
|
||||
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
|
||||
and R0,R0,#1
|
||||
bx LR
|
||||
|
||||
ArmDisableMmu
|
||||
mrc p15,0,R0,c1,c0,0
|
||||
bic R0,R0,#1
|
||||
mcr p15,0,R0,c1,c0,0 ;Disable MMU
|
||||
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
|
||||
bic R0,R0,#1 ; Clear SCTLR.M bit : Disable MMU
|
||||
mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
|
||||
|
||||
mcr p15,0,R0,c8,c7,0 ;Invalidate TLB
|
||||
mcr p15,0,R0,c7,c5,6 ;Invalidate Branch predictor array
|
||||
mcr p15,0,R0,c8,c7,0 ; TLBIALL : Invalidate unified TLB
|
||||
mcr p15,0,R0,c7,c5,6 ; BPIALL : Invalidate entire branch predictor array
|
||||
dsb
|
||||
isb
|
||||
bx LR
|
||||
|
||||
ArmDisableCachesAndMmu
|
||||
mrc p15, 0, r0, c1, c0, 0 ; Get control register
|
||||
bic r0, r0, #CTRL_M_BIT ; Disable MMU
|
||||
bic r0, r0, #CTRL_C_BIT ; Disable D Cache
|
||||
bic r0, r0, #CTRL_I_BIT ; Disable I Cache
|
||||
mcr p15, 0, r0, c1, c0, 0 ; Write control register
|
||||
dsb
|
||||
isb
|
||||
bx LR
|
||||
|
||||
ArmEnableDataCache
|
||||
ldr R1,=DC_ON
|
||||
mrc p15,0,R0,c1,c0,0 ;Read control register configuration data
|
||||
orr R0,R0,R1 ;Set C bit
|
||||
mcr p15,0,R0,c1,c0,0 ;Write control register configuration data
|
||||
ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit
|
||||
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
|
||||
orr R0,R0,R1 ; Set SCTLR.C bit : Data and unified caches enabled
|
||||
mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
|
||||
dsb
|
||||
isb
|
||||
bx LR
|
||||
|
||||
ArmDisableDataCache
|
||||
ldr R1,=DC_ON
|
||||
mrc p15,0,R0,c1,c0,0 ;Read control register configuration data
|
||||
bic R0,R0,R1 ;Clear C bit
|
||||
mcr p15,0,R0,c1,c0,0 ;Write control register configuration data
|
||||
ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit
|
||||
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
|
||||
bic R0,R0,R1 ; Clear SCTLR.C bit : Data and unified caches disabled
|
||||
mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
|
||||
isb
|
||||
bx LR
|
||||
|
||||
ArmEnableInstructionCache
|
||||
ldr R1,=IC_ON
|
||||
mrc p15,0,R0,c1,c0,0 ;Read control register configuration data
|
||||
orr R0,R0,R1 ;Set I bit
|
||||
mcr p15,0,R0,c1,c0,0 ;Write control register configuration data
|
||||
ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit
|
||||
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
|
||||
orr R0,R0,R1 ; Set SCTLR.I bit : Instruction caches enabled
|
||||
mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
|
||||
dsb
|
||||
isb
|
||||
bx LR
|
||||
|
||||
ArmDisableInstructionCache
|
||||
ldr R1,=IC_ON
|
||||
mrc p15,0,R0,c1,c0,0 ;Read control register configuration data
|
||||
BIC R0,R0,R1 ;Clear I bit.
|
||||
mcr p15,0,R0,c1,c0,0 ;Write control register configuration data
|
||||
ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit
|
||||
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
|
||||
BIC R0,R0,R1 ; Clear SCTLR.I bit : Instruction caches disabled
|
||||
mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
|
||||
isb
|
||||
bx LR
|
||||
|
||||
ArmEnableSWPInstruction
|
||||
mrc p15, 0, r0, c1, c0, 0
|
||||
orr r0, r0, #0x00000400
|
||||
mcr p15, 0, r0, c1, c0, 0
|
||||
isb
|
||||
bx LR
|
||||
|
||||
ArmEnableBranchPrediction
|
||||
mrc p15, 0, r0, c1, c0, 0
|
||||
orr r0, r0, #0x00000800
|
||||
mcr p15, 0, r0, c1, c0, 0
|
||||
mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
|
||||
orr r0, r0, #0x00000800 ;
|
||||
mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
|
||||
isb
|
||||
bx LR
|
||||
|
||||
ArmDisableBranchPrediction
|
||||
mrc p15, 0, r0, c1, c0, 0
|
||||
bic r0, r0, #0x00000800
|
||||
mcr p15, 0, r0, c1, c0, 0
|
||||
mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
|
||||
bic r0, r0, #0x00000800 ;
|
||||
mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
|
||||
isb
|
||||
bx LR
|
||||
|
||||
@@ -173,9 +207,9 @@ ArmV7AllDataCachesOperation
|
||||
mov R10, #0
|
||||
|
||||
Loop1
|
||||
add R2, R10, R10, LSR #1 ; Work out 3xcachelevel
|
||||
mov R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level
|
||||
and R12, R12, #7 ; get those 3 bits alone
|
||||
add R2, R10, R10, LSR #1 ; Work out 3xcachelevel
|
||||
mov R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level
|
||||
and R12, R12, #7 ; get those 3 bits alone
|
||||
cmp R12, #2
|
||||
blt Skip ; no cache or only instruction cache at this level
|
||||
mcr p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
|
||||
@@ -226,5 +260,64 @@ ArmInstructionSynchronizationBarrier
|
||||
isb
|
||||
bx LR
|
||||
|
||||
END
|
||||
ArmWriteNsacr
|
||||
mcr p15, 0, r0, c1, c1, 2
|
||||
bx lr
|
||||
|
||||
ArmWriteScr
|
||||
mcr p15, 0, r0, c1, c1, 0
|
||||
bx lr
|
||||
|
||||
ArmWriteAuxCr
|
||||
mcr p15, 0, r0, c1, c0, 1
|
||||
bx lr
|
||||
|
||||
ArmReadAuxCr
|
||||
mrc p15, 0, r0, c1, c0, 1
|
||||
bx lr
|
||||
|
||||
ArmWriteVMBar
|
||||
mcr p15, 0, r0, c12, c0, 1
|
||||
bx lr
|
||||
|
||||
ArmWriteVBar
|
||||
mcr p15, 0, r0, c12, c0, 0
|
||||
bx lr
|
||||
|
||||
ArmReadVBar
|
||||
mrc p15, 0, r0, c12, c0, 0
|
||||
bx lr
|
||||
|
||||
ArmWriteCPACR
|
||||
mcr p15, 0, r0, c1, c0, 2
|
||||
bx lr
|
||||
|
||||
ArmEnableVFP
|
||||
// Enable VFP registers
|
||||
mrc p15, 0, r0, c1, c0, 2
|
||||
orr r0, r0, #0x00f00000 // Enable VPF access (V* instructions)
|
||||
mcr p15, 0, r0, c1, c0, 2
|
||||
mov r0, #0x40000000 // Set EN bit in FPEXC
|
||||
mcr p10,#0x7,r0,c8,c0,#0 // msr FPEXC,r0 in ARM assembly
|
||||
bx lr
|
||||
|
||||
ArmCallWFI
|
||||
wfi
|
||||
bx lr
|
||||
|
||||
//Note: Return 0 in Uniprocessor implementation
|
||||
ArmReadCbar
|
||||
mrc p15, 4, r0, c15, c0, 0 //Read Configuration Base Address Register
|
||||
bx lr
|
||||
|
||||
ArmInvalidateInstructionAndDataTlb
|
||||
mcr p15, 0, r0, c8, c7, 0 ; Invalidate Inst TLB and Data TLB
|
||||
dsb
|
||||
bx lr
|
||||
|
||||
ArmReadMpidr
|
||||
mrc p15, 0, r0, c0, c0, 5 ; read MPIDR
|
||||
bx lr
|
||||
|
||||
END
|
||||
|
||||
|
||||
Reference in New Issue
Block a user