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Improve coding style in MdeModulePkg.

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git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9793 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
rsun3
2010-01-19 06:42:21 +00:00
parent cd730ec08d
commit 1ccdbf2a3e
45 changed files with 953 additions and 936 deletions
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8
MdeModulePkg/Bus/Pci/EhciDxe/Ehci.c
View File

@@ -10,7 +10,7 @@
This way avoids the control transfer on a shared port between EHCI and companion host
controller when UHCI gets attached earlier than EHCI and a USB 2.0 device inserts.
Copyright (c) 2006 - 2009, Intel Corporation
Copyright (c) 2006 - 2010, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -1363,7 +1363,7 @@ EhcDriverBindingSupported (
// Test whether the controller belongs to Ehci type
//
if ((UsbClassCReg.BaseCode != PCI_CLASS_SERIAL) || (UsbClassCReg.SubClassCode != PCI_CLASS_SERIAL_USB)
|| ((UsbClassCReg.PI != PCI_IF_EHCI) && (UsbClassCReg.PI !=PCI_IF_UHCI))) {
|| ((UsbClassCReg.ProgInterface != PCI_IF_EHCI) && (UsbClassCReg.ProgInterface !=PCI_IF_UHCI))) {
Status = EFI_UNSUPPORTED;
}
@@ -1598,7 +1598,7 @@ EhcDriverBindingStart (
// companion usb ehci host controller and force EHCI driver get attached to it before
// UHCI driver attaches to UHCI host controller.
//
if ((UsbClassCReg.PI == PCI_IF_UHCI) &&
if ((UsbClassCReg.ProgInterface == PCI_IF_UHCI) &&
(UsbClassCReg.BaseCode == PCI_CLASS_SERIAL) &&
(UsbClassCReg.SubClassCode == PCI_CLASS_SERIAL_USB)) {
Status = PciIo->GetLocation (
@@ -1647,7 +1647,7 @@ EhcDriverBindingStart (
goto CLOSE_PCIIO;
}
if ((UsbClassCReg.PI == PCI_IF_EHCI) &&
if ((UsbClassCReg.ProgInterface == PCI_IF_EHCI) &&
(UsbClassCReg.BaseCode == PCI_CLASS_SERIAL) &&
(UsbClassCReg.SubClassCode == PCI_CLASS_SERIAL_USB)) {
Status = Instance->GetLocation (

43
MdeModulePkg/Bus/Pci/EhciDxe/Ehci.h
View File

@@ -2,7 +2,7 @@
Provides some data struct used by EHCI controller driver.
Copyright (c) 2006 - 2009, Intel Corporation
Copyright (c) 2006 - 2010, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -44,30 +44,31 @@ typedef struct _USB2_HC_DEV USB2_HC_DEV;
#include "EhciDebug.h"
#include "ComponentName.h"
typedef enum {
EHC_1_MICROSECOND = 1,
EHC_1_MILLISECOND = 1000 * EHC_1_MICROSECOND,
EHC_1_SECOND = 1000 * EHC_1_MILLISECOND,
//
// EHC timeout experience values
//
//
// EHCI register operation timeout, set by experience
//
EHC_RESET_TIMEOUT = 1 * EHC_1_SECOND,
EHC_GENERIC_TIMEOUT = 10 * EHC_1_MILLISECOND,
#define EHC_1_MICROSECOND 1
#define EHC_1_MILLISECOND (1000 * EHC_1_MICROSECOND)
#define EHC_1_SECOND (1000 * EHC_1_MILLISECOND)
//
// Wait for roothub port power stable, refers to Spec[EHCI1.0-2.3.9]
//
EHC_ROOT_PORT_RECOVERY_STALL = 20 * EHC_1_MILLISECOND,
//
// EHCI register operation timeout, set by experience
//
#define EHC_RESET_TIMEOUT (1 * EHC_1_SECOND)
#define EHC_GENERIC_TIMEOUT (10 * EHC_1_MILLISECOND)
//
// Sync and Async transfer polling interval, set by experience,
// and the unit of Async is 100us, means 50ms as interval.
//
EHC_SYNC_POLL_INTERVAL = 1 * EHC_1_MILLISECOND,
EHC_ASYNC_POLL_INTERVAL = 50 * 10000U
} EHC_TIMEOUT_EXPERIENCE_VALUE;
//
// Wait for roothub port power stable, refers to Spec[EHCI1.0-2.3.9]
//
#define EHC_ROOT_PORT_RECOVERY_STALL (20 * EHC_1_MILLISECOND)
//
// Sync and Async transfer polling interval, set by experience,
// and the unit of Async is 100us, means 50ms as interval.
//
#define EHC_SYNC_POLL_INTERVAL (1 * EHC_1_MILLISECOND)
#define EHC_ASYNC_POLL_INTERVAL (50 * 10000U)
//
// EHC raises TPL to TPL_NOTIFY to serialize all its operations

6
MdeModulePkg/Bus/Pci/EhciDxe/EhciDebug.c
View File

@@ -2,7 +2,7 @@
This file provides the information dump support for EHCI when in debug mode.
Copyright (c) 2007 - 2009, Intel Corporation
Copyright (c) 2007 - 2010, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -105,7 +105,7 @@ EhcDumpQtd (
DEBUG ((EFI_D_INFO, "Error Count : %d\n", QtdHw->ErrCnt));
DEBUG ((EFI_D_INFO, "Current Page : %d\n", QtdHw->CurPage));
DEBUG ((EFI_D_INFO, "IOC : %d\n", QtdHw->IOC));
DEBUG ((EFI_D_INFO, "IOC : %d\n", QtdHw->Ioc));
DEBUG ((EFI_D_INFO, "Total Bytes : %d\n", QtdHw->TotalBytes));
DEBUG ((EFI_D_INFO, "Data Toggle : %d\n", QtdHw->DataToggle));
@@ -181,7 +181,7 @@ EhcDumpQh (
DEBUG ((EFI_D_INFO, "Error Count : %d\n", QhHw->ErrCnt));
DEBUG ((EFI_D_INFO, "Current Page : %d\n", QhHw->CurPage));
DEBUG ((EFI_D_INFO, "IOC : %d\n", QhHw->IOC));
DEBUG ((EFI_D_INFO, "IOC : %d\n", QhHw->Ioc));
DEBUG ((EFI_D_INFO, "Total Bytes : %d\n", QhHw->TotalBytes));
DEBUG ((EFI_D_INFO, "Data Toggle : %d\n", QhHw->DataToggle));

128
MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.h
View File

@@ -2,7 +2,7 @@
This file contains the definination for host controller register operation routines.
Copyright (c) 2007 - 2009, Intel Corporation
Copyright (c) 2007 - 2010, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -16,75 +16,77 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#ifndef _EFI_EHCI_REG_H_
#define _EFI_EHCI_REG_H_
//
// EHCI register offset
//
typedef enum {
//
// Capability register offset
//
EHC_CAPLENGTH_OFFSET = 0, // Capability register length offset
EHC_HCSPARAMS_OFFSET = 0x04, // Structural Parameters 04-07h
EHC_HCCPARAMS_OFFSET = 0x08, // Capability parameters offset
//
// Capability register bit definition
//
HCSP_NPORTS = 0x0F, // Number of root hub port
HCCP_64BIT = 0x01, // 64-bit addressing capability
//
// Capability register offset
//
#define EHC_CAPLENGTH_OFFSET 0 // Capability register length offset
#define EHC_HCSPARAMS_OFFSET 0x04 // Structural Parameters 04-07h
#define EHC_HCCPARAMS_OFFSET 0x08 // Capability parameters offset
//
// Operational register offset
//
EHC_USBCMD_OFFSET = 0x0, // USB command register offset
EHC_USBSTS_OFFSET = 0x04, // Statue register offset
EHC_USBINTR_OFFSET = 0x08, // USB interrutp offset
EHC_FRINDEX_OFFSET = 0x0C, // Frame index offset
EHC_CTRLDSSEG_OFFSET = 0x10, // Control data structure segment offset
EHC_FRAME_BASE_OFFSET = 0x14, // Frame list base address offset
EHC_ASYNC_HEAD_OFFSET = 0x18, // Next asynchronous list address offset
EHC_CONFIG_FLAG_OFFSET = 0x40, // Configure flag register offset
EHC_PORT_STAT_OFFSET = 0x44, // Port status/control offset
//
// Capability register bit definition
//
#define HCSP_NPORTS 0x0F // Number of root hub port
#define HCCP_64BIT 0x01 // 64-bit addressing capability
EHC_FRAME_LEN = 1024,
//
// Operational register offset
//
#define EHC_USBCMD_OFFSET 0x0 // USB command register offset
#define EHC_USBSTS_OFFSET 0x04 // Statue register offset
#define EHC_USBINTR_OFFSET 0x08 // USB interrutp offset
#define EHC_FRINDEX_OFFSET 0x0C // Frame index offset
#define EHC_CTRLDSSEG_OFFSET 0x10 // Control data structure segment offset
#define EHC_FRAME_BASE_OFFSET 0x14 // Frame list base address offset
#define EHC_ASYNC_HEAD_OFFSET 0x18 // Next asynchronous list address offset
#define EHC_CONFIG_FLAG_OFFSET 0x40 // Configure flag register offset
#define EHC_PORT_STAT_OFFSET 0x44 // Port status/control offset
//
// Register bit definition
//
CONFIGFLAG_ROUTE_EHC = 0x01, // Route port to EHC
#define EHC_FRAME_LEN 1024
USBCMD_RUN = 0x01, // Run/stop
USBCMD_RESET = 0x02, // Start the host controller reset
USBCMD_ENABLE_PERIOD = 0x10, // Enable periodic schedule
USBCMD_ENABLE_ASYNC = 0x20, // Enable asynchronous schedule
USBCMD_IAAD = 0x40, // Interrupt on async advance doorbell
//
// Register bit definition
//
#define CONFIGFLAG_ROUTE_EHC 0x01 // Route port to EHC
USBSTS_IAA = 0x20, // Interrupt on async advance
USBSTS_PERIOD_ENABLED = 0x4000, // Periodic schedule status
USBSTS_ASYNC_ENABLED = 0x8000, // Asynchronous schedule status
USBSTS_HALT = 0x1000, // Host controller halted
USBSTS_SYS_ERROR = 0x10, // Host system error
USBSTS_INTACK_MASK = 0x003F, // Mask for the interrupt ACK, the WC
// (write clean) bits in USBSTS register
#define USBCMD_RUN 0x01 // Run/stop
#define USBCMD_RESET 0x02 // Start the host controller reset
#define USBCMD_ENABLE_PERIOD 0x10 // Enable periodic schedule
#define USBCMD_ENABLE_ASYNC 0x20 // Enable asynchronous schedule
#define USBCMD_IAAD 0x40 // Interrupt on async advance doorbell
PORTSC_CONN = 0x01, // Current Connect Status
PORTSC_CONN_CHANGE = 0x02, // Connect Status Change
PORTSC_ENABLED = 0x04, // Port Enable / Disable
PORTSC_ENABLE_CHANGE = 0x08, // Port Enable / Disable Change
PORTSC_OVERCUR = 0x10, // Over current Active
PORTSC_OVERCUR_CHANGE = 0x20, // Over current Change
PORSTSC_RESUME = 0x40, // Force Port Resume
PORTSC_SUSPEND = 0x80, // Port Suspend State
PORTSC_RESET = 0x100, // Port Reset
PORTSC_LINESTATE_K = 0x400, // Line Status K-state
PORTSC_LINESTATE_J = 0x800, // Line Status J-state
PORTSC_POWER = 0x1000, // Port Power
PORTSC_OWNER = 0x2000, // Port Owner
PORTSC_CHANGE_MASK = 0x2A, // Mask of the port change bits,
// they are WC (write clean)
//
// PCI Configuration Registers
//
EHC_BAR_INDEX = 0 /* how many bytes away from USB_BASE to 0x10 */
}EHCI_REGISTER_OFFSET;
#define USBSTS_IAA 0x20 // Interrupt on async advance
#define USBSTS_PERIOD_ENABLED 0x4000 // Periodic schedule status
#define USBSTS_ASYNC_ENABLED 0x8000 // Asynchronous schedule status
#define USBSTS_HALT 0x1000 // Host controller halted
#define USBSTS_SYS_ERROR 0x10 // Host system error
#define USBSTS_INTACK_MASK 0x003F // Mask for the interrupt ACK, the WC
// (write clean) bits in USBSTS register
#define PORTSC_CONN 0x01 // Current Connect Status
#define PORTSC_CONN_CHANGE 0x02 // Connect Status Change
#define PORTSC_ENABLED 0x04 // Port Enable / Disable
#define PORTSC_ENABLE_CHANGE 0x08 // Port Enable / Disable Change
#define PORTSC_OVERCUR 0x10 // Over current Active
#define PORTSC_OVERCUR_CHANGE 0x20 // Over current Change
#define PORSTSC_RESUME 0x40 // Force Port Resume
#define PORTSC_SUSPEND 0x80 // Port Suspend State
#define PORTSC_RESET 0x100 // Port Reset
#define PORTSC_LINESTATE_K 0x400 // Line Status K-state
#define PORTSC_LINESTATE_J 0x800 // Line Status J-state
#define PORTSC_POWER 0x1000 // Port Power
#define PORTSC_OWNER 0x2000 // Port Owner
#define PORTSC_CHANGE_MASK 0x2A // Mask of the port change bits,
// they are WC (write clean)
//
// PCI Configuration Registers
//
#define EHC_BAR_INDEX 0 // how many bytes away from USB_BASE to 0x10
#define EHC_LINK_TERMINATED(Link) (((Link) & 0x01) != 0)
@@ -107,7 +109,7 @@ typedef struct {
//
#pragma pack(1)
typedef struct {
UINT8 PI;
UINT8 ProgInterface;
UINT8 SubClassCode;
UINT8 BaseCode;
} USB_CLASSC;

4
MdeModulePkg/Bus/Pci/EhciDxe/EhciSched.c
View File

@@ -2,7 +2,7 @@
EHCI transfer scheduling routines.
Copyright (c) 2007 - 2009, Intel Corporation
Copyright (c) 2007 - 2010, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -881,7 +881,7 @@ EhcUpdateAsyncRequest (
QhHw->Pid = 0;
QhHw->ErrCnt = 0;
QhHw->CurPage = 0;
QhHw->IOC = 0;
QhHw->Ioc = 0;
QhHw->TotalBytes = 0;
for (Index = 0; Index < 5; Index++) {

4
MdeModulePkg/Bus/Pci/EhciDxe/EhciUrb.c
View File

@@ -3,7 +3,7 @@
This file contains URB request, each request is warpped in a
URB (Usb Request Block).
Copyright (c) 2007 - 2009, Intel Corporation
Copyright (c) 2007 - 2010, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -68,7 +68,7 @@ EhcCreateQtd (
QtdHw->Status = QTD_STAT_ACTIVE;
QtdHw->Pid = PktId;
QtdHw->ErrCnt = QTD_MAX_ERR;
QtdHw->IOC = 0;
QtdHw->Ioc = 0;
QtdHw->TotalBytes = 0;
QtdHw->DataToggle = Toggle;

98
MdeModulePkg/Bus/Pci/EhciDxe/EhciUrb.h
View File

@@ -3,7 +3,7 @@
This file contains URB request, each request is warpped in a
URB (Usb Request Block).
Copyright (c) 2007 - 2009, Intel Corporation
Copyright (c) 2007 - 2010, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -22,61 +22,59 @@ typedef struct _EHC_QTD EHC_QTD;
typedef struct _EHC_QH EHC_QH;
typedef struct _URB URB;
typedef enum {
//
// Transfer types, used in URB to identify the transfer type
//
EHC_CTRL_TRANSFER = 0x01,
EHC_BULK_TRANSFER = 0x02,
EHC_INT_TRANSFER_SYNC = 0x04,
EHC_INT_TRANSFER_ASYNC = 0x08,
//
// Transfer types, used in URB to identify the transfer type
//
#define EHC_CTRL_TRANSFER 0x01
#define EHC_BULK_TRANSFER 0x02
#define EHC_INT_TRANSFER_SYNC 0x04
#define EHC_INT_TRANSFER_ASYNC 0x08
EHC_QTD_SIG = SIGNATURE_32 ('U', 'S', 'B', 'T'),
EHC_QH_SIG = SIGNATURE_32 ('U', 'S', 'B', 'H'),
EHC_URB_SIG = SIGNATURE_32 ('U', 'S', 'B', 'R'),
#define EHC_QTD_SIG SIGNATURE_32 ('U', 'S', 'B', 'T')
#define EHC_QH_SIG SIGNATURE_32 ('U', 'S', 'B', 'H')
#define EHC_URB_SIG SIGNATURE_32 ('U', 'S', 'B', 'R')
//
// Hardware related bit definitions
//
EHC_TYPE_ITD = 0x00,
EHC_TYPE_QH = 0x02,
EHC_TYPE_SITD = 0x04,
EHC_TYPE_FSTN = 0x06,
//
// Hardware related bit definitions
//
#define EHC_TYPE_ITD 0x00
#define EHC_TYPE_QH 0x02
#define EHC_TYPE_SITD 0x04
#define EHC_TYPE_FSTN 0x06
QH_NAK_RELOAD = 3,
QH_HSHBW_MULTI = 1,
#define QH_NAK_RELOAD 3
#define QH_HSHBW_MULTI 1
QTD_MAX_ERR = 3,
QTD_PID_OUTPUT = 0x00,
QTD_PID_INPUT = 0x01,
QTD_PID_SETUP = 0x02,
#define QTD_MAX_ERR 3
#define QTD_PID_OUTPUT 0x00
#define QTD_PID_INPUT 0x01
#define QTD_PID_SETUP 0x02
QTD_STAT_DO_OUT = 0,
QTD_STAT_DO_SS = 0,
QTD_STAT_DO_PING = 0x01,
QTD_STAT_DO_CS = 0x02,
QTD_STAT_TRANS_ERR = 0x08,
QTD_STAT_BABBLE_ERR = 0x10,
QTD_STAT_BUFF_ERR = 0x20,
QTD_STAT_HALTED = 0x40,
QTD_STAT_ACTIVE = 0x80,
QTD_STAT_ERR_MASK = QTD_STAT_TRANS_ERR | QTD_STAT_BABBLE_ERR | QTD_STAT_BUFF_ERR,
#define QTD_STAT_DO_OUT 0
#define QTD_STAT_DO_SS 0
#define QTD_STAT_DO_PING 0x01
#define QTD_STAT_DO_CS 0x02
#define QTD_STAT_TRANS_ERR 0x08
#define QTD_STAT_BABBLE_ERR 0x10
#define QTD_STAT_BUFF_ERR 0x20
#define QTD_STAT_HALTED 0x40
#define QTD_STAT_ACTIVE 0x80
#define QTD_STAT_ERR_MASK (QTD_STAT_TRANS_ERR | QTD_STAT_BABBLE_ERR | QTD_STAT_BUFF_ERR)
QTD_MAX_BUFFER = 4,
QTD_BUF_LEN = 4096,
QTD_BUF_MASK = 0x0FFF,
#define QTD_MAX_BUFFER 4
#define QTD_BUF_LEN 4096
#define QTD_BUF_MASK 0x0FFF
QH_MICROFRAME_0 = 0x01,
QH_MICROFRAME_1 = 0x02,
QH_MICROFRAME_2 = 0x04,
QH_MICROFRAME_3 = 0x08,
QH_MICROFRAME_4 = 0x10,
QH_MICROFRAME_5 = 0x20,
QH_MICROFRAME_6 = 0x40,
QH_MICROFRAME_7 = 0x80,
#define QH_MICROFRAME_0 0x01
#define QH_MICROFRAME_1 0x02
#define QH_MICROFRAME_2 0x04
#define QH_MICROFRAME_3 0x08
#define QH_MICROFRAME_4 0x10
#define QH_MICROFRAME_5 0x20
#define QH_MICROFRAME_6 0x40
#define QH_MICROFRAME_7 0x80
USB_ERR_SHORT_PACKET = 0x200
}EHCI_URB_FLAG_VALUE;
#define USB_ERR_SHORT_PACKET 0x200
//
// Fill in the hardware link point: pass in a EHC_QH/QH_HW
@@ -102,7 +100,7 @@ typedef struct {
UINT32 Pid : 2;
UINT32 ErrCnt : 2;
UINT32 CurPage : 3;
UINT32 IOC : 1;
UINT32 Ioc : 1;
UINT32 TotalBytes : 15;
UINT32 DataToggle : 1;
@@ -142,7 +140,7 @@ typedef struct {
UINT32 Pid : 2;
UINT32 ErrCnt : 2;
UINT32 CurPage : 3;
UINT32 IOC : 1;
UINT32 Ioc : 1;
UINT32 TotalBytes : 15;
UINT32 DataToggle : 1;

20
MdeModulePkg/Bus/Pci/EhciDxe/UsbHcMem.h
View File

@@ -2,7 +2,7 @@
This file contains the definination for host controller memory management routines.
Copyright (c) 2007 - 2009, Intel Corporation
Copyright (c) 2007 - 2010, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -24,15 +24,16 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#define USB_HC_HIGH_32BIT(Addr64) \
((UINT32)(RShiftU64((UINTN)(Addr64), 32) & 0XFFFFFFFF))
typedef struct _USBHC_MEM_BLOCK {
typedef struct _USBHC_MEM_BLOCK USBHC_MEM_BLOCK;
struct _USBHC_MEM_BLOCK {
UINT8 *Bits; // Bit array to record which unit is allocated
UINTN BitsLen;
UINT8 *Buf;
UINT8 *BufHost;
UINTN BufLen; // Memory size in bytes
VOID *Mapping;
struct _USBHC_MEM_BLOCK *Next;
} USBHC_MEM_BLOCK;
USBHC_MEM_BLOCK *Next;
};
//
// USBHC_MEM_POOL is used to manage the memory used by USB
@@ -46,12 +47,13 @@ typedef struct _USBHC_MEM_POOL {
USBHC_MEM_BLOCK *Head;
} USBHC_MEM_POOL;
typedef enum {
USBHC_MEM_UNIT = 64, // Memory allocation unit, must be 2^n, n>4
//
// Memory allocation unit, must be 2^n, n>4
//
#define USBHC_MEM_UNIT 64
USBHC_MEM_UNIT_MASK = USBHC_MEM_UNIT - 1,
USBHC_MEM_DEFAULT_PAGES = 16
} USBHC_MEM_UNIT_DATA;
#define USBHC_MEM_UNIT_MASK (USBHC_MEM_UNIT - 1)
#define USBHC_MEM_DEFAULT_PAGES 16
#define USBHC_MEM_ROUND(Len) (((Len) + USBHC_MEM_UNIT_MASK) & (~USBHC_MEM_UNIT_MASK))