Improve coding style in MdeModulePkg.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9793 6f19259b-4bc3-4df7-8a09-765794883524
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@@ -2,7 +2,7 @@
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This file contains the definination for host controller register operation routines.
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Copyright (c) 2007 - 2009, Intel Corporation
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Copyright (c) 2007 - 2010, Intel Corporation
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All rights reserved. This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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@@ -16,75 +16,77 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#ifndef _EFI_EHCI_REG_H_
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#define _EFI_EHCI_REG_H_
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//
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// EHCI register offset
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//
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typedef enum {
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//
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// Capability register offset
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//
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EHC_CAPLENGTH_OFFSET = 0, // Capability register length offset
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EHC_HCSPARAMS_OFFSET = 0x04, // Structural Parameters 04-07h
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EHC_HCCPARAMS_OFFSET = 0x08, // Capability parameters offset
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//
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// Capability register bit definition
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//
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HCSP_NPORTS = 0x0F, // Number of root hub port
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HCCP_64BIT = 0x01, // 64-bit addressing capability
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//
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// Capability register offset
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//
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#define EHC_CAPLENGTH_OFFSET 0 // Capability register length offset
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#define EHC_HCSPARAMS_OFFSET 0x04 // Structural Parameters 04-07h
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#define EHC_HCCPARAMS_OFFSET 0x08 // Capability parameters offset
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//
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// Operational register offset
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//
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EHC_USBCMD_OFFSET = 0x0, // USB command register offset
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EHC_USBSTS_OFFSET = 0x04, // Statue register offset
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EHC_USBINTR_OFFSET = 0x08, // USB interrutp offset
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EHC_FRINDEX_OFFSET = 0x0C, // Frame index offset
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EHC_CTRLDSSEG_OFFSET = 0x10, // Control data structure segment offset
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EHC_FRAME_BASE_OFFSET = 0x14, // Frame list base address offset
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EHC_ASYNC_HEAD_OFFSET = 0x18, // Next asynchronous list address offset
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EHC_CONFIG_FLAG_OFFSET = 0x40, // Configure flag register offset
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EHC_PORT_STAT_OFFSET = 0x44, // Port status/control offset
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//
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// Capability register bit definition
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//
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#define HCSP_NPORTS 0x0F // Number of root hub port
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#define HCCP_64BIT 0x01 // 64-bit addressing capability
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EHC_FRAME_LEN = 1024,
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//
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// Operational register offset
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//
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#define EHC_USBCMD_OFFSET 0x0 // USB command register offset
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#define EHC_USBSTS_OFFSET 0x04 // Statue register offset
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#define EHC_USBINTR_OFFSET 0x08 // USB interrutp offset
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#define EHC_FRINDEX_OFFSET 0x0C // Frame index offset
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#define EHC_CTRLDSSEG_OFFSET 0x10 // Control data structure segment offset
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#define EHC_FRAME_BASE_OFFSET 0x14 // Frame list base address offset
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#define EHC_ASYNC_HEAD_OFFSET 0x18 // Next asynchronous list address offset
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#define EHC_CONFIG_FLAG_OFFSET 0x40 // Configure flag register offset
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#define EHC_PORT_STAT_OFFSET 0x44 // Port status/control offset
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//
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// Register bit definition
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//
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CONFIGFLAG_ROUTE_EHC = 0x01, // Route port to EHC
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#define EHC_FRAME_LEN 1024
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USBCMD_RUN = 0x01, // Run/stop
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USBCMD_RESET = 0x02, // Start the host controller reset
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USBCMD_ENABLE_PERIOD = 0x10, // Enable periodic schedule
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USBCMD_ENABLE_ASYNC = 0x20, // Enable asynchronous schedule
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USBCMD_IAAD = 0x40, // Interrupt on async advance doorbell
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//
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// Register bit definition
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//
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#define CONFIGFLAG_ROUTE_EHC 0x01 // Route port to EHC
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USBSTS_IAA = 0x20, // Interrupt on async advance
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USBSTS_PERIOD_ENABLED = 0x4000, // Periodic schedule status
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USBSTS_ASYNC_ENABLED = 0x8000, // Asynchronous schedule status
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USBSTS_HALT = 0x1000, // Host controller halted
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USBSTS_SYS_ERROR = 0x10, // Host system error
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USBSTS_INTACK_MASK = 0x003F, // Mask for the interrupt ACK, the WC
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// (write clean) bits in USBSTS register
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#define USBCMD_RUN 0x01 // Run/stop
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#define USBCMD_RESET 0x02 // Start the host controller reset
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#define USBCMD_ENABLE_PERIOD 0x10 // Enable periodic schedule
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#define USBCMD_ENABLE_ASYNC 0x20 // Enable asynchronous schedule
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#define USBCMD_IAAD 0x40 // Interrupt on async advance doorbell
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PORTSC_CONN = 0x01, // Current Connect Status
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PORTSC_CONN_CHANGE = 0x02, // Connect Status Change
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PORTSC_ENABLED = 0x04, // Port Enable / Disable
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PORTSC_ENABLE_CHANGE = 0x08, // Port Enable / Disable Change
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PORTSC_OVERCUR = 0x10, // Over current Active
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PORTSC_OVERCUR_CHANGE = 0x20, // Over current Change
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PORSTSC_RESUME = 0x40, // Force Port Resume
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PORTSC_SUSPEND = 0x80, // Port Suspend State
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PORTSC_RESET = 0x100, // Port Reset
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PORTSC_LINESTATE_K = 0x400, // Line Status K-state
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PORTSC_LINESTATE_J = 0x800, // Line Status J-state
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PORTSC_POWER = 0x1000, // Port Power
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PORTSC_OWNER = 0x2000, // Port Owner
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PORTSC_CHANGE_MASK = 0x2A, // Mask of the port change bits,
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// they are WC (write clean)
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//
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// PCI Configuration Registers
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//
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EHC_BAR_INDEX = 0 /* how many bytes away from USB_BASE to 0x10 */
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}EHCI_REGISTER_OFFSET;
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#define USBSTS_IAA 0x20 // Interrupt on async advance
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#define USBSTS_PERIOD_ENABLED 0x4000 // Periodic schedule status
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#define USBSTS_ASYNC_ENABLED 0x8000 // Asynchronous schedule status
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#define USBSTS_HALT 0x1000 // Host controller halted
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#define USBSTS_SYS_ERROR 0x10 // Host system error
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#define USBSTS_INTACK_MASK 0x003F // Mask for the interrupt ACK, the WC
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// (write clean) bits in USBSTS register
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#define PORTSC_CONN 0x01 // Current Connect Status
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#define PORTSC_CONN_CHANGE 0x02 // Connect Status Change
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#define PORTSC_ENABLED 0x04 // Port Enable / Disable
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#define PORTSC_ENABLE_CHANGE 0x08 // Port Enable / Disable Change
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#define PORTSC_OVERCUR 0x10 // Over current Active
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#define PORTSC_OVERCUR_CHANGE 0x20 // Over current Change
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#define PORSTSC_RESUME 0x40 // Force Port Resume
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#define PORTSC_SUSPEND 0x80 // Port Suspend State
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#define PORTSC_RESET 0x100 // Port Reset
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#define PORTSC_LINESTATE_K 0x400 // Line Status K-state
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#define PORTSC_LINESTATE_J 0x800 // Line Status J-state
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#define PORTSC_POWER 0x1000 // Port Power
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#define PORTSC_OWNER 0x2000 // Port Owner
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#define PORTSC_CHANGE_MASK 0x2A // Mask of the port change bits,
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// they are WC (write clean)
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//
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// PCI Configuration Registers
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//
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#define EHC_BAR_INDEX 0 // how many bytes away from USB_BASE to 0x10
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#define EHC_LINK_TERMINATED(Link) (((Link) & 0x01) != 0)
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@@ -107,7 +109,7 @@ typedef struct {
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//
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#pragma pack(1)
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typedef struct {
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UINT8 PI;
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UINT8 ProgInterface;
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UINT8 SubClassCode;
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UINT8 BaseCode;
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} USB_CLASSC;
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