Improve coding style in MdeModulePkg.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9793 6f19259b-4bc3-4df7-8a09-765794883524
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@@ -2,7 +2,7 @@
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The definition for UHCI register operation routines.
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Copyright (c) 2007 - 2008, Intel Corporation
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Copyright (c) 2007 - 2010, Intel Corporation
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All rights reserved. This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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@@ -16,81 +16,83 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#ifndef _EFI_UHCI_REG_H_
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#define _EFI_UHCI_REG_H_
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typedef enum {
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UHCI_FRAME_NUM = 1024,
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//
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// UHCI register offset
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//
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//
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// Register offset and PCI related staff
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//
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USB_BAR_INDEX = 4,
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#define UHCI_FRAME_NUM 1024
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USBCMD_OFFSET = 0,
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USBSTS_OFFSET = 2,
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USBINTR_OFFSET = 4,
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USBPORTSC_OFFSET = 0x10,
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USB_FRAME_NO_OFFSET = 6,
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USB_FRAME_BASE_OFFSET = 8,
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USB_EMULATION_OFFSET = 0xC0,
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//
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// Register offset and PCI related staff
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//
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#define USB_BAR_INDEX 4
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//
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// Packet IDs
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//
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SETUP_PACKET_ID = 0x2D,
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INPUT_PACKET_ID = 0x69,
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OUTPUT_PACKET_ID = 0xE1,
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ERROR_PACKET_ID = 0x55,
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#define USBCMD_OFFSET 0
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#define USBSTS_OFFSET 2
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#define USBINTR_OFFSET 4
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#define USBPORTSC_OFFSET 0x10
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#define USB_FRAME_NO_OFFSET 6
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#define USB_FRAME_BASE_OFFSET 8
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#define USB_EMULATION_OFFSET 0xC0
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//
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// USB port status and control bit definition.
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//
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USBPORTSC_CCS = BIT0, // Current Connect Status
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USBPORTSC_CSC = BIT1, // Connect Status Change
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USBPORTSC_PED = BIT2, // Port Enable / Disable
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USBPORTSC_PEDC = BIT3, // Port Enable / Disable Change
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USBPORTSC_LSL = BIT4, // Line Status Low BIT
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USBPORTSC_LSH = BIT5, // Line Status High BIT
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USBPORTSC_RD = BIT6, // Resume Detect
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USBPORTSC_LSDA = BIT8, // Low Speed Device Attached
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USBPORTSC_PR = BIT9, // Port Reset
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USBPORTSC_SUSP = BIT12, // Suspend
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//
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// Packet IDs
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//
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#define SETUP_PACKET_ID 0x2D
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#define INPUT_PACKET_ID 0x69
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#define OUTPUT_PACKET_ID 0xE1
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#define ERROR_PACKET_ID 0x55
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//
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// UHCI Spec said it must implement 2 ports each host at least,
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// and if more, check whether the bit7 of PORTSC is always 1.
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// So here assume the max of port number each host is 16.
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//
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USB_MAX_ROOTHUB_PORT = 0x0F,
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//
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// Command register bit definitions
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//
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USBCMD_RS = BIT0, // Run/Stop
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USBCMD_HCRESET = BIT1, // Host reset
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USBCMD_GRESET = BIT2, // Global reset
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USBCMD_EGSM = BIT3, // Global Suspend Mode
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USBCMD_FGR = BIT4, // Force Global Resume
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USBCMD_SWDBG = BIT5, // SW Debug mode
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USBCMD_CF = BIT6, // Config Flag (sw only)
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USBCMD_MAXP = BIT7, // Max Packet (0 = 32, 1 = 64)
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//
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// USB port status and control bit definition.
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//
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#define USBPORTSC_CCS BIT0 // Current Connect Status
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#define USBPORTSC_CSC BIT1 // Connect Status Change
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#define USBPORTSC_PED BIT2 // Port Enable / Disable
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#define USBPORTSC_PEDC BIT3 // Port Enable / Disable Change
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#define USBPORTSC_LSL BIT4 // Line Status Low BIT
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#define USBPORTSC_LSH BIT5 // Line Status High BIT
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#define USBPORTSC_RD BIT6 // Resume Detect
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#define USBPORTSC_LSDA BIT8 // Low Speed Device Attached
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#define USBPORTSC_PR BIT9 // Port Reset
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#define USBPORTSC_SUSP BIT12 // Suspend
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//
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// USB Status register bit definitions
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//
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USBSTS_USBINT = BIT0, // Interrupt due to IOC
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USBSTS_ERROR = BIT1, // Interrupt due to error
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USBSTS_RD = BIT2, // Resume Detect
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USBSTS_HSE = BIT3, // Host System Error
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USBSTS_HCPE = BIT4, // Host Controller Process Error
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USBSTS_HCH = BIT5, // HC Halted
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//
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// UHCI Spec said it must implement 2 ports each host at least,
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// and if more, check whether the bit7 of PORTSC is always 1.
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// So here assume the max of port number each host is 16.
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//
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#define USB_MAX_ROOTHUB_PORT 0x0F
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USBTD_ACTIVE = BIT7, // TD is still active
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USBTD_STALLED = BIT6, // TD is stalled
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USBTD_BUFFERR = BIT5, // Buffer underflow or overflow
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USBTD_BABBLE = BIT4, // Babble condition
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USBTD_NAK = BIT3, // NAK is received
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USBTD_CRC = BIT2, // CRC/Time out error
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USBTD_BITSTUFF = BIT1 // Bit stuff error
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}UHCI_REGISTER_OFFSET;
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//
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// Command register bit definitions
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//
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#define USBCMD_RS BIT0 // Run/Stop
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#define USBCMD_HCRESET BIT1 // Host reset
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#define USBCMD_GRESET BIT2 // Global reset
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#define USBCMD_EGSM BIT3 // Global Suspend Mode
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#define USBCMD_FGR BIT4 // Force Global Resume
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#define USBCMD_SWDBG BIT5 // SW Debug mode
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#define USBCMD_CF BIT6 // Config Flag (sw only)
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#define USBCMD_MAXP BIT7 // Max Packet (0 = 32, 1 = 64)
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//
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// USB Status register bit definitions
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//
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#define USBSTS_USBINT BIT0 // Interrupt due to IOC
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#define USBSTS_ERROR BIT1 // Interrupt due to error
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#define USBSTS_RD BIT2 // Resume Detect
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#define USBSTS_HSE BIT3 // Host System Error
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#define USBSTS_HCPE BIT4 // Host Controller Process Error
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#define USBSTS_HCH BIT5 // HC Halted
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#define USBTD_ACTIVE BIT7 // TD is still active
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#define USBTD_STALLED BIT6 // TD is stalled
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#define USBTD_BUFFERR BIT5 // Buffer underflow or overflow
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#define USBTD_BABBLE BIT4 // Babble condition
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#define USBTD_NAK BIT3 // NAK is received
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#define USBTD_CRC BIT2 // CRC/Time out error
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#define USBTD_BITSTUFF BIT1 // Bit stuff error
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/**
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