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MdeModulePkg XhciDxe: Fix Map and Unmap inconsistency

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We found there are loops of *2* Maps and only *1* Unmap and
the DMA buffer address is decreasing.

It is caused by the below code flow.
XhcAsyncInterruptTransfer ->
  XhcCreateUrb ->
    XhcCreateTransferTrb ->
      Map Urb->DataMap           (1)

Timer: loops of *2* Maps and only *1* Unmap
XhcMonitorAsyncRequests ->
  XhcFlushAsyncIntMap ->
    Unmap and Map Urb->DataMap   (2)
  XhcUpdateAsyncRequest ->
    XhcCreateTransferTrb ->
      Map Urb->DataMap           (3)

This patch is to eliminate (3).

Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
(cherry picked from commit 0b9c0c6540)
This commit is contained in:
Star Zeng
2017-08-24 17:42:49 +08:00
parent d4fd304f8e
commit 1cf1eebf69
1 changed files with 5 additions and 2 deletions
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5
MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
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@@ -260,7 +260,10 @@ XhcCreateTransferTrb (
EPType = (UINT8) ((DEVICE_CONTEXT_64 *)OutputContext)->EP[Dci-1].EPType; EPType = (UINT8) ((DEVICE_CONTEXT_64 *)OutputContext)->EP[Dci-1].EPType;
} }
if (Urb->Data != NULL) { //
// No need to remap.
//
if ((Urb->Data != NULL) && (Urb->DataMap == NULL)) {
if (((UINT8) (Urb->Ep.Direction)) == EfiUsbDataIn) { if (((UINT8) (Urb->Ep.Direction)) == EfiUsbDataIn) {
MapOp = EfiPciIoOperationBusMasterWrite; MapOp = EfiPciIoOperationBusMasterWrite;
} else { } else {