UefiPayloadPkg: Add SpiFlashLib
This is a common SPI Flash library used for the Intel platform that supports SPI hardware sequence. This library provides actual SPI flash operation via Intel PCH SPI controller. Signed-off-by: Guo Dong <guo.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Cc: Benjamin You <benjamin.you@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Benjamin You <benjamin.you@intel.com>
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Guo Dong
mergify[bot]
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UefiPayloadPkg/Library/SpiFlashLib/SpiCommon.h
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208
UefiPayloadPkg/Library/SpiFlashLib/SpiCommon.h
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/** @file
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Header file for the SPI flash module.
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Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef SPI_COMMON_LIB_H_
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#define SPI_COMMON_LIB_H_
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#include <PiDxe.h>
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#include <Uefi/UefiBaseType.h>
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#include <IndustryStandard/Pci30.h>
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#include <Library/IoLib.h>
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#include <Library/DebugLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/SpiFlashLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/BaseLib.h>
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#include <Library/HobLib.h>
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#include <Library/TimerLib.h>
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#include <Guid/SpiFlashInfoGuid.h>
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#include "RegsSpi.h"
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///
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/// Maximum time allowed while waiting the SPI cycle to complete
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/// Wait Time = 6 seconds = 6000000 microseconds
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/// Wait Period = 10 microseconds
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///
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#define WAIT_TIME 6000000 ///< Wait Time = 6 seconds = 6000000 microseconds
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#define WAIT_PERIOD 10 ///< Wait Period = 10 microseconds
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///
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/// Flash cycle Type
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///
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typedef enum {
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FlashCycleRead,
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FlashCycleWrite,
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FlashCycleErase,
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FlashCycleReadSfdp,
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FlashCycleReadJedecId,
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FlashCycleWriteStatus,
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FlashCycleReadStatus,
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FlashCycleMax
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} FLASH_CYCLE_TYPE;
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///
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/// Flash Component Number
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///
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typedef enum {
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FlashComponent0,
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FlashComponent1,
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FlashComponentMax
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} FLASH_COMPONENT_NUM;
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///
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/// Private data structure definitions for the driver
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///
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#define SC_SPI_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('P', 'S', 'P', 'I')
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typedef struct {
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UINTN Signature;
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EFI_HANDLE Handle;
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UINT32 AcpiTmrReg;
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UINTN PchSpiBase;
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UINT16 RegionPermission;
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UINT32 SfdpVscc0Value;
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UINT32 SfdpVscc1Value;
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UINT32 StrapBaseAddress;
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UINT8 NumberOfComponents;
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UINT16 Flags;
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UINT32 Component1StartAddr;
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} SPI_INSTANCE;
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/**
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Acquire SPI MMIO BAR
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@param[in] PchSpiBase PCH SPI PCI Base Address
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@retval Return SPI BAR Address
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**/
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UINT32
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AcquireSpiBar0 (
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IN UINTN PchSpiBase
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);
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/**
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Release SPI MMIO BAR. Do nothing.
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@param[in] PchSpiBase PCH SPI PCI Base Address
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@retval None
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**/
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VOID
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ReleaseSpiBar0 (
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IN UINTN PchSpiBase
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);
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/**
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This function is a hook for Spi to disable BIOS Write Protect
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@param[in] PchSpiBase PCH SPI PCI Base Address
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@param[in] CpuSmmBwp Need to disable CPU SMM Bios write protection or not
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@retval EFI_SUCCESS The protocol instance was properly initialized
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@retval EFI_ACCESS_DENIED The BIOS Region can only be updated in SMM phase
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**/
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EFI_STATUS
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EFIAPI
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DisableBiosWriteProtect (
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IN UINTN PchSpiBase,
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IN UINT8 CpuSmmBwp
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);
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/**
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This function is a hook for Spi to enable BIOS Write Protect
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@param[in] PchSpiBase PCH SPI PCI Base Address
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@param[in] CpuSmmBwp Need to disable CPU SMM Bios write protection or not
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@retval None
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**/
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VOID
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EFIAPI
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EnableBiosWriteProtect (
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IN UINTN PchSpiBase,
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IN UINT8 CpuSmmBwp
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);
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/**
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This function disables SPI Prefetching and caching,
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and returns previous BIOS Control Register value before disabling.
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@param[in] PchSpiBase PCH SPI PCI Base Address
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@retval Previous BIOS Control Register value
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**/
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UINT8
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SaveAndDisableSpiPrefetchCache (
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IN UINTN PchSpiBase
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);
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/**
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This function updates BIOS Control Register with the given value.
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@param[in] PchSpiBase PCH SPI PCI Base Address
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@param[in] BiosCtlValue BIOS Control Register Value to be updated
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@retval None
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**/
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VOID
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SetSpiBiosControlRegister (
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IN UINTN PchSpiBase,
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IN UINT8 BiosCtlValue
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);
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/**
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This function sends the programmed SPI command to the slave device.
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@param[in] SpiRegionType The SPI Region type for flash cycle which is listed in the Descriptor
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@param[in] FlashCycleType The Flash SPI cycle type list in HSFC (Hardware Sequencing Flash Control Register) register
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@param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions.
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@param[in] ByteCount Number of bytes in the data portion of the SPI cycle.
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@param[in,out] Buffer Pointer to caller-allocated buffer containing the data received or sent during the SPI cycle.
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@retval EFI_SUCCESS SPI command completes successfully.
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@retval EFI_DEVICE_ERROR Device error, the command aborts abnormally.
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@retval EFI_ACCESS_DENIED Some unrecognized command encountered in hardware sequencing mode
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@retval EFI_INVALID_PARAMETER The parameters specified are not valid.
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**/
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EFI_STATUS
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SendSpiCmd (
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IN FLASH_REGION_TYPE FlashRegionType,
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IN FLASH_CYCLE_TYPE FlashCycleType,
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IN UINT32 Address,
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IN UINT32 ByteCount,
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IN OUT UINT8 *Buffer
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);
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/**
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Wait execution cycle to complete on the SPI interface.
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@param[in] PchSpiBar0 Spi MMIO base address
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@param[in] ErrorCheck TRUE if the SpiCycle needs to do the error check
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@retval TRUE SPI cycle completed on the interface.
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@retval FALSE Time out while waiting the SPI cycle to complete.
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It's not safe to program the next command on the SPI interface.
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**/
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BOOLEAN
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WaitForSpiCycleComplete (
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IN UINT32 PchSpiBar0,
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IN BOOLEAN ErrorCheck
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);
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#endif
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