ARM Packages: Fixed line endings
This large code change only modifies the line endings to be CRLF to be compliant with the EDK2 coding convention document. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14088 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin
@@ -1,133 +1,133 @@
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/** @file
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Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include <Chipset/ARM1176JZ-S.h>
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#include <Library/ArmLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/MemoryAllocationLib.h>
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VOID
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FillTranslationTable (
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IN UINT32 *TranslationTable,
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IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryRegion
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)
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{
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UINT32 *Entry;
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UINTN Sections;
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UINTN Index;
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UINT32 Attributes;
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UINT32 PhysicalBase = MemoryRegion->PhysicalBase;
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switch (MemoryRegion->Attributes) {
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case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
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Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(0);
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break;
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case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
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Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0);
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break;
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case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
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Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);
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break;
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case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:
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Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(1);
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break;
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case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:
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Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(1);
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break;
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case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:
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Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(1);
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break;
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default:
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Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);
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break;
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}
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Entry = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);
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Sections = ((( MemoryRegion->Length - 1 ) / TT_DESCRIPTOR_SECTION_SIZE ) + 1 );
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for (Index = 0; Index < Sections; Index++)
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{
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*Entry++ = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;
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PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;
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}
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}
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VOID
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EFIAPI
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ArmConfigureMmu (
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IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,
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OUT VOID **TranslationTableBase OPTIONAL,
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OUT UINTN *TranslationTableSize OPTIONAL
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)
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{
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VOID *TranslationTable;
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// Allocate pages for translation table.
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TranslationTable = AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_SIZE + TRANSLATION_TABLE_ALIGNMENT));
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TranslationTable = (VOID *)(((UINTN)TranslationTable + TRANSLATION_TABLE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_ALIGNMENT_MASK);
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if (TranslationTableBase != NULL) {
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*TranslationTableBase = TranslationTable;
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}
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if (TranslationTableBase != NULL) {
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*TranslationTableSize = TRANSLATION_TABLE_SIZE;
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}
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ZeroMem(TranslationTable, TRANSLATION_TABLE_SIZE);
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ArmCleanInvalidateDataCache();
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ArmInvalidateInstructionCache();
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ArmInvalidateTlb();
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ArmDisableDataCache();
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ArmDisableInstructionCache();
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ArmDisableMmu();
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// Make sure nothing sneaked into the cache
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ArmCleanInvalidateDataCache();
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ArmInvalidateInstructionCache();
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while (MemoryTable->Length != 0) {
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FillTranslationTable(TranslationTable, MemoryTable);
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MemoryTable++;
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}
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ArmSetTTBR0(TranslationTable);
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ArmSetDomainAccessControl(DOMAIN_ACCESS_CONTROL_NONE(15) |
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DOMAIN_ACCESS_CONTROL_NONE(14) |
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DOMAIN_ACCESS_CONTROL_NONE(13) |
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DOMAIN_ACCESS_CONTROL_NONE(12) |
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DOMAIN_ACCESS_CONTROL_NONE(11) |
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DOMAIN_ACCESS_CONTROL_NONE(10) |
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DOMAIN_ACCESS_CONTROL_NONE( 9) |
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DOMAIN_ACCESS_CONTROL_NONE( 8) |
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DOMAIN_ACCESS_CONTROL_NONE( 7) |
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DOMAIN_ACCESS_CONTROL_NONE( 6) |
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DOMAIN_ACCESS_CONTROL_NONE( 5) |
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DOMAIN_ACCESS_CONTROL_NONE( 4) |
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DOMAIN_ACCESS_CONTROL_NONE( 3) |
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DOMAIN_ACCESS_CONTROL_NONE( 2) |
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DOMAIN_ACCESS_CONTROL_NONE( 1) |
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DOMAIN_ACCESS_CONTROL_MANAGER(0));
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ArmEnableInstructionCache();
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ArmEnableDataCache();
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ArmEnableMmu();
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}
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/** @file
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Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include <Chipset/ARM1176JZ-S.h>
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#include <Library/ArmLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/MemoryAllocationLib.h>
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VOID
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FillTranslationTable (
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IN UINT32 *TranslationTable,
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IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryRegion
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)
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{
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UINT32 *Entry;
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UINTN Sections;
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UINTN Index;
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UINT32 Attributes;
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UINT32 PhysicalBase = MemoryRegion->PhysicalBase;
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switch (MemoryRegion->Attributes) {
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case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
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Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(0);
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break;
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case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
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Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0);
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break;
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case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
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Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);
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break;
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case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:
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Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(1);
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break;
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case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:
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Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(1);
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break;
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case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:
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Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(1);
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break;
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default:
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Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);
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break;
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}
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Entry = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);
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Sections = ((( MemoryRegion->Length - 1 ) / TT_DESCRIPTOR_SECTION_SIZE ) + 1 );
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for (Index = 0; Index < Sections; Index++)
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{
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*Entry++ = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;
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PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;
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}
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}
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VOID
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EFIAPI
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ArmConfigureMmu (
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IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,
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OUT VOID **TranslationTableBase OPTIONAL,
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OUT UINTN *TranslationTableSize OPTIONAL
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)
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{
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VOID *TranslationTable;
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// Allocate pages for translation table.
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TranslationTable = AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_SIZE + TRANSLATION_TABLE_ALIGNMENT));
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TranslationTable = (VOID *)(((UINTN)TranslationTable + TRANSLATION_TABLE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_ALIGNMENT_MASK);
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if (TranslationTableBase != NULL) {
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*TranslationTableBase = TranslationTable;
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}
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if (TranslationTableBase != NULL) {
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*TranslationTableSize = TRANSLATION_TABLE_SIZE;
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}
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ZeroMem(TranslationTable, TRANSLATION_TABLE_SIZE);
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ArmCleanInvalidateDataCache();
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ArmInvalidateInstructionCache();
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ArmInvalidateTlb();
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ArmDisableDataCache();
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ArmDisableInstructionCache();
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ArmDisableMmu();
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// Make sure nothing sneaked into the cache
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ArmCleanInvalidateDataCache();
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ArmInvalidateInstructionCache();
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while (MemoryTable->Length != 0) {
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FillTranslationTable(TranslationTable, MemoryTable);
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MemoryTable++;
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}
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ArmSetTTBR0(TranslationTable);
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ArmSetDomainAccessControl(DOMAIN_ACCESS_CONTROL_NONE(15) |
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DOMAIN_ACCESS_CONTROL_NONE(14) |
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DOMAIN_ACCESS_CONTROL_NONE(13) |
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DOMAIN_ACCESS_CONTROL_NONE(12) |
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DOMAIN_ACCESS_CONTROL_NONE(11) |
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DOMAIN_ACCESS_CONTROL_NONE(10) |
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DOMAIN_ACCESS_CONTROL_NONE( 9) |
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DOMAIN_ACCESS_CONTROL_NONE( 8) |
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DOMAIN_ACCESS_CONTROL_NONE( 7) |
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DOMAIN_ACCESS_CONTROL_NONE( 6) |
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DOMAIN_ACCESS_CONTROL_NONE( 5) |
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DOMAIN_ACCESS_CONTROL_NONE( 4) |
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DOMAIN_ACCESS_CONTROL_NONE( 3) |
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DOMAIN_ACCESS_CONTROL_NONE( 2) |
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DOMAIN_ACCESS_CONTROL_NONE( 1) |
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DOMAIN_ACCESS_CONTROL_MANAGER(0));
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ArmEnableInstructionCache();
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ArmEnableDataCache();
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ArmEnableMmu();
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}
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@@ -1,262 +1,262 @@
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#------------------------------------------------------------------------------
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#
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# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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# Copyright (c) 2011, ARM Limited. All rights reserved.
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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#------------------------------------------------------------------------------
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#include <AsmMacroIoLib.h>
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.text
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.align 2
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GCC_ASM_EXPORT(ArmDisableCachesAndMmu)
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GCC_ASM_EXPORT(ArmInvalidateInstructionAndDataTlb)
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GCC_ASM_EXPORT(ArmCleanInvalidateDataCache)
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GCC_ASM_EXPORT(ArmCleanDataCache)
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GCC_ASM_EXPORT(ArmInvalidateDataCache)
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GCC_ASM_EXPORT(ArmInvalidateInstructionCache)
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GCC_ASM_EXPORT(ArmInvalidateDataCacheEntryByMVA)
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GCC_ASM_EXPORT(ArmCleanDataCacheEntryByMVA)
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GCC_ASM_EXPORT(ArmCleanInvalidateDataCacheEntryByMVA)
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GCC_ASM_EXPORT(ArmEnableMmu)
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GCC_ASM_EXPORT(ArmDisableMmu)
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GCC_ASM_EXPORT(ArmMmuEnabled)
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GCC_ASM_EXPORT(ArmEnableDataCache)
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GCC_ASM_EXPORT(ArmDisableDataCache)
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GCC_ASM_EXPORT(ArmEnableInstructionCache)
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GCC_ASM_EXPORT(ArmDisableInstructionCache)
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GCC_ASM_EXPORT(ArmEnableBranchPrediction)
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GCC_ASM_EXPORT(ArmDisableBranchPrediction)
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GCC_ASM_EXPORT(ArmDataMemoryBarrier)
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GCC_ASM_EXPORT(ArmDataSyncronizationBarrier)
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GCC_ASM_EXPORT(ArmInstructionSynchronizationBarrier)
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GCC_ASM_EXPORT(ArmSetLowVectors)
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GCC_ASM_EXPORT(ArmSetHighVectors)
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GCC_ASM_EXPORT(ArmIsMpCore)
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GCC_ASM_EXPORT(ArmCallWFI)
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GCC_ASM_EXPORT(ArmReadMpidr)
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GCC_ASM_EXPORT(ArmUpdateTranslationTableEntry)
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GCC_ASM_EXPORT(ArmEnableFiq)
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GCC_ASM_EXPORT(ArmDisableFiq)
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GCC_ASM_EXPORT(ArmEnableInterrupts)
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GCC_ASM_EXPORT(ArmDisableInterrupts)
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GCC_ASM_EXPORT (ArmEnableVFP)
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Arm11PartNumberMask: .word 0xFFF0
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Arm11PartNumber: .word 0xB020
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.set DC_ON, (0x1<<2)
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.set IC_ON, (0x1<<12)
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.set XP_ON, (0x1<<23)
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.set CTRL_M_BIT, (1 << 0)
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.set CTRL_C_BIT, (1 << 2)
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.set CTRL_I_BIT, (1 << 12)
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ASM_PFX(ArmDisableCachesAndMmu):
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mrc p15, 0, r0, c1, c0, 0 @ Get control register
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bic r0, r0, #CTRL_M_BIT @ Disable MMU
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bic r0, r0, #CTRL_C_BIT @ Disable D Cache
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bic r0, r0, #CTRL_I_BIT @ Disable I Cache
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mcr p15, 0, r0, c1, c0, 0 @ Write control register
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bx LR
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ASM_PFX(ArmInvalidateInstructionAndDataTlb):
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mcr p15, 0, r0, c8, c7, 0 @ Invalidate Inst TLB and Data TLB
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bx lr
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ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
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mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line
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bx lr
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ASM_PFX(ArmCleanDataCacheEntryByMVA):
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mcr p15, 0, r0, c7, c10, 1 @clean single data cache line
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bx lr
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ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
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mcr p15, 0, r0, c7, c14, 1 @clean and invalidate single data cache line
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bx lr
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ASM_PFX(ArmCleanDataCache):
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mcr p15, 0, r0, c7, c10, 0 @ clean entire data cache
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bx lr
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ASM_PFX(ArmCleanInvalidateDataCache):
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mcr p15, 0, r0, c7, c14, 0 @ clean and invalidate entire data cache
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bx lr
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ASM_PFX(ArmInvalidateDataCache):
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mcr p15, 0, r0, c7, c6, 0 @ invalidate entire data cache
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bx lr
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ASM_PFX(ArmInvalidateInstructionCache):
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mcr p15, 0, r0, c7, c5, 0 @invalidate entire instruction cache
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mov R0,#0
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mcr p15,0,R0,c7,c5,4 @Flush Prefetch buffer
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bx lr
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ASM_PFX(ArmEnableMmu):
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mrc p15,0,R0,c1,c0,0
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orr R0,R0,#1
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mcr p15,0,R0,c1,c0,0
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bx LR
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ASM_PFX(ArmMmuEnabled):
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mrc p15,0,R0,c1,c0,0
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and R0,R0,#1
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bx LR
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ASM_PFX(ArmDisableMmu):
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mrc p15,0,R0,c1,c0,0
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bic R0,R0,#1
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mcr p15,0,R0,c1,c0,0
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mov R0,#0
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mcr p15,0,R0,c7,c10,4 @Data synchronization barrier
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mov R0,#0
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mcr p15,0,R0,c7,c5,4 @Flush Prefetch buffer
|
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bx LR
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ASM_PFX(ArmEnableDataCache):
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LoadConstantToReg(DC_ON, R1) @ldr R1,=DC_ON
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mrc p15,0,R0,c1,c0,0 @Read control register configuration data
|
||||
orr R0,R0,R1 @Set C bit
|
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mcr p15,0,r0,c1,c0,0 @Write control register configuration data
|
||||
bx LR
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||||
|
||||
ASM_PFX(ArmDisableDataCache):
|
||||
LoadConstantToReg(DC_ON, R1) @ldr R1,=DC_ON
|
||||
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
|
||||
bic R0,R0,R1 @Clear C bit
|
||||
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmEnableInstructionCache):
|
||||
ldr R1,=IC_ON
|
||||
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
|
||||
orr R0,R0,R1 @Set I bit
|
||||
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmDisableInstructionCache):
|
||||
ldr R1,=IC_ON
|
||||
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
|
||||
bic R0,R0,R1 @Clear I bit.
|
||||
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmEnableBranchPrediction):
|
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mrc p15, 0, r0, c1, c0, 0
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orr r0, r0, #0x00000800
|
||||
mcr p15, 0, r0, c1, c0, 0
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmDisableBranchPrediction):
|
||||
mrc p15, 0, r0, c1, c0, 0
|
||||
bic r0, r0, #0x00000800
|
||||
mcr p15, 0, r0, c1, c0, 0
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmDataMemoryBarrier):
|
||||
mov R0, #0
|
||||
mcr P15, #0, R0, C7, C10, #5
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmDataSyncronizationBarrier):
|
||||
mov R0, #0
|
||||
mcr P15, #0, R0, C7, C10, #4
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmInstructionSynchronizationBarrier):
|
||||
mov R0, #0
|
||||
mcr P15, #0, R0, C7, C5, #4
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmSetLowVectors):
|
||||
mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
|
||||
bic r0, r0, #0x00002000 @ clear V bit
|
||||
mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmSetHighVectors):
|
||||
mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
|
||||
orr r0, r0, #0x00002000 @ clear V bit
|
||||
mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmIsMpCore):
|
||||
push { r1 }
|
||||
mrc p15, 0, r0, c0, c0, 0
|
||||
# Extract Part Number to check it is an ARM11MP core (0xB02)
|
||||
LoadConstantToReg (Arm11PartNumberMask, r1)
|
||||
and r0, r0, r1
|
||||
LoadConstantToReg (Arm11PartNumber, r1)
|
||||
cmp r0, r1
|
||||
movne r0, #0
|
||||
pop { r1 }
|
||||
bx lr
|
||||
|
||||
ASM_PFX(ArmCallWFI):
|
||||
wfi
|
||||
bx lr
|
||||
|
||||
ASM_PFX(ArmReadMpidr):
|
||||
mrc p15, 0, r0, c0, c0, 5 @ read MPIDR
|
||||
bx lr
|
||||
|
||||
ASM_PFX(ArmEnableFiq):
|
||||
mrs R0,CPSR
|
||||
bic R0,R0,#0x40 @Enable FIQ interrupts
|
||||
msr CPSR_c,R0
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmDisableFiq):
|
||||
mrs R0,CPSR
|
||||
orr R1,R0,#0x40 @Disable FIQ interrupts
|
||||
msr CPSR_c,R1
|
||||
tst R0,#0x80
|
||||
moveq R0,#1
|
||||
movne R0,#0
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmEnableInterrupts):
|
||||
mrs R0,CPSR
|
||||
bic R0,R0,#0x80 @Enable IRQ interrupts
|
||||
msr CPSR_c,R0
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmDisableInterrupts):
|
||||
mrs R0,CPSR
|
||||
orr R1,R0,#0x80 @Disable IRQ interrupts
|
||||
msr CPSR_c,R1
|
||||
tst R0,#0x80
|
||||
moveq R0,#1
|
||||
movne R0,#0
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmEnableVFP):
|
||||
# Read CPACR (Coprocessor Access Control Register)
|
||||
mrc p15, 0, r0, c1, c0, 2
|
||||
# Enable VPF access (Full Access to CP10, CP11) (V* instructions)
|
||||
orr r0, r0, #0x00f00000
|
||||
# Write back CPACR (Coprocessor Access Control Register)
|
||||
mcr p15, 0, r0, c1, c0, 2
|
||||
# Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
|
||||
mov r0, #0x40000000
|
||||
#TODO: Fixme - need compilation flag
|
||||
#fmxr FPEXC, r0
|
||||
bx lr
|
||||
|
||||
ASM_FUNCTION_REMOVE_IF_UNREFERENCED
|
||||
#------------------------------------------------------------------------------
|
||||
#
|
||||
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
||||
# Copyright (c) 2011, ARM Limited. All rights reserved.
|
||||
#
|
||||
# This program and the accompanying materials
|
||||
# are licensed and made available under the terms and conditions of the BSD License
|
||||
# which accompanies this distribution. The full text of the license may be found at
|
||||
# http://opensource.org/licenses/bsd-license.php
|
||||
#
|
||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
#
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
#include <AsmMacroIoLib.h>
|
||||
|
||||
.text
|
||||
.align 2
|
||||
GCC_ASM_EXPORT(ArmDisableCachesAndMmu)
|
||||
GCC_ASM_EXPORT(ArmInvalidateInstructionAndDataTlb)
|
||||
GCC_ASM_EXPORT(ArmCleanInvalidateDataCache)
|
||||
GCC_ASM_EXPORT(ArmCleanDataCache)
|
||||
GCC_ASM_EXPORT(ArmInvalidateDataCache)
|
||||
GCC_ASM_EXPORT(ArmInvalidateInstructionCache)
|
||||
GCC_ASM_EXPORT(ArmInvalidateDataCacheEntryByMVA)
|
||||
GCC_ASM_EXPORT(ArmCleanDataCacheEntryByMVA)
|
||||
GCC_ASM_EXPORT(ArmCleanInvalidateDataCacheEntryByMVA)
|
||||
GCC_ASM_EXPORT(ArmEnableMmu)
|
||||
GCC_ASM_EXPORT(ArmDisableMmu)
|
||||
GCC_ASM_EXPORT(ArmMmuEnabled)
|
||||
GCC_ASM_EXPORT(ArmEnableDataCache)
|
||||
GCC_ASM_EXPORT(ArmDisableDataCache)
|
||||
GCC_ASM_EXPORT(ArmEnableInstructionCache)
|
||||
GCC_ASM_EXPORT(ArmDisableInstructionCache)
|
||||
GCC_ASM_EXPORT(ArmEnableBranchPrediction)
|
||||
GCC_ASM_EXPORT(ArmDisableBranchPrediction)
|
||||
GCC_ASM_EXPORT(ArmDataMemoryBarrier)
|
||||
GCC_ASM_EXPORT(ArmDataSyncronizationBarrier)
|
||||
GCC_ASM_EXPORT(ArmInstructionSynchronizationBarrier)
|
||||
GCC_ASM_EXPORT(ArmSetLowVectors)
|
||||
GCC_ASM_EXPORT(ArmSetHighVectors)
|
||||
GCC_ASM_EXPORT(ArmIsMpCore)
|
||||
GCC_ASM_EXPORT(ArmCallWFI)
|
||||
GCC_ASM_EXPORT(ArmReadMpidr)
|
||||
GCC_ASM_EXPORT(ArmUpdateTranslationTableEntry)
|
||||
GCC_ASM_EXPORT(ArmEnableFiq)
|
||||
GCC_ASM_EXPORT(ArmDisableFiq)
|
||||
GCC_ASM_EXPORT(ArmEnableInterrupts)
|
||||
GCC_ASM_EXPORT(ArmDisableInterrupts)
|
||||
GCC_ASM_EXPORT (ArmEnableVFP)
|
||||
|
||||
Arm11PartNumberMask: .word 0xFFF0
|
||||
Arm11PartNumber: .word 0xB020
|
||||
|
||||
.set DC_ON, (0x1<<2)
|
||||
.set IC_ON, (0x1<<12)
|
||||
.set XP_ON, (0x1<<23)
|
||||
.set CTRL_M_BIT, (1 << 0)
|
||||
.set CTRL_C_BIT, (1 << 2)
|
||||
.set CTRL_I_BIT, (1 << 12)
|
||||
|
||||
ASM_PFX(ArmDisableCachesAndMmu):
|
||||
mrc p15, 0, r0, c1, c0, 0 @ Get control register
|
||||
bic r0, r0, #CTRL_M_BIT @ Disable MMU
|
||||
bic r0, r0, #CTRL_C_BIT @ Disable D Cache
|
||||
bic r0, r0, #CTRL_I_BIT @ Disable I Cache
|
||||
mcr p15, 0, r0, c1, c0, 0 @ Write control register
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmInvalidateInstructionAndDataTlb):
|
||||
mcr p15, 0, r0, c8, c7, 0 @ Invalidate Inst TLB and Data TLB
|
||||
bx lr
|
||||
|
||||
ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
|
||||
mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line
|
||||
bx lr
|
||||
|
||||
|
||||
ASM_PFX(ArmCleanDataCacheEntryByMVA):
|
||||
mcr p15, 0, r0, c7, c10, 1 @clean single data cache line
|
||||
bx lr
|
||||
|
||||
|
||||
ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
|
||||
mcr p15, 0, r0, c7, c14, 1 @clean and invalidate single data cache line
|
||||
bx lr
|
||||
|
||||
|
||||
ASM_PFX(ArmCleanDataCache):
|
||||
mcr p15, 0, r0, c7, c10, 0 @ clean entire data cache
|
||||
bx lr
|
||||
|
||||
|
||||
ASM_PFX(ArmCleanInvalidateDataCache):
|
||||
mcr p15, 0, r0, c7, c14, 0 @ clean and invalidate entire data cache
|
||||
bx lr
|
||||
|
||||
|
||||
ASM_PFX(ArmInvalidateDataCache):
|
||||
mcr p15, 0, r0, c7, c6, 0 @ invalidate entire data cache
|
||||
bx lr
|
||||
|
||||
|
||||
ASM_PFX(ArmInvalidateInstructionCache):
|
||||
mcr p15, 0, r0, c7, c5, 0 @invalidate entire instruction cache
|
||||
mov R0,#0
|
||||
mcr p15,0,R0,c7,c5,4 @Flush Prefetch buffer
|
||||
bx lr
|
||||
|
||||
ASM_PFX(ArmEnableMmu):
|
||||
mrc p15,0,R0,c1,c0,0
|
||||
orr R0,R0,#1
|
||||
mcr p15,0,R0,c1,c0,0
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmMmuEnabled):
|
||||
mrc p15,0,R0,c1,c0,0
|
||||
and R0,R0,#1
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmDisableMmu):
|
||||
mrc p15,0,R0,c1,c0,0
|
||||
bic R0,R0,#1
|
||||
mcr p15,0,R0,c1,c0,0
|
||||
mov R0,#0
|
||||
mcr p15,0,R0,c7,c10,4 @Data synchronization barrier
|
||||
mov R0,#0
|
||||
mcr p15,0,R0,c7,c5,4 @Flush Prefetch buffer
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmEnableDataCache):
|
||||
LoadConstantToReg(DC_ON, R1) @ldr R1,=DC_ON
|
||||
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
|
||||
orr R0,R0,R1 @Set C bit
|
||||
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmDisableDataCache):
|
||||
LoadConstantToReg(DC_ON, R1) @ldr R1,=DC_ON
|
||||
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
|
||||
bic R0,R0,R1 @Clear C bit
|
||||
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmEnableInstructionCache):
|
||||
ldr R1,=IC_ON
|
||||
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
|
||||
orr R0,R0,R1 @Set I bit
|
||||
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmDisableInstructionCache):
|
||||
ldr R1,=IC_ON
|
||||
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
|
||||
bic R0,R0,R1 @Clear I bit.
|
||||
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmEnableBranchPrediction):
|
||||
mrc p15, 0, r0, c1, c0, 0
|
||||
orr r0, r0, #0x00000800
|
||||
mcr p15, 0, r0, c1, c0, 0
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmDisableBranchPrediction):
|
||||
mrc p15, 0, r0, c1, c0, 0
|
||||
bic r0, r0, #0x00000800
|
||||
mcr p15, 0, r0, c1, c0, 0
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmDataMemoryBarrier):
|
||||
mov R0, #0
|
||||
mcr P15, #0, R0, C7, C10, #5
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmDataSyncronizationBarrier):
|
||||
mov R0, #0
|
||||
mcr P15, #0, R0, C7, C10, #4
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmInstructionSynchronizationBarrier):
|
||||
mov R0, #0
|
||||
mcr P15, #0, R0, C7, C5, #4
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmSetLowVectors):
|
||||
mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
|
||||
bic r0, r0, #0x00002000 @ clear V bit
|
||||
mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmSetHighVectors):
|
||||
mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
|
||||
orr r0, r0, #0x00002000 @ clear V bit
|
||||
mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmIsMpCore):
|
||||
push { r1 }
|
||||
mrc p15, 0, r0, c0, c0, 0
|
||||
# Extract Part Number to check it is an ARM11MP core (0xB02)
|
||||
LoadConstantToReg (Arm11PartNumberMask, r1)
|
||||
and r0, r0, r1
|
||||
LoadConstantToReg (Arm11PartNumber, r1)
|
||||
cmp r0, r1
|
||||
movne r0, #0
|
||||
pop { r1 }
|
||||
bx lr
|
||||
|
||||
ASM_PFX(ArmCallWFI):
|
||||
wfi
|
||||
bx lr
|
||||
|
||||
ASM_PFX(ArmReadMpidr):
|
||||
mrc p15, 0, r0, c0, c0, 5 @ read MPIDR
|
||||
bx lr
|
||||
|
||||
ASM_PFX(ArmEnableFiq):
|
||||
mrs R0,CPSR
|
||||
bic R0,R0,#0x40 @Enable FIQ interrupts
|
||||
msr CPSR_c,R0
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmDisableFiq):
|
||||
mrs R0,CPSR
|
||||
orr R1,R0,#0x40 @Disable FIQ interrupts
|
||||
msr CPSR_c,R1
|
||||
tst R0,#0x80
|
||||
moveq R0,#1
|
||||
movne R0,#0
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmEnableInterrupts):
|
||||
mrs R0,CPSR
|
||||
bic R0,R0,#0x80 @Enable IRQ interrupts
|
||||
msr CPSR_c,R0
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmDisableInterrupts):
|
||||
mrs R0,CPSR
|
||||
orr R1,R0,#0x80 @Disable IRQ interrupts
|
||||
msr CPSR_c,R1
|
||||
tst R0,#0x80
|
||||
moveq R0,#1
|
||||
movne R0,#0
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmEnableVFP):
|
||||
# Read CPACR (Coprocessor Access Control Register)
|
||||
mrc p15, 0, r0, c1, c0, 2
|
||||
# Enable VPF access (Full Access to CP10, CP11) (V* instructions)
|
||||
orr r0, r0, #0x00f00000
|
||||
# Write back CPACR (Coprocessor Access Control Register)
|
||||
mcr p15, 0, r0, c1, c0, 2
|
||||
# Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
|
||||
mov r0, #0x40000000
|
||||
#TODO: Fixme - need compilation flag
|
||||
#fmxr FPEXC, r0
|
||||
bx lr
|
||||
|
||||
ASM_FUNCTION_REMOVE_IF_UNREFERENCED
|
||||
|
||||
@@ -1,157 +1,157 @@
|
||||
//------------------------------------------------------------------------------
|
||||
//
|
||||
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
||||
//
|
||||
// This program and the accompanying materials
|
||||
// are licensed and made available under the terms and conditions of the BSD License
|
||||
// which accompanies this distribution. The full text of the license may be found at
|
||||
// http://opensource.org/licenses/bsd-license.php
|
||||
//
|
||||
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
EXPORT ArmCleanInvalidateDataCache
|
||||
EXPORT ArmCleanDataCache
|
||||
EXPORT ArmInvalidateDataCache
|
||||
EXPORT ArmInvalidateInstructionCache
|
||||
EXPORT ArmInvalidateDataCacheEntryByMVA
|
||||
EXPORT ArmCleanDataCacheEntryByMVA
|
||||
EXPORT ArmCleanInvalidateDataCacheEntryByMVA
|
||||
EXPORT ArmEnableMmu
|
||||
EXPORT ArmDisableMmu
|
||||
EXPORT ArmMmuEnabled
|
||||
EXPORT ArmEnableDataCache
|
||||
EXPORT ArmDisableDataCache
|
||||
EXPORT ArmEnableInstructionCache
|
||||
EXPORT ArmDisableInstructionCache
|
||||
EXPORT ArmEnableBranchPrediction
|
||||
EXPORT ArmDisableBranchPrediction
|
||||
EXPORT ArmDataMemoryBarrier
|
||||
EXPORT ArmDataSyncronizationBarrier
|
||||
EXPORT ArmInstructionSynchronizationBarrier
|
||||
|
||||
|
||||
DC_ON EQU ( 0x1:SHL:2 )
|
||||
IC_ON EQU ( 0x1:SHL:12 )
|
||||
XP_ON EQU ( 0x1:SHL:23 )
|
||||
|
||||
|
||||
AREA ArmCacheLib, CODE, READONLY
|
||||
PRESERVE8
|
||||
|
||||
|
||||
ArmInvalidateDataCacheEntryByMVA
|
||||
mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
|
||||
bx lr
|
||||
|
||||
|
||||
ArmCleanDataCacheEntryByMVA
|
||||
mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line
|
||||
bx lr
|
||||
|
||||
|
||||
ArmCleanInvalidateDataCacheEntryByMVA
|
||||
mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
|
||||
bx lr
|
||||
|
||||
|
||||
ArmCleanDataCache
|
||||
mcr p15, 0, r0, c7, c10, 0 ; clean entire data cache
|
||||
bx lr
|
||||
|
||||
|
||||
ArmCleanInvalidateDataCache
|
||||
mcr p15, 0, r0, c7, c14, 0 ; clean and invalidate entire data cache
|
||||
bx lr
|
||||
|
||||
|
||||
ArmInvalidateDataCache
|
||||
mcr p15, 0, r0, c7, c6, 0 ; invalidate entire data cache
|
||||
bx lr
|
||||
|
||||
|
||||
ArmInvalidateInstructionCache
|
||||
mcr p15, 0, r0, c7, c5, 0 ;invalidate entire instruction cache
|
||||
mov R0,#0
|
||||
mcr p15,0,R0,c7,c5,4 ;Flush Prefetch buffer
|
||||
bx lr
|
||||
|
||||
ArmEnableMmu
|
||||
mrc p15,0,R0,c1,c0,0
|
||||
orr R0,R0,#1
|
||||
mcr p15,0,R0,c1,c0,0
|
||||
bx LR
|
||||
|
||||
ArmMmuEnabled
|
||||
mrc p15,0,R0,c1,c0,0
|
||||
and R0,R0,#1
|
||||
bx LR
|
||||
|
||||
ArmDisableMmu
|
||||
mrc p15,0,R0,c1,c0,0
|
||||
bic R0,R0,#1
|
||||
mcr p15,0,R0,c1,c0,0
|
||||
mov R0,#0
|
||||
mcr p15,0,R0,c7,c10,4 ;Data synchronization barrier
|
||||
mov R0,#0
|
||||
mcr p15,0,R0,c7,c5,4 ;Flush Prefetch buffer
|
||||
bx LR
|
||||
|
||||
ArmEnableDataCache
|
||||
LDR R1,=DC_ON
|
||||
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
|
||||
ORR R0,R0,R1 ;Set C bit
|
||||
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
|
||||
BX LR
|
||||
|
||||
ArmDisableDataCache
|
||||
LDR R1,=DC_ON
|
||||
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
|
||||
BIC R0,R0,R1 ;Clear C bit
|
||||
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
|
||||
BX LR
|
||||
|
||||
ArmEnableInstructionCache
|
||||
LDR R1,=IC_ON
|
||||
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
|
||||
ORR R0,R0,R1 ;Set I bit
|
||||
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
|
||||
BX LR
|
||||
|
||||
ArmDisableInstructionCache
|
||||
LDR R1,=IC_ON
|
||||
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
|
||||
BIC R0,R0,R1 ;Clear I bit.
|
||||
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
|
||||
BX LR
|
||||
|
||||
ArmEnableBranchPrediction
|
||||
mrc p15, 0, r0, c1, c0, 0
|
||||
orr r0, r0, #0x00000800
|
||||
mcr p15, 0, r0, c1, c0, 0
|
||||
bx LR
|
||||
|
||||
ArmDisableBranchPrediction
|
||||
mrc p15, 0, r0, c1, c0, 0
|
||||
bic r0, r0, #0x00000800
|
||||
mcr p15, 0, r0, c1, c0, 0
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmDataMemoryBarrier):
|
||||
mov R0, #0
|
||||
mcr P15, #0, R0, C7, C10, #5
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmDataSyncronizationBarrier):
|
||||
mov R0, #0
|
||||
mcr P15, #0, R0, C7, C10, #4
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmInstructionSynchronizationBarrier):
|
||||
MOV R0, #0
|
||||
MCR P15, #0, R0, C7, C5, #4
|
||||
bx LR
|
||||
|
||||
END
|
||||
//------------------------------------------------------------------------------
|
||||
//
|
||||
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
||||
//
|
||||
// This program and the accompanying materials
|
||||
// are licensed and made available under the terms and conditions of the BSD License
|
||||
// which accompanies this distribution. The full text of the license may be found at
|
||||
// http://opensource.org/licenses/bsd-license.php
|
||||
//
|
||||
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
EXPORT ArmCleanInvalidateDataCache
|
||||
EXPORT ArmCleanDataCache
|
||||
EXPORT ArmInvalidateDataCache
|
||||
EXPORT ArmInvalidateInstructionCache
|
||||
EXPORT ArmInvalidateDataCacheEntryByMVA
|
||||
EXPORT ArmCleanDataCacheEntryByMVA
|
||||
EXPORT ArmCleanInvalidateDataCacheEntryByMVA
|
||||
EXPORT ArmEnableMmu
|
||||
EXPORT ArmDisableMmu
|
||||
EXPORT ArmMmuEnabled
|
||||
EXPORT ArmEnableDataCache
|
||||
EXPORT ArmDisableDataCache
|
||||
EXPORT ArmEnableInstructionCache
|
||||
EXPORT ArmDisableInstructionCache
|
||||
EXPORT ArmEnableBranchPrediction
|
||||
EXPORT ArmDisableBranchPrediction
|
||||
EXPORT ArmDataMemoryBarrier
|
||||
EXPORT ArmDataSyncronizationBarrier
|
||||
EXPORT ArmInstructionSynchronizationBarrier
|
||||
|
||||
|
||||
DC_ON EQU ( 0x1:SHL:2 )
|
||||
IC_ON EQU ( 0x1:SHL:12 )
|
||||
XP_ON EQU ( 0x1:SHL:23 )
|
||||
|
||||
|
||||
AREA ArmCacheLib, CODE, READONLY
|
||||
PRESERVE8
|
||||
|
||||
|
||||
ArmInvalidateDataCacheEntryByMVA
|
||||
mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
|
||||
bx lr
|
||||
|
||||
|
||||
ArmCleanDataCacheEntryByMVA
|
||||
mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line
|
||||
bx lr
|
||||
|
||||
|
||||
ArmCleanInvalidateDataCacheEntryByMVA
|
||||
mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
|
||||
bx lr
|
||||
|
||||
|
||||
ArmCleanDataCache
|
||||
mcr p15, 0, r0, c7, c10, 0 ; clean entire data cache
|
||||
bx lr
|
||||
|
||||
|
||||
ArmCleanInvalidateDataCache
|
||||
mcr p15, 0, r0, c7, c14, 0 ; clean and invalidate entire data cache
|
||||
bx lr
|
||||
|
||||
|
||||
ArmInvalidateDataCache
|
||||
mcr p15, 0, r0, c7, c6, 0 ; invalidate entire data cache
|
||||
bx lr
|
||||
|
||||
|
||||
ArmInvalidateInstructionCache
|
||||
mcr p15, 0, r0, c7, c5, 0 ;invalidate entire instruction cache
|
||||
mov R0,#0
|
||||
mcr p15,0,R0,c7,c5,4 ;Flush Prefetch buffer
|
||||
bx lr
|
||||
|
||||
ArmEnableMmu
|
||||
mrc p15,0,R0,c1,c0,0
|
||||
orr R0,R0,#1
|
||||
mcr p15,0,R0,c1,c0,0
|
||||
bx LR
|
||||
|
||||
ArmMmuEnabled
|
||||
mrc p15,0,R0,c1,c0,0
|
||||
and R0,R0,#1
|
||||
bx LR
|
||||
|
||||
ArmDisableMmu
|
||||
mrc p15,0,R0,c1,c0,0
|
||||
bic R0,R0,#1
|
||||
mcr p15,0,R0,c1,c0,0
|
||||
mov R0,#0
|
||||
mcr p15,0,R0,c7,c10,4 ;Data synchronization barrier
|
||||
mov R0,#0
|
||||
mcr p15,0,R0,c7,c5,4 ;Flush Prefetch buffer
|
||||
bx LR
|
||||
|
||||
ArmEnableDataCache
|
||||
LDR R1,=DC_ON
|
||||
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
|
||||
ORR R0,R0,R1 ;Set C bit
|
||||
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
|
||||
BX LR
|
||||
|
||||
ArmDisableDataCache
|
||||
LDR R1,=DC_ON
|
||||
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
|
||||
BIC R0,R0,R1 ;Clear C bit
|
||||
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
|
||||
BX LR
|
||||
|
||||
ArmEnableInstructionCache
|
||||
LDR R1,=IC_ON
|
||||
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
|
||||
ORR R0,R0,R1 ;Set I bit
|
||||
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
|
||||
BX LR
|
||||
|
||||
ArmDisableInstructionCache
|
||||
LDR R1,=IC_ON
|
||||
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
|
||||
BIC R0,R0,R1 ;Clear I bit.
|
||||
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
|
||||
BX LR
|
||||
|
||||
ArmEnableBranchPrediction
|
||||
mrc p15, 0, r0, c1, c0, 0
|
||||
orr r0, r0, #0x00000800
|
||||
mcr p15, 0, r0, c1, c0, 0
|
||||
bx LR
|
||||
|
||||
ArmDisableBranchPrediction
|
||||
mrc p15, 0, r0, c1, c0, 0
|
||||
bic r0, r0, #0x00000800
|
||||
mcr p15, 0, r0, c1, c0, 0
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmDataMemoryBarrier):
|
||||
mov R0, #0
|
||||
mcr P15, #0, R0, C7, C10, #5
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmDataSyncronizationBarrier):
|
||||
mov R0, #0
|
||||
mcr P15, #0, R0, C7, C10, #4
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmInstructionSynchronizationBarrier):
|
||||
MOV R0, #0
|
||||
MCR P15, #0, R0, C7, C5, #4
|
||||
bx LR
|
||||
|
||||
END
|
||||
|
||||
@@ -1,131 +1,131 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
||||
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#include <Chipset/ARM926EJ-S.h>
|
||||
#include <Library/ArmLib.h>
|
||||
#include <Library/BaseMemoryLib.h>
|
||||
#include <Library/MemoryAllocationLib.h>
|
||||
#include <Library/DebugLib.h>
|
||||
|
||||
VOID
|
||||
FillTranslationTable (
|
||||
IN UINT32 *TranslationTable,
|
||||
IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryRegion
|
||||
)
|
||||
{
|
||||
UINT32 *Entry;
|
||||
UINTN Sections;
|
||||
UINTN Index;
|
||||
UINT32 Attributes;
|
||||
UINT32 PhysicalBase = MemoryRegion->PhysicalBase;
|
||||
|
||||
switch (MemoryRegion->Attributes) {
|
||||
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
|
||||
Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK;
|
||||
break;
|
||||
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
|
||||
Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH;
|
||||
break;
|
||||
case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
|
||||
Attributes = TT_DESCRIPTOR_SECTION_UNCACHED_UNBUFFERED;
|
||||
break;
|
||||
case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:
|
||||
case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:
|
||||
case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:
|
||||
ASSERT(0); // Trustzone is not supported on ARMv5
|
||||
default:
|
||||
Attributes = TT_DESCRIPTOR_SECTION_UNCACHED_UNBUFFERED;
|
||||
break;
|
||||
}
|
||||
|
||||
Entry = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);
|
||||
Sections = MemoryRegion->Length / TT_DESCRIPTOR_SECTION_SIZE;
|
||||
|
||||
// The current code does not support memory region size that is not aligned on TT_DESCRIPTOR_SECTION_SIZE boundary
|
||||
ASSERT (MemoryRegion->Length % TT_DESCRIPTOR_SECTION_SIZE == 0);
|
||||
|
||||
for (Index = 0; Index < Sections; Index++)
|
||||
{
|
||||
*Entry++ = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;
|
||||
PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;
|
||||
}
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmConfigureMmu (
|
||||
IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,
|
||||
OUT VOID **TranslationTableBase OPTIONAL,
|
||||
OUT UINTN *TranslationTableSize OPTIONAL
|
||||
)
|
||||
{
|
||||
VOID *TranslationTable;
|
||||
|
||||
// Allocate pages for translation table.
|
||||
TranslationTable = AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_SIZE + TRANSLATION_TABLE_ALIGNMENT));
|
||||
TranslationTable = (VOID *)(((UINTN)TranslationTable + TRANSLATION_TABLE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_ALIGNMENT_MASK);
|
||||
|
||||
if (TranslationTableBase != NULL) {
|
||||
*TranslationTableBase = TranslationTable;
|
||||
}
|
||||
|
||||
if (TranslationTableBase != NULL) {
|
||||
*TranslationTableSize = TRANSLATION_TABLE_SIZE;
|
||||
}
|
||||
|
||||
ZeroMem(TranslationTable, TRANSLATION_TABLE_SIZE);
|
||||
|
||||
ArmCleanInvalidateDataCache();
|
||||
ArmInvalidateInstructionCache();
|
||||
ArmInvalidateTlb();
|
||||
|
||||
ArmDisableDataCache();
|
||||
ArmDisableInstructionCache();
|
||||
ArmDisableMmu();
|
||||
|
||||
// Make sure nothing sneaked into the cache
|
||||
ArmCleanInvalidateDataCache();
|
||||
ArmInvalidateInstructionCache();
|
||||
|
||||
while (MemoryTable->Length != 0) {
|
||||
FillTranslationTable(TranslationTable, MemoryTable);
|
||||
MemoryTable++;
|
||||
}
|
||||
|
||||
ArmSetTTBR0(TranslationTable);
|
||||
|
||||
ArmSetDomainAccessControl(DOMAIN_ACCESS_CONTROL_NONE(15) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE(14) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE(13) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE(12) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE(11) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE(10) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE( 9) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE( 8) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE( 7) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE( 6) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE( 5) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE( 4) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE( 3) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE( 2) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE( 1) |
|
||||
DOMAIN_ACCESS_CONTROL_MANAGER(0));
|
||||
|
||||
ArmEnableInstructionCache();
|
||||
ArmEnableDataCache();
|
||||
ArmEnableMmu();
|
||||
}
|
||||
|
||||
|
||||
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
||||
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#include <Chipset/ARM926EJ-S.h>
|
||||
#include <Library/ArmLib.h>
|
||||
#include <Library/BaseMemoryLib.h>
|
||||
#include <Library/MemoryAllocationLib.h>
|
||||
#include <Library/DebugLib.h>
|
||||
|
||||
VOID
|
||||
FillTranslationTable (
|
||||
IN UINT32 *TranslationTable,
|
||||
IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryRegion
|
||||
)
|
||||
{
|
||||
UINT32 *Entry;
|
||||
UINTN Sections;
|
||||
UINTN Index;
|
||||
UINT32 Attributes;
|
||||
UINT32 PhysicalBase = MemoryRegion->PhysicalBase;
|
||||
|
||||
switch (MemoryRegion->Attributes) {
|
||||
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
|
||||
Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK;
|
||||
break;
|
||||
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
|
||||
Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH;
|
||||
break;
|
||||
case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
|
||||
Attributes = TT_DESCRIPTOR_SECTION_UNCACHED_UNBUFFERED;
|
||||
break;
|
||||
case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:
|
||||
case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:
|
||||
case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:
|
||||
ASSERT(0); // Trustzone is not supported on ARMv5
|
||||
default:
|
||||
Attributes = TT_DESCRIPTOR_SECTION_UNCACHED_UNBUFFERED;
|
||||
break;
|
||||
}
|
||||
|
||||
Entry = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);
|
||||
Sections = MemoryRegion->Length / TT_DESCRIPTOR_SECTION_SIZE;
|
||||
|
||||
// The current code does not support memory region size that is not aligned on TT_DESCRIPTOR_SECTION_SIZE boundary
|
||||
ASSERT (MemoryRegion->Length % TT_DESCRIPTOR_SECTION_SIZE == 0);
|
||||
|
||||
for (Index = 0; Index < Sections; Index++)
|
||||
{
|
||||
*Entry++ = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;
|
||||
PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;
|
||||
}
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmConfigureMmu (
|
||||
IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,
|
||||
OUT VOID **TranslationTableBase OPTIONAL,
|
||||
OUT UINTN *TranslationTableSize OPTIONAL
|
||||
)
|
||||
{
|
||||
VOID *TranslationTable;
|
||||
|
||||
// Allocate pages for translation table.
|
||||
TranslationTable = AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_SIZE + TRANSLATION_TABLE_ALIGNMENT));
|
||||
TranslationTable = (VOID *)(((UINTN)TranslationTable + TRANSLATION_TABLE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_ALIGNMENT_MASK);
|
||||
|
||||
if (TranslationTableBase != NULL) {
|
||||
*TranslationTableBase = TranslationTable;
|
||||
}
|
||||
|
||||
if (TranslationTableBase != NULL) {
|
||||
*TranslationTableSize = TRANSLATION_TABLE_SIZE;
|
||||
}
|
||||
|
||||
ZeroMem(TranslationTable, TRANSLATION_TABLE_SIZE);
|
||||
|
||||
ArmCleanInvalidateDataCache();
|
||||
ArmInvalidateInstructionCache();
|
||||
ArmInvalidateTlb();
|
||||
|
||||
ArmDisableDataCache();
|
||||
ArmDisableInstructionCache();
|
||||
ArmDisableMmu();
|
||||
|
||||
// Make sure nothing sneaked into the cache
|
||||
ArmCleanInvalidateDataCache();
|
||||
ArmInvalidateInstructionCache();
|
||||
|
||||
while (MemoryTable->Length != 0) {
|
||||
FillTranslationTable(TranslationTable, MemoryTable);
|
||||
MemoryTable++;
|
||||
}
|
||||
|
||||
ArmSetTTBR0(TranslationTable);
|
||||
|
||||
ArmSetDomainAccessControl(DOMAIN_ACCESS_CONTROL_NONE(15) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE(14) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE(13) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE(12) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE(11) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE(10) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE( 9) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE( 8) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE( 7) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE( 6) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE( 5) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE( 4) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE( 3) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE( 2) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE( 1) |
|
||||
DOMAIN_ACCESS_CONTROL_MANAGER(0));
|
||||
|
||||
ArmEnableInstructionCache();
|
||||
ArmEnableDataCache();
|
||||
ArmEnableMmu();
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -1,153 +1,153 @@
|
||||
#------------------------------------------------------------------------------
|
||||
#
|
||||
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
||||
#
|
||||
# This program and the accompanying materials
|
||||
# are licensed and made available under the terms and conditions of the BSD License
|
||||
# which accompanies this distribution. The full text of the license may be found at
|
||||
# http://opensource.org/licenses/bsd-license.php
|
||||
#
|
||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
#
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
.text
|
||||
.align 2
|
||||
GCC_ASM_EXPORT(ArmCleanInvalidateDataCache)
|
||||
GCC_ASM_EXPORT(ArmCleanDataCache)
|
||||
GCC_ASM_EXPORT(ArmInvalidateDataCache)
|
||||
GCC_ASM_EXPORT(ArmInvalidateInstructionCache)
|
||||
GCC_ASM_EXPORT(ArmInvalidateDataCacheEntryByMVA)
|
||||
GCC_ASM_EXPORT(ArmCleanDataCacheEntryByMVA)
|
||||
GCC_ASM_EXPORT(ArmCleanInvalidateDataCacheEntryByMVA)
|
||||
GCC_ASM_EXPORT(ArmEnableMmu)
|
||||
GCC_ASM_EXPORT(ArmDisableMmu)
|
||||
GCC_ASM_EXPORT(ArmMmuEnabled)
|
||||
GCC_ASM_EXPORT(ArmEnableDataCache)
|
||||
GCC_ASM_EXPORT(ArmDisableDataCache)
|
||||
GCC_ASM_EXPORT(ArmEnableInstructionCache)
|
||||
GCC_ASM_EXPORT(ArmDisableInstructionCache)
|
||||
GCC_ASM_EXPORT(ArmEnableBranchPrediction)
|
||||
GCC_ASM_EXPORT(ArmDisableBranchPrediction)
|
||||
GCC_ASM_EXPORT(ArmDataMemoryBarrier)
|
||||
GCC_ASM_EXPORT(ArmDataSyncronizationBarrier)
|
||||
GCC_ASM_EXPORT(ArmInstructionSynchronizationBarrier)
|
||||
|
||||
|
||||
.set DC_ON, (1<<2)
|
||||
.set IC_ON, (1<<12)
|
||||
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
|
||||
mcr p15, 0, r0, c7, c6, 1 @ invalidate single data cache line
|
||||
bx lr
|
||||
|
||||
ASM_PFX(ArmCleanDataCacheEntryByMVA):
|
||||
mcr p15, 0, r0, c7, c10, 1 @ clean single data cache line
|
||||
bx lr
|
||||
|
||||
ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
|
||||
mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate single data cache line
|
||||
bx lr
|
||||
|
||||
ASM_PFX(ArmEnableInstructionCache):
|
||||
ldr r1,=IC_ON
|
||||
mrc p15,0,r0,c1,c0,0 @Read control register configuration data
|
||||
orr r0,r0,r1 @Set I bit
|
||||
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmDisableInstructionCache):
|
||||
ldr r1,=IC_ON
|
||||
mrc p15,0,r0,c1,c0,0 @Read control register configuration data
|
||||
bic r0,r0,r1 @Clear I bit.
|
||||
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmInvalidateInstructionCache):
|
||||
mov r0,#0
|
||||
mcr p15,0,r0,c7,c5,0 @Invalidate entire Instruction cache.
|
||||
@Also flushes the branch target cache.
|
||||
mov r0,#0
|
||||
mcr p15,0,r0,c7,c10,4 @Data write buffer
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmEnableMmu):
|
||||
mrc p15,0,R0,c1,c0,0
|
||||
orr R0,R0,#1
|
||||
mcr p15,0,R0,c1,c0,0
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmMmuEnabled):
|
||||
mrc p15,0,R0,c1,c0,0
|
||||
and R0,R0,#1
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmDisableMmu):
|
||||
mrc p15,0,R0,c1,c0,0
|
||||
bic R0,R0,#1
|
||||
mcr p15,0,R0,c1,c0,0
|
||||
mov R0,#0
|
||||
mcr p15,0,R0,c7,c10,4 @Drain write buffer
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmEnableDataCache):
|
||||
ldr R1,=DC_ON
|
||||
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
|
||||
orr R0,R0,R1 @Set C bit
|
||||
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmDisableDataCache):
|
||||
ldr R1,=DC_ON
|
||||
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
|
||||
bic R0,R0,R1 @Clear C bit
|
||||
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmCleanDataCache):
|
||||
mrc p15,0,r15,c7,c10,3
|
||||
bne ASM_PFX(ArmCleanDataCache)
|
||||
mov R0,#0
|
||||
mcr p15,0,R0,c7,c10,4 @Drain write buffer
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmInvalidateDataCache):
|
||||
mov R0,#0
|
||||
mcr p15,0,R0,c7,c6,0 @Invalidate entire data cache
|
||||
mov R0,#0
|
||||
mcr p15,0,R0,c7,c10,4 @Drain write buffer
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmCleanInvalidateDataCache):
|
||||
mrc p15,0,r15,c7,c14,3
|
||||
bne ASM_PFX(ArmCleanInvalidateDataCache)
|
||||
mov R0,#0
|
||||
mcr p15,0,R0,c7,c10,4 @Drain write buffer
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmEnableBranchPrediction):
|
||||
bx LR @Branch prediction is not supported.
|
||||
|
||||
ASM_PFX(ArmDisableBranchPrediction):
|
||||
bx LR @Branch prediction is not supported.
|
||||
|
||||
ASM_PFX(ArmDataMemoryBarrier):
|
||||
mov R0, #0
|
||||
mcr P15, #0, R0, C7, C10, #5 @ check if this is OK?
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmDataSyncronizationBarrier):
|
||||
mov R0, #0
|
||||
mcr P15, #0, R0, C7, C10, #4 @ check if this is OK?
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmInstructionSynchronizationBarrier):
|
||||
mov R0, #0
|
||||
mcr P15, #0, R0, C7, C5, #4 @ check if this is OK?
|
||||
bx LR
|
||||
|
||||
ASM_FUNCTION_REMOVE_IF_UNREFERENCED
|
||||
|
||||
#------------------------------------------------------------------------------
|
||||
#
|
||||
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
||||
#
|
||||
# This program and the accompanying materials
|
||||
# are licensed and made available under the terms and conditions of the BSD License
|
||||
# which accompanies this distribution. The full text of the license may be found at
|
||||
# http://opensource.org/licenses/bsd-license.php
|
||||
#
|
||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
#
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
.text
|
||||
.align 2
|
||||
GCC_ASM_EXPORT(ArmCleanInvalidateDataCache)
|
||||
GCC_ASM_EXPORT(ArmCleanDataCache)
|
||||
GCC_ASM_EXPORT(ArmInvalidateDataCache)
|
||||
GCC_ASM_EXPORT(ArmInvalidateInstructionCache)
|
||||
GCC_ASM_EXPORT(ArmInvalidateDataCacheEntryByMVA)
|
||||
GCC_ASM_EXPORT(ArmCleanDataCacheEntryByMVA)
|
||||
GCC_ASM_EXPORT(ArmCleanInvalidateDataCacheEntryByMVA)
|
||||
GCC_ASM_EXPORT(ArmEnableMmu)
|
||||
GCC_ASM_EXPORT(ArmDisableMmu)
|
||||
GCC_ASM_EXPORT(ArmMmuEnabled)
|
||||
GCC_ASM_EXPORT(ArmEnableDataCache)
|
||||
GCC_ASM_EXPORT(ArmDisableDataCache)
|
||||
GCC_ASM_EXPORT(ArmEnableInstructionCache)
|
||||
GCC_ASM_EXPORT(ArmDisableInstructionCache)
|
||||
GCC_ASM_EXPORT(ArmEnableBranchPrediction)
|
||||
GCC_ASM_EXPORT(ArmDisableBranchPrediction)
|
||||
GCC_ASM_EXPORT(ArmDataMemoryBarrier)
|
||||
GCC_ASM_EXPORT(ArmDataSyncronizationBarrier)
|
||||
GCC_ASM_EXPORT(ArmInstructionSynchronizationBarrier)
|
||||
|
||||
|
||||
.set DC_ON, (1<<2)
|
||||
.set IC_ON, (1<<12)
|
||||
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
|
||||
mcr p15, 0, r0, c7, c6, 1 @ invalidate single data cache line
|
||||
bx lr
|
||||
|
||||
ASM_PFX(ArmCleanDataCacheEntryByMVA):
|
||||
mcr p15, 0, r0, c7, c10, 1 @ clean single data cache line
|
||||
bx lr
|
||||
|
||||
ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
|
||||
mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate single data cache line
|
||||
bx lr
|
||||
|
||||
ASM_PFX(ArmEnableInstructionCache):
|
||||
ldr r1,=IC_ON
|
||||
mrc p15,0,r0,c1,c0,0 @Read control register configuration data
|
||||
orr r0,r0,r1 @Set I bit
|
||||
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmDisableInstructionCache):
|
||||
ldr r1,=IC_ON
|
||||
mrc p15,0,r0,c1,c0,0 @Read control register configuration data
|
||||
bic r0,r0,r1 @Clear I bit.
|
||||
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmInvalidateInstructionCache):
|
||||
mov r0,#0
|
||||
mcr p15,0,r0,c7,c5,0 @Invalidate entire Instruction cache.
|
||||
@Also flushes the branch target cache.
|
||||
mov r0,#0
|
||||
mcr p15,0,r0,c7,c10,4 @Data write buffer
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmEnableMmu):
|
||||
mrc p15,0,R0,c1,c0,0
|
||||
orr R0,R0,#1
|
||||
mcr p15,0,R0,c1,c0,0
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmMmuEnabled):
|
||||
mrc p15,0,R0,c1,c0,0
|
||||
and R0,R0,#1
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmDisableMmu):
|
||||
mrc p15,0,R0,c1,c0,0
|
||||
bic R0,R0,#1
|
||||
mcr p15,0,R0,c1,c0,0
|
||||
mov R0,#0
|
||||
mcr p15,0,R0,c7,c10,4 @Drain write buffer
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmEnableDataCache):
|
||||
ldr R1,=DC_ON
|
||||
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
|
||||
orr R0,R0,R1 @Set C bit
|
||||
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmDisableDataCache):
|
||||
ldr R1,=DC_ON
|
||||
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
|
||||
bic R0,R0,R1 @Clear C bit
|
||||
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmCleanDataCache):
|
||||
mrc p15,0,r15,c7,c10,3
|
||||
bne ASM_PFX(ArmCleanDataCache)
|
||||
mov R0,#0
|
||||
mcr p15,0,R0,c7,c10,4 @Drain write buffer
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmInvalidateDataCache):
|
||||
mov R0,#0
|
||||
mcr p15,0,R0,c7,c6,0 @Invalidate entire data cache
|
||||
mov R0,#0
|
||||
mcr p15,0,R0,c7,c10,4 @Drain write buffer
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmCleanInvalidateDataCache):
|
||||
mrc p15,0,r15,c7,c14,3
|
||||
bne ASM_PFX(ArmCleanInvalidateDataCache)
|
||||
mov R0,#0
|
||||
mcr p15,0,R0,c7,c10,4 @Drain write buffer
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmEnableBranchPrediction):
|
||||
bx LR @Branch prediction is not supported.
|
||||
|
||||
ASM_PFX(ArmDisableBranchPrediction):
|
||||
bx LR @Branch prediction is not supported.
|
||||
|
||||
ASM_PFX(ArmDataMemoryBarrier):
|
||||
mov R0, #0
|
||||
mcr P15, #0, R0, C7, C10, #5 @ check if this is OK?
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmDataSyncronizationBarrier):
|
||||
mov R0, #0
|
||||
mcr P15, #0, R0, C7, C10, #4 @ check if this is OK?
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmInstructionSynchronizationBarrier):
|
||||
mov R0, #0
|
||||
mcr P15, #0, R0, C7, C5, #4 @ check if this is OK?
|
||||
bx LR
|
||||
|
||||
ASM_FUNCTION_REMOVE_IF_UNREFERENCED
|
||||
|
||||
|
||||
@@ -1,153 +1,153 @@
|
||||
//------------------------------------------------------------------------------
|
||||
//
|
||||
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
||||
//
|
||||
// This program and the accompanying materials
|
||||
// are licensed and made available under the terms and conditions of the BSD License
|
||||
// which accompanies this distribution. The full text of the license may be found at
|
||||
// http://opensource.org/licenses/bsd-license.php
|
||||
//
|
||||
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
EXPORT ArmCleanInvalidateDataCache
|
||||
EXPORT ArmCleanDataCache
|
||||
EXPORT ArmInvalidateDataCache
|
||||
EXPORT ArmInvalidateInstructionCache
|
||||
EXPORT ArmInvalidateDataCacheEntryByMVA
|
||||
EXPORT ArmCleanDataCacheEntryByMVA
|
||||
EXPORT ArmCleanInvalidateDataCacheEntryByMVA
|
||||
EXPORT ArmEnableMmu
|
||||
EXPORT ArmDisableMmu
|
||||
EXPORT ArmMmuEnabled
|
||||
EXPORT ArmEnableDataCache
|
||||
EXPORT ArmDisableDataCache
|
||||
EXPORT ArmEnableInstructionCache
|
||||
EXPORT ArmDisableInstructionCache
|
||||
EXPORT ArmEnableBranchPrediction
|
||||
EXPORT ArmDisableBranchPrediction
|
||||
EXPORT ArmDataMemoryBarrier
|
||||
EXPORT ArmDataSyncronizationBarrier
|
||||
EXPORT ArmInstructionSynchronizationBarrier
|
||||
|
||||
|
||||
DC_ON EQU ( 0x1:SHL:2 )
|
||||
IC_ON EQU ( 0x1:SHL:12 )
|
||||
|
||||
AREA ArmCacheLib, CODE, READONLY
|
||||
PRESERVE8
|
||||
|
||||
|
||||
ArmInvalidateDataCacheEntryByMVA
|
||||
MCR p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
|
||||
BX lr
|
||||
|
||||
|
||||
ArmCleanDataCacheEntryByMVA
|
||||
MCR p15, 0, r0, c7, c10, 1 ; clean single data cache line
|
||||
BX lr
|
||||
|
||||
|
||||
ArmCleanInvalidateDataCacheEntryByMVA
|
||||
MCR p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
|
||||
BX lr
|
||||
|
||||
ArmEnableInstructionCache
|
||||
LDR R1,=IC_ON
|
||||
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
|
||||
ORR R0,R0,R1 ;Set I bit
|
||||
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
|
||||
BX LR
|
||||
|
||||
ArmDisableInstructionCache
|
||||
LDR R1,=IC_ON
|
||||
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
|
||||
BIC R0,R0,R1 ;Clear I bit.
|
||||
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
|
||||
BX LR
|
||||
|
||||
ArmInvalidateInstructionCache
|
||||
MOV R0,#0
|
||||
MCR p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache
|
||||
MOV R0,#0
|
||||
MCR p15,0,R0,c7,c10,4 ;Drain write buffer
|
||||
BX LR
|
||||
|
||||
ArmEnableMmu
|
||||
mrc p15,0,R0,c1,c0,0
|
||||
orr R0,R0,#1
|
||||
mcr p15,0,R0,c1,c0,0
|
||||
bx LR
|
||||
|
||||
ArmMmuEnabled
|
||||
mrc p15,0,R0,c1,c0,0
|
||||
and R0,R0,#1
|
||||
bx LR
|
||||
|
||||
ArmDisableMmu
|
||||
mrc p15,0,R0,c1,c0,0
|
||||
bic R0,R0,#1
|
||||
mcr p15,0,R0,c1,c0,0
|
||||
mov R0,#0
|
||||
mcr p15,0,R0,c7,c10,4 ;Drain write buffer
|
||||
bx LR
|
||||
|
||||
ArmEnableDataCache
|
||||
LDR R1,=DC_ON
|
||||
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
|
||||
ORR R0,R0,R1 ;Set C bit
|
||||
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
|
||||
BX LR
|
||||
|
||||
ArmDisableDataCache
|
||||
LDR R1,=DC_ON
|
||||
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
|
||||
BIC R0,R0,R1 ;Clear C bit
|
||||
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
|
||||
BX LR
|
||||
|
||||
ArmCleanDataCache
|
||||
MRC p15,0,r15,c7,c10,3
|
||||
BNE ArmCleanDataCache
|
||||
MOV R0,#0
|
||||
MCR p15,0,R0,c7,c10,4 ;Drain write buffer
|
||||
BX LR
|
||||
|
||||
ArmInvalidateDataCache
|
||||
MOV R0,#0
|
||||
MCR p15,0,R0,c7,c6,0 ;Invalidate entire data cache
|
||||
MOV R0,#0
|
||||
MCR p15,0,R0,c7,c10,4 ;Drain write buffer
|
||||
BX LR
|
||||
|
||||
ArmCleanInvalidateDataCache
|
||||
MRC p15,0,r15,c7,c14,3
|
||||
BNE ArmCleanInvalidateDataCache
|
||||
MOV R0,#0
|
||||
MCR p15,0,R0,c7,c10,4 ;Drain write buffer
|
||||
BX LR
|
||||
|
||||
ArmEnableBranchPrediction
|
||||
bx LR ;Branch prediction is not supported.
|
||||
|
||||
ArmDisableBranchPrediction
|
||||
bx LR ;Branch prediction is not supported.
|
||||
|
||||
ASM_PFX(ArmDataMemoryBarrier):
|
||||
mov R0, #0
|
||||
mcr P15, #0, R0, C7, C10, #5 ; Check to see if this is correct
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmDataSyncronizationBarrier):
|
||||
mov R0, #0
|
||||
mcr P15, #0, R0, C7, C10, #4 ; Check to see if this is correct
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmInstructionSynchronizationBarrier):
|
||||
MOV R0, #0
|
||||
MCR P15, #0, R0, C7, C5, #4 ; Check to see if this is correct
|
||||
bx LR
|
||||
|
||||
END
|
||||
//------------------------------------------------------------------------------
|
||||
//
|
||||
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
||||
//
|
||||
// This program and the accompanying materials
|
||||
// are licensed and made available under the terms and conditions of the BSD License
|
||||
// which accompanies this distribution. The full text of the license may be found at
|
||||
// http://opensource.org/licenses/bsd-license.php
|
||||
//
|
||||
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
EXPORT ArmCleanInvalidateDataCache
|
||||
EXPORT ArmCleanDataCache
|
||||
EXPORT ArmInvalidateDataCache
|
||||
EXPORT ArmInvalidateInstructionCache
|
||||
EXPORT ArmInvalidateDataCacheEntryByMVA
|
||||
EXPORT ArmCleanDataCacheEntryByMVA
|
||||
EXPORT ArmCleanInvalidateDataCacheEntryByMVA
|
||||
EXPORT ArmEnableMmu
|
||||
EXPORT ArmDisableMmu
|
||||
EXPORT ArmMmuEnabled
|
||||
EXPORT ArmEnableDataCache
|
||||
EXPORT ArmDisableDataCache
|
||||
EXPORT ArmEnableInstructionCache
|
||||
EXPORT ArmDisableInstructionCache
|
||||
EXPORT ArmEnableBranchPrediction
|
||||
EXPORT ArmDisableBranchPrediction
|
||||
EXPORT ArmDataMemoryBarrier
|
||||
EXPORT ArmDataSyncronizationBarrier
|
||||
EXPORT ArmInstructionSynchronizationBarrier
|
||||
|
||||
|
||||
DC_ON EQU ( 0x1:SHL:2 )
|
||||
IC_ON EQU ( 0x1:SHL:12 )
|
||||
|
||||
AREA ArmCacheLib, CODE, READONLY
|
||||
PRESERVE8
|
||||
|
||||
|
||||
ArmInvalidateDataCacheEntryByMVA
|
||||
MCR p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
|
||||
BX lr
|
||||
|
||||
|
||||
ArmCleanDataCacheEntryByMVA
|
||||
MCR p15, 0, r0, c7, c10, 1 ; clean single data cache line
|
||||
BX lr
|
||||
|
||||
|
||||
ArmCleanInvalidateDataCacheEntryByMVA
|
||||
MCR p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
|
||||
BX lr
|
||||
|
||||
ArmEnableInstructionCache
|
||||
LDR R1,=IC_ON
|
||||
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
|
||||
ORR R0,R0,R1 ;Set I bit
|
||||
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
|
||||
BX LR
|
||||
|
||||
ArmDisableInstructionCache
|
||||
LDR R1,=IC_ON
|
||||
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
|
||||
BIC R0,R0,R1 ;Clear I bit.
|
||||
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
|
||||
BX LR
|
||||
|
||||
ArmInvalidateInstructionCache
|
||||
MOV R0,#0
|
||||
MCR p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache
|
||||
MOV R0,#0
|
||||
MCR p15,0,R0,c7,c10,4 ;Drain write buffer
|
||||
BX LR
|
||||
|
||||
ArmEnableMmu
|
||||
mrc p15,0,R0,c1,c0,0
|
||||
orr R0,R0,#1
|
||||
mcr p15,0,R0,c1,c0,0
|
||||
bx LR
|
||||
|
||||
ArmMmuEnabled
|
||||
mrc p15,0,R0,c1,c0,0
|
||||
and R0,R0,#1
|
||||
bx LR
|
||||
|
||||
ArmDisableMmu
|
||||
mrc p15,0,R0,c1,c0,0
|
||||
bic R0,R0,#1
|
||||
mcr p15,0,R0,c1,c0,0
|
||||
mov R0,#0
|
||||
mcr p15,0,R0,c7,c10,4 ;Drain write buffer
|
||||
bx LR
|
||||
|
||||
ArmEnableDataCache
|
||||
LDR R1,=DC_ON
|
||||
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
|
||||
ORR R0,R0,R1 ;Set C bit
|
||||
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
|
||||
BX LR
|
||||
|
||||
ArmDisableDataCache
|
||||
LDR R1,=DC_ON
|
||||
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
|
||||
BIC R0,R0,R1 ;Clear C bit
|
||||
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
|
||||
BX LR
|
||||
|
||||
ArmCleanDataCache
|
||||
MRC p15,0,r15,c7,c10,3
|
||||
BNE ArmCleanDataCache
|
||||
MOV R0,#0
|
||||
MCR p15,0,R0,c7,c10,4 ;Drain write buffer
|
||||
BX LR
|
||||
|
||||
ArmInvalidateDataCache
|
||||
MOV R0,#0
|
||||
MCR p15,0,R0,c7,c6,0 ;Invalidate entire data cache
|
||||
MOV R0,#0
|
||||
MCR p15,0,R0,c7,c10,4 ;Drain write buffer
|
||||
BX LR
|
||||
|
||||
ArmCleanInvalidateDataCache
|
||||
MRC p15,0,r15,c7,c14,3
|
||||
BNE ArmCleanInvalidateDataCache
|
||||
MOV R0,#0
|
||||
MCR p15,0,R0,c7,c10,4 ;Drain write buffer
|
||||
BX LR
|
||||
|
||||
ArmEnableBranchPrediction
|
||||
bx LR ;Branch prediction is not supported.
|
||||
|
||||
ArmDisableBranchPrediction
|
||||
bx LR ;Branch prediction is not supported.
|
||||
|
||||
ASM_PFX(ArmDataMemoryBarrier):
|
||||
mov R0, #0
|
||||
mcr P15, #0, R0, C7, C10, #5 ; Check to see if this is correct
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmDataSyncronizationBarrier):
|
||||
mov R0, #0
|
||||
mcr P15, #0, R0, C7, C10, #4 ; Check to see if this is correct
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmInstructionSynchronizationBarrier):
|
||||
MOV R0, #0
|
||||
MCR P15, #0, R0, C7, C5, #4 ; Check to see if this is correct
|
||||
bx LR
|
||||
|
||||
END
|
||||
|
||||
@@ -1,275 +1,275 @@
|
||||
/** @file
|
||||
*
|
||||
* Copyright (c) 2011, ARM Limited. All rights reserved.
|
||||
*
|
||||
* This program and the accompanying materials
|
||||
* are licensed and made available under the terms and conditions of the BSD License
|
||||
* which accompanies this distribution. The full text of the license may be found at
|
||||
* http://opensource.org/licenses/bsd-license.php
|
||||
*
|
||||
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
*
|
||||
**/
|
||||
|
||||
#include <Uefi.h>
|
||||
#include <Chipset/ArmV7.h>
|
||||
#include <Library/BaseMemoryLib.h>
|
||||
#include <Library/MemoryAllocationLib.h>
|
||||
#include <Library/ArmLib.h>
|
||||
#include <Library/BaseLib.h>
|
||||
#include <Library/DebugLib.h>
|
||||
#include "ArmV7Lib.h"
|
||||
#include "ArmLibPrivate.h"
|
||||
#include <Library/ArmV7ArchTimerLib.h>
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmArchTimerReadReg (
|
||||
IN ARM_ARCH_TIMER_REGS Reg,
|
||||
OUT VOID *DstBuf
|
||||
)
|
||||
{
|
||||
// Check if the Generic/Architecture timer is implemented
|
||||
if (ArmIsArchTimerImplemented ()) {
|
||||
|
||||
switch (Reg) {
|
||||
|
||||
case CntFrq:
|
||||
*((UINTN *)DstBuf) = ArmReadCntFrq ();
|
||||
break;
|
||||
|
||||
case CntPct:
|
||||
*((UINT64 *)DstBuf) = ArmReadCntPct ();
|
||||
break;
|
||||
|
||||
case CntkCtl:
|
||||
*((UINTN *)DstBuf) = ArmReadCntkCtl();
|
||||
break;
|
||||
|
||||
case CntpTval:
|
||||
*((UINTN *)DstBuf) = ArmReadCntpTval ();
|
||||
break;
|
||||
|
||||
case CntpCtl:
|
||||
*((UINTN *)DstBuf) = ArmReadCntpCtl ();
|
||||
break;
|
||||
|
||||
case CntvTval:
|
||||
*((UINTN *)DstBuf) = ArmReadCntvTval ();
|
||||
break;
|
||||
|
||||
case CntvCtl:
|
||||
*((UINTN *)DstBuf) = ArmReadCntvCtl ();
|
||||
break;
|
||||
|
||||
case CntvCt:
|
||||
*((UINT64 *)DstBuf) = ArmReadCntvCt ();
|
||||
break;
|
||||
|
||||
case CntpCval:
|
||||
*((UINT64 *)DstBuf) = ArmReadCntpCval ();
|
||||
break;
|
||||
|
||||
case CntvCval:
|
||||
*((UINT64 *)DstBuf) = ArmReadCntvCval ();
|
||||
break;
|
||||
|
||||
case CntvOff:
|
||||
*((UINT64 *)DstBuf) = ArmReadCntvOff ();
|
||||
break;
|
||||
|
||||
case CnthCtl:
|
||||
case CnthpTval:
|
||||
case CnthpCtl:
|
||||
case CnthpCval:
|
||||
DEBUG ((EFI_D_ERROR, "The register is related to Hypervisor Mode. Can't perform requested operation\n "));
|
||||
break;
|
||||
|
||||
default:
|
||||
DEBUG ((EFI_D_ERROR, "Unknown ARM Generic Timer register %x. \n ", Reg));
|
||||
}
|
||||
} else {
|
||||
DEBUG ((EFI_D_ERROR, "Attempt to read ARM Generic Timer registers. But ARM Generic Timer extension is not implemented \n "));
|
||||
ASSERT (0);
|
||||
}
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmArchTimerWriteReg (
|
||||
IN ARM_ARCH_TIMER_REGS Reg,
|
||||
IN VOID *SrcBuf
|
||||
)
|
||||
{
|
||||
// Check if the Generic/Architecture timer is implemented
|
||||
if (ArmIsArchTimerImplemented ()) {
|
||||
|
||||
switch (Reg) {
|
||||
|
||||
case CntFrq:
|
||||
ArmWriteCntFrq (*((UINTN *)SrcBuf));
|
||||
break;
|
||||
|
||||
case CntPct:
|
||||
DEBUG ((EFI_D_ERROR, "Can't write to Read Only Register: CNTPCT \n"));
|
||||
break;
|
||||
|
||||
case CntkCtl:
|
||||
ArmWriteCntkCtl (*((UINTN *)SrcBuf));
|
||||
break;
|
||||
|
||||
case CntpTval:
|
||||
ArmWriteCntpTval (*((UINTN *)SrcBuf));
|
||||
break;
|
||||
|
||||
case CntpCtl:
|
||||
ArmWriteCntpCtl (*((UINTN *)SrcBuf));
|
||||
break;
|
||||
|
||||
case CntvTval:
|
||||
ArmWriteCntvTval (*((UINTN *)SrcBuf));
|
||||
break;
|
||||
|
||||
case CntvCtl:
|
||||
ArmWriteCntvCtl (*((UINTN *)SrcBuf));
|
||||
break;
|
||||
|
||||
case CntvCt:
|
||||
DEBUG ((EFI_D_ERROR, "Can't write to Read Only Register: CNTVCT \n"));
|
||||
break;
|
||||
|
||||
case CntpCval:
|
||||
ArmWriteCntpCval (*((UINT64 *)SrcBuf) );
|
||||
break;
|
||||
|
||||
case CntvCval:
|
||||
ArmWriteCntvCval (*((UINT64 *)SrcBuf) );
|
||||
break;
|
||||
|
||||
case CntvOff:
|
||||
ArmWriteCntvOff (*((UINT64 *)SrcBuf));
|
||||
break;
|
||||
|
||||
case CnthCtl:
|
||||
case CnthpTval:
|
||||
case CnthpCtl:
|
||||
case CnthpCval:
|
||||
DEBUG ((EFI_D_ERROR, "The register is related to Hypervisor Mode. Can't perform requested operation\n "));
|
||||
break;
|
||||
|
||||
default:
|
||||
DEBUG ((EFI_D_ERROR, "Unknown ARM Generic Timer register %x. \n ", Reg));
|
||||
}
|
||||
} else {
|
||||
DEBUG ((EFI_D_ERROR, "Attempt to write to ARM Generic Timer registers. But ARM Generic Timer extension is not implemented \n "));
|
||||
ASSERT (0);
|
||||
}
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmArchTimerEnableTimer (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINTN TimerCtrlReg;
|
||||
|
||||
ArmArchTimerReadReg (CntpCtl, (VOID *)&TimerCtrlReg);
|
||||
TimerCtrlReg |= ARM_ARCH_TIMER_ENABLE;
|
||||
ArmArchTimerWriteReg (CntpCtl, (VOID *)&TimerCtrlReg);
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmArchTimerDisableTimer (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINTN TimerCtrlReg;
|
||||
|
||||
ArmArchTimerReadReg (CntpCtl, (VOID *)&TimerCtrlReg);
|
||||
TimerCtrlReg &= ~ARM_ARCH_TIMER_ENABLE;
|
||||
ArmArchTimerWriteReg (CntpCtl, (VOID *)&TimerCtrlReg);
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmArchTimerSetTimerFreq (
|
||||
IN UINTN FreqInHz
|
||||
)
|
||||
{
|
||||
ArmArchTimerWriteReg (CntFrq, (VOID *)&FreqInHz);
|
||||
}
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmArchTimerGetTimerFreq (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINTN ArchTimerFreq = 0;
|
||||
ArmArchTimerReadReg (CntFrq, (VOID *)&ArchTimerFreq);
|
||||
return ArchTimerFreq;
|
||||
}
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmArchTimerGetTimerVal (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINTN ArchTimerVal;
|
||||
ArmArchTimerReadReg (CntpTval, (VOID *)&ArchTimerVal);
|
||||
return ArchTimerVal;
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmArchTimerSetTimerVal (
|
||||
IN UINTN Val
|
||||
)
|
||||
{
|
||||
ArmArchTimerWriteReg (CntpTval, (VOID *)&Val);
|
||||
}
|
||||
|
||||
UINT64
|
||||
EFIAPI
|
||||
ArmArchTimerGetSystemCount (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINT64 SystemCount;
|
||||
ArmArchTimerReadReg (CntPct, (VOID *)&SystemCount);
|
||||
return SystemCount;
|
||||
}
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmArchTimerGetTimerCtrlReg (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINTN Val;
|
||||
ArmArchTimerReadReg (CntpCtl, (VOID *)&Val);
|
||||
return Val;
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmArchTimerSetTimerCtrlReg (
|
||||
UINTN Val
|
||||
)
|
||||
{
|
||||
ArmArchTimerWriteReg (CntpCtl, (VOID *)&Val);
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmArchTimerSetCompareVal (
|
||||
IN UINT64 Val
|
||||
)
|
||||
{
|
||||
ArmArchTimerWriteReg (CntpCval, (VOID *)&Val);
|
||||
}
|
||||
/** @file
|
||||
*
|
||||
* Copyright (c) 2011, ARM Limited. All rights reserved.
|
||||
*
|
||||
* This program and the accompanying materials
|
||||
* are licensed and made available under the terms and conditions of the BSD License
|
||||
* which accompanies this distribution. The full text of the license may be found at
|
||||
* http://opensource.org/licenses/bsd-license.php
|
||||
*
|
||||
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
*
|
||||
**/
|
||||
|
||||
#include <Uefi.h>
|
||||
#include <Chipset/ArmV7.h>
|
||||
#include <Library/BaseMemoryLib.h>
|
||||
#include <Library/MemoryAllocationLib.h>
|
||||
#include <Library/ArmLib.h>
|
||||
#include <Library/BaseLib.h>
|
||||
#include <Library/DebugLib.h>
|
||||
#include "ArmV7Lib.h"
|
||||
#include "ArmLibPrivate.h"
|
||||
#include <Library/ArmV7ArchTimerLib.h>
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmArchTimerReadReg (
|
||||
IN ARM_ARCH_TIMER_REGS Reg,
|
||||
OUT VOID *DstBuf
|
||||
)
|
||||
{
|
||||
// Check if the Generic/Architecture timer is implemented
|
||||
if (ArmIsArchTimerImplemented ()) {
|
||||
|
||||
switch (Reg) {
|
||||
|
||||
case CntFrq:
|
||||
*((UINTN *)DstBuf) = ArmReadCntFrq ();
|
||||
break;
|
||||
|
||||
case CntPct:
|
||||
*((UINT64 *)DstBuf) = ArmReadCntPct ();
|
||||
break;
|
||||
|
||||
case CntkCtl:
|
||||
*((UINTN *)DstBuf) = ArmReadCntkCtl();
|
||||
break;
|
||||
|
||||
case CntpTval:
|
||||
*((UINTN *)DstBuf) = ArmReadCntpTval ();
|
||||
break;
|
||||
|
||||
case CntpCtl:
|
||||
*((UINTN *)DstBuf) = ArmReadCntpCtl ();
|
||||
break;
|
||||
|
||||
case CntvTval:
|
||||
*((UINTN *)DstBuf) = ArmReadCntvTval ();
|
||||
break;
|
||||
|
||||
case CntvCtl:
|
||||
*((UINTN *)DstBuf) = ArmReadCntvCtl ();
|
||||
break;
|
||||
|
||||
case CntvCt:
|
||||
*((UINT64 *)DstBuf) = ArmReadCntvCt ();
|
||||
break;
|
||||
|
||||
case CntpCval:
|
||||
*((UINT64 *)DstBuf) = ArmReadCntpCval ();
|
||||
break;
|
||||
|
||||
case CntvCval:
|
||||
*((UINT64 *)DstBuf) = ArmReadCntvCval ();
|
||||
break;
|
||||
|
||||
case CntvOff:
|
||||
*((UINT64 *)DstBuf) = ArmReadCntvOff ();
|
||||
break;
|
||||
|
||||
case CnthCtl:
|
||||
case CnthpTval:
|
||||
case CnthpCtl:
|
||||
case CnthpCval:
|
||||
DEBUG ((EFI_D_ERROR, "The register is related to Hypervisor Mode. Can't perform requested operation\n "));
|
||||
break;
|
||||
|
||||
default:
|
||||
DEBUG ((EFI_D_ERROR, "Unknown ARM Generic Timer register %x. \n ", Reg));
|
||||
}
|
||||
} else {
|
||||
DEBUG ((EFI_D_ERROR, "Attempt to read ARM Generic Timer registers. But ARM Generic Timer extension is not implemented \n "));
|
||||
ASSERT (0);
|
||||
}
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmArchTimerWriteReg (
|
||||
IN ARM_ARCH_TIMER_REGS Reg,
|
||||
IN VOID *SrcBuf
|
||||
)
|
||||
{
|
||||
// Check if the Generic/Architecture timer is implemented
|
||||
if (ArmIsArchTimerImplemented ()) {
|
||||
|
||||
switch (Reg) {
|
||||
|
||||
case CntFrq:
|
||||
ArmWriteCntFrq (*((UINTN *)SrcBuf));
|
||||
break;
|
||||
|
||||
case CntPct:
|
||||
DEBUG ((EFI_D_ERROR, "Can't write to Read Only Register: CNTPCT \n"));
|
||||
break;
|
||||
|
||||
case CntkCtl:
|
||||
ArmWriteCntkCtl (*((UINTN *)SrcBuf));
|
||||
break;
|
||||
|
||||
case CntpTval:
|
||||
ArmWriteCntpTval (*((UINTN *)SrcBuf));
|
||||
break;
|
||||
|
||||
case CntpCtl:
|
||||
ArmWriteCntpCtl (*((UINTN *)SrcBuf));
|
||||
break;
|
||||
|
||||
case CntvTval:
|
||||
ArmWriteCntvTval (*((UINTN *)SrcBuf));
|
||||
break;
|
||||
|
||||
case CntvCtl:
|
||||
ArmWriteCntvCtl (*((UINTN *)SrcBuf));
|
||||
break;
|
||||
|
||||
case CntvCt:
|
||||
DEBUG ((EFI_D_ERROR, "Can't write to Read Only Register: CNTVCT \n"));
|
||||
break;
|
||||
|
||||
case CntpCval:
|
||||
ArmWriteCntpCval (*((UINT64 *)SrcBuf) );
|
||||
break;
|
||||
|
||||
case CntvCval:
|
||||
ArmWriteCntvCval (*((UINT64 *)SrcBuf) );
|
||||
break;
|
||||
|
||||
case CntvOff:
|
||||
ArmWriteCntvOff (*((UINT64 *)SrcBuf));
|
||||
break;
|
||||
|
||||
case CnthCtl:
|
||||
case CnthpTval:
|
||||
case CnthpCtl:
|
||||
case CnthpCval:
|
||||
DEBUG ((EFI_D_ERROR, "The register is related to Hypervisor Mode. Can't perform requested operation\n "));
|
||||
break;
|
||||
|
||||
default:
|
||||
DEBUG ((EFI_D_ERROR, "Unknown ARM Generic Timer register %x. \n ", Reg));
|
||||
}
|
||||
} else {
|
||||
DEBUG ((EFI_D_ERROR, "Attempt to write to ARM Generic Timer registers. But ARM Generic Timer extension is not implemented \n "));
|
||||
ASSERT (0);
|
||||
}
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmArchTimerEnableTimer (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINTN TimerCtrlReg;
|
||||
|
||||
ArmArchTimerReadReg (CntpCtl, (VOID *)&TimerCtrlReg);
|
||||
TimerCtrlReg |= ARM_ARCH_TIMER_ENABLE;
|
||||
ArmArchTimerWriteReg (CntpCtl, (VOID *)&TimerCtrlReg);
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmArchTimerDisableTimer (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINTN TimerCtrlReg;
|
||||
|
||||
ArmArchTimerReadReg (CntpCtl, (VOID *)&TimerCtrlReg);
|
||||
TimerCtrlReg &= ~ARM_ARCH_TIMER_ENABLE;
|
||||
ArmArchTimerWriteReg (CntpCtl, (VOID *)&TimerCtrlReg);
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmArchTimerSetTimerFreq (
|
||||
IN UINTN FreqInHz
|
||||
)
|
||||
{
|
||||
ArmArchTimerWriteReg (CntFrq, (VOID *)&FreqInHz);
|
||||
}
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmArchTimerGetTimerFreq (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINTN ArchTimerFreq = 0;
|
||||
ArmArchTimerReadReg (CntFrq, (VOID *)&ArchTimerFreq);
|
||||
return ArchTimerFreq;
|
||||
}
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmArchTimerGetTimerVal (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINTN ArchTimerVal;
|
||||
ArmArchTimerReadReg (CntpTval, (VOID *)&ArchTimerVal);
|
||||
return ArchTimerVal;
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmArchTimerSetTimerVal (
|
||||
IN UINTN Val
|
||||
)
|
||||
{
|
||||
ArmArchTimerWriteReg (CntpTval, (VOID *)&Val);
|
||||
}
|
||||
|
||||
UINT64
|
||||
EFIAPI
|
||||
ArmArchTimerGetSystemCount (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINT64 SystemCount;
|
||||
ArmArchTimerReadReg (CntPct, (VOID *)&SystemCount);
|
||||
return SystemCount;
|
||||
}
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmArchTimerGetTimerCtrlReg (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINTN Val;
|
||||
ArmArchTimerReadReg (CntpCtl, (VOID *)&Val);
|
||||
return Val;
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmArchTimerSetTimerCtrlReg (
|
||||
UINTN Val
|
||||
)
|
||||
{
|
||||
ArmArchTimerWriteReg (CntpCtl, (VOID *)&Val);
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmArchTimerSetCompareVal (
|
||||
IN UINT64 Val
|
||||
)
|
||||
{
|
||||
ArmArchTimerWriteReg (CntpCval, (VOID *)&Val);
|
||||
}
|
||||
|
||||
@@ -1,264 +1,264 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
||||
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
#include <Uefi.h>
|
||||
#include <Chipset/ArmV7.h>
|
||||
#include <Library/ArmLib.h>
|
||||
#include <Library/BaseLib.h>
|
||||
#include <Library/IoLib.h>
|
||||
#include "ArmV7Lib.h"
|
||||
#include "ArmLibPrivate.h"
|
||||
|
||||
ARM_CACHE_TYPE
|
||||
EFIAPI
|
||||
ArmCacheType (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
return ARM_CACHE_TYPE_WRITE_BACK;
|
||||
}
|
||||
|
||||
ARM_CACHE_ARCHITECTURE
|
||||
EFIAPI
|
||||
ArmCacheArchitecture (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINT32 CLIDR = ReadCLIDR ();
|
||||
|
||||
return (ARM_CACHE_ARCHITECTURE)CLIDR; // BugBug Fix Me
|
||||
}
|
||||
|
||||
BOOLEAN
|
||||
EFIAPI
|
||||
ArmDataCachePresent (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINT32 CLIDR = ReadCLIDR ();
|
||||
|
||||
if ((CLIDR & 0x2) == 0x2) {
|
||||
// Instruction cache exists
|
||||
return TRUE;
|
||||
}
|
||||
if ((CLIDR & 0x7) == 0x4) {
|
||||
// Unified cache
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmDataCacheSize (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINT32 NumSets;
|
||||
UINT32 Associativity;
|
||||
UINT32 LineSize;
|
||||
UINT32 CCSIDR = ReadCCSIDR (0);
|
||||
|
||||
LineSize = (1 << ((CCSIDR & 0x7) + 2));
|
||||
Associativity = ((CCSIDR >> 3) & 0x3ff) + 1;
|
||||
NumSets = ((CCSIDR >> 13) & 0x7fff) + 1;
|
||||
|
||||
// LineSize is in words (4 byte chunks)
|
||||
return NumSets * Associativity * LineSize * 4;
|
||||
}
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmDataCacheAssociativity (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINT32 CCSIDR = ReadCCSIDR (0);
|
||||
|
||||
return ((CCSIDR >> 3) & 0x3ff) + 1;
|
||||
}
|
||||
|
||||
UINTN
|
||||
ArmDataCacheSets (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINT32 CCSIDR = ReadCCSIDR (0);
|
||||
|
||||
return ((CCSIDR >> 13) & 0x7fff) + 1;
|
||||
}
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmDataCacheLineLength (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINT32 CCSIDR = ReadCCSIDR (0) & 7;
|
||||
|
||||
// * 4 converts to bytes
|
||||
return (1 << (CCSIDR + 2)) * 4;
|
||||
}
|
||||
|
||||
BOOLEAN
|
||||
EFIAPI
|
||||
ArmInstructionCachePresent (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINT32 CLIDR = ReadCLIDR ();
|
||||
|
||||
if ((CLIDR & 1) == 1) {
|
||||
// Instruction cache exists
|
||||
return TRUE;
|
||||
}
|
||||
if ((CLIDR & 0x7) == 0x4) {
|
||||
// Unified cache
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmInstructionCacheSize (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINT32 NumSets;
|
||||
UINT32 Associativity;
|
||||
UINT32 LineSize;
|
||||
UINT32 CCSIDR = ReadCCSIDR (1);
|
||||
|
||||
LineSize = (1 << ((CCSIDR & 0x7) + 2));
|
||||
Associativity = ((CCSIDR >> 3) & 0x3ff) + 1;
|
||||
NumSets = ((CCSIDR >> 13) & 0x7fff) + 1;
|
||||
|
||||
// LineSize is in words (4 byte chunks)
|
||||
return NumSets * Associativity * LineSize * 4;
|
||||
}
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmInstructionCacheAssociativity (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINT32 CCSIDR = ReadCCSIDR (1);
|
||||
|
||||
return ((CCSIDR >> 3) & 0x3ff) + 1;
|
||||
// return 4;
|
||||
}
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmInstructionCacheSets (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINT32 CCSIDR = ReadCCSIDR (1);
|
||||
|
||||
return ((CCSIDR >> 13) & 0x7fff) + 1;
|
||||
}
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmInstructionCacheLineLength (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINT32 CCSIDR = ReadCCSIDR (1) & 7;
|
||||
|
||||
// * 4 converts to bytes
|
||||
return (1 << (CCSIDR + 2)) * 4;
|
||||
|
||||
// return 64;
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
ArmV7DataCacheOperation (
|
||||
IN ARM_V7_CACHE_OPERATION DataCacheOperation
|
||||
)
|
||||
{
|
||||
UINTN SavedInterruptState;
|
||||
|
||||
SavedInterruptState = ArmGetInterruptState ();
|
||||
ArmDisableInterrupts ();
|
||||
|
||||
ArmV7AllDataCachesOperation (DataCacheOperation);
|
||||
|
||||
ArmDrainWriteBuffer ();
|
||||
|
||||
if (SavedInterruptState) {
|
||||
ArmEnableInterrupts ();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
ArmV7PoUDataCacheOperation (
|
||||
IN ARM_V7_CACHE_OPERATION DataCacheOperation
|
||||
)
|
||||
{
|
||||
UINTN SavedInterruptState;
|
||||
|
||||
SavedInterruptState = ArmGetInterruptState ();
|
||||
ArmDisableInterrupts ();
|
||||
|
||||
ArmV7PerformPoUDataCacheOperation (DataCacheOperation);
|
||||
|
||||
ArmDrainWriteBuffer ();
|
||||
|
||||
if (SavedInterruptState) {
|
||||
ArmEnableInterrupts ();
|
||||
}
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmInvalidateDataCache (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
ArmV7DataCacheOperation (ArmInvalidateDataCacheEntryBySetWay);
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmCleanInvalidateDataCache (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
ArmV7DataCacheOperation (ArmCleanInvalidateDataCacheEntryBySetWay);
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmCleanDataCache (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
ArmV7DataCacheOperation (ArmCleanDataCacheEntryBySetWay);
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmCleanDataCacheToPoU (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
ArmV7PoUDataCacheOperation (ArmCleanDataCacheEntryBySetWay);
|
||||
}
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
||||
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
#include <Uefi.h>
|
||||
#include <Chipset/ArmV7.h>
|
||||
#include <Library/ArmLib.h>
|
||||
#include <Library/BaseLib.h>
|
||||
#include <Library/IoLib.h>
|
||||
#include "ArmV7Lib.h"
|
||||
#include "ArmLibPrivate.h"
|
||||
|
||||
ARM_CACHE_TYPE
|
||||
EFIAPI
|
||||
ArmCacheType (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
return ARM_CACHE_TYPE_WRITE_BACK;
|
||||
}
|
||||
|
||||
ARM_CACHE_ARCHITECTURE
|
||||
EFIAPI
|
||||
ArmCacheArchitecture (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINT32 CLIDR = ReadCLIDR ();
|
||||
|
||||
return (ARM_CACHE_ARCHITECTURE)CLIDR; // BugBug Fix Me
|
||||
}
|
||||
|
||||
BOOLEAN
|
||||
EFIAPI
|
||||
ArmDataCachePresent (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINT32 CLIDR = ReadCLIDR ();
|
||||
|
||||
if ((CLIDR & 0x2) == 0x2) {
|
||||
// Instruction cache exists
|
||||
return TRUE;
|
||||
}
|
||||
if ((CLIDR & 0x7) == 0x4) {
|
||||
// Unified cache
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmDataCacheSize (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINT32 NumSets;
|
||||
UINT32 Associativity;
|
||||
UINT32 LineSize;
|
||||
UINT32 CCSIDR = ReadCCSIDR (0);
|
||||
|
||||
LineSize = (1 << ((CCSIDR & 0x7) + 2));
|
||||
Associativity = ((CCSIDR >> 3) & 0x3ff) + 1;
|
||||
NumSets = ((CCSIDR >> 13) & 0x7fff) + 1;
|
||||
|
||||
// LineSize is in words (4 byte chunks)
|
||||
return NumSets * Associativity * LineSize * 4;
|
||||
}
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmDataCacheAssociativity (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINT32 CCSIDR = ReadCCSIDR (0);
|
||||
|
||||
return ((CCSIDR >> 3) & 0x3ff) + 1;
|
||||
}
|
||||
|
||||
UINTN
|
||||
ArmDataCacheSets (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINT32 CCSIDR = ReadCCSIDR (0);
|
||||
|
||||
return ((CCSIDR >> 13) & 0x7fff) + 1;
|
||||
}
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmDataCacheLineLength (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINT32 CCSIDR = ReadCCSIDR (0) & 7;
|
||||
|
||||
// * 4 converts to bytes
|
||||
return (1 << (CCSIDR + 2)) * 4;
|
||||
}
|
||||
|
||||
BOOLEAN
|
||||
EFIAPI
|
||||
ArmInstructionCachePresent (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINT32 CLIDR = ReadCLIDR ();
|
||||
|
||||
if ((CLIDR & 1) == 1) {
|
||||
// Instruction cache exists
|
||||
return TRUE;
|
||||
}
|
||||
if ((CLIDR & 0x7) == 0x4) {
|
||||
// Unified cache
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmInstructionCacheSize (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINT32 NumSets;
|
||||
UINT32 Associativity;
|
||||
UINT32 LineSize;
|
||||
UINT32 CCSIDR = ReadCCSIDR (1);
|
||||
|
||||
LineSize = (1 << ((CCSIDR & 0x7) + 2));
|
||||
Associativity = ((CCSIDR >> 3) & 0x3ff) + 1;
|
||||
NumSets = ((CCSIDR >> 13) & 0x7fff) + 1;
|
||||
|
||||
// LineSize is in words (4 byte chunks)
|
||||
return NumSets * Associativity * LineSize * 4;
|
||||
}
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmInstructionCacheAssociativity (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINT32 CCSIDR = ReadCCSIDR (1);
|
||||
|
||||
return ((CCSIDR >> 3) & 0x3ff) + 1;
|
||||
// return 4;
|
||||
}
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmInstructionCacheSets (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINT32 CCSIDR = ReadCCSIDR (1);
|
||||
|
||||
return ((CCSIDR >> 13) & 0x7fff) + 1;
|
||||
}
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmInstructionCacheLineLength (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINT32 CCSIDR = ReadCCSIDR (1) & 7;
|
||||
|
||||
// * 4 converts to bytes
|
||||
return (1 << (CCSIDR + 2)) * 4;
|
||||
|
||||
// return 64;
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
ArmV7DataCacheOperation (
|
||||
IN ARM_V7_CACHE_OPERATION DataCacheOperation
|
||||
)
|
||||
{
|
||||
UINTN SavedInterruptState;
|
||||
|
||||
SavedInterruptState = ArmGetInterruptState ();
|
||||
ArmDisableInterrupts ();
|
||||
|
||||
ArmV7AllDataCachesOperation (DataCacheOperation);
|
||||
|
||||
ArmDrainWriteBuffer ();
|
||||
|
||||
if (SavedInterruptState) {
|
||||
ArmEnableInterrupts ();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
ArmV7PoUDataCacheOperation (
|
||||
IN ARM_V7_CACHE_OPERATION DataCacheOperation
|
||||
)
|
||||
{
|
||||
UINTN SavedInterruptState;
|
||||
|
||||
SavedInterruptState = ArmGetInterruptState ();
|
||||
ArmDisableInterrupts ();
|
||||
|
||||
ArmV7PerformPoUDataCacheOperation (DataCacheOperation);
|
||||
|
||||
ArmDrainWriteBuffer ();
|
||||
|
||||
if (SavedInterruptState) {
|
||||
ArmEnableInterrupts ();
|
||||
}
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmInvalidateDataCache (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
ArmV7DataCacheOperation (ArmInvalidateDataCacheEntryBySetWay);
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmCleanInvalidateDataCache (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
ArmV7DataCacheOperation (ArmCleanInvalidateDataCacheEntryBySetWay);
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmCleanDataCache (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
ArmV7DataCacheOperation (ArmCleanDataCacheEntryBySetWay);
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmCleanDataCacheToPoU (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
ArmV7PoUDataCacheOperation (ArmCleanDataCacheEntryBySetWay);
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user