ARM Packages: Fixed line endings
This large code change only modifies the line endings to be CRLF to be compliant with the EDK2 coding convention document. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14088 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin
@@ -1,262 +1,262 @@
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#------------------------------------------------------------------------------
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#
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# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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# Copyright (c) 2011, ARM Limited. All rights reserved.
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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#------------------------------------------------------------------------------
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#include <AsmMacroIoLib.h>
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.text
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.align 2
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GCC_ASM_EXPORT(ArmDisableCachesAndMmu)
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GCC_ASM_EXPORT(ArmInvalidateInstructionAndDataTlb)
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GCC_ASM_EXPORT(ArmCleanInvalidateDataCache)
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GCC_ASM_EXPORT(ArmCleanDataCache)
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GCC_ASM_EXPORT(ArmInvalidateDataCache)
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GCC_ASM_EXPORT(ArmInvalidateInstructionCache)
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GCC_ASM_EXPORT(ArmInvalidateDataCacheEntryByMVA)
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GCC_ASM_EXPORT(ArmCleanDataCacheEntryByMVA)
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GCC_ASM_EXPORT(ArmCleanInvalidateDataCacheEntryByMVA)
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GCC_ASM_EXPORT(ArmEnableMmu)
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GCC_ASM_EXPORT(ArmDisableMmu)
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GCC_ASM_EXPORT(ArmMmuEnabled)
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GCC_ASM_EXPORT(ArmEnableDataCache)
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GCC_ASM_EXPORT(ArmDisableDataCache)
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GCC_ASM_EXPORT(ArmEnableInstructionCache)
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GCC_ASM_EXPORT(ArmDisableInstructionCache)
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GCC_ASM_EXPORT(ArmEnableBranchPrediction)
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GCC_ASM_EXPORT(ArmDisableBranchPrediction)
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GCC_ASM_EXPORT(ArmDataMemoryBarrier)
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GCC_ASM_EXPORT(ArmDataSyncronizationBarrier)
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GCC_ASM_EXPORT(ArmInstructionSynchronizationBarrier)
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GCC_ASM_EXPORT(ArmSetLowVectors)
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GCC_ASM_EXPORT(ArmSetHighVectors)
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GCC_ASM_EXPORT(ArmIsMpCore)
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GCC_ASM_EXPORT(ArmCallWFI)
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GCC_ASM_EXPORT(ArmReadMpidr)
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GCC_ASM_EXPORT(ArmUpdateTranslationTableEntry)
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GCC_ASM_EXPORT(ArmEnableFiq)
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GCC_ASM_EXPORT(ArmDisableFiq)
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GCC_ASM_EXPORT(ArmEnableInterrupts)
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GCC_ASM_EXPORT(ArmDisableInterrupts)
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GCC_ASM_EXPORT (ArmEnableVFP)
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Arm11PartNumberMask: .word 0xFFF0
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Arm11PartNumber: .word 0xB020
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.set DC_ON, (0x1<<2)
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.set IC_ON, (0x1<<12)
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.set XP_ON, (0x1<<23)
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.set CTRL_M_BIT, (1 << 0)
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.set CTRL_C_BIT, (1 << 2)
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.set CTRL_I_BIT, (1 << 12)
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ASM_PFX(ArmDisableCachesAndMmu):
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mrc p15, 0, r0, c1, c0, 0 @ Get control register
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bic r0, r0, #CTRL_M_BIT @ Disable MMU
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bic r0, r0, #CTRL_C_BIT @ Disable D Cache
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bic r0, r0, #CTRL_I_BIT @ Disable I Cache
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mcr p15, 0, r0, c1, c0, 0 @ Write control register
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bx LR
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ASM_PFX(ArmInvalidateInstructionAndDataTlb):
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mcr p15, 0, r0, c8, c7, 0 @ Invalidate Inst TLB and Data TLB
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bx lr
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ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
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mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line
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bx lr
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ASM_PFX(ArmCleanDataCacheEntryByMVA):
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mcr p15, 0, r0, c7, c10, 1 @clean single data cache line
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bx lr
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ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
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mcr p15, 0, r0, c7, c14, 1 @clean and invalidate single data cache line
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bx lr
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ASM_PFX(ArmCleanDataCache):
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mcr p15, 0, r0, c7, c10, 0 @ clean entire data cache
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bx lr
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ASM_PFX(ArmCleanInvalidateDataCache):
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mcr p15, 0, r0, c7, c14, 0 @ clean and invalidate entire data cache
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bx lr
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ASM_PFX(ArmInvalidateDataCache):
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mcr p15, 0, r0, c7, c6, 0 @ invalidate entire data cache
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bx lr
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ASM_PFX(ArmInvalidateInstructionCache):
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mcr p15, 0, r0, c7, c5, 0 @invalidate entire instruction cache
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mov R0,#0
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mcr p15,0,R0,c7,c5,4 @Flush Prefetch buffer
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bx lr
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ASM_PFX(ArmEnableMmu):
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mrc p15,0,R0,c1,c0,0
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orr R0,R0,#1
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mcr p15,0,R0,c1,c0,0
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bx LR
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ASM_PFX(ArmMmuEnabled):
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mrc p15,0,R0,c1,c0,0
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and R0,R0,#1
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bx LR
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ASM_PFX(ArmDisableMmu):
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mrc p15,0,R0,c1,c0,0
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bic R0,R0,#1
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mcr p15,0,R0,c1,c0,0
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mov R0,#0
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mcr p15,0,R0,c7,c10,4 @Data synchronization barrier
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mov R0,#0
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mcr p15,0,R0,c7,c5,4 @Flush Prefetch buffer
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bx LR
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ASM_PFX(ArmEnableDataCache):
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LoadConstantToReg(DC_ON, R1) @ldr R1,=DC_ON
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mrc p15,0,R0,c1,c0,0 @Read control register configuration data
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orr R0,R0,R1 @Set C bit
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mcr p15,0,r0,c1,c0,0 @Write control register configuration data
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bx LR
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ASM_PFX(ArmDisableDataCache):
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LoadConstantToReg(DC_ON, R1) @ldr R1,=DC_ON
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mrc p15,0,R0,c1,c0,0 @Read control register configuration data
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bic R0,R0,R1 @Clear C bit
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mcr p15,0,r0,c1,c0,0 @Write control register configuration data
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bx LR
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ASM_PFX(ArmEnableInstructionCache):
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ldr R1,=IC_ON
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mrc p15,0,R0,c1,c0,0 @Read control register configuration data
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orr R0,R0,R1 @Set I bit
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mcr p15,0,r0,c1,c0,0 @Write control register configuration data
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bx LR
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ASM_PFX(ArmDisableInstructionCache):
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ldr R1,=IC_ON
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mrc p15,0,R0,c1,c0,0 @Read control register configuration data
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bic R0,R0,R1 @Clear I bit.
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mcr p15,0,r0,c1,c0,0 @Write control register configuration data
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bx LR
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ASM_PFX(ArmEnableBranchPrediction):
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mrc p15, 0, r0, c1, c0, 0
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orr r0, r0, #0x00000800
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mcr p15, 0, r0, c1, c0, 0
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bx LR
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ASM_PFX(ArmDisableBranchPrediction):
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #0x00000800
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mcr p15, 0, r0, c1, c0, 0
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bx LR
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ASM_PFX(ArmDataMemoryBarrier):
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mov R0, #0
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mcr P15, #0, R0, C7, C10, #5
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bx LR
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ASM_PFX(ArmDataSyncronizationBarrier):
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mov R0, #0
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mcr P15, #0, R0, C7, C10, #4
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bx LR
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ASM_PFX(ArmInstructionSynchronizationBarrier):
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mov R0, #0
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mcr P15, #0, R0, C7, C5, #4
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bx LR
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ASM_PFX(ArmSetLowVectors):
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mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
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bic r0, r0, #0x00002000 @ clear V bit
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mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
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bx LR
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ASM_PFX(ArmSetHighVectors):
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mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
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orr r0, r0, #0x00002000 @ clear V bit
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mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
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bx LR
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ASM_PFX(ArmIsMpCore):
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push { r1 }
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mrc p15, 0, r0, c0, c0, 0
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# Extract Part Number to check it is an ARM11MP core (0xB02)
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LoadConstantToReg (Arm11PartNumberMask, r1)
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and r0, r0, r1
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LoadConstantToReg (Arm11PartNumber, r1)
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cmp r0, r1
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movne r0, #0
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pop { r1 }
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bx lr
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ASM_PFX(ArmCallWFI):
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wfi
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bx lr
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ASM_PFX(ArmReadMpidr):
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mrc p15, 0, r0, c0, c0, 5 @ read MPIDR
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bx lr
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ASM_PFX(ArmEnableFiq):
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mrs R0,CPSR
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bic R0,R0,#0x40 @Enable FIQ interrupts
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msr CPSR_c,R0
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bx LR
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ASM_PFX(ArmDisableFiq):
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mrs R0,CPSR
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orr R1,R0,#0x40 @Disable FIQ interrupts
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msr CPSR_c,R1
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tst R0,#0x80
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moveq R0,#1
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movne R0,#0
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bx LR
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ASM_PFX(ArmEnableInterrupts):
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mrs R0,CPSR
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bic R0,R0,#0x80 @Enable IRQ interrupts
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msr CPSR_c,R0
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bx LR
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ASM_PFX(ArmDisableInterrupts):
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mrs R0,CPSR
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orr R1,R0,#0x80 @Disable IRQ interrupts
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msr CPSR_c,R1
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tst R0,#0x80
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moveq R0,#1
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movne R0,#0
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bx LR
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ASM_PFX(ArmEnableVFP):
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# Read CPACR (Coprocessor Access Control Register)
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mrc p15, 0, r0, c1, c0, 2
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# Enable VPF access (Full Access to CP10, CP11) (V* instructions)
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orr r0, r0, #0x00f00000
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# Write back CPACR (Coprocessor Access Control Register)
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mcr p15, 0, r0, c1, c0, 2
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# Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
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mov r0, #0x40000000
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#TODO: Fixme - need compilation flag
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#fmxr FPEXC, r0
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bx lr
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ASM_FUNCTION_REMOVE_IF_UNREFERENCED
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#------------------------------------------------------------------------------
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#
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# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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# Copyright (c) 2011, ARM Limited. All rights reserved.
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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#------------------------------------------------------------------------------
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#include <AsmMacroIoLib.h>
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.text
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.align 2
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GCC_ASM_EXPORT(ArmDisableCachesAndMmu)
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GCC_ASM_EXPORT(ArmInvalidateInstructionAndDataTlb)
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GCC_ASM_EXPORT(ArmCleanInvalidateDataCache)
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GCC_ASM_EXPORT(ArmCleanDataCache)
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GCC_ASM_EXPORT(ArmInvalidateDataCache)
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GCC_ASM_EXPORT(ArmInvalidateInstructionCache)
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GCC_ASM_EXPORT(ArmInvalidateDataCacheEntryByMVA)
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GCC_ASM_EXPORT(ArmCleanDataCacheEntryByMVA)
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GCC_ASM_EXPORT(ArmCleanInvalidateDataCacheEntryByMVA)
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GCC_ASM_EXPORT(ArmEnableMmu)
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GCC_ASM_EXPORT(ArmDisableMmu)
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GCC_ASM_EXPORT(ArmMmuEnabled)
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GCC_ASM_EXPORT(ArmEnableDataCache)
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GCC_ASM_EXPORT(ArmDisableDataCache)
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GCC_ASM_EXPORT(ArmEnableInstructionCache)
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GCC_ASM_EXPORT(ArmDisableInstructionCache)
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GCC_ASM_EXPORT(ArmEnableBranchPrediction)
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GCC_ASM_EXPORT(ArmDisableBranchPrediction)
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GCC_ASM_EXPORT(ArmDataMemoryBarrier)
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GCC_ASM_EXPORT(ArmDataSyncronizationBarrier)
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GCC_ASM_EXPORT(ArmInstructionSynchronizationBarrier)
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GCC_ASM_EXPORT(ArmSetLowVectors)
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GCC_ASM_EXPORT(ArmSetHighVectors)
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GCC_ASM_EXPORT(ArmIsMpCore)
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GCC_ASM_EXPORT(ArmCallWFI)
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GCC_ASM_EXPORT(ArmReadMpidr)
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GCC_ASM_EXPORT(ArmUpdateTranslationTableEntry)
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GCC_ASM_EXPORT(ArmEnableFiq)
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GCC_ASM_EXPORT(ArmDisableFiq)
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GCC_ASM_EXPORT(ArmEnableInterrupts)
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GCC_ASM_EXPORT(ArmDisableInterrupts)
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GCC_ASM_EXPORT (ArmEnableVFP)
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Arm11PartNumberMask: .word 0xFFF0
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Arm11PartNumber: .word 0xB020
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.set DC_ON, (0x1<<2)
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.set IC_ON, (0x1<<12)
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.set XP_ON, (0x1<<23)
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.set CTRL_M_BIT, (1 << 0)
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.set CTRL_C_BIT, (1 << 2)
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.set CTRL_I_BIT, (1 << 12)
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ASM_PFX(ArmDisableCachesAndMmu):
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mrc p15, 0, r0, c1, c0, 0 @ Get control register
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bic r0, r0, #CTRL_M_BIT @ Disable MMU
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bic r0, r0, #CTRL_C_BIT @ Disable D Cache
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bic r0, r0, #CTRL_I_BIT @ Disable I Cache
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mcr p15, 0, r0, c1, c0, 0 @ Write control register
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bx LR
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ASM_PFX(ArmInvalidateInstructionAndDataTlb):
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mcr p15, 0, r0, c8, c7, 0 @ Invalidate Inst TLB and Data TLB
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bx lr
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ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
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mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line
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bx lr
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ASM_PFX(ArmCleanDataCacheEntryByMVA):
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mcr p15, 0, r0, c7, c10, 1 @clean single data cache line
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bx lr
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ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
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mcr p15, 0, r0, c7, c14, 1 @clean and invalidate single data cache line
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bx lr
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ASM_PFX(ArmCleanDataCache):
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mcr p15, 0, r0, c7, c10, 0 @ clean entire data cache
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bx lr
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ASM_PFX(ArmCleanInvalidateDataCache):
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mcr p15, 0, r0, c7, c14, 0 @ clean and invalidate entire data cache
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bx lr
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ASM_PFX(ArmInvalidateDataCache):
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mcr p15, 0, r0, c7, c6, 0 @ invalidate entire data cache
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bx lr
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ASM_PFX(ArmInvalidateInstructionCache):
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mcr p15, 0, r0, c7, c5, 0 @invalidate entire instruction cache
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mov R0,#0
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mcr p15,0,R0,c7,c5,4 @Flush Prefetch buffer
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bx lr
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ASM_PFX(ArmEnableMmu):
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mrc p15,0,R0,c1,c0,0
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orr R0,R0,#1
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mcr p15,0,R0,c1,c0,0
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bx LR
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ASM_PFX(ArmMmuEnabled):
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mrc p15,0,R0,c1,c0,0
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and R0,R0,#1
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bx LR
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ASM_PFX(ArmDisableMmu):
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mrc p15,0,R0,c1,c0,0
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bic R0,R0,#1
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mcr p15,0,R0,c1,c0,0
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mov R0,#0
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mcr p15,0,R0,c7,c10,4 @Data synchronization barrier
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mov R0,#0
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mcr p15,0,R0,c7,c5,4 @Flush Prefetch buffer
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bx LR
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ASM_PFX(ArmEnableDataCache):
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LoadConstantToReg(DC_ON, R1) @ldr R1,=DC_ON
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mrc p15,0,R0,c1,c0,0 @Read control register configuration data
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||||
orr R0,R0,R1 @Set C bit
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mcr p15,0,r0,c1,c0,0 @Write control register configuration data
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bx LR
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ASM_PFX(ArmDisableDataCache):
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LoadConstantToReg(DC_ON, R1) @ldr R1,=DC_ON
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mrc p15,0,R0,c1,c0,0 @Read control register configuration data
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bic R0,R0,R1 @Clear C bit
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mcr p15,0,r0,c1,c0,0 @Write control register configuration data
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bx LR
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ASM_PFX(ArmEnableInstructionCache):
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ldr R1,=IC_ON
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mrc p15,0,R0,c1,c0,0 @Read control register configuration data
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orr R0,R0,R1 @Set I bit
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mcr p15,0,r0,c1,c0,0 @Write control register configuration data
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bx LR
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ASM_PFX(ArmDisableInstructionCache):
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ldr R1,=IC_ON
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mrc p15,0,R0,c1,c0,0 @Read control register configuration data
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bic R0,R0,R1 @Clear I bit.
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mcr p15,0,r0,c1,c0,0 @Write control register configuration data
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bx LR
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ASM_PFX(ArmEnableBranchPrediction):
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mrc p15, 0, r0, c1, c0, 0
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orr r0, r0, #0x00000800
|
||||
mcr p15, 0, r0, c1, c0, 0
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmDisableBranchPrediction):
|
||||
mrc p15, 0, r0, c1, c0, 0
|
||||
bic r0, r0, #0x00000800
|
||||
mcr p15, 0, r0, c1, c0, 0
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmDataMemoryBarrier):
|
||||
mov R0, #0
|
||||
mcr P15, #0, R0, C7, C10, #5
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmDataSyncronizationBarrier):
|
||||
mov R0, #0
|
||||
mcr P15, #0, R0, C7, C10, #4
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmInstructionSynchronizationBarrier):
|
||||
mov R0, #0
|
||||
mcr P15, #0, R0, C7, C5, #4
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmSetLowVectors):
|
||||
mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
|
||||
bic r0, r0, #0x00002000 @ clear V bit
|
||||
mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmSetHighVectors):
|
||||
mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
|
||||
orr r0, r0, #0x00002000 @ clear V bit
|
||||
mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmIsMpCore):
|
||||
push { r1 }
|
||||
mrc p15, 0, r0, c0, c0, 0
|
||||
# Extract Part Number to check it is an ARM11MP core (0xB02)
|
||||
LoadConstantToReg (Arm11PartNumberMask, r1)
|
||||
and r0, r0, r1
|
||||
LoadConstantToReg (Arm11PartNumber, r1)
|
||||
cmp r0, r1
|
||||
movne r0, #0
|
||||
pop { r1 }
|
||||
bx lr
|
||||
|
||||
ASM_PFX(ArmCallWFI):
|
||||
wfi
|
||||
bx lr
|
||||
|
||||
ASM_PFX(ArmReadMpidr):
|
||||
mrc p15, 0, r0, c0, c0, 5 @ read MPIDR
|
||||
bx lr
|
||||
|
||||
ASM_PFX(ArmEnableFiq):
|
||||
mrs R0,CPSR
|
||||
bic R0,R0,#0x40 @Enable FIQ interrupts
|
||||
msr CPSR_c,R0
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmDisableFiq):
|
||||
mrs R0,CPSR
|
||||
orr R1,R0,#0x40 @Disable FIQ interrupts
|
||||
msr CPSR_c,R1
|
||||
tst R0,#0x80
|
||||
moveq R0,#1
|
||||
movne R0,#0
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmEnableInterrupts):
|
||||
mrs R0,CPSR
|
||||
bic R0,R0,#0x80 @Enable IRQ interrupts
|
||||
msr CPSR_c,R0
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmDisableInterrupts):
|
||||
mrs R0,CPSR
|
||||
orr R1,R0,#0x80 @Disable IRQ interrupts
|
||||
msr CPSR_c,R1
|
||||
tst R0,#0x80
|
||||
moveq R0,#1
|
||||
movne R0,#0
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmEnableVFP):
|
||||
# Read CPACR (Coprocessor Access Control Register)
|
||||
mrc p15, 0, r0, c1, c0, 2
|
||||
# Enable VPF access (Full Access to CP10, CP11) (V* instructions)
|
||||
orr r0, r0, #0x00f00000
|
||||
# Write back CPACR (Coprocessor Access Control Register)
|
||||
mcr p15, 0, r0, c1, c0, 2
|
||||
# Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
|
||||
mov r0, #0x40000000
|
||||
#TODO: Fixme - need compilation flag
|
||||
#fmxr FPEXC, r0
|
||||
bx lr
|
||||
|
||||
ASM_FUNCTION_REMOVE_IF_UNREFERENCED
|
||||
|
||||
Reference in New Issue
Block a user