ARM Packages: Fixed line endings
This large code change only modifies the line endings to be CRLF to be compliant with the EDK2 coding convention document. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14088 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin
@@ -1,153 +1,153 @@
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#------------------------------------------------------------------------------
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#
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# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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#------------------------------------------------------------------------------
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.text
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.align 2
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GCC_ASM_EXPORT(ArmCleanInvalidateDataCache)
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GCC_ASM_EXPORT(ArmCleanDataCache)
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GCC_ASM_EXPORT(ArmInvalidateDataCache)
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GCC_ASM_EXPORT(ArmInvalidateInstructionCache)
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GCC_ASM_EXPORT(ArmInvalidateDataCacheEntryByMVA)
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GCC_ASM_EXPORT(ArmCleanDataCacheEntryByMVA)
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GCC_ASM_EXPORT(ArmCleanInvalidateDataCacheEntryByMVA)
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GCC_ASM_EXPORT(ArmEnableMmu)
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GCC_ASM_EXPORT(ArmDisableMmu)
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GCC_ASM_EXPORT(ArmMmuEnabled)
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GCC_ASM_EXPORT(ArmEnableDataCache)
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GCC_ASM_EXPORT(ArmDisableDataCache)
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GCC_ASM_EXPORT(ArmEnableInstructionCache)
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GCC_ASM_EXPORT(ArmDisableInstructionCache)
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GCC_ASM_EXPORT(ArmEnableBranchPrediction)
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GCC_ASM_EXPORT(ArmDisableBranchPrediction)
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GCC_ASM_EXPORT(ArmDataMemoryBarrier)
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GCC_ASM_EXPORT(ArmDataSyncronizationBarrier)
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GCC_ASM_EXPORT(ArmInstructionSynchronizationBarrier)
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.set DC_ON, (1<<2)
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.set IC_ON, (1<<12)
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#------------------------------------------------------------------------------
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ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
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mcr p15, 0, r0, c7, c6, 1 @ invalidate single data cache line
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bx lr
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ASM_PFX(ArmCleanDataCacheEntryByMVA):
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mcr p15, 0, r0, c7, c10, 1 @ clean single data cache line
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bx lr
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ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
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mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate single data cache line
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bx lr
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ASM_PFX(ArmEnableInstructionCache):
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ldr r1,=IC_ON
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mrc p15,0,r0,c1,c0,0 @Read control register configuration data
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orr r0,r0,r1 @Set I bit
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mcr p15,0,r0,c1,c0,0 @Write control register configuration data
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bx LR
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ASM_PFX(ArmDisableInstructionCache):
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ldr r1,=IC_ON
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mrc p15,0,r0,c1,c0,0 @Read control register configuration data
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bic r0,r0,r1 @Clear I bit.
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mcr p15,0,r0,c1,c0,0 @Write control register configuration data
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bx LR
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ASM_PFX(ArmInvalidateInstructionCache):
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mov r0,#0
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mcr p15,0,r0,c7,c5,0 @Invalidate entire Instruction cache.
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@Also flushes the branch target cache.
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mov r0,#0
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mcr p15,0,r0,c7,c10,4 @Data write buffer
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bx LR
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ASM_PFX(ArmEnableMmu):
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mrc p15,0,R0,c1,c0,0
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orr R0,R0,#1
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mcr p15,0,R0,c1,c0,0
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bx LR
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ASM_PFX(ArmMmuEnabled):
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mrc p15,0,R0,c1,c0,0
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and R0,R0,#1
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bx LR
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ASM_PFX(ArmDisableMmu):
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mrc p15,0,R0,c1,c0,0
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bic R0,R0,#1
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mcr p15,0,R0,c1,c0,0
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mov R0,#0
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mcr p15,0,R0,c7,c10,4 @Drain write buffer
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bx LR
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ASM_PFX(ArmEnableDataCache):
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ldr R1,=DC_ON
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mrc p15,0,R0,c1,c0,0 @Read control register configuration data
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orr R0,R0,R1 @Set C bit
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mcr p15,0,r0,c1,c0,0 @Write control register configuration data
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bx LR
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ASM_PFX(ArmDisableDataCache):
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ldr R1,=DC_ON
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mrc p15,0,R0,c1,c0,0 @Read control register configuration data
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bic R0,R0,R1 @Clear C bit
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mcr p15,0,r0,c1,c0,0 @Write control register configuration data
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bx LR
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ASM_PFX(ArmCleanDataCache):
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mrc p15,0,r15,c7,c10,3
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bne ASM_PFX(ArmCleanDataCache)
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mov R0,#0
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mcr p15,0,R0,c7,c10,4 @Drain write buffer
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bx LR
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ASM_PFX(ArmInvalidateDataCache):
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mov R0,#0
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mcr p15,0,R0,c7,c6,0 @Invalidate entire data cache
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mov R0,#0
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mcr p15,0,R0,c7,c10,4 @Drain write buffer
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bx LR
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ASM_PFX(ArmCleanInvalidateDataCache):
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mrc p15,0,r15,c7,c14,3
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bne ASM_PFX(ArmCleanInvalidateDataCache)
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mov R0,#0
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mcr p15,0,R0,c7,c10,4 @Drain write buffer
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bx LR
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ASM_PFX(ArmEnableBranchPrediction):
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bx LR @Branch prediction is not supported.
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ASM_PFX(ArmDisableBranchPrediction):
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bx LR @Branch prediction is not supported.
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ASM_PFX(ArmDataMemoryBarrier):
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mov R0, #0
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mcr P15, #0, R0, C7, C10, #5 @ check if this is OK?
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bx LR
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ASM_PFX(ArmDataSyncronizationBarrier):
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mov R0, #0
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mcr P15, #0, R0, C7, C10, #4 @ check if this is OK?
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bx LR
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ASM_PFX(ArmInstructionSynchronizationBarrier):
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mov R0, #0
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mcr P15, #0, R0, C7, C5, #4 @ check if this is OK?
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bx LR
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ASM_FUNCTION_REMOVE_IF_UNREFERENCED
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#------------------------------------------------------------------------------
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#
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# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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#------------------------------------------------------------------------------
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.text
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.align 2
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GCC_ASM_EXPORT(ArmCleanInvalidateDataCache)
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GCC_ASM_EXPORT(ArmCleanDataCache)
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GCC_ASM_EXPORT(ArmInvalidateDataCache)
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GCC_ASM_EXPORT(ArmInvalidateInstructionCache)
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GCC_ASM_EXPORT(ArmInvalidateDataCacheEntryByMVA)
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GCC_ASM_EXPORT(ArmCleanDataCacheEntryByMVA)
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GCC_ASM_EXPORT(ArmCleanInvalidateDataCacheEntryByMVA)
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GCC_ASM_EXPORT(ArmEnableMmu)
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GCC_ASM_EXPORT(ArmDisableMmu)
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GCC_ASM_EXPORT(ArmMmuEnabled)
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GCC_ASM_EXPORT(ArmEnableDataCache)
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GCC_ASM_EXPORT(ArmDisableDataCache)
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GCC_ASM_EXPORT(ArmEnableInstructionCache)
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GCC_ASM_EXPORT(ArmDisableInstructionCache)
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GCC_ASM_EXPORT(ArmEnableBranchPrediction)
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GCC_ASM_EXPORT(ArmDisableBranchPrediction)
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GCC_ASM_EXPORT(ArmDataMemoryBarrier)
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GCC_ASM_EXPORT(ArmDataSyncronizationBarrier)
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GCC_ASM_EXPORT(ArmInstructionSynchronizationBarrier)
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.set DC_ON, (1<<2)
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.set IC_ON, (1<<12)
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#------------------------------------------------------------------------------
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ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
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mcr p15, 0, r0, c7, c6, 1 @ invalidate single data cache line
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bx lr
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ASM_PFX(ArmCleanDataCacheEntryByMVA):
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mcr p15, 0, r0, c7, c10, 1 @ clean single data cache line
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bx lr
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ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
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mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate single data cache line
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bx lr
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ASM_PFX(ArmEnableInstructionCache):
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ldr r1,=IC_ON
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mrc p15,0,r0,c1,c0,0 @Read control register configuration data
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orr r0,r0,r1 @Set I bit
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mcr p15,0,r0,c1,c0,0 @Write control register configuration data
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bx LR
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ASM_PFX(ArmDisableInstructionCache):
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ldr r1,=IC_ON
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mrc p15,0,r0,c1,c0,0 @Read control register configuration data
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bic r0,r0,r1 @Clear I bit.
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mcr p15,0,r0,c1,c0,0 @Write control register configuration data
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bx LR
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ASM_PFX(ArmInvalidateInstructionCache):
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mov r0,#0
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mcr p15,0,r0,c7,c5,0 @Invalidate entire Instruction cache.
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@Also flushes the branch target cache.
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mov r0,#0
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mcr p15,0,r0,c7,c10,4 @Data write buffer
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bx LR
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ASM_PFX(ArmEnableMmu):
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mrc p15,0,R0,c1,c0,0
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orr R0,R0,#1
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mcr p15,0,R0,c1,c0,0
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bx LR
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ASM_PFX(ArmMmuEnabled):
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mrc p15,0,R0,c1,c0,0
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and R0,R0,#1
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bx LR
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ASM_PFX(ArmDisableMmu):
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mrc p15,0,R0,c1,c0,0
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bic R0,R0,#1
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mcr p15,0,R0,c1,c0,0
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mov R0,#0
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mcr p15,0,R0,c7,c10,4 @Drain write buffer
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bx LR
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ASM_PFX(ArmEnableDataCache):
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ldr R1,=DC_ON
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mrc p15,0,R0,c1,c0,0 @Read control register configuration data
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orr R0,R0,R1 @Set C bit
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mcr p15,0,r0,c1,c0,0 @Write control register configuration data
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bx LR
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ASM_PFX(ArmDisableDataCache):
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ldr R1,=DC_ON
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mrc p15,0,R0,c1,c0,0 @Read control register configuration data
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bic R0,R0,R1 @Clear C bit
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mcr p15,0,r0,c1,c0,0 @Write control register configuration data
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bx LR
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ASM_PFX(ArmCleanDataCache):
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mrc p15,0,r15,c7,c10,3
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bne ASM_PFX(ArmCleanDataCache)
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mov R0,#0
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mcr p15,0,R0,c7,c10,4 @Drain write buffer
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bx LR
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ASM_PFX(ArmInvalidateDataCache):
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mov R0,#0
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mcr p15,0,R0,c7,c6,0 @Invalidate entire data cache
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mov R0,#0
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mcr p15,0,R0,c7,c10,4 @Drain write buffer
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bx LR
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ASM_PFX(ArmCleanInvalidateDataCache):
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mrc p15,0,r15,c7,c14,3
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bne ASM_PFX(ArmCleanInvalidateDataCache)
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mov R0,#0
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mcr p15,0,R0,c7,c10,4 @Drain write buffer
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bx LR
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ASM_PFX(ArmEnableBranchPrediction):
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bx LR @Branch prediction is not supported.
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ASM_PFX(ArmDisableBranchPrediction):
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bx LR @Branch prediction is not supported.
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ASM_PFX(ArmDataMemoryBarrier):
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mov R0, #0
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mcr P15, #0, R0, C7, C10, #5 @ check if this is OK?
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bx LR
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ASM_PFX(ArmDataSyncronizationBarrier):
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mov R0, #0
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mcr P15, #0, R0, C7, C10, #4 @ check if this is OK?
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bx LR
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ASM_PFX(ArmInstructionSynchronizationBarrier):
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mov R0, #0
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mcr P15, #0, R0, C7, C5, #4 @ check if this is OK?
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bx LR
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ASM_FUNCTION_REMOVE_IF_UNREFERENCED
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