ARM Packages: Fixed line endings
This large code change only modifies the line endings to be CRLF to be compliant with the EDK2 coding convention document. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14088 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin
@@ -1,275 +1,275 @@
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/** @file
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*
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* Copyright (c) 2011, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#include <Uefi.h>
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#include <Chipset/ArmV7.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/ArmLib.h>
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#include <Library/BaseLib.h>
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#include <Library/DebugLib.h>
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#include "ArmV7Lib.h"
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#include "ArmLibPrivate.h"
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#include <Library/ArmV7ArchTimerLib.h>
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VOID
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EFIAPI
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ArmArchTimerReadReg (
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IN ARM_ARCH_TIMER_REGS Reg,
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OUT VOID *DstBuf
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)
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{
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// Check if the Generic/Architecture timer is implemented
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if (ArmIsArchTimerImplemented ()) {
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switch (Reg) {
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case CntFrq:
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*((UINTN *)DstBuf) = ArmReadCntFrq ();
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break;
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case CntPct:
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*((UINT64 *)DstBuf) = ArmReadCntPct ();
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break;
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case CntkCtl:
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*((UINTN *)DstBuf) = ArmReadCntkCtl();
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break;
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case CntpTval:
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*((UINTN *)DstBuf) = ArmReadCntpTval ();
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break;
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case CntpCtl:
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*((UINTN *)DstBuf) = ArmReadCntpCtl ();
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break;
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case CntvTval:
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*((UINTN *)DstBuf) = ArmReadCntvTval ();
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break;
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case CntvCtl:
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*((UINTN *)DstBuf) = ArmReadCntvCtl ();
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break;
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case CntvCt:
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*((UINT64 *)DstBuf) = ArmReadCntvCt ();
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break;
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case CntpCval:
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*((UINT64 *)DstBuf) = ArmReadCntpCval ();
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break;
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case CntvCval:
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*((UINT64 *)DstBuf) = ArmReadCntvCval ();
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break;
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case CntvOff:
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*((UINT64 *)DstBuf) = ArmReadCntvOff ();
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break;
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case CnthCtl:
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case CnthpTval:
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case CnthpCtl:
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case CnthpCval:
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DEBUG ((EFI_D_ERROR, "The register is related to Hypervisor Mode. Can't perform requested operation\n "));
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break;
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default:
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DEBUG ((EFI_D_ERROR, "Unknown ARM Generic Timer register %x. \n ", Reg));
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}
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} else {
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DEBUG ((EFI_D_ERROR, "Attempt to read ARM Generic Timer registers. But ARM Generic Timer extension is not implemented \n "));
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ASSERT (0);
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}
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}
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VOID
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EFIAPI
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ArmArchTimerWriteReg (
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IN ARM_ARCH_TIMER_REGS Reg,
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IN VOID *SrcBuf
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)
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{
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// Check if the Generic/Architecture timer is implemented
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if (ArmIsArchTimerImplemented ()) {
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switch (Reg) {
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case CntFrq:
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ArmWriteCntFrq (*((UINTN *)SrcBuf));
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break;
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case CntPct:
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DEBUG ((EFI_D_ERROR, "Can't write to Read Only Register: CNTPCT \n"));
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break;
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case CntkCtl:
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ArmWriteCntkCtl (*((UINTN *)SrcBuf));
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break;
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case CntpTval:
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ArmWriteCntpTval (*((UINTN *)SrcBuf));
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break;
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case CntpCtl:
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ArmWriteCntpCtl (*((UINTN *)SrcBuf));
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break;
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case CntvTval:
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ArmWriteCntvTval (*((UINTN *)SrcBuf));
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break;
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case CntvCtl:
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ArmWriteCntvCtl (*((UINTN *)SrcBuf));
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break;
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case CntvCt:
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DEBUG ((EFI_D_ERROR, "Can't write to Read Only Register: CNTVCT \n"));
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break;
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case CntpCval:
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ArmWriteCntpCval (*((UINT64 *)SrcBuf) );
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break;
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case CntvCval:
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ArmWriteCntvCval (*((UINT64 *)SrcBuf) );
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break;
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case CntvOff:
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ArmWriteCntvOff (*((UINT64 *)SrcBuf));
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break;
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case CnthCtl:
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case CnthpTval:
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case CnthpCtl:
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case CnthpCval:
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DEBUG ((EFI_D_ERROR, "The register is related to Hypervisor Mode. Can't perform requested operation\n "));
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break;
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default:
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DEBUG ((EFI_D_ERROR, "Unknown ARM Generic Timer register %x. \n ", Reg));
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}
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} else {
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DEBUG ((EFI_D_ERROR, "Attempt to write to ARM Generic Timer registers. But ARM Generic Timer extension is not implemented \n "));
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ASSERT (0);
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}
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}
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VOID
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EFIAPI
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ArmArchTimerEnableTimer (
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VOID
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)
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{
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UINTN TimerCtrlReg;
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ArmArchTimerReadReg (CntpCtl, (VOID *)&TimerCtrlReg);
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TimerCtrlReg |= ARM_ARCH_TIMER_ENABLE;
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ArmArchTimerWriteReg (CntpCtl, (VOID *)&TimerCtrlReg);
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}
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VOID
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EFIAPI
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ArmArchTimerDisableTimer (
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VOID
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)
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{
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UINTN TimerCtrlReg;
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ArmArchTimerReadReg (CntpCtl, (VOID *)&TimerCtrlReg);
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TimerCtrlReg &= ~ARM_ARCH_TIMER_ENABLE;
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ArmArchTimerWriteReg (CntpCtl, (VOID *)&TimerCtrlReg);
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}
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VOID
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EFIAPI
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ArmArchTimerSetTimerFreq (
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IN UINTN FreqInHz
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)
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{
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ArmArchTimerWriteReg (CntFrq, (VOID *)&FreqInHz);
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}
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UINTN
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EFIAPI
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ArmArchTimerGetTimerFreq (
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VOID
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)
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{
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UINTN ArchTimerFreq = 0;
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ArmArchTimerReadReg (CntFrq, (VOID *)&ArchTimerFreq);
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return ArchTimerFreq;
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}
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UINTN
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EFIAPI
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ArmArchTimerGetTimerVal (
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VOID
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)
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{
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UINTN ArchTimerVal;
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ArmArchTimerReadReg (CntpTval, (VOID *)&ArchTimerVal);
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return ArchTimerVal;
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}
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VOID
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EFIAPI
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ArmArchTimerSetTimerVal (
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IN UINTN Val
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)
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{
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ArmArchTimerWriteReg (CntpTval, (VOID *)&Val);
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}
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UINT64
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EFIAPI
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ArmArchTimerGetSystemCount (
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VOID
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)
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{
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UINT64 SystemCount;
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ArmArchTimerReadReg (CntPct, (VOID *)&SystemCount);
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return SystemCount;
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}
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UINTN
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EFIAPI
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ArmArchTimerGetTimerCtrlReg (
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VOID
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)
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{
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UINTN Val;
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ArmArchTimerReadReg (CntpCtl, (VOID *)&Val);
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return Val;
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}
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VOID
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EFIAPI
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ArmArchTimerSetTimerCtrlReg (
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UINTN Val
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)
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{
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ArmArchTimerWriteReg (CntpCtl, (VOID *)&Val);
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}
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VOID
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EFIAPI
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ArmArchTimerSetCompareVal (
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IN UINT64 Val
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)
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{
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ArmArchTimerWriteReg (CntpCval, (VOID *)&Val);
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}
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/** @file
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*
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* Copyright (c) 2011, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
|
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#include <Uefi.h>
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#include <Chipset/ArmV7.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/ArmLib.h>
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#include <Library/BaseLib.h>
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#include <Library/DebugLib.h>
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#include "ArmV7Lib.h"
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#include "ArmLibPrivate.h"
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#include <Library/ArmV7ArchTimerLib.h>
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VOID
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EFIAPI
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ArmArchTimerReadReg (
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IN ARM_ARCH_TIMER_REGS Reg,
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OUT VOID *DstBuf
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)
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{
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// Check if the Generic/Architecture timer is implemented
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if (ArmIsArchTimerImplemented ()) {
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switch (Reg) {
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case CntFrq:
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*((UINTN *)DstBuf) = ArmReadCntFrq ();
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break;
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case CntPct:
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*((UINT64 *)DstBuf) = ArmReadCntPct ();
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break;
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case CntkCtl:
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*((UINTN *)DstBuf) = ArmReadCntkCtl();
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break;
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case CntpTval:
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*((UINTN *)DstBuf) = ArmReadCntpTval ();
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break;
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case CntpCtl:
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*((UINTN *)DstBuf) = ArmReadCntpCtl ();
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break;
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case CntvTval:
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*((UINTN *)DstBuf) = ArmReadCntvTval ();
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break;
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case CntvCtl:
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*((UINTN *)DstBuf) = ArmReadCntvCtl ();
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break;
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case CntvCt:
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*((UINT64 *)DstBuf) = ArmReadCntvCt ();
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break;
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case CntpCval:
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*((UINT64 *)DstBuf) = ArmReadCntpCval ();
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break;
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case CntvCval:
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*((UINT64 *)DstBuf) = ArmReadCntvCval ();
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break;
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case CntvOff:
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*((UINT64 *)DstBuf) = ArmReadCntvOff ();
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break;
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case CnthCtl:
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case CnthpTval:
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case CnthpCtl:
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case CnthpCval:
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DEBUG ((EFI_D_ERROR, "The register is related to Hypervisor Mode. Can't perform requested operation\n "));
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break;
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default:
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DEBUG ((EFI_D_ERROR, "Unknown ARM Generic Timer register %x. \n ", Reg));
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}
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} else {
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DEBUG ((EFI_D_ERROR, "Attempt to read ARM Generic Timer registers. But ARM Generic Timer extension is not implemented \n "));
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ASSERT (0);
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}
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}
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VOID
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EFIAPI
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ArmArchTimerWriteReg (
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IN ARM_ARCH_TIMER_REGS Reg,
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IN VOID *SrcBuf
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)
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{
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// Check if the Generic/Architecture timer is implemented
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if (ArmIsArchTimerImplemented ()) {
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switch (Reg) {
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case CntFrq:
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ArmWriteCntFrq (*((UINTN *)SrcBuf));
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break;
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case CntPct:
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DEBUG ((EFI_D_ERROR, "Can't write to Read Only Register: CNTPCT \n"));
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break;
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case CntkCtl:
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ArmWriteCntkCtl (*((UINTN *)SrcBuf));
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break;
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case CntpTval:
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ArmWriteCntpTval (*((UINTN *)SrcBuf));
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break;
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case CntpCtl:
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ArmWriteCntpCtl (*((UINTN *)SrcBuf));
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break;
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case CntvTval:
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ArmWriteCntvTval (*((UINTN *)SrcBuf));
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break;
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case CntvCtl:
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ArmWriteCntvCtl (*((UINTN *)SrcBuf));
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break;
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case CntvCt:
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DEBUG ((EFI_D_ERROR, "Can't write to Read Only Register: CNTVCT \n"));
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break;
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case CntpCval:
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ArmWriteCntpCval (*((UINT64 *)SrcBuf) );
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break;
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case CntvCval:
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ArmWriteCntvCval (*((UINT64 *)SrcBuf) );
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break;
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case CntvOff:
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ArmWriteCntvOff (*((UINT64 *)SrcBuf));
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break;
|
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case CnthCtl:
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case CnthpTval:
|
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case CnthpCtl:
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case CnthpCval:
|
||||
DEBUG ((EFI_D_ERROR, "The register is related to Hypervisor Mode. Can't perform requested operation\n "));
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break;
|
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|
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default:
|
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DEBUG ((EFI_D_ERROR, "Unknown ARM Generic Timer register %x. \n ", Reg));
|
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}
|
||||
} else {
|
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DEBUG ((EFI_D_ERROR, "Attempt to write to ARM Generic Timer registers. But ARM Generic Timer extension is not implemented \n "));
|
||||
ASSERT (0);
|
||||
}
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmArchTimerEnableTimer (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINTN TimerCtrlReg;
|
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|
||||
ArmArchTimerReadReg (CntpCtl, (VOID *)&TimerCtrlReg);
|
||||
TimerCtrlReg |= ARM_ARCH_TIMER_ENABLE;
|
||||
ArmArchTimerWriteReg (CntpCtl, (VOID *)&TimerCtrlReg);
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmArchTimerDisableTimer (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINTN TimerCtrlReg;
|
||||
|
||||
ArmArchTimerReadReg (CntpCtl, (VOID *)&TimerCtrlReg);
|
||||
TimerCtrlReg &= ~ARM_ARCH_TIMER_ENABLE;
|
||||
ArmArchTimerWriteReg (CntpCtl, (VOID *)&TimerCtrlReg);
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmArchTimerSetTimerFreq (
|
||||
IN UINTN FreqInHz
|
||||
)
|
||||
{
|
||||
ArmArchTimerWriteReg (CntFrq, (VOID *)&FreqInHz);
|
||||
}
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmArchTimerGetTimerFreq (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINTN ArchTimerFreq = 0;
|
||||
ArmArchTimerReadReg (CntFrq, (VOID *)&ArchTimerFreq);
|
||||
return ArchTimerFreq;
|
||||
}
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmArchTimerGetTimerVal (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINTN ArchTimerVal;
|
||||
ArmArchTimerReadReg (CntpTval, (VOID *)&ArchTimerVal);
|
||||
return ArchTimerVal;
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmArchTimerSetTimerVal (
|
||||
IN UINTN Val
|
||||
)
|
||||
{
|
||||
ArmArchTimerWriteReg (CntpTval, (VOID *)&Val);
|
||||
}
|
||||
|
||||
UINT64
|
||||
EFIAPI
|
||||
ArmArchTimerGetSystemCount (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINT64 SystemCount;
|
||||
ArmArchTimerReadReg (CntPct, (VOID *)&SystemCount);
|
||||
return SystemCount;
|
||||
}
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmArchTimerGetTimerCtrlReg (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINTN Val;
|
||||
ArmArchTimerReadReg (CntpCtl, (VOID *)&Val);
|
||||
return Val;
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmArchTimerSetTimerCtrlReg (
|
||||
UINTN Val
|
||||
)
|
||||
{
|
||||
ArmArchTimerWriteReg (CntpCtl, (VOID *)&Val);
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmArchTimerSetCompareVal (
|
||||
IN UINT64 Val
|
||||
)
|
||||
{
|
||||
ArmArchTimerWriteReg (CntpCval, (VOID *)&Val);
|
||||
}
|
||||
|
||||
@@ -1,264 +1,264 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
||||
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
#include <Uefi.h>
|
||||
#include <Chipset/ArmV7.h>
|
||||
#include <Library/ArmLib.h>
|
||||
#include <Library/BaseLib.h>
|
||||
#include <Library/IoLib.h>
|
||||
#include "ArmV7Lib.h"
|
||||
#include "ArmLibPrivate.h"
|
||||
|
||||
ARM_CACHE_TYPE
|
||||
EFIAPI
|
||||
ArmCacheType (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
return ARM_CACHE_TYPE_WRITE_BACK;
|
||||
}
|
||||
|
||||
ARM_CACHE_ARCHITECTURE
|
||||
EFIAPI
|
||||
ArmCacheArchitecture (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINT32 CLIDR = ReadCLIDR ();
|
||||
|
||||
return (ARM_CACHE_ARCHITECTURE)CLIDR; // BugBug Fix Me
|
||||
}
|
||||
|
||||
BOOLEAN
|
||||
EFIAPI
|
||||
ArmDataCachePresent (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINT32 CLIDR = ReadCLIDR ();
|
||||
|
||||
if ((CLIDR & 0x2) == 0x2) {
|
||||
// Instruction cache exists
|
||||
return TRUE;
|
||||
}
|
||||
if ((CLIDR & 0x7) == 0x4) {
|
||||
// Unified cache
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmDataCacheSize (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINT32 NumSets;
|
||||
UINT32 Associativity;
|
||||
UINT32 LineSize;
|
||||
UINT32 CCSIDR = ReadCCSIDR (0);
|
||||
|
||||
LineSize = (1 << ((CCSIDR & 0x7) + 2));
|
||||
Associativity = ((CCSIDR >> 3) & 0x3ff) + 1;
|
||||
NumSets = ((CCSIDR >> 13) & 0x7fff) + 1;
|
||||
|
||||
// LineSize is in words (4 byte chunks)
|
||||
return NumSets * Associativity * LineSize * 4;
|
||||
}
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmDataCacheAssociativity (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINT32 CCSIDR = ReadCCSIDR (0);
|
||||
|
||||
return ((CCSIDR >> 3) & 0x3ff) + 1;
|
||||
}
|
||||
|
||||
UINTN
|
||||
ArmDataCacheSets (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINT32 CCSIDR = ReadCCSIDR (0);
|
||||
|
||||
return ((CCSIDR >> 13) & 0x7fff) + 1;
|
||||
}
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmDataCacheLineLength (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINT32 CCSIDR = ReadCCSIDR (0) & 7;
|
||||
|
||||
// * 4 converts to bytes
|
||||
return (1 << (CCSIDR + 2)) * 4;
|
||||
}
|
||||
|
||||
BOOLEAN
|
||||
EFIAPI
|
||||
ArmInstructionCachePresent (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINT32 CLIDR = ReadCLIDR ();
|
||||
|
||||
if ((CLIDR & 1) == 1) {
|
||||
// Instruction cache exists
|
||||
return TRUE;
|
||||
}
|
||||
if ((CLIDR & 0x7) == 0x4) {
|
||||
// Unified cache
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmInstructionCacheSize (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINT32 NumSets;
|
||||
UINT32 Associativity;
|
||||
UINT32 LineSize;
|
||||
UINT32 CCSIDR = ReadCCSIDR (1);
|
||||
|
||||
LineSize = (1 << ((CCSIDR & 0x7) + 2));
|
||||
Associativity = ((CCSIDR >> 3) & 0x3ff) + 1;
|
||||
NumSets = ((CCSIDR >> 13) & 0x7fff) + 1;
|
||||
|
||||
// LineSize is in words (4 byte chunks)
|
||||
return NumSets * Associativity * LineSize * 4;
|
||||
}
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmInstructionCacheAssociativity (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINT32 CCSIDR = ReadCCSIDR (1);
|
||||
|
||||
return ((CCSIDR >> 3) & 0x3ff) + 1;
|
||||
// return 4;
|
||||
}
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmInstructionCacheSets (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINT32 CCSIDR = ReadCCSIDR (1);
|
||||
|
||||
return ((CCSIDR >> 13) & 0x7fff) + 1;
|
||||
}
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmInstructionCacheLineLength (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINT32 CCSIDR = ReadCCSIDR (1) & 7;
|
||||
|
||||
// * 4 converts to bytes
|
||||
return (1 << (CCSIDR + 2)) * 4;
|
||||
|
||||
// return 64;
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
ArmV7DataCacheOperation (
|
||||
IN ARM_V7_CACHE_OPERATION DataCacheOperation
|
||||
)
|
||||
{
|
||||
UINTN SavedInterruptState;
|
||||
|
||||
SavedInterruptState = ArmGetInterruptState ();
|
||||
ArmDisableInterrupts ();
|
||||
|
||||
ArmV7AllDataCachesOperation (DataCacheOperation);
|
||||
|
||||
ArmDrainWriteBuffer ();
|
||||
|
||||
if (SavedInterruptState) {
|
||||
ArmEnableInterrupts ();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
ArmV7PoUDataCacheOperation (
|
||||
IN ARM_V7_CACHE_OPERATION DataCacheOperation
|
||||
)
|
||||
{
|
||||
UINTN SavedInterruptState;
|
||||
|
||||
SavedInterruptState = ArmGetInterruptState ();
|
||||
ArmDisableInterrupts ();
|
||||
|
||||
ArmV7PerformPoUDataCacheOperation (DataCacheOperation);
|
||||
|
||||
ArmDrainWriteBuffer ();
|
||||
|
||||
if (SavedInterruptState) {
|
||||
ArmEnableInterrupts ();
|
||||
}
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmInvalidateDataCache (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
ArmV7DataCacheOperation (ArmInvalidateDataCacheEntryBySetWay);
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmCleanInvalidateDataCache (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
ArmV7DataCacheOperation (ArmCleanInvalidateDataCacheEntryBySetWay);
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmCleanDataCache (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
ArmV7DataCacheOperation (ArmCleanDataCacheEntryBySetWay);
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmCleanDataCacheToPoU (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
ArmV7PoUDataCacheOperation (ArmCleanDataCacheEntryBySetWay);
|
||||
}
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
||||
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
#include <Uefi.h>
|
||||
#include <Chipset/ArmV7.h>
|
||||
#include <Library/ArmLib.h>
|
||||
#include <Library/BaseLib.h>
|
||||
#include <Library/IoLib.h>
|
||||
#include "ArmV7Lib.h"
|
||||
#include "ArmLibPrivate.h"
|
||||
|
||||
ARM_CACHE_TYPE
|
||||
EFIAPI
|
||||
ArmCacheType (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
return ARM_CACHE_TYPE_WRITE_BACK;
|
||||
}
|
||||
|
||||
ARM_CACHE_ARCHITECTURE
|
||||
EFIAPI
|
||||
ArmCacheArchitecture (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINT32 CLIDR = ReadCLIDR ();
|
||||
|
||||
return (ARM_CACHE_ARCHITECTURE)CLIDR; // BugBug Fix Me
|
||||
}
|
||||
|
||||
BOOLEAN
|
||||
EFIAPI
|
||||
ArmDataCachePresent (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINT32 CLIDR = ReadCLIDR ();
|
||||
|
||||
if ((CLIDR & 0x2) == 0x2) {
|
||||
// Instruction cache exists
|
||||
return TRUE;
|
||||
}
|
||||
if ((CLIDR & 0x7) == 0x4) {
|
||||
// Unified cache
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmDataCacheSize (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINT32 NumSets;
|
||||
UINT32 Associativity;
|
||||
UINT32 LineSize;
|
||||
UINT32 CCSIDR = ReadCCSIDR (0);
|
||||
|
||||
LineSize = (1 << ((CCSIDR & 0x7) + 2));
|
||||
Associativity = ((CCSIDR >> 3) & 0x3ff) + 1;
|
||||
NumSets = ((CCSIDR >> 13) & 0x7fff) + 1;
|
||||
|
||||
// LineSize is in words (4 byte chunks)
|
||||
return NumSets * Associativity * LineSize * 4;
|
||||
}
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmDataCacheAssociativity (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINT32 CCSIDR = ReadCCSIDR (0);
|
||||
|
||||
return ((CCSIDR >> 3) & 0x3ff) + 1;
|
||||
}
|
||||
|
||||
UINTN
|
||||
ArmDataCacheSets (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINT32 CCSIDR = ReadCCSIDR (0);
|
||||
|
||||
return ((CCSIDR >> 13) & 0x7fff) + 1;
|
||||
}
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmDataCacheLineLength (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINT32 CCSIDR = ReadCCSIDR (0) & 7;
|
||||
|
||||
// * 4 converts to bytes
|
||||
return (1 << (CCSIDR + 2)) * 4;
|
||||
}
|
||||
|
||||
BOOLEAN
|
||||
EFIAPI
|
||||
ArmInstructionCachePresent (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINT32 CLIDR = ReadCLIDR ();
|
||||
|
||||
if ((CLIDR & 1) == 1) {
|
||||
// Instruction cache exists
|
||||
return TRUE;
|
||||
}
|
||||
if ((CLIDR & 0x7) == 0x4) {
|
||||
// Unified cache
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmInstructionCacheSize (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINT32 NumSets;
|
||||
UINT32 Associativity;
|
||||
UINT32 LineSize;
|
||||
UINT32 CCSIDR = ReadCCSIDR (1);
|
||||
|
||||
LineSize = (1 << ((CCSIDR & 0x7) + 2));
|
||||
Associativity = ((CCSIDR >> 3) & 0x3ff) + 1;
|
||||
NumSets = ((CCSIDR >> 13) & 0x7fff) + 1;
|
||||
|
||||
// LineSize is in words (4 byte chunks)
|
||||
return NumSets * Associativity * LineSize * 4;
|
||||
}
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmInstructionCacheAssociativity (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINT32 CCSIDR = ReadCCSIDR (1);
|
||||
|
||||
return ((CCSIDR >> 3) & 0x3ff) + 1;
|
||||
// return 4;
|
||||
}
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmInstructionCacheSets (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINT32 CCSIDR = ReadCCSIDR (1);
|
||||
|
||||
return ((CCSIDR >> 13) & 0x7fff) + 1;
|
||||
}
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmInstructionCacheLineLength (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINT32 CCSIDR = ReadCCSIDR (1) & 7;
|
||||
|
||||
// * 4 converts to bytes
|
||||
return (1 << (CCSIDR + 2)) * 4;
|
||||
|
||||
// return 64;
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
ArmV7DataCacheOperation (
|
||||
IN ARM_V7_CACHE_OPERATION DataCacheOperation
|
||||
)
|
||||
{
|
||||
UINTN SavedInterruptState;
|
||||
|
||||
SavedInterruptState = ArmGetInterruptState ();
|
||||
ArmDisableInterrupts ();
|
||||
|
||||
ArmV7AllDataCachesOperation (DataCacheOperation);
|
||||
|
||||
ArmDrainWriteBuffer ();
|
||||
|
||||
if (SavedInterruptState) {
|
||||
ArmEnableInterrupts ();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
ArmV7PoUDataCacheOperation (
|
||||
IN ARM_V7_CACHE_OPERATION DataCacheOperation
|
||||
)
|
||||
{
|
||||
UINTN SavedInterruptState;
|
||||
|
||||
SavedInterruptState = ArmGetInterruptState ();
|
||||
ArmDisableInterrupts ();
|
||||
|
||||
ArmV7PerformPoUDataCacheOperation (DataCacheOperation);
|
||||
|
||||
ArmDrainWriteBuffer ();
|
||||
|
||||
if (SavedInterruptState) {
|
||||
ArmEnableInterrupts ();
|
||||
}
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmInvalidateDataCache (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
ArmV7DataCacheOperation (ArmInvalidateDataCacheEntryBySetWay);
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmCleanInvalidateDataCache (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
ArmV7DataCacheOperation (ArmCleanInvalidateDataCacheEntryBySetWay);
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmCleanDataCache (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
ArmV7DataCacheOperation (ArmCleanDataCacheEntryBySetWay);
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmCleanDataCacheToPoU (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
ArmV7PoUDataCacheOperation (ArmCleanDataCacheEntryBySetWay);
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user