ARM Packages: Fixed line endings
This large code change only modifies the line endings to be CRLF to be compliant with the EDK2 coding convention document. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14088 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin
@@ -1,140 +1,140 @@
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/** @file PL111Lcd.h
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Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef _PL111LCD_H__
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#define _PL111LCD_H__
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/**********************************************************************
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*
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* This header file contains all the bits of the PL111 that are
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* platform independent.
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*
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**********************************************************************/
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// Controller Register Offsets
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#define PL111_REG_LCD_TIMING_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x000)
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#define PL111_REG_LCD_TIMING_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x004)
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#define PL111_REG_LCD_TIMING_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x008)
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#define PL111_REG_LCD_TIMING_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x00C)
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#define PL111_REG_LCD_UP_BASE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x010)
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#define PL111_REG_LCD_LP_BASE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x014)
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#define PL111_REG_LCD_CONTROL ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x018)
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#define PL111_REG_LCD_IMSC ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x01C)
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#define PL111_REG_LCD_RIS ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x020)
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#define PL111_REG_LCD_MIS ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x024)
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#define PL111_REG_LCD_ICR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x028)
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#define PL111_REG_LCD_UP_CURR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x02C)
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#define PL111_REG_LCD_LP_CURR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x030)
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#define PL111_REG_LCD_PALETTE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x200)
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// Identification Register Offsets
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#define PL111_REG_CLCD_PERIPH_ID_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE0)
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#define PL111_REG_CLCD_PERIPH_ID_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE4)
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#define PL111_REG_CLCD_PERIPH_ID_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE8)
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#define PL111_REG_CLCD_PERIPH_ID_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFEC)
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#define PL111_REG_CLCD_P_CELL_ID_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF0)
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#define PL111_REG_CLCD_P_CELL_ID_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF4)
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#define PL111_REG_CLCD_P_CELL_ID_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF8)
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#define PL111_REG_CLCD_P_CELL_ID_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFFC)
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/**********************************************************************/
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// Register components (register bits)
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// This should make life easier to program specific settings in the different registers
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// by simplifying the setting up of the individual bits of each register
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// and then assembling the final register value.
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/**********************************************************************/
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// Register: PL111_REG_LCD_TIMING_0
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#define HOR_AXIS_PANEL(hbp,hfp,hsw,hor_res) (UINT32)(((UINT32)(hbp) << 24) | ((UINT32)(hfp) << 16) | ((UINT32)(hsw) << 8) | (((UINT32)((hor_res)/16)-1) << 2))
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// Register: PL111_REG_LCD_TIMING_1
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#define VER_AXIS_PANEL(vbp,vfp,vsw,ver_res) (UINT32)(((UINT32)(vbp) << 24) | ((UINT32)(vfp) << 16) | ((UINT32)(vsw) << 10) | ((ver_res)-1))
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// Register: PL111_REG_LCD_TIMING_2
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#define PL111_BIT_SHIFT_PCD_HI 27
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#define PL111_BIT_SHIFT_BCD 26
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#define PL111_BIT_SHIFT_CPL 16
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#define PL111_BIT_SHIFT_IOE 14
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#define PL111_BIT_SHIFT_IPC 13
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#define PL111_BIT_SHIFT_IHS 12
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#define PL111_BIT_SHIFT_IVS 11
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#define PL111_BIT_SHIFT_ACB 6
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#define PL111_BIT_SHIFT_CLKSEL 5
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#define PL111_BIT_SHIFT_PCD_LO 0
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#define PL111_BCD (1 << 26)
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#define PL111_IPC (1 << 13)
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#define PL111_IHS (1 << 12)
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#define PL111_IVS (1 << 11)
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#define CLK_SIG_POLARITY(hor_res) (UINT32)(PL111_BCD | PL111_IPC | PL111_IHS | PL111_IVS | (((hor_res)-1) << 16))
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// Register: PL111_REG_LCD_TIMING_3
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#define PL111_BIT_SHIFT_LEE 16
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#define PL111_BIT_SHIFT_LED 0
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#define PL111_CTRL_WATERMARK (1 << 16)
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#define PL111_CTRL_LCD_V_COMP (1 << 12)
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#define PL111_CTRL_LCD_PWR (1 << 11)
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#define PL111_CTRL_BEPO (1 << 10)
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#define PL111_CTRL_BEBO (1 << 9)
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#define PL111_CTRL_BGR (1 << 8)
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#define PL111_CTRL_LCD_DUAL (1 << 7)
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#define PL111_CTRL_LCD_MONO_8 (1 << 6)
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#define PL111_CTRL_LCD_TFT (1 << 5)
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#define PL111_CTRL_LCD_BW (1 << 4)
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#define PL111_CTRL_LCD_1BPP (0 << 1)
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#define PL111_CTRL_LCD_2BPP (1 << 1)
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#define PL111_CTRL_LCD_4BPP (2 << 1)
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#define PL111_CTRL_LCD_8BPP (3 << 1)
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#define PL111_CTRL_LCD_16BPP (4 << 1)
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#define PL111_CTRL_LCD_24BPP (5 << 1)
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#define PL111_CTRL_LCD_16BPP_565 (6 << 1)
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#define PL111_CTRL_LCD_12BPP_444 (7 << 1)
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#define PL111_CTRL_LCD_BPP(Bpp) ((Bpp) << 1)
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#define PL111_CTRL_LCD_EN 1
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/**********************************************************************/
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// Register: PL111_REG_LCD_TIMING_0
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#define PL111_LCD_TIMING_0_HBP(hbp) (((hbp) & 0xFF) << 24)
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#define PL111_LCD_TIMING_0_HFP(hfp) (((hfp) & 0xFF) << 16)
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#define PL111_LCD_TIMING_0_HSW(hsw) (((hsw) & 0xFF) << 8)
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#define PL111_LCD_TIMING_0_PPL(ppl) (((hsw) & 0x3F) << 2)
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// Register: PL111_REG_LCD_TIMING_1
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#define PL111_LCD_TIMING_1_VBP(vbp) (((vbp) & 0xFF) << 24)
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#define PL111_LCD_TIMING_1_VFP(vfp) (((vfp) & 0xFF) << 16)
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#define PL111_LCD_TIMING_1_VSW(vsw) (((vsw) & 0x3F) << 10)
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#define PL111_LCD_TIMING_1_LPP(lpp) ((lpp) & 0xFC)
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// Register: PL111_REG_LCD_TIMING_2
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#define PL111_BIT_MASK_PCD_HI 0xF8000000
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#define PL111_BIT_MASK_BCD 0x04000000
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#define PL111_BIT_MASK_CPL 0x03FF0000
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#define PL111_BIT_MASK_IOE 0x00004000
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#define PL111_BIT_MASK_IPC 0x00002000
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#define PL111_BIT_MASK_IHS 0x00001000
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#define PL111_BIT_MASK_IVS 0x00000800
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#define PL111_BIT_MASK_ACB 0x000007C0
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#define PL111_BIT_MASK_CLKSEL 0x00000020
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#define PL111_BIT_MASK_PCD_LO 0x0000001F
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// Register: PL111_REG_LCD_TIMING_3
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#define PL111_BIT_MASK_LEE 0x00010000
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#define PL111_BIT_MASK_LED 0x0000007F
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#endif /* _PL111LCD_H__ */
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/** @file PL111Lcd.h
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Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef _PL111LCD_H__
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#define _PL111LCD_H__
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/**********************************************************************
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*
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* This header file contains all the bits of the PL111 that are
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* platform independent.
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*
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**********************************************************************/
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// Controller Register Offsets
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#define PL111_REG_LCD_TIMING_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x000)
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#define PL111_REG_LCD_TIMING_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x004)
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#define PL111_REG_LCD_TIMING_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x008)
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#define PL111_REG_LCD_TIMING_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x00C)
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#define PL111_REG_LCD_UP_BASE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x010)
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#define PL111_REG_LCD_LP_BASE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x014)
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#define PL111_REG_LCD_CONTROL ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x018)
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#define PL111_REG_LCD_IMSC ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x01C)
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#define PL111_REG_LCD_RIS ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x020)
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#define PL111_REG_LCD_MIS ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x024)
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#define PL111_REG_LCD_ICR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x028)
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#define PL111_REG_LCD_UP_CURR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x02C)
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#define PL111_REG_LCD_LP_CURR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x030)
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#define PL111_REG_LCD_PALETTE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x200)
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// Identification Register Offsets
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#define PL111_REG_CLCD_PERIPH_ID_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE0)
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#define PL111_REG_CLCD_PERIPH_ID_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE4)
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#define PL111_REG_CLCD_PERIPH_ID_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE8)
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#define PL111_REG_CLCD_PERIPH_ID_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFEC)
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#define PL111_REG_CLCD_P_CELL_ID_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF0)
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#define PL111_REG_CLCD_P_CELL_ID_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF4)
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#define PL111_REG_CLCD_P_CELL_ID_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF8)
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#define PL111_REG_CLCD_P_CELL_ID_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFFC)
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/**********************************************************************/
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// Register components (register bits)
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// This should make life easier to program specific settings in the different registers
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// by simplifying the setting up of the individual bits of each register
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// and then assembling the final register value.
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/**********************************************************************/
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// Register: PL111_REG_LCD_TIMING_0
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#define HOR_AXIS_PANEL(hbp,hfp,hsw,hor_res) (UINT32)(((UINT32)(hbp) << 24) | ((UINT32)(hfp) << 16) | ((UINT32)(hsw) << 8) | (((UINT32)((hor_res)/16)-1) << 2))
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// Register: PL111_REG_LCD_TIMING_1
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#define VER_AXIS_PANEL(vbp,vfp,vsw,ver_res) (UINT32)(((UINT32)(vbp) << 24) | ((UINT32)(vfp) << 16) | ((UINT32)(vsw) << 10) | ((ver_res)-1))
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// Register: PL111_REG_LCD_TIMING_2
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#define PL111_BIT_SHIFT_PCD_HI 27
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#define PL111_BIT_SHIFT_BCD 26
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#define PL111_BIT_SHIFT_CPL 16
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#define PL111_BIT_SHIFT_IOE 14
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#define PL111_BIT_SHIFT_IPC 13
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#define PL111_BIT_SHIFT_IHS 12
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#define PL111_BIT_SHIFT_IVS 11
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#define PL111_BIT_SHIFT_ACB 6
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#define PL111_BIT_SHIFT_CLKSEL 5
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#define PL111_BIT_SHIFT_PCD_LO 0
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#define PL111_BCD (1 << 26)
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#define PL111_IPC (1 << 13)
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#define PL111_IHS (1 << 12)
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#define PL111_IVS (1 << 11)
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#define CLK_SIG_POLARITY(hor_res) (UINT32)(PL111_BCD | PL111_IPC | PL111_IHS | PL111_IVS | (((hor_res)-1) << 16))
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// Register: PL111_REG_LCD_TIMING_3
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#define PL111_BIT_SHIFT_LEE 16
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#define PL111_BIT_SHIFT_LED 0
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#define PL111_CTRL_WATERMARK (1 << 16)
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#define PL111_CTRL_LCD_V_COMP (1 << 12)
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#define PL111_CTRL_LCD_PWR (1 << 11)
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#define PL111_CTRL_BEPO (1 << 10)
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#define PL111_CTRL_BEBO (1 << 9)
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#define PL111_CTRL_BGR (1 << 8)
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#define PL111_CTRL_LCD_DUAL (1 << 7)
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#define PL111_CTRL_LCD_MONO_8 (1 << 6)
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#define PL111_CTRL_LCD_TFT (1 << 5)
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#define PL111_CTRL_LCD_BW (1 << 4)
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#define PL111_CTRL_LCD_1BPP (0 << 1)
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#define PL111_CTRL_LCD_2BPP (1 << 1)
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#define PL111_CTRL_LCD_4BPP (2 << 1)
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#define PL111_CTRL_LCD_8BPP (3 << 1)
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#define PL111_CTRL_LCD_16BPP (4 << 1)
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#define PL111_CTRL_LCD_24BPP (5 << 1)
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#define PL111_CTRL_LCD_16BPP_565 (6 << 1)
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#define PL111_CTRL_LCD_12BPP_444 (7 << 1)
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#define PL111_CTRL_LCD_BPP(Bpp) ((Bpp) << 1)
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#define PL111_CTRL_LCD_EN 1
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/**********************************************************************/
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// Register: PL111_REG_LCD_TIMING_0
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#define PL111_LCD_TIMING_0_HBP(hbp) (((hbp) & 0xFF) << 24)
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#define PL111_LCD_TIMING_0_HFP(hfp) (((hfp) & 0xFF) << 16)
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#define PL111_LCD_TIMING_0_HSW(hsw) (((hsw) & 0xFF) << 8)
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#define PL111_LCD_TIMING_0_PPL(ppl) (((hsw) & 0x3F) << 2)
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// Register: PL111_REG_LCD_TIMING_1
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#define PL111_LCD_TIMING_1_VBP(vbp) (((vbp) & 0xFF) << 24)
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#define PL111_LCD_TIMING_1_VFP(vfp) (((vfp) & 0xFF) << 16)
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#define PL111_LCD_TIMING_1_VSW(vsw) (((vsw) & 0x3F) << 10)
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#define PL111_LCD_TIMING_1_LPP(lpp) ((lpp) & 0xFC)
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// Register: PL111_REG_LCD_TIMING_2
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#define PL111_BIT_MASK_PCD_HI 0xF8000000
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#define PL111_BIT_MASK_BCD 0x04000000
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#define PL111_BIT_MASK_CPL 0x03FF0000
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#define PL111_BIT_MASK_IOE 0x00004000
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#define PL111_BIT_MASK_IPC 0x00002000
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#define PL111_BIT_MASK_IHS 0x00001000
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#define PL111_BIT_MASK_IVS 0x00000800
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#define PL111_BIT_MASK_ACB 0x000007C0
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#define PL111_BIT_MASK_CLKSEL 0x00000020
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#define PL111_BIT_MASK_PCD_LO 0x0000001F
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// Register: PL111_REG_LCD_TIMING_3
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#define PL111_BIT_MASK_LEE 0x00010000
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#define PL111_BIT_MASK_LED 0x0000007F
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#endif /* _PL111LCD_H__ */
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@@ -1,21 +1,21 @@
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/** @file
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*
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* Copyright (c) 2011, ARM Limited. All rights reserved.
|
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*
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* This program and the accompanying materials
|
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* are licensed and made available under the terms and conditions of the BSD License
|
||||
* which accompanies this distribution. The full text of the license may be found at
|
||||
* http://opensource.org/licenses/bsd-license.php
|
||||
*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
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*
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**/
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#ifndef PL301AXI_H_
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#define PL301AXI_H_
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VOID PL301AxiInit(UINTN FAxiBase);
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#endif /* PL301AXI_H_ */
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/** @file
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*
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* Copyright (c) 2011, ARM Limited. All rights reserved.
|
||||
*
|
||||
* This program and the accompanying materials
|
||||
* are licensed and made available under the terms and conditions of the BSD License
|
||||
* which accompanies this distribution. The full text of the license may be found at
|
||||
* http://opensource.org/licenses/bsd-license.php
|
||||
*
|
||||
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
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*
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**/
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#ifndef PL301AXI_H_
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#define PL301AXI_H_
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VOID PL301AxiInit(UINTN FAxiBase);
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#endif /* PL301AXI_H_ */
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@@ -1,336 +1,336 @@
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/** @file
|
||||
*
|
||||
* Copyright (c) 2011, ARM Limited. All rights reserved.
|
||||
*
|
||||
* This program and the accompanying materials
|
||||
* are licensed and made available under the terms and conditions of the BSD License
|
||||
* which accompanies this distribution. The full text of the license may be found at
|
||||
* http://opensource.org/licenses/bsd-license.php
|
||||
*
|
||||
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
*
|
||||
**/
|
||||
|
||||
#ifndef _PL341DMC_H_
|
||||
#define _PL341DMC_H_
|
||||
|
||||
|
||||
typedef struct {
|
||||
UINTN HasQos; // has QoS registers
|
||||
UINTN MaxChip; // number of memory chips accessible
|
||||
BOOLEAN IsUserCfg;
|
||||
UINT32 User0Cfg;
|
||||
UINT32 User2Cfg;
|
||||
UINT32 RefreshPeriod;
|
||||
UINT32 CasLatency;
|
||||
UINT32 WriteLatency;
|
||||
UINT32 t_mrd;
|
||||
UINT32 t_ras;
|
||||
UINT32 t_rc;
|
||||
UINT32 t_rcd;
|
||||
UINT32 t_rfc;
|
||||
UINT32 t_rp;
|
||||
UINT32 t_rrd;
|
||||
UINT32 t_wr;
|
||||
UINT32 t_wtr;
|
||||
UINT32 t_xp;
|
||||
UINT32 t_xsr;
|
||||
UINT32 t_esr;
|
||||
UINT32 MemoryCfg;
|
||||
UINT32 MemoryCfg2;
|
||||
UINT32 MemoryCfg3;
|
||||
UINT32 ChipCfg0;
|
||||
UINT32 ChipCfg1;
|
||||
UINT32 ChipCfg2;
|
||||
UINT32 ChipCfg3;
|
||||
UINT32 t_faw;
|
||||
UINT32 t_data_en;
|
||||
UINT32 t_wdata_en;
|
||||
UINT32 ModeReg;
|
||||
UINT32 ExtModeReg;
|
||||
} PL341_DMC_CONFIG;
|
||||
|
||||
/* Memory config bit fields */
|
||||
#define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_9 0x1
|
||||
#define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_10 0x2
|
||||
#define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_11 0x3
|
||||
#define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_12 0x4
|
||||
#define DMC_MEMORY_CONFIG_ROW_ADDRESS_11 (0x0 << 3)
|
||||
#define DMC_MEMORY_CONFIG_ROW_ADDRESS_12 (0x1 << 3)
|
||||
#define DMC_MEMORY_CONFIG_ROW_ADDRESS_13 (0x2 << 3)
|
||||
#define DMC_MEMORY_CONFIG_ROW_ADDRESS_14 (0x3 << 3)
|
||||
#define DMC_MEMORY_CONFIG_ROW_ADDRESS_15 (0x4 << 3)
|
||||
#define DMC_MEMORY_CONFIG_ROW_ADDRESS_16 (0x5 << 3)
|
||||
#define DMC_MEMORY_CONFIG_BURST_2 (0x1 << 15)
|
||||
#define DMC_MEMORY_CONFIG_BURST_4 (0x2 << 15)
|
||||
#define DMC_MEMORY_CONFIG_BURST_8 (0x3 << 15)
|
||||
#define DMC_MEMORY_CONFIG_BURST_16 (0x4 << 15)
|
||||
#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_1 (0x0 << 21)
|
||||
#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_2 (0x1 << 21)
|
||||
#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_3 (0x2 << 21)
|
||||
#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_4 (0x3 << 21)
|
||||
|
||||
#define DMC_MEMORY_CFG2_CLK_ASYNC (0x0 << 0)
|
||||
#define DMC_MEMORY_CFG2_CLK_SYNC (0x1 << 0)
|
||||
#define DMC_MEMORY_CFG2_DQM_INIT (0x1 << 2)
|
||||
#define DMC_MEMORY_CFG2_CKE_INIT (0x1 << 3)
|
||||
#define DMC_MEMORY_CFG2_BANK_BITS_2 (0x0 << 4)
|
||||
#define DMC_MEMORY_CFG2_BANK_BITS_3 (0x3 << 4)
|
||||
#define DMC_MEMORY_CFG2_MEM_WIDTH_16 (0x0 << 6)
|
||||
#define DMC_MEMORY_CFG2_MEM_WIDTH_32 (0x1 << 6)
|
||||
#define DMC_MEMORY_CFG2_MEM_WIDTH_64 (0x2 << 6)
|
||||
#define DMC_MEMORY_CFG2_MEM_WIDTH_RESERVED (0x3 << 6)
|
||||
|
||||
//
|
||||
// DMC Configuration Register Map
|
||||
//
|
||||
#define DMC_STATUS_REG 0x00
|
||||
#define DMC_COMMAND_REG 0x04
|
||||
#define DMC_DIRECT_CMD_REG 0x08
|
||||
#define DMC_MEMORY_CONFIG_REG 0x0C
|
||||
#define DMC_REFRESH_PRD_REG 0x10
|
||||
#define DMC_CAS_LATENCY_REG 0x14
|
||||
#define DMC_WRITE_LATENCY_REG 0x18
|
||||
#define DMC_T_MRD_REG 0x1C
|
||||
#define DMC_T_RAS_REG 0x20
|
||||
#define DMC_T_RC_REG 0x24
|
||||
#define DMC_T_RCD_REG 0x28
|
||||
#define DMC_T_RFC_REG 0x2C
|
||||
#define DMC_T_RP_REG 0x30
|
||||
#define DMC_T_RRD_REG 0x34
|
||||
#define DMC_T_WR_REG 0x38
|
||||
#define DMC_T_WTR_REG 0x3C
|
||||
#define DMC_T_XP_REG 0x40
|
||||
#define DMC_T_XSR_REG 0x44
|
||||
#define DMC_T_ESR_REG 0x48
|
||||
#define DMC_MEMORY_CFG2_REG 0x4C
|
||||
#define DMC_MEMORY_CFG3_REG 0x50
|
||||
#define DMC_T_FAW_REG 0x54
|
||||
#define DMC_T_RDATA_EN 0x5C /* DFI read data enable register */
|
||||
#define DMC_T_WRLAT_DIFF 0x60 /* DFI write data enable register */
|
||||
|
||||
// Returns the state of the memory controller:
|
||||
#define DMC_STATUS_CONFIG 0x0
|
||||
#define DMC_STATUS_READY 0x1
|
||||
#define DMC_STATUS_PAUSED 0x2
|
||||
#define DMC_STATUS_LOWPOWER 0x3
|
||||
|
||||
// Changes the state of the memory controller:
|
||||
#define DMC_COMMAND_GO 0x0
|
||||
#define DMC_COMMAND_SLEEP 0x1
|
||||
#define DMC_COMMAND_WAKEUP 0x2
|
||||
#define DMC_COMMAND_PAUSE 0x3
|
||||
#define DMC_COMMAND_CONFIGURE 0x4
|
||||
#define DMC_COMMAND_ACTIVEPAUSE 0x7
|
||||
|
||||
// Determines the command required
|
||||
#define DMC_DIRECT_CMD_MEMCMD_PRECHARGEALL 0x0
|
||||
#define DMC_DIRECT_CMD_MEMCMD_AUTOREFRESH (0x1 << 18)
|
||||
#define DMC_DIRECT_CMD_MEMCMD_MODEREG (0x2 << 18)
|
||||
#define DMC_DIRECT_CMD_MEMCMD_EXTMODEREG (0x2 << 18)
|
||||
#define DMC_DIRECT_CMD_MEMCMD_NOP (0x3 << 18)
|
||||
#define DMC_DIRECT_CMD_MEMCMD_DPD (0x1 << 22)
|
||||
#define DMC_DIRECT_CMD_BANKADDR(n) ((n & 0x3) << 16)
|
||||
#define DMC_DIRECT_CMD_CHIP_ADDR(n) ((n & 0x3) << 20)
|
||||
|
||||
|
||||
//
|
||||
// AXI ID configuration register map
|
||||
//
|
||||
#define DMC_ID_0_CFG_REG 0x100
|
||||
#define DMC_ID_1_CFG_REG 0x104
|
||||
#define DMC_ID_2_CFG_REG 0x108
|
||||
#define DMC_ID_3_CFG_REG 0x10C
|
||||
#define DMC_ID_4_CFG_REG 0x110
|
||||
#define DMC_ID_5_CFG_REG 0x114
|
||||
#define DMC_ID_6_CFG_REG 0x118
|
||||
#define DMC_ID_7_CFG_REG 0x11C
|
||||
#define DMC_ID_8_CFG_REG 0x120
|
||||
#define DMC_ID_9_CFG_REG 0x124
|
||||
#define DMC_ID_10_CFG_REG 0x128
|
||||
#define DMC_ID_11_CFG_REG 0x12C
|
||||
#define DMC_ID_12_CFG_REG 0x130
|
||||
#define DMC_ID_13_CFG_REG 0x134
|
||||
#define DMC_ID_14_CFG_REG 0x138
|
||||
#define DMC_ID_15_CFG_REG 0x13C
|
||||
|
||||
// Set the QoS
|
||||
#define DMC_ID_CFG_QOS_DISABLE 0
|
||||
#define DMC_ID_CFG_QOS_ENABLE 1
|
||||
#define DMC_ID_CFG_QOS_MIN 2
|
||||
|
||||
|
||||
//
|
||||
// Chip configuration register map
|
||||
//
|
||||
#define DMC_CHIP_0_CFG_REG 0x200
|
||||
#define DMC_CHIP_1_CFG_REG 0x204
|
||||
#define DMC_CHIP_2_CFG_REG 0x208
|
||||
#define DMC_CHIP_3_CFG_REG 0x20C
|
||||
|
||||
//
|
||||
// User Defined Pins
|
||||
//
|
||||
#define DMC_USER_STATUS_REG 0x300
|
||||
#define DMC_USER_0_CFG_REG 0x304
|
||||
#define DMC_USER_1_CFG_REG 0x308
|
||||
#define DMC_FEATURE_CRTL_REG 0x30C
|
||||
#define DMC_USER_2_CFG_REG 0x310
|
||||
|
||||
|
||||
//
|
||||
// PHY Register Settings
|
||||
//
|
||||
#define PHY_PTM_DFI_CLK_RANGE 0xE00 // DDR2 PHY PTM register offset
|
||||
#define PHY_PTM_IOTERM 0xE04
|
||||
#define PHY_PTM_PLL_EN 0xe0c
|
||||
#define PHY_PTM_PLL_RANGE 0xe18
|
||||
#define PHY_PTM_FEEBACK_DIV 0xe1c
|
||||
#define PHY_PTM_RCLK_DIV 0xe20
|
||||
#define PHY_PTM_LOCK_STATUS 0xe28
|
||||
#define PHY_PTM_INIT_DONE 0xe34
|
||||
#define PHY_PTM_ADDCOM_IOSTR_OFF 0xec8
|
||||
#define PHY_PTM_SQU_TRAINING 0xee8
|
||||
#define PHY_PTM_SQU_STAT 0xeec
|
||||
|
||||
// ==============================================================================
|
||||
// PIPD 40G DDR2/DDR3 PHY Register definitions
|
||||
//
|
||||
// Offsets from APB Base Address
|
||||
// ==============================================================================
|
||||
#define PHY_BYTE0_OFFSET 0x000
|
||||
#define PHY_BYTE1_OFFSET 0x200
|
||||
#define PHY_BYTE2_OFFSET 0x400
|
||||
#define PHY_BYTE3_OFFSET 0x600
|
||||
|
||||
#define PHY_BYTE0_COARSE_SQADJ_INIT 0x064 ;// Coarse squelch adjust
|
||||
#define PHY_BYTE1_COARSE_SQADJ_INIT 0x264 ;// Coarse squelch adjust
|
||||
#define PHY_BYTE2_COARSE_SQADJ_INIT 0x464 ;// Coarse squelch adjust
|
||||
#define PHY_BYTE3_COARSE_SQADJ_INIT 0x664 ;// Coarse squelch adjust
|
||||
|
||||
#define PHY_BYTE0_IOSTR_OFFSET 0x004
|
||||
#define PHY_BYTE1_IOSTR_OFFSET 0x204
|
||||
#define PHY_BYTE2_IOSTR_OFFSET 0x404
|
||||
#define PHY_BYTE3_IOSTR_OFFSET 0x604
|
||||
|
||||
|
||||
;//--------------------------------------------------------------------------
|
||||
|
||||
// DFI Clock ranges:
|
||||
|
||||
#define PHY_PTM_DFI_CLK_RANGE_200MHz 0x0
|
||||
#define PHY_PTM_DFI_CLK_RANGE_201_267MHz 0x1
|
||||
#define PHY_PTM_DFI_CLK_RANGE_268_333MHz 0x2
|
||||
#define PHY_PTM_DFI_CLK_RANGE_334_400MHz 0x3
|
||||
#define PHY_PTM_DFI_CLK_RANGE_401_533MHz 0x4
|
||||
#define PHY_PTM_DFI_CLK_RANGE_534_667MHz 0x5
|
||||
#define PHY_PTM_DFI_CLK_RANGE_668_800MHz 0x6
|
||||
|
||||
|
||||
|
||||
#define PHY_PTM_DFI_CLK_RANGE_VAL PHY_PTM_DFI_CLK_RANGE_334_400MHz
|
||||
|
||||
//--------------------------------------------------------------------------
|
||||
|
||||
|
||||
// PLL Range
|
||||
|
||||
#define PHY_PTM_PLL_RANGE_200_400MHz 0x0 // b0 = frequency >= 200 MHz and < 400 MHz
|
||||
#define PHY_PTM_PLL_RANGE_400_800MHz 0x1 // b1 = frequency >= 400 MHz.
|
||||
#define PHY_PTM_FEEBACK_DIV_200_400MHz 0x0 // b0 = frequency >= 200 MHz and < 400 MHz
|
||||
#define PHY_PTM_FEEBACK_DIV_400_800MHz 0x1 // b1 = frequency >= 400 MHz.
|
||||
#define PHY_PTM_REFCLK_DIV_200_400MHz 0x0
|
||||
#define PHY_PTM_REFCLK_DIV_400_800MHz 0x1
|
||||
|
||||
#define TC_UIOLHNC_MASK 0x000003C0
|
||||
#define TC_UIOLHNC_SHIFT 0x6
|
||||
#define TC_UIOLHPC_MASK 0x0000003F
|
||||
#define TC_UIOLHPC_SHIFT 0x2
|
||||
#define TC_UIOHOCT_MASK 0x2
|
||||
#define TC_UIOHOCT_SHIFT 0x1
|
||||
#define TC_UIOHSTOP_SHIFT 0x0
|
||||
#define TC_UIOLHXC_VALUE 0x4
|
||||
|
||||
#define PHY_PTM_SQU_TRAINING_ENABLE 0x1
|
||||
#define PHY_PTM_SQU_TRAINING_DISABLE 0x0
|
||||
|
||||
|
||||
//--------------------------------------
|
||||
// JEDEC DDR2 Device Register definitions and settings
|
||||
//--------------------------------------
|
||||
#define DDR_MODESET_SHFT 14
|
||||
#define DDR_MODESET_MR 0x0 ;// Mode register
|
||||
#define DDR_MODESET_EMR 0x1 ;// Extended Mode register
|
||||
#define DDR_MODESET_EMR2 0x2
|
||||
#define DDR_MODESET_EMR3 0x3
|
||||
|
||||
//
|
||||
// Extended Mode Register settings
|
||||
//
|
||||
#define DDR_EMR_OCD_MASK 0x0000380
|
||||
#define DDR_EMR_OCD_SHIFT 0x7
|
||||
#define DDR_EMR_RTT_MASK 0x00000044 // DDR2 Device RTT (ODT) settings
|
||||
#define DDR_EMR_RTT_SHIFT 0x2
|
||||
#define DDR_EMR_ODS_MASK 0x00000002 // DDR2 Output Drive Strength
|
||||
#define DDR_EMR_ODS_SHIFT 0x0001
|
||||
|
||||
// Termination Values:
|
||||
#define DDR_EMR_RTT_50R 0x00000044 // DDR2 50 Ohm termination
|
||||
#define DDR_EMR_RTT_75R 0x00000004 // DDR2 75 Ohm termination
|
||||
#define DDR_EMR_RTT_150 0x00000040 // DDR2 150 Ohm termination
|
||||
|
||||
// Output Drive Strength Values:
|
||||
#define DDR_EMR_ODS_FULL 0x0 // DDR2 Full Drive Strength
|
||||
#define DDR_EMR_ODS_HALF 0x1 // DDR2 Half Drive Strength
|
||||
|
||||
// OCD values
|
||||
#define DDR_EMR_OCD_DEFAULT 0x7
|
||||
#define DDR_EMR_OCD_NS 0x0
|
||||
|
||||
#define DDR_EMR_ODS_VAL DDR_EMR_ODS_FULL
|
||||
|
||||
#define DDR_SDRAM_START_ADDR 0x10000000
|
||||
|
||||
|
||||
// ----------------------------------------
|
||||
// PHY IOTERM values
|
||||
// ----------------------------------------
|
||||
#define PHY_PTM_IOTERM_OFF 0x0
|
||||
#define PHY_PTM_IOTERM_150R 0x1
|
||||
#define PHY_PTM_IOTERM_75R 0x2
|
||||
#define PHY_PTM_IOTERM_50R 0x3
|
||||
|
||||
#define PHY_BYTE_IOSTR_60OHM 0x0
|
||||
#define PHY_BYTE_IOSTR_40OHM 0x1
|
||||
#define PHY_BYTE_IOSTR_30OHM 0x2
|
||||
#define PHY_BYTE_IOSTR_30AOHM 0x3
|
||||
|
||||
#define DDR2_MR_BURST_LENGTH_4 (2)
|
||||
#define DDR2_MR_BURST_LENGTH_8 (3)
|
||||
#define DDR2_MR_DLL_RESET (1 << 8)
|
||||
#define DDR2_MR_CAS_LATENCY_4 (4 << 4)
|
||||
#define DDR2_MR_CAS_LATENCY_5 (5 << 4)
|
||||
#define DDR2_MR_CAS_LATENCY_6 (6 << 4)
|
||||
#define DDR2_MR_WR_CYCLES_2 (1 << 9)
|
||||
#define DDR2_MR_WR_CYCLES_3 (2 << 9)
|
||||
#define DDR2_MR_WR_CYCLES_4 (3 << 9)
|
||||
#define DDR2_MR_WR_CYCLES_5 (4 << 9)
|
||||
#define DDR2_MR_WR_CYCLES_6 (5 << 9)
|
||||
|
||||
|
||||
VOID
|
||||
PL341DmcInit (
|
||||
IN UINTN DmcBase,
|
||||
IN PL341_DMC_CONFIG* DmcConfig
|
||||
);
|
||||
|
||||
VOID PL341DmcPhyInit (
|
||||
IN UINTN DmcPhyBase
|
||||
);
|
||||
|
||||
VOID PL341DmcTrainPHY (
|
||||
IN UINTN DmcPhyBase
|
||||
);
|
||||
|
||||
#endif /* _PL341DMC_H_ */
|
||||
/** @file
|
||||
*
|
||||
* Copyright (c) 2011, ARM Limited. All rights reserved.
|
||||
*
|
||||
* This program and the accompanying materials
|
||||
* are licensed and made available under the terms and conditions of the BSD License
|
||||
* which accompanies this distribution. The full text of the license may be found at
|
||||
* http://opensource.org/licenses/bsd-license.php
|
||||
*
|
||||
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
*
|
||||
**/
|
||||
|
||||
#ifndef _PL341DMC_H_
|
||||
#define _PL341DMC_H_
|
||||
|
||||
|
||||
typedef struct {
|
||||
UINTN HasQos; // has QoS registers
|
||||
UINTN MaxChip; // number of memory chips accessible
|
||||
BOOLEAN IsUserCfg;
|
||||
UINT32 User0Cfg;
|
||||
UINT32 User2Cfg;
|
||||
UINT32 RefreshPeriod;
|
||||
UINT32 CasLatency;
|
||||
UINT32 WriteLatency;
|
||||
UINT32 t_mrd;
|
||||
UINT32 t_ras;
|
||||
UINT32 t_rc;
|
||||
UINT32 t_rcd;
|
||||
UINT32 t_rfc;
|
||||
UINT32 t_rp;
|
||||
UINT32 t_rrd;
|
||||
UINT32 t_wr;
|
||||
UINT32 t_wtr;
|
||||
UINT32 t_xp;
|
||||
UINT32 t_xsr;
|
||||
UINT32 t_esr;
|
||||
UINT32 MemoryCfg;
|
||||
UINT32 MemoryCfg2;
|
||||
UINT32 MemoryCfg3;
|
||||
UINT32 ChipCfg0;
|
||||
UINT32 ChipCfg1;
|
||||
UINT32 ChipCfg2;
|
||||
UINT32 ChipCfg3;
|
||||
UINT32 t_faw;
|
||||
UINT32 t_data_en;
|
||||
UINT32 t_wdata_en;
|
||||
UINT32 ModeReg;
|
||||
UINT32 ExtModeReg;
|
||||
} PL341_DMC_CONFIG;
|
||||
|
||||
/* Memory config bit fields */
|
||||
#define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_9 0x1
|
||||
#define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_10 0x2
|
||||
#define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_11 0x3
|
||||
#define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_12 0x4
|
||||
#define DMC_MEMORY_CONFIG_ROW_ADDRESS_11 (0x0 << 3)
|
||||
#define DMC_MEMORY_CONFIG_ROW_ADDRESS_12 (0x1 << 3)
|
||||
#define DMC_MEMORY_CONFIG_ROW_ADDRESS_13 (0x2 << 3)
|
||||
#define DMC_MEMORY_CONFIG_ROW_ADDRESS_14 (0x3 << 3)
|
||||
#define DMC_MEMORY_CONFIG_ROW_ADDRESS_15 (0x4 << 3)
|
||||
#define DMC_MEMORY_CONFIG_ROW_ADDRESS_16 (0x5 << 3)
|
||||
#define DMC_MEMORY_CONFIG_BURST_2 (0x1 << 15)
|
||||
#define DMC_MEMORY_CONFIG_BURST_4 (0x2 << 15)
|
||||
#define DMC_MEMORY_CONFIG_BURST_8 (0x3 << 15)
|
||||
#define DMC_MEMORY_CONFIG_BURST_16 (0x4 << 15)
|
||||
#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_1 (0x0 << 21)
|
||||
#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_2 (0x1 << 21)
|
||||
#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_3 (0x2 << 21)
|
||||
#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_4 (0x3 << 21)
|
||||
|
||||
#define DMC_MEMORY_CFG2_CLK_ASYNC (0x0 << 0)
|
||||
#define DMC_MEMORY_CFG2_CLK_SYNC (0x1 << 0)
|
||||
#define DMC_MEMORY_CFG2_DQM_INIT (0x1 << 2)
|
||||
#define DMC_MEMORY_CFG2_CKE_INIT (0x1 << 3)
|
||||
#define DMC_MEMORY_CFG2_BANK_BITS_2 (0x0 << 4)
|
||||
#define DMC_MEMORY_CFG2_BANK_BITS_3 (0x3 << 4)
|
||||
#define DMC_MEMORY_CFG2_MEM_WIDTH_16 (0x0 << 6)
|
||||
#define DMC_MEMORY_CFG2_MEM_WIDTH_32 (0x1 << 6)
|
||||
#define DMC_MEMORY_CFG2_MEM_WIDTH_64 (0x2 << 6)
|
||||
#define DMC_MEMORY_CFG2_MEM_WIDTH_RESERVED (0x3 << 6)
|
||||
|
||||
//
|
||||
// DMC Configuration Register Map
|
||||
//
|
||||
#define DMC_STATUS_REG 0x00
|
||||
#define DMC_COMMAND_REG 0x04
|
||||
#define DMC_DIRECT_CMD_REG 0x08
|
||||
#define DMC_MEMORY_CONFIG_REG 0x0C
|
||||
#define DMC_REFRESH_PRD_REG 0x10
|
||||
#define DMC_CAS_LATENCY_REG 0x14
|
||||
#define DMC_WRITE_LATENCY_REG 0x18
|
||||
#define DMC_T_MRD_REG 0x1C
|
||||
#define DMC_T_RAS_REG 0x20
|
||||
#define DMC_T_RC_REG 0x24
|
||||
#define DMC_T_RCD_REG 0x28
|
||||
#define DMC_T_RFC_REG 0x2C
|
||||
#define DMC_T_RP_REG 0x30
|
||||
#define DMC_T_RRD_REG 0x34
|
||||
#define DMC_T_WR_REG 0x38
|
||||
#define DMC_T_WTR_REG 0x3C
|
||||
#define DMC_T_XP_REG 0x40
|
||||
#define DMC_T_XSR_REG 0x44
|
||||
#define DMC_T_ESR_REG 0x48
|
||||
#define DMC_MEMORY_CFG2_REG 0x4C
|
||||
#define DMC_MEMORY_CFG3_REG 0x50
|
||||
#define DMC_T_FAW_REG 0x54
|
||||
#define DMC_T_RDATA_EN 0x5C /* DFI read data enable register */
|
||||
#define DMC_T_WRLAT_DIFF 0x60 /* DFI write data enable register */
|
||||
|
||||
// Returns the state of the memory controller:
|
||||
#define DMC_STATUS_CONFIG 0x0
|
||||
#define DMC_STATUS_READY 0x1
|
||||
#define DMC_STATUS_PAUSED 0x2
|
||||
#define DMC_STATUS_LOWPOWER 0x3
|
||||
|
||||
// Changes the state of the memory controller:
|
||||
#define DMC_COMMAND_GO 0x0
|
||||
#define DMC_COMMAND_SLEEP 0x1
|
||||
#define DMC_COMMAND_WAKEUP 0x2
|
||||
#define DMC_COMMAND_PAUSE 0x3
|
||||
#define DMC_COMMAND_CONFIGURE 0x4
|
||||
#define DMC_COMMAND_ACTIVEPAUSE 0x7
|
||||
|
||||
// Determines the command required
|
||||
#define DMC_DIRECT_CMD_MEMCMD_PRECHARGEALL 0x0
|
||||
#define DMC_DIRECT_CMD_MEMCMD_AUTOREFRESH (0x1 << 18)
|
||||
#define DMC_DIRECT_CMD_MEMCMD_MODEREG (0x2 << 18)
|
||||
#define DMC_DIRECT_CMD_MEMCMD_EXTMODEREG (0x2 << 18)
|
||||
#define DMC_DIRECT_CMD_MEMCMD_NOP (0x3 << 18)
|
||||
#define DMC_DIRECT_CMD_MEMCMD_DPD (0x1 << 22)
|
||||
#define DMC_DIRECT_CMD_BANKADDR(n) ((n & 0x3) << 16)
|
||||
#define DMC_DIRECT_CMD_CHIP_ADDR(n) ((n & 0x3) << 20)
|
||||
|
||||
|
||||
//
|
||||
// AXI ID configuration register map
|
||||
//
|
||||
#define DMC_ID_0_CFG_REG 0x100
|
||||
#define DMC_ID_1_CFG_REG 0x104
|
||||
#define DMC_ID_2_CFG_REG 0x108
|
||||
#define DMC_ID_3_CFG_REG 0x10C
|
||||
#define DMC_ID_4_CFG_REG 0x110
|
||||
#define DMC_ID_5_CFG_REG 0x114
|
||||
#define DMC_ID_6_CFG_REG 0x118
|
||||
#define DMC_ID_7_CFG_REG 0x11C
|
||||
#define DMC_ID_8_CFG_REG 0x120
|
||||
#define DMC_ID_9_CFG_REG 0x124
|
||||
#define DMC_ID_10_CFG_REG 0x128
|
||||
#define DMC_ID_11_CFG_REG 0x12C
|
||||
#define DMC_ID_12_CFG_REG 0x130
|
||||
#define DMC_ID_13_CFG_REG 0x134
|
||||
#define DMC_ID_14_CFG_REG 0x138
|
||||
#define DMC_ID_15_CFG_REG 0x13C
|
||||
|
||||
// Set the QoS
|
||||
#define DMC_ID_CFG_QOS_DISABLE 0
|
||||
#define DMC_ID_CFG_QOS_ENABLE 1
|
||||
#define DMC_ID_CFG_QOS_MIN 2
|
||||
|
||||
|
||||
//
|
||||
// Chip configuration register map
|
||||
//
|
||||
#define DMC_CHIP_0_CFG_REG 0x200
|
||||
#define DMC_CHIP_1_CFG_REG 0x204
|
||||
#define DMC_CHIP_2_CFG_REG 0x208
|
||||
#define DMC_CHIP_3_CFG_REG 0x20C
|
||||
|
||||
//
|
||||
// User Defined Pins
|
||||
//
|
||||
#define DMC_USER_STATUS_REG 0x300
|
||||
#define DMC_USER_0_CFG_REG 0x304
|
||||
#define DMC_USER_1_CFG_REG 0x308
|
||||
#define DMC_FEATURE_CRTL_REG 0x30C
|
||||
#define DMC_USER_2_CFG_REG 0x310
|
||||
|
||||
|
||||
//
|
||||
// PHY Register Settings
|
||||
//
|
||||
#define PHY_PTM_DFI_CLK_RANGE 0xE00 // DDR2 PHY PTM register offset
|
||||
#define PHY_PTM_IOTERM 0xE04
|
||||
#define PHY_PTM_PLL_EN 0xe0c
|
||||
#define PHY_PTM_PLL_RANGE 0xe18
|
||||
#define PHY_PTM_FEEBACK_DIV 0xe1c
|
||||
#define PHY_PTM_RCLK_DIV 0xe20
|
||||
#define PHY_PTM_LOCK_STATUS 0xe28
|
||||
#define PHY_PTM_INIT_DONE 0xe34
|
||||
#define PHY_PTM_ADDCOM_IOSTR_OFF 0xec8
|
||||
#define PHY_PTM_SQU_TRAINING 0xee8
|
||||
#define PHY_PTM_SQU_STAT 0xeec
|
||||
|
||||
// ==============================================================================
|
||||
// PIPD 40G DDR2/DDR3 PHY Register definitions
|
||||
//
|
||||
// Offsets from APB Base Address
|
||||
// ==============================================================================
|
||||
#define PHY_BYTE0_OFFSET 0x000
|
||||
#define PHY_BYTE1_OFFSET 0x200
|
||||
#define PHY_BYTE2_OFFSET 0x400
|
||||
#define PHY_BYTE3_OFFSET 0x600
|
||||
|
||||
#define PHY_BYTE0_COARSE_SQADJ_INIT 0x064 ;// Coarse squelch adjust
|
||||
#define PHY_BYTE1_COARSE_SQADJ_INIT 0x264 ;// Coarse squelch adjust
|
||||
#define PHY_BYTE2_COARSE_SQADJ_INIT 0x464 ;// Coarse squelch adjust
|
||||
#define PHY_BYTE3_COARSE_SQADJ_INIT 0x664 ;// Coarse squelch adjust
|
||||
|
||||
#define PHY_BYTE0_IOSTR_OFFSET 0x004
|
||||
#define PHY_BYTE1_IOSTR_OFFSET 0x204
|
||||
#define PHY_BYTE2_IOSTR_OFFSET 0x404
|
||||
#define PHY_BYTE3_IOSTR_OFFSET 0x604
|
||||
|
||||
|
||||
;//--------------------------------------------------------------------------
|
||||
|
||||
// DFI Clock ranges:
|
||||
|
||||
#define PHY_PTM_DFI_CLK_RANGE_200MHz 0x0
|
||||
#define PHY_PTM_DFI_CLK_RANGE_201_267MHz 0x1
|
||||
#define PHY_PTM_DFI_CLK_RANGE_268_333MHz 0x2
|
||||
#define PHY_PTM_DFI_CLK_RANGE_334_400MHz 0x3
|
||||
#define PHY_PTM_DFI_CLK_RANGE_401_533MHz 0x4
|
||||
#define PHY_PTM_DFI_CLK_RANGE_534_667MHz 0x5
|
||||
#define PHY_PTM_DFI_CLK_RANGE_668_800MHz 0x6
|
||||
|
||||
|
||||
|
||||
#define PHY_PTM_DFI_CLK_RANGE_VAL PHY_PTM_DFI_CLK_RANGE_334_400MHz
|
||||
|
||||
//--------------------------------------------------------------------------
|
||||
|
||||
|
||||
// PLL Range
|
||||
|
||||
#define PHY_PTM_PLL_RANGE_200_400MHz 0x0 // b0 = frequency >= 200 MHz and < 400 MHz
|
||||
#define PHY_PTM_PLL_RANGE_400_800MHz 0x1 // b1 = frequency >= 400 MHz.
|
||||
#define PHY_PTM_FEEBACK_DIV_200_400MHz 0x0 // b0 = frequency >= 200 MHz and < 400 MHz
|
||||
#define PHY_PTM_FEEBACK_DIV_400_800MHz 0x1 // b1 = frequency >= 400 MHz.
|
||||
#define PHY_PTM_REFCLK_DIV_200_400MHz 0x0
|
||||
#define PHY_PTM_REFCLK_DIV_400_800MHz 0x1
|
||||
|
||||
#define TC_UIOLHNC_MASK 0x000003C0
|
||||
#define TC_UIOLHNC_SHIFT 0x6
|
||||
#define TC_UIOLHPC_MASK 0x0000003F
|
||||
#define TC_UIOLHPC_SHIFT 0x2
|
||||
#define TC_UIOHOCT_MASK 0x2
|
||||
#define TC_UIOHOCT_SHIFT 0x1
|
||||
#define TC_UIOHSTOP_SHIFT 0x0
|
||||
#define TC_UIOLHXC_VALUE 0x4
|
||||
|
||||
#define PHY_PTM_SQU_TRAINING_ENABLE 0x1
|
||||
#define PHY_PTM_SQU_TRAINING_DISABLE 0x0
|
||||
|
||||
|
||||
//--------------------------------------
|
||||
// JEDEC DDR2 Device Register definitions and settings
|
||||
//--------------------------------------
|
||||
#define DDR_MODESET_SHFT 14
|
||||
#define DDR_MODESET_MR 0x0 ;// Mode register
|
||||
#define DDR_MODESET_EMR 0x1 ;// Extended Mode register
|
||||
#define DDR_MODESET_EMR2 0x2
|
||||
#define DDR_MODESET_EMR3 0x3
|
||||
|
||||
//
|
||||
// Extended Mode Register settings
|
||||
//
|
||||
#define DDR_EMR_OCD_MASK 0x0000380
|
||||
#define DDR_EMR_OCD_SHIFT 0x7
|
||||
#define DDR_EMR_RTT_MASK 0x00000044 // DDR2 Device RTT (ODT) settings
|
||||
#define DDR_EMR_RTT_SHIFT 0x2
|
||||
#define DDR_EMR_ODS_MASK 0x00000002 // DDR2 Output Drive Strength
|
||||
#define DDR_EMR_ODS_SHIFT 0x0001
|
||||
|
||||
// Termination Values:
|
||||
#define DDR_EMR_RTT_50R 0x00000044 // DDR2 50 Ohm termination
|
||||
#define DDR_EMR_RTT_75R 0x00000004 // DDR2 75 Ohm termination
|
||||
#define DDR_EMR_RTT_150 0x00000040 // DDR2 150 Ohm termination
|
||||
|
||||
// Output Drive Strength Values:
|
||||
#define DDR_EMR_ODS_FULL 0x0 // DDR2 Full Drive Strength
|
||||
#define DDR_EMR_ODS_HALF 0x1 // DDR2 Half Drive Strength
|
||||
|
||||
// OCD values
|
||||
#define DDR_EMR_OCD_DEFAULT 0x7
|
||||
#define DDR_EMR_OCD_NS 0x0
|
||||
|
||||
#define DDR_EMR_ODS_VAL DDR_EMR_ODS_FULL
|
||||
|
||||
#define DDR_SDRAM_START_ADDR 0x10000000
|
||||
|
||||
|
||||
// ----------------------------------------
|
||||
// PHY IOTERM values
|
||||
// ----------------------------------------
|
||||
#define PHY_PTM_IOTERM_OFF 0x0
|
||||
#define PHY_PTM_IOTERM_150R 0x1
|
||||
#define PHY_PTM_IOTERM_75R 0x2
|
||||
#define PHY_PTM_IOTERM_50R 0x3
|
||||
|
||||
#define PHY_BYTE_IOSTR_60OHM 0x0
|
||||
#define PHY_BYTE_IOSTR_40OHM 0x1
|
||||
#define PHY_BYTE_IOSTR_30OHM 0x2
|
||||
#define PHY_BYTE_IOSTR_30AOHM 0x3
|
||||
|
||||
#define DDR2_MR_BURST_LENGTH_4 (2)
|
||||
#define DDR2_MR_BURST_LENGTH_8 (3)
|
||||
#define DDR2_MR_DLL_RESET (1 << 8)
|
||||
#define DDR2_MR_CAS_LATENCY_4 (4 << 4)
|
||||
#define DDR2_MR_CAS_LATENCY_5 (5 << 4)
|
||||
#define DDR2_MR_CAS_LATENCY_6 (6 << 4)
|
||||
#define DDR2_MR_WR_CYCLES_2 (1 << 9)
|
||||
#define DDR2_MR_WR_CYCLES_3 (2 << 9)
|
||||
#define DDR2_MR_WR_CYCLES_4 (3 << 9)
|
||||
#define DDR2_MR_WR_CYCLES_5 (4 << 9)
|
||||
#define DDR2_MR_WR_CYCLES_6 (5 << 9)
|
||||
|
||||
|
||||
VOID
|
||||
PL341DmcInit (
|
||||
IN UINTN DmcBase,
|
||||
IN PL341_DMC_CONFIG* DmcConfig
|
||||
);
|
||||
|
||||
VOID PL341DmcPhyInit (
|
||||
IN UINTN DmcPhyBase
|
||||
);
|
||||
|
||||
VOID PL341DmcTrainPHY (
|
||||
IN UINTN DmcPhyBase
|
||||
);
|
||||
|
||||
#endif /* _PL341DMC_H_ */
|
||||
|
||||
@@ -1,48 +1,48 @@
|
||||
/** @file
|
||||
*
|
||||
* Copyright (c) 2011, ARM Limited. All rights reserved.
|
||||
*
|
||||
* This program and the accompanying materials
|
||||
* are licensed and made available under the terms and conditions of the BSD License
|
||||
* which accompanies this distribution. The full text of the license may be found at
|
||||
* http://opensource.org/licenses/bsd-license.php
|
||||
*
|
||||
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
*
|
||||
**/
|
||||
|
||||
#ifndef __ARM_GLOBAL_VARIABLE_GUID_H__
|
||||
#define __ARM_GLOBAL_VARIABLE_GUID_H__
|
||||
|
||||
#define ARM_HOB_GLOBAL_VARIABLE_GUID \
|
||||
{ 0xc3253c90, 0xa24f, 0x4599, { 0xa6, 0x64, 0x1f, 0x88, 0x13, 0x77, 0x8f, 0xc9} };
|
||||
|
||||
extern EFI_GUID gArmGlobalVariableGuid;
|
||||
|
||||
///
|
||||
/// Describes all memory ranges used during the HOB producer
|
||||
/// phase that exist outside the HOB list. This HOB type
|
||||
/// describes how memory is used, not the physical attributes of memory.
|
||||
///
|
||||
typedef struct {
|
||||
///
|
||||
/// The Guid HOB header. Header.HobType = EFI_HOB_TYPE_GUID_EXTENSION
|
||||
/// and Header.Name = gArmGlobalVariableGuid
|
||||
///
|
||||
EFI_HOB_GUID_TYPE Header;
|
||||
|
||||
///
|
||||
/// The base address of memory allocated by this HOB. Type
|
||||
/// EFI_PHYSICAL_ADDRESS is defined in AllocatePages() in the UEFI 2.0
|
||||
/// specification.
|
||||
///
|
||||
EFI_PHYSICAL_ADDRESS GlobalVariableBase;
|
||||
|
||||
///
|
||||
/// The length in bytes of memory allocated by this HOB.
|
||||
///
|
||||
UINT32 GlobalVariableSize;
|
||||
} ARM_HOB_GLOBAL_VARIABLE;
|
||||
|
||||
#endif
|
||||
/** @file
|
||||
*
|
||||
* Copyright (c) 2011, ARM Limited. All rights reserved.
|
||||
*
|
||||
* This program and the accompanying materials
|
||||
* are licensed and made available under the terms and conditions of the BSD License
|
||||
* which accompanies this distribution. The full text of the license may be found at
|
||||
* http://opensource.org/licenses/bsd-license.php
|
||||
*
|
||||
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
*
|
||||
**/
|
||||
|
||||
#ifndef __ARM_GLOBAL_VARIABLE_GUID_H__
|
||||
#define __ARM_GLOBAL_VARIABLE_GUID_H__
|
||||
|
||||
#define ARM_HOB_GLOBAL_VARIABLE_GUID \
|
||||
{ 0xc3253c90, 0xa24f, 0x4599, { 0xa6, 0x64, 0x1f, 0x88, 0x13, 0x77, 0x8f, 0xc9} };
|
||||
|
||||
extern EFI_GUID gArmGlobalVariableGuid;
|
||||
|
||||
///
|
||||
/// Describes all memory ranges used during the HOB producer
|
||||
/// phase that exist outside the HOB list. This HOB type
|
||||
/// describes how memory is used, not the physical attributes of memory.
|
||||
///
|
||||
typedef struct {
|
||||
///
|
||||
/// The Guid HOB header. Header.HobType = EFI_HOB_TYPE_GUID_EXTENSION
|
||||
/// and Header.Name = gArmGlobalVariableGuid
|
||||
///
|
||||
EFI_HOB_GUID_TYPE Header;
|
||||
|
||||
///
|
||||
/// The base address of memory allocated by this HOB. Type
|
||||
/// EFI_PHYSICAL_ADDRESS is defined in AllocatePages() in the UEFI 2.0
|
||||
/// specification.
|
||||
///
|
||||
EFI_PHYSICAL_ADDRESS GlobalVariableBase;
|
||||
|
||||
///
|
||||
/// The length in bytes of memory allocated by this HOB.
|
||||
///
|
||||
UINT32 GlobalVariableSize;
|
||||
} ARM_HOB_GLOBAL_VARIABLE;
|
||||
|
||||
#endif
|
||||
|
||||
@@ -1,38 +1,38 @@
|
||||
/** @file
|
||||
*
|
||||
* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
|
||||
*
|
||||
* This program and the accompanying materials
|
||||
* are licensed and made available under the terms and conditions of the BSD License
|
||||
* which accompanies this distribution. The full text of the license may be found at
|
||||
* http://opensource.org/licenses/bsd-license.php
|
||||
*
|
||||
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
*
|
||||
**/
|
||||
|
||||
#ifndef __ARM_PLATFORM_GLOBAL_VARIABLE_LIB_H_
|
||||
#define __ARM_PLATFORM_GLOBAL_VARIABLE_LIB_H_
|
||||
|
||||
VOID
|
||||
ArmPlatformGetGlobalVariable (
|
||||
IN UINTN VariableOffset,
|
||||
IN UINTN VariableSize,
|
||||
OUT VOID* Variable
|
||||
);
|
||||
|
||||
VOID
|
||||
ArmPlatformSetGlobalVariable (
|
||||
IN UINTN VariableOffset,
|
||||
IN UINTN VariableSize,
|
||||
OUT VOID* Variable
|
||||
);
|
||||
|
||||
VOID*
|
||||
ArmPlatformGetGlobalVariableAddress (
|
||||
IN UINTN VariableOffset
|
||||
);
|
||||
|
||||
#endif
|
||||
|
||||
/** @file
|
||||
*
|
||||
* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
|
||||
*
|
||||
* This program and the accompanying materials
|
||||
* are licensed and made available under the terms and conditions of the BSD License
|
||||
* which accompanies this distribution. The full text of the license may be found at
|
||||
* http://opensource.org/licenses/bsd-license.php
|
||||
*
|
||||
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
*
|
||||
**/
|
||||
|
||||
#ifndef __ARM_PLATFORM_GLOBAL_VARIABLE_LIB_H_
|
||||
#define __ARM_PLATFORM_GLOBAL_VARIABLE_LIB_H_
|
||||
|
||||
VOID
|
||||
ArmPlatformGetGlobalVariable (
|
||||
IN UINTN VariableOffset,
|
||||
IN UINTN VariableSize,
|
||||
OUT VOID* Variable
|
||||
);
|
||||
|
||||
VOID
|
||||
ArmPlatformSetGlobalVariable (
|
||||
IN UINTN VariableOffset,
|
||||
IN UINTN VariableSize,
|
||||
OUT VOID* Variable
|
||||
);
|
||||
|
||||
VOID*
|
||||
ArmPlatformGetGlobalVariableAddress (
|
||||
IN UINTN VariableOffset
|
||||
);
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
@@ -1,131 +1,131 @@
|
||||
/** @file
|
||||
*
|
||||
* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
|
||||
*
|
||||
* This program and the accompanying materials
|
||||
* are licensed and made available under the terms and conditions of the BSD License
|
||||
* which accompanies this distribution. The full text of the license may be found at
|
||||
* http://opensource.org/licenses/bsd-license.php
|
||||
*
|
||||
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
*
|
||||
**/
|
||||
|
||||
#ifndef _ARMPLATFORMLIB_H_
|
||||
#define _ARMPLATFORMLIB_H_
|
||||
|
||||
//
|
||||
// The package level header files this module uses
|
||||
//
|
||||
#include <PiPei.h>
|
||||
//
|
||||
// The protocols, PPI and GUID defintions for this module
|
||||
//
|
||||
#include <Ppi/MasterBootMode.h>
|
||||
#include <Ppi/BootInRecoveryMode.h>
|
||||
#include <Guid/MemoryTypeInformation.h>
|
||||
|
||||
#include <Library/ArmLib.h>
|
||||
|
||||
/**
|
||||
This structure is used to describe a region of the EFI memory map
|
||||
|
||||
Every EFI regions of the system memory described by their physical start address and their size
|
||||
can have different attributes. Some regions can be tested and other untested.
|
||||
|
||||
**/
|
||||
typedef struct {
|
||||
EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute;
|
||||
EFI_PHYSICAL_ADDRESS PhysicalStart;
|
||||
UINT64 NumberOfBytes;
|
||||
} ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR;
|
||||
|
||||
UINTN
|
||||
ArmPlatformGetCorePosition (
|
||||
IN UINTN MpId
|
||||
);
|
||||
|
||||
/**
|
||||
Return the current Boot Mode
|
||||
|
||||
This function returns the boot reason on the platform
|
||||
|
||||
@return Return the current Boot Mode of the platform
|
||||
|
||||
**/
|
||||
EFI_BOOT_MODE
|
||||
ArmPlatformGetBootMode (
|
||||
VOID
|
||||
);
|
||||
|
||||
/**
|
||||
Initialize controllers that must setup in the normal world
|
||||
|
||||
This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei
|
||||
in the PEI phase.
|
||||
|
||||
**/
|
||||
RETURN_STATUS
|
||||
ArmPlatformInitialize (
|
||||
IN UINTN MpId
|
||||
);
|
||||
|
||||
/**
|
||||
Initialize the system (or sometimes called permanent) memory
|
||||
|
||||
This memory is generally represented by the DRAM.
|
||||
|
||||
**/
|
||||
VOID
|
||||
ArmPlatformInitializeSystemMemory (
|
||||
VOID
|
||||
);
|
||||
|
||||
/**
|
||||
Return the Virtual Memory Map of your platform
|
||||
|
||||
This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
|
||||
|
||||
@param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
|
||||
Virtual Memory mapping. This array must be ended by a zero-filled
|
||||
entry
|
||||
|
||||
**/
|
||||
VOID
|
||||
ArmPlatformGetVirtualMemoryMap (
|
||||
OUT ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
|
||||
);
|
||||
|
||||
/**
|
||||
Return the EFI Memory Map of your platform
|
||||
|
||||
This EFI Memory Map of the System Memory is used by MemoryInitPei module to create the Resource
|
||||
Descriptor HOBs used by DXE core.
|
||||
|
||||
@param[out] EfiMemoryMap Array of ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR describing an
|
||||
EFI Memory region. This array must be ended by a zero-filled entry
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
ArmPlatformGetAdditionalSystemMemory (
|
||||
OUT ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR** EfiMemoryMap
|
||||
);
|
||||
|
||||
/**
|
||||
Return the Platform specific PPIs
|
||||
|
||||
This function exposes the Platform Specific PPIs. They can be used by any PrePi modules or passed
|
||||
to the PeiCore by PrePeiCore.
|
||||
|
||||
@param[out] PpiListSize Size in Bytes of the Platform PPI List
|
||||
@param[out] PpiList Platform PPI List
|
||||
|
||||
**/
|
||||
VOID
|
||||
ArmPlatformGetPlatformPpiList (
|
||||
OUT UINTN *PpiListSize,
|
||||
OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
|
||||
);
|
||||
|
||||
#endif
|
||||
/** @file
|
||||
*
|
||||
* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
|
||||
*
|
||||
* This program and the accompanying materials
|
||||
* are licensed and made available under the terms and conditions of the BSD License
|
||||
* which accompanies this distribution. The full text of the license may be found at
|
||||
* http://opensource.org/licenses/bsd-license.php
|
||||
*
|
||||
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
*
|
||||
**/
|
||||
|
||||
#ifndef _ARMPLATFORMLIB_H_
|
||||
#define _ARMPLATFORMLIB_H_
|
||||
|
||||
//
|
||||
// The package level header files this module uses
|
||||
//
|
||||
#include <PiPei.h>
|
||||
//
|
||||
// The protocols, PPI and GUID defintions for this module
|
||||
//
|
||||
#include <Ppi/MasterBootMode.h>
|
||||
#include <Ppi/BootInRecoveryMode.h>
|
||||
#include <Guid/MemoryTypeInformation.h>
|
||||
|
||||
#include <Library/ArmLib.h>
|
||||
|
||||
/**
|
||||
This structure is used to describe a region of the EFI memory map
|
||||
|
||||
Every EFI regions of the system memory described by their physical start address and their size
|
||||
can have different attributes. Some regions can be tested and other untested.
|
||||
|
||||
**/
|
||||
typedef struct {
|
||||
EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute;
|
||||
EFI_PHYSICAL_ADDRESS PhysicalStart;
|
||||
UINT64 NumberOfBytes;
|
||||
} ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR;
|
||||
|
||||
UINTN
|
||||
ArmPlatformGetCorePosition (
|
||||
IN UINTN MpId
|
||||
);
|
||||
|
||||
/**
|
||||
Return the current Boot Mode
|
||||
|
||||
This function returns the boot reason on the platform
|
||||
|
||||
@return Return the current Boot Mode of the platform
|
||||
|
||||
**/
|
||||
EFI_BOOT_MODE
|
||||
ArmPlatformGetBootMode (
|
||||
VOID
|
||||
);
|
||||
|
||||
/**
|
||||
Initialize controllers that must setup in the normal world
|
||||
|
||||
This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei
|
||||
in the PEI phase.
|
||||
|
||||
**/
|
||||
RETURN_STATUS
|
||||
ArmPlatformInitialize (
|
||||
IN UINTN MpId
|
||||
);
|
||||
|
||||
/**
|
||||
Initialize the system (or sometimes called permanent) memory
|
||||
|
||||
This memory is generally represented by the DRAM.
|
||||
|
||||
**/
|
||||
VOID
|
||||
ArmPlatformInitializeSystemMemory (
|
||||
VOID
|
||||
);
|
||||
|
||||
/**
|
||||
Return the Virtual Memory Map of your platform
|
||||
|
||||
This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
|
||||
|
||||
@param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
|
||||
Virtual Memory mapping. This array must be ended by a zero-filled
|
||||
entry
|
||||
|
||||
**/
|
||||
VOID
|
||||
ArmPlatformGetVirtualMemoryMap (
|
||||
OUT ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
|
||||
);
|
||||
|
||||
/**
|
||||
Return the EFI Memory Map of your platform
|
||||
|
||||
This EFI Memory Map of the System Memory is used by MemoryInitPei module to create the Resource
|
||||
Descriptor HOBs used by DXE core.
|
||||
|
||||
@param[out] EfiMemoryMap Array of ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR describing an
|
||||
EFI Memory region. This array must be ended by a zero-filled entry
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
ArmPlatformGetAdditionalSystemMemory (
|
||||
OUT ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR** EfiMemoryMap
|
||||
);
|
||||
|
||||
/**
|
||||
Return the Platform specific PPIs
|
||||
|
||||
This function exposes the Platform Specific PPIs. They can be used by any PrePi modules or passed
|
||||
to the PeiCore by PrePeiCore.
|
||||
|
||||
@param[out] PpiListSize Size in Bytes of the Platform PPI List
|
||||
@param[out] PpiList Platform PPI List
|
||||
|
||||
**/
|
||||
VOID
|
||||
ArmPlatformGetPlatformPpiList (
|
||||
OUT UINTN *PpiListSize,
|
||||
OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
|
||||
);
|
||||
|
||||
#endif
|
||||
|
||||
@@ -1,88 +1,88 @@
|
||||
/** @file
|
||||
*
|
||||
* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
|
||||
*
|
||||
* This program and the accompanying materials
|
||||
* are licensed and made available under the terms and conditions of the BSD License
|
||||
* which accompanies this distribution. The full text of the license may be found at
|
||||
* http://opensource.org/licenses/bsd-license.php
|
||||
*
|
||||
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
*
|
||||
**/
|
||||
|
||||
#ifndef _ARMPLATFORMSECLIB_H_
|
||||
#define _ARMPLATFORMSECLIB_H_
|
||||
|
||||
#define ARM_SEC_BOOT_MASK ~0
|
||||
#define ARM_SEC_COLD_BOOT (1 << 0)
|
||||
#define ARM_SEC_SECONDARY_COLD_BOOT (1 << 1)
|
||||
|
||||
/**
|
||||
Initialize the memory where the initial stacks will reside
|
||||
|
||||
This memory can contain the initial stacks (Secure and Secure Monitor stacks).
|
||||
In some platform, this region is already initialized and the implementation of this function can
|
||||
do nothing. This memory can also represent the Secure RAM.
|
||||
This function is called before the satck has been set up. Its implementation must ensure the stack
|
||||
pointer is not used (probably required to use assembly language)
|
||||
|
||||
**/
|
||||
VOID
|
||||
ArmPlatformSecBootMemoryInit (
|
||||
VOID
|
||||
);
|
||||
|
||||
/**
|
||||
Call at the beginning of the platform boot up
|
||||
|
||||
This function allows the firmware platform to do extra actions at the early
|
||||
stage of the platform power up.
|
||||
|
||||
Note: This function must be implemented in assembler as there is no stack set up yet
|
||||
|
||||
**/
|
||||
VOID
|
||||
ArmPlatformSecBootAction (
|
||||
VOID
|
||||
);
|
||||
|
||||
/**
|
||||
Initialize controllers that must setup at the early stage
|
||||
|
||||
Some peripherals must be initialized in Secure World.
|
||||
For example: Some L2 controller, interconnect, clock, DMC, etc
|
||||
|
||||
**/
|
||||
RETURN_STATUS
|
||||
ArmPlatformSecInitialize (
|
||||
IN UINTN MpId
|
||||
);
|
||||
|
||||
/**
|
||||
Call before jumping to Normal World
|
||||
|
||||
This function allows the firmware platform to do extra actions before
|
||||
jumping to the Normal World
|
||||
|
||||
**/
|
||||
VOID
|
||||
ArmPlatformSecExtraAction (
|
||||
IN UINTN MpId,
|
||||
OUT UINTN* JumpAddress
|
||||
);
|
||||
|
||||
/**
|
||||
Initialize the Secure peripherals and memory regions
|
||||
|
||||
If Trustzone is supported by your platform then this function makes the required initialization
|
||||
of the secure peripherals and memory regions.
|
||||
|
||||
**/
|
||||
VOID
|
||||
ArmPlatformSecTrustzoneInit (
|
||||
IN UINTN MpId
|
||||
);
|
||||
|
||||
#endif
|
||||
/** @file
|
||||
*
|
||||
* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
|
||||
*
|
||||
* This program and the accompanying materials
|
||||
* are licensed and made available under the terms and conditions of the BSD License
|
||||
* which accompanies this distribution. The full text of the license may be found at
|
||||
* http://opensource.org/licenses/bsd-license.php
|
||||
*
|
||||
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
*
|
||||
**/
|
||||
|
||||
#ifndef _ARMPLATFORMSECLIB_H_
|
||||
#define _ARMPLATFORMSECLIB_H_
|
||||
|
||||
#define ARM_SEC_BOOT_MASK ~0
|
||||
#define ARM_SEC_COLD_BOOT (1 << 0)
|
||||
#define ARM_SEC_SECONDARY_COLD_BOOT (1 << 1)
|
||||
|
||||
/**
|
||||
Initialize the memory where the initial stacks will reside
|
||||
|
||||
This memory can contain the initial stacks (Secure and Secure Monitor stacks).
|
||||
In some platform, this region is already initialized and the implementation of this function can
|
||||
do nothing. This memory can also represent the Secure RAM.
|
||||
This function is called before the satck has been set up. Its implementation must ensure the stack
|
||||
pointer is not used (probably required to use assembly language)
|
||||
|
||||
**/
|
||||
VOID
|
||||
ArmPlatformSecBootMemoryInit (
|
||||
VOID
|
||||
);
|
||||
|
||||
/**
|
||||
Call at the beginning of the platform boot up
|
||||
|
||||
This function allows the firmware platform to do extra actions at the early
|
||||
stage of the platform power up.
|
||||
|
||||
Note: This function must be implemented in assembler as there is no stack set up yet
|
||||
|
||||
**/
|
||||
VOID
|
||||
ArmPlatformSecBootAction (
|
||||
VOID
|
||||
);
|
||||
|
||||
/**
|
||||
Initialize controllers that must setup at the early stage
|
||||
|
||||
Some peripherals must be initialized in Secure World.
|
||||
For example: Some L2 controller, interconnect, clock, DMC, etc
|
||||
|
||||
**/
|
||||
RETURN_STATUS
|
||||
ArmPlatformSecInitialize (
|
||||
IN UINTN MpId
|
||||
);
|
||||
|
||||
/**
|
||||
Call before jumping to Normal World
|
||||
|
||||
This function allows the firmware platform to do extra actions before
|
||||
jumping to the Normal World
|
||||
|
||||
**/
|
||||
VOID
|
||||
ArmPlatformSecExtraAction (
|
||||
IN UINTN MpId,
|
||||
OUT UINTN* JumpAddress
|
||||
);
|
||||
|
||||
/**
|
||||
Initialize the Secure peripherals and memory regions
|
||||
|
||||
If Trustzone is supported by your platform then this function makes the required initialization
|
||||
of the secure peripherals and memory regions.
|
||||
|
||||
**/
|
||||
VOID
|
||||
ArmPlatformSecTrustzoneInit (
|
||||
IN UINTN MpId
|
||||
);
|
||||
|
||||
#endif
|
||||
|
||||
@@ -1,63 +1,63 @@
|
||||
/** @file ArmPlatformSysConfigLib.h
|
||||
|
||||
Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>
|
||||
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __ARM_PLATFORM_SYS_CONFIG_H__
|
||||
#define __ARM_PLATFORM_SYS_CONFIG_H__
|
||||
|
||||
#include <Base.h>
|
||||
|
||||
/* This header file makes it easier to access the System Configuration Registers
|
||||
* in the ARM Versatile Express motherboard.
|
||||
*/
|
||||
|
||||
//
|
||||
// Typedef
|
||||
//
|
||||
typedef UINT32 SYS_CONFIG_FUNCTION;
|
||||
|
||||
//
|
||||
// Functions
|
||||
//
|
||||
RETURN_STATUS
|
||||
ArmPlatformSysConfigInitialize (
|
||||
VOID
|
||||
);
|
||||
|
||||
RETURN_STATUS
|
||||
ArmPlatformSysConfigGet (
|
||||
IN SYS_CONFIG_FUNCTION Function,
|
||||
OUT UINT32* Value
|
||||
);
|
||||
|
||||
RETURN_STATUS
|
||||
ArmPlatformSysConfigGetValues (
|
||||
IN SYS_CONFIG_FUNCTION Function,
|
||||
IN UINTN Size,
|
||||
OUT UINT32* Values
|
||||
);
|
||||
|
||||
RETURN_STATUS
|
||||
ArmPlatformSysConfigSet (
|
||||
IN SYS_CONFIG_FUNCTION Function,
|
||||
IN UINT32 Value
|
||||
);
|
||||
|
||||
RETURN_STATUS
|
||||
ArmPlatformSysConfigSetDevice (
|
||||
IN SYS_CONFIG_FUNCTION Function,
|
||||
IN UINT32 Device,
|
||||
IN UINT32 Value
|
||||
);
|
||||
|
||||
#endif /* __SYS_CFG_REGISTERS_H__ */
|
||||
/** @file ArmPlatformSysConfigLib.h
|
||||
|
||||
Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>
|
||||
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __ARM_PLATFORM_SYS_CONFIG_H__
|
||||
#define __ARM_PLATFORM_SYS_CONFIG_H__
|
||||
|
||||
#include <Base.h>
|
||||
|
||||
/* This header file makes it easier to access the System Configuration Registers
|
||||
* in the ARM Versatile Express motherboard.
|
||||
*/
|
||||
|
||||
//
|
||||
// Typedef
|
||||
//
|
||||
typedef UINT32 SYS_CONFIG_FUNCTION;
|
||||
|
||||
//
|
||||
// Functions
|
||||
//
|
||||
RETURN_STATUS
|
||||
ArmPlatformSysConfigInitialize (
|
||||
VOID
|
||||
);
|
||||
|
||||
RETURN_STATUS
|
||||
ArmPlatformSysConfigGet (
|
||||
IN SYS_CONFIG_FUNCTION Function,
|
||||
OUT UINT32* Value
|
||||
);
|
||||
|
||||
RETURN_STATUS
|
||||
ArmPlatformSysConfigGetValues (
|
||||
IN SYS_CONFIG_FUNCTION Function,
|
||||
IN UINTN Size,
|
||||
OUT UINT32* Values
|
||||
);
|
||||
|
||||
RETURN_STATUS
|
||||
ArmPlatformSysConfigSet (
|
||||
IN SYS_CONFIG_FUNCTION Function,
|
||||
IN UINT32 Value
|
||||
);
|
||||
|
||||
RETURN_STATUS
|
||||
ArmPlatformSysConfigSetDevice (
|
||||
IN SYS_CONFIG_FUNCTION Function,
|
||||
IN UINT32 Device,
|
||||
IN UINT32 Value
|
||||
);
|
||||
|
||||
#endif /* __SYS_CFG_REGISTERS_H__ */
|
||||
|
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Reference in New Issue
Block a user