ARM Packages: Fixed line endings
This large code change only modifies the line endings to be CRLF to be compliant with the EDK2 coding convention document. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14088 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin
@@ -1,40 +1,40 @@
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/** @file
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Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef __OMAP3530_H__
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#define __OMAP3530_H__
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#include "Omap3530Gpio.h"
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#include "Omap3530Interrupt.h"
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#include "Omap3530Prcm.h"
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#include "Omap3530Timer.h"
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#include "Omap3530Uart.h"
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#include "Omap3530Usb.h"
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#include "Omap3530MMCHS.h"
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#include "Omap3530I2c.h"
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#include "Omap3530PadConfiguration.h"
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#include "Omap3530Gpmc.h"
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#include "Omap3530Dma.h"
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//CONTROL_PBIAS_LITE
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#define CONTROL_PBIAS_LITE 0x48002520
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#define PBIASLITEVMODE0 BIT0
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#define PBIASLITEPWRDNZ0 BIT1
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#define PBIASSPEEDCTRL0 BIT2
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#define PBIASLITEVMODE1 BIT8
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#define PBIASLITEWRDNZ1 BIT9
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#endif // __OMAP3530_H__
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/** @file
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Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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||||
which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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||||
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef __OMAP3530_H__
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#define __OMAP3530_H__
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#include "Omap3530Gpio.h"
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#include "Omap3530Interrupt.h"
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#include "Omap3530Prcm.h"
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#include "Omap3530Timer.h"
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#include "Omap3530Uart.h"
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#include "Omap3530Usb.h"
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#include "Omap3530MMCHS.h"
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#include "Omap3530I2c.h"
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#include "Omap3530PadConfiguration.h"
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#include "Omap3530Gpmc.h"
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#include "Omap3530Dma.h"
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//CONTROL_PBIAS_LITE
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#define CONTROL_PBIAS_LITE 0x48002520
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#define PBIASLITEVMODE0 BIT0
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#define PBIASLITEPWRDNZ0 BIT1
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#define PBIASSPEEDCTRL0 BIT2
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#define PBIASLITEVMODE1 BIT8
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#define PBIASLITEWRDNZ1 BIT9
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#endif // __OMAP3530_H__
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@@ -1,130 +1,130 @@
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/** @file
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Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
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|
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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||||
which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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||||
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef __OMAP3530DMA_H__
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#define __OMAP3530DMA_H__
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#define DMA4_MAX_CHANNEL 31
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#define DMA4_IRQENABLE_L(_i) (0x48056018 + (0x4*(_i)))
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#define DMA4_CCR(_i) (0x48056080 + (0x60*(_i)))
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#define DMA4_CICR(_i) (0x48056088 + (0x60*(_i)))
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#define DMA4_CSR(_i) (0x4805608c + (0x60*(_i)))
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#define DMA4_CSDP(_i) (0x48056090 + (0x60*(_i)))
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#define DMA4_CEN(_i) (0x48056094 + (0x60*(_i)))
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#define DMA4_CFN(_i) (0x48056098 + (0x60*(_i)))
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#define DMA4_CSSA(_i) (0x4805609c + (0x60*(_i)))
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#define DMA4_CDSA(_i) (0x480560a0 + (0x60*(_i)))
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#define DMA4_CSEI(_i) (0x480560a4 + (0x60*(_i)))
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#define DMA4_CSFI(_i) (0x480560a8 + (0x60*(_i)))
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#define DMA4_CDEI(_i) (0x480560ac + (0x60*(_i)))
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#define DMA4_CDFI(_i) (0x480560b0 + (0x60*(_i)))
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#define DMA4_GCR (0x48056078)
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// Channel Source Destination parameters
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#define DMA4_CSDP_DATA_TYPE8 0
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#define DMA4_CSDP_DATA_TYPE16 1
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#define DMA4_CSDP_DATA_TYPE32 2
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#define DMA4_CSDP_SRC_PACKED BIT6
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#define DMA4_CSDP_SRC_NONPACKED 0
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#define DMA4_CSDP_SRC_BURST_EN (0x0 << 7)
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#define DMA4_CSDP_SRC_BURST_EN16 (0x1 << 7)
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#define DMA4_CSDP_SRC_BURST_EN32 (0x2 << 7)
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#define DMA4_CSDP_SRC_BURST_EN64 (0x3 << 7)
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#define DMA4_CSDP_DST_PACKED BIT13
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#define DMA4_CSDP_DST_NONPACKED 0
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#define DMA4_CSDP_BURST_EN (0x0 << 14)
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#define DMA4_CSDP_BURST_EN16 (0x1 << 14)
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#define DMA4_CSDP_BURST_EN32 (0x2 << 14)
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#define DMA4_CSDP_BURST_EN64 (0x3 << 14)
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#define DMA4_CSDP_WRITE_MODE_NONE_POSTED (0x0 << 16)
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#define DMA4_CSDP_WRITE_MODE_POSTED (0x1 << 16)
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#define DMA4_CSDP_WRITE_MODE_LAST_NON_POSTED (0x2 << 16)
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#define DMA4_CSDP_DST_ENDIAN_LOCK_LOCK BIT18
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#define DMA4_CSDP_DST_ENDIAN_LOCK_ADAPT 0
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#define DMA4_CSDP_DST_ENDIAN_BIG BIT19
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#define DMA4_CSDP_DST_ENDIAN_LITTLE 0
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#define DMA4_CSDP_SRC_ENDIAN_LOCK_LOCK BIT20
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#define DMA4_CSDP_SRC_ENDIAN_LOCK_ADAPT 0
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#define DMA4_CSDP_SRC_ENDIAN_BIG BIT21
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#define DMA4_CSDP_SRC_ENDIAN_LITTLE 0
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// Channel Control
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#define DMA4_CCR_SYNCHRO_CONTROL_MASK 0x1f
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#define DMA4_CCR_FS_ELEMENT (0 | 0)
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#define DMA4_CCR_FS_BLOCK (0 | BIT18)
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#define DMA4_CCR_FS_FRAME (BIT5 | 0)
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#define DMA4_CCR_FS_PACKET (BIT5 | BIT18)
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#define DMA4_CCR_READ_PRIORITY_HIGH BIT6
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#define DMA4_CCR_READ_PRIORITY_LOW 0
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#define DMA4_CCR_ENABLE BIT7
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#define DMA4_CCR_DISABLE 0
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#define DMA4_CCR_SUSPEND_SENSITIVE_IGNORE BIT8
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#define DMA4_CCR_SUSPEND_SENSITIVE 0
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#define DMA4_CCR_RD_ACTIVE BIT9
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#define DMA4_CCR_WR_ACTIVE BIT10
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#define DMA4_CCR_SRC_AMODE (0 | 0)
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#define DMA4_CCR_SRC_AMODE_POST_INC (0 | BIT12)
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#define DMA4_CCR_SRC_AMODE_SINGLE_INDEX (BIT13 | 0)
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#define DMA4_CCR_SRC_AMODE_DOUBLE_INDEX (BIT13 | BIT12)
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#define DMA4_CCR_DST_AMODE (0 | 0)
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#define DMA4_CCR_DST_AMODE_POST_INC (0 | BIT14)
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#define DMA4_CCR_DST_AMODE_SINGLE_INDEX (BIT15 | 0)
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#define DMA4_CCR_DST_AMODE_DOUBLE_INDEX (BIT15 | BIT14)
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#define DMA4_CCR_CONST_FILL_ENABLE BIT16
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#define DMA4_CCR_TRANSPARENT_COPY_ENABLE BIT17
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#define DMA4_CCR_SEL_SRC_DEST_SYNC_SOURCE BIT24
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#define DMA4_CSR_DROP BIT1
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#define DMA4_CSR_HALF BIT2
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#define DMA4_CSR_FRAME BIT3
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#define DMA4_CSR_LAST BIT4
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#define DMA4_CSR_BLOCK BIT5
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#define DMA4_CSR_SYNC BIT6
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#define DMA4_CSR_PKT BIT7
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#define DMA4_CSR_TRANS_ERR BIT8
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#define DMA4_CSR_SECURE_ERR BIT9
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#define DMA4_CSR_SUPERVISOR_ERR BIT10
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#define DMA4_CSR_MISALIGNED_ADRS_ERR BIT11
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#define DMA4_CSR_DRAIN_END BIT12
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#define DMA4_CSR_RESET 0x1FE
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#define DMA4_CSR_ERR (DMA4_CSR_TRANS_ERR | DMA4_CSR_SECURE_ERR | DMA4_CSR_SUPERVISOR_ERR | DMA4_CSR_MISALIGNED_ADRS_ERR)
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// same mapping as CSR except for SYNC. Enable all since we are polling
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#define DMA4_CICR_ENABLE_ALL 0x1FBE
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#endif
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/** @file
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Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
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http://opensource.org/licenses/bsd-license.php
|
||||
|
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef __OMAP3530DMA_H__
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#define __OMAP3530DMA_H__
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#define DMA4_MAX_CHANNEL 31
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#define DMA4_IRQENABLE_L(_i) (0x48056018 + (0x4*(_i)))
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#define DMA4_CCR(_i) (0x48056080 + (0x60*(_i)))
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#define DMA4_CICR(_i) (0x48056088 + (0x60*(_i)))
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#define DMA4_CSR(_i) (0x4805608c + (0x60*(_i)))
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#define DMA4_CSDP(_i) (0x48056090 + (0x60*(_i)))
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#define DMA4_CEN(_i) (0x48056094 + (0x60*(_i)))
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#define DMA4_CFN(_i) (0x48056098 + (0x60*(_i)))
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#define DMA4_CSSA(_i) (0x4805609c + (0x60*(_i)))
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#define DMA4_CDSA(_i) (0x480560a0 + (0x60*(_i)))
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#define DMA4_CSEI(_i) (0x480560a4 + (0x60*(_i)))
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#define DMA4_CSFI(_i) (0x480560a8 + (0x60*(_i)))
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#define DMA4_CDEI(_i) (0x480560ac + (0x60*(_i)))
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#define DMA4_CDFI(_i) (0x480560b0 + (0x60*(_i)))
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#define DMA4_GCR (0x48056078)
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// Channel Source Destination parameters
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#define DMA4_CSDP_DATA_TYPE8 0
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#define DMA4_CSDP_DATA_TYPE16 1
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#define DMA4_CSDP_DATA_TYPE32 2
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#define DMA4_CSDP_SRC_PACKED BIT6
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#define DMA4_CSDP_SRC_NONPACKED 0
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#define DMA4_CSDP_SRC_BURST_EN (0x0 << 7)
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#define DMA4_CSDP_SRC_BURST_EN16 (0x1 << 7)
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#define DMA4_CSDP_SRC_BURST_EN32 (0x2 << 7)
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#define DMA4_CSDP_SRC_BURST_EN64 (0x3 << 7)
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#define DMA4_CSDP_DST_PACKED BIT13
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#define DMA4_CSDP_DST_NONPACKED 0
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#define DMA4_CSDP_BURST_EN (0x0 << 14)
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#define DMA4_CSDP_BURST_EN16 (0x1 << 14)
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#define DMA4_CSDP_BURST_EN32 (0x2 << 14)
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#define DMA4_CSDP_BURST_EN64 (0x3 << 14)
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#define DMA4_CSDP_WRITE_MODE_NONE_POSTED (0x0 << 16)
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#define DMA4_CSDP_WRITE_MODE_POSTED (0x1 << 16)
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#define DMA4_CSDP_WRITE_MODE_LAST_NON_POSTED (0x2 << 16)
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#define DMA4_CSDP_DST_ENDIAN_LOCK_LOCK BIT18
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#define DMA4_CSDP_DST_ENDIAN_LOCK_ADAPT 0
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#define DMA4_CSDP_DST_ENDIAN_BIG BIT19
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#define DMA4_CSDP_DST_ENDIAN_LITTLE 0
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#define DMA4_CSDP_SRC_ENDIAN_LOCK_LOCK BIT20
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#define DMA4_CSDP_SRC_ENDIAN_LOCK_ADAPT 0
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#define DMA4_CSDP_SRC_ENDIAN_BIG BIT21
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#define DMA4_CSDP_SRC_ENDIAN_LITTLE 0
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// Channel Control
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#define DMA4_CCR_SYNCHRO_CONTROL_MASK 0x1f
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#define DMA4_CCR_FS_ELEMENT (0 | 0)
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#define DMA4_CCR_FS_BLOCK (0 | BIT18)
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#define DMA4_CCR_FS_FRAME (BIT5 | 0)
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#define DMA4_CCR_FS_PACKET (BIT5 | BIT18)
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#define DMA4_CCR_READ_PRIORITY_HIGH BIT6
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#define DMA4_CCR_READ_PRIORITY_LOW 0
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#define DMA4_CCR_ENABLE BIT7
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#define DMA4_CCR_DISABLE 0
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#define DMA4_CCR_SUSPEND_SENSITIVE_IGNORE BIT8
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#define DMA4_CCR_SUSPEND_SENSITIVE 0
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#define DMA4_CCR_RD_ACTIVE BIT9
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#define DMA4_CCR_WR_ACTIVE BIT10
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#define DMA4_CCR_SRC_AMODE (0 | 0)
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#define DMA4_CCR_SRC_AMODE_POST_INC (0 | BIT12)
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#define DMA4_CCR_SRC_AMODE_SINGLE_INDEX (BIT13 | 0)
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#define DMA4_CCR_SRC_AMODE_DOUBLE_INDEX (BIT13 | BIT12)
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#define DMA4_CCR_DST_AMODE (0 | 0)
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#define DMA4_CCR_DST_AMODE_POST_INC (0 | BIT14)
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#define DMA4_CCR_DST_AMODE_SINGLE_INDEX (BIT15 | 0)
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#define DMA4_CCR_DST_AMODE_DOUBLE_INDEX (BIT15 | BIT14)
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||||
|
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#define DMA4_CCR_CONST_FILL_ENABLE BIT16
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#define DMA4_CCR_TRANSPARENT_COPY_ENABLE BIT17
|
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||||
#define DMA4_CCR_SEL_SRC_DEST_SYNC_SOURCE BIT24
|
||||
|
||||
#define DMA4_CSR_DROP BIT1
|
||||
#define DMA4_CSR_HALF BIT2
|
||||
#define DMA4_CSR_FRAME BIT3
|
||||
#define DMA4_CSR_LAST BIT4
|
||||
#define DMA4_CSR_BLOCK BIT5
|
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#define DMA4_CSR_SYNC BIT6
|
||||
#define DMA4_CSR_PKT BIT7
|
||||
#define DMA4_CSR_TRANS_ERR BIT8
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||||
#define DMA4_CSR_SECURE_ERR BIT9
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||||
#define DMA4_CSR_SUPERVISOR_ERR BIT10
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||||
#define DMA4_CSR_MISALIGNED_ADRS_ERR BIT11
|
||||
#define DMA4_CSR_DRAIN_END BIT12
|
||||
#define DMA4_CSR_RESET 0x1FE
|
||||
#define DMA4_CSR_ERR (DMA4_CSR_TRANS_ERR | DMA4_CSR_SECURE_ERR | DMA4_CSR_SUPERVISOR_ERR | DMA4_CSR_MISALIGNED_ADRS_ERR)
|
||||
|
||||
// same mapping as CSR except for SYNC. Enable all since we are polling
|
||||
#define DMA4_CICR_ENABLE_ALL 0x1FBE
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
@@ -1,131 +1,131 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
||||
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __OMAP3530GPIO_H__
|
||||
#define __OMAP3530GPIO_H__
|
||||
|
||||
#define GPIO1_BASE (0x48310000)
|
||||
#define GPIO2_BASE (0x49050000)
|
||||
#define GPIO3_BASE (0x49052000)
|
||||
#define GPIO4_BASE (0x49054000)
|
||||
#define GPIO5_BASE (0x49056000)
|
||||
#define GPIO6_BASE (0x49058000)
|
||||
|
||||
#define GPIO_SYSCONFIG (0x0010)
|
||||
#define GPIO_SYSSTATUS (0x0014)
|
||||
#define GPIO_IRQSTATUS1 (0x0018)
|
||||
#define GPIO_IRQENABLE1 (0x001C)
|
||||
#define GPIO_WAKEUPENABLE (0x0020)
|
||||
#define GPIO_IRQSTATUS2 (0x0028)
|
||||
#define GPIO_IRQENABLE2 (0x002C)
|
||||
#define GPIO_CTRL (0x0030)
|
||||
#define GPIO_OE (0x0034)
|
||||
#define GPIO_DATAIN (0x0038)
|
||||
#define GPIO_DATAOUT (0x003C)
|
||||
#define GPIO_LEVELDETECT0 (0x0040)
|
||||
#define GPIO_LEVELDETECT1 (0x0044)
|
||||
#define GPIO_RISINGDETECT (0x0048)
|
||||
#define GPIO_FALLINGDETECT (0x004C)
|
||||
#define GPIO_DEBOUNCENABLE (0x0050)
|
||||
#define GPIO_DEBOUNCINGTIME (0x0054)
|
||||
#define GPIO_CLEARIRQENABLE1 (0x0060)
|
||||
#define GPIO_SETIRQENABLE1 (0x0064)
|
||||
#define GPIO_CLEARIRQENABLE2 (0x0070)
|
||||
#define GPIO_SETIRQENABLE2 (0x0074)
|
||||
#define GPIO_CLEARWKUENA (0x0080)
|
||||
#define GPIO_SETWKUENA (0x0084)
|
||||
#define GPIO_CLEARDATAOUT (0x0090)
|
||||
#define GPIO_SETDATAOUT (0x0094)
|
||||
|
||||
#define GPIO_SYSCONFIG_IDLEMODE_MASK (3UL << 3)
|
||||
#define GPIO_SYSCONFIG_IDLEMODE_FORCE (0UL << 3)
|
||||
#define GPIO_SYSCONFIG_IDLEMODE_NONE BIT3
|
||||
#define GPIO_SYSCONFIG_IDLEMODE_SMART (2UL << 3)
|
||||
#define GPIO_SYSCONFIG_ENAWAKEUP_MASK BIT2
|
||||
#define GPIO_SYSCONFIG_ENAWAKEUP_DISABLE (0UL << 2)
|
||||
#define GPIO_SYSCONFIG_ENAWAKEUP_ENABLE BIT2
|
||||
#define GPIO_SYSCONFIG_SOFTRESET_MASK BIT1
|
||||
#define GPIO_SYSCONFIG_SOFTRESET_NORMAL (0UL << 1)
|
||||
#define GPIO_SYSCONFIG_SOFTRESET_RESET BIT1
|
||||
#define GPIO_SYSCONFIG_AUTOIDLE_MASK BIT0
|
||||
#define GPIO_SYSCONFIG_AUTOIDLE_FREE_RUN (0UL << 0)
|
||||
#define GPIO_SYSCONFIG_AUTOIDLE_ON BIT0
|
||||
|
||||
#define GPIO_SYSSTATUS_RESETDONE_MASK BIT0
|
||||
#define GPIO_SYSSTATUS_RESETDONE_ONGOING (0UL << 0)
|
||||
#define GPIO_SYSSTATUS_RESETDONE_COMPLETE BIT0
|
||||
|
||||
#define GPIO_IRQSTATUS_MASK(x) (1UL << (x))
|
||||
#define GPIO_IRQSTATUS_NOT_TRIGGERED(x) (0UL << (x))
|
||||
#define GPIO_IRQSTATUS_TRIGGERED(x) (1UL << (x))
|
||||
#define GPIO_IRQSTATUS_CLEAR(x) (1UL << (x))
|
||||
|
||||
#define GPIO_IRQENABLE_MASK(x) (1UL << (x))
|
||||
#define GPIO_IRQENABLE_DISABLE(x) (0UL << (x))
|
||||
#define GPIO_IRQENABLE_ENABLE(x) (1UL << (x))
|
||||
|
||||
#define GPIO_WAKEUPENABLE_MASK(x) (1UL << (x))
|
||||
#define GPIO_WAKEUPENABLE_DISABLE(x) (0UL << (x))
|
||||
#define GPIO_WAKEUPENABLE_ENABLE(x) (1UL << (x))
|
||||
|
||||
#define GPIO_CTRL_GATINGRATIO_MASK (3UL << 1)
|
||||
#define GPIO_CTRL_GATINGRATIO_DIV_1 (0UL << 1)
|
||||
#define GPIO_CTRL_GATINGRATIO_DIV_2 BIT1
|
||||
#define GPIO_CTRL_GATINGRATIO_DIV_4 (2UL << 1)
|
||||
#define GPIO_CTRL_GATINGRATIO_DIV_8 (3UL << 1)
|
||||
#define GPIO_CTRL_DISABLEMODULE_MASK BIT0
|
||||
#define GPIO_CTRL_DISABLEMODULE_ENABLE (0UL << 0)
|
||||
#define GPIO_CTRL_DISABLEMODULE_DISABLE BIT0
|
||||
|
||||
#define GPIO_OE_MASK(x) (1UL << (x))
|
||||
#define GPIO_OE_OUTPUT(x) (0UL << (x))
|
||||
#define GPIO_OE_INPUT(x) (1UL << (x))
|
||||
|
||||
#define GPIO_DATAIN_MASK(x) (1UL << (x))
|
||||
|
||||
#define GPIO_DATAOUT_MASK(x) (1UL << (x))
|
||||
|
||||
#define GPIO_LEVELDETECT_MASK(x) (1UL << (x))
|
||||
#define GPIO_LEVELDETECT_DISABLE(x) (0UL << (x))
|
||||
#define GPIO_LEVELDETECT_ENABLE(x) (1UL << (x))
|
||||
|
||||
#define GPIO_RISINGDETECT_MASK(x) (1UL << (x))
|
||||
#define GPIO_RISINGDETECT_DISABLE(x) (0UL << (x))
|
||||
#define GPIO_RISINGDETECT_ENABLE(x) (1UL << (x))
|
||||
|
||||
#define GPIO_FALLINGDETECT_MASK(x) (1UL << (x))
|
||||
#define GPIO_FALLINGDETECT_DISABLE(x) (0UL << (x))
|
||||
#define GPIO_FALLINGDETECT_ENABLE(x) (1UL << (x))
|
||||
|
||||
#define GPIO_DEBOUNCENABLE_MASK(x) (1UL << (x))
|
||||
#define GPIO_DEBOUNCENABLE_DISABLE(x) (0UL << (x))
|
||||
#define GPIO_DEBOUNCENABLE_ENABLE(x) (1UL << (x))
|
||||
|
||||
#define GPIO_DEBOUNCINGTIME_MASK (0xFF)
|
||||
#define GPIO_DEBOUNCINGTIME_US(x) ((((x) / 31) - 1) & GPIO_DEBOUNCINGTIME_MASK)
|
||||
|
||||
#define GPIO_CLEARIRQENABLE_BIT(x) (1UL << (x))
|
||||
|
||||
#define GPIO_SETIRQENABLE_BIT(x) (1UL << (x))
|
||||
|
||||
#define GPIO_CLEARWKUENA_BIT(x) (1UL << (x))
|
||||
|
||||
#define GPIO_SETWKUENA_BIT(x) (1UL << (x))
|
||||
|
||||
#define GPIO_CLEARDATAOUT_BIT(x) (1UL << (x))
|
||||
|
||||
#define GPIO_SETDATAOUT_BIT(x) (1UL << (x))
|
||||
|
||||
#endif // __OMAP3530GPIO_H__
|
||||
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
||||
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __OMAP3530GPIO_H__
|
||||
#define __OMAP3530GPIO_H__
|
||||
|
||||
#define GPIO1_BASE (0x48310000)
|
||||
#define GPIO2_BASE (0x49050000)
|
||||
#define GPIO3_BASE (0x49052000)
|
||||
#define GPIO4_BASE (0x49054000)
|
||||
#define GPIO5_BASE (0x49056000)
|
||||
#define GPIO6_BASE (0x49058000)
|
||||
|
||||
#define GPIO_SYSCONFIG (0x0010)
|
||||
#define GPIO_SYSSTATUS (0x0014)
|
||||
#define GPIO_IRQSTATUS1 (0x0018)
|
||||
#define GPIO_IRQENABLE1 (0x001C)
|
||||
#define GPIO_WAKEUPENABLE (0x0020)
|
||||
#define GPIO_IRQSTATUS2 (0x0028)
|
||||
#define GPIO_IRQENABLE2 (0x002C)
|
||||
#define GPIO_CTRL (0x0030)
|
||||
#define GPIO_OE (0x0034)
|
||||
#define GPIO_DATAIN (0x0038)
|
||||
#define GPIO_DATAOUT (0x003C)
|
||||
#define GPIO_LEVELDETECT0 (0x0040)
|
||||
#define GPIO_LEVELDETECT1 (0x0044)
|
||||
#define GPIO_RISINGDETECT (0x0048)
|
||||
#define GPIO_FALLINGDETECT (0x004C)
|
||||
#define GPIO_DEBOUNCENABLE (0x0050)
|
||||
#define GPIO_DEBOUNCINGTIME (0x0054)
|
||||
#define GPIO_CLEARIRQENABLE1 (0x0060)
|
||||
#define GPIO_SETIRQENABLE1 (0x0064)
|
||||
#define GPIO_CLEARIRQENABLE2 (0x0070)
|
||||
#define GPIO_SETIRQENABLE2 (0x0074)
|
||||
#define GPIO_CLEARWKUENA (0x0080)
|
||||
#define GPIO_SETWKUENA (0x0084)
|
||||
#define GPIO_CLEARDATAOUT (0x0090)
|
||||
#define GPIO_SETDATAOUT (0x0094)
|
||||
|
||||
#define GPIO_SYSCONFIG_IDLEMODE_MASK (3UL << 3)
|
||||
#define GPIO_SYSCONFIG_IDLEMODE_FORCE (0UL << 3)
|
||||
#define GPIO_SYSCONFIG_IDLEMODE_NONE BIT3
|
||||
#define GPIO_SYSCONFIG_IDLEMODE_SMART (2UL << 3)
|
||||
#define GPIO_SYSCONFIG_ENAWAKEUP_MASK BIT2
|
||||
#define GPIO_SYSCONFIG_ENAWAKEUP_DISABLE (0UL << 2)
|
||||
#define GPIO_SYSCONFIG_ENAWAKEUP_ENABLE BIT2
|
||||
#define GPIO_SYSCONFIG_SOFTRESET_MASK BIT1
|
||||
#define GPIO_SYSCONFIG_SOFTRESET_NORMAL (0UL << 1)
|
||||
#define GPIO_SYSCONFIG_SOFTRESET_RESET BIT1
|
||||
#define GPIO_SYSCONFIG_AUTOIDLE_MASK BIT0
|
||||
#define GPIO_SYSCONFIG_AUTOIDLE_FREE_RUN (0UL << 0)
|
||||
#define GPIO_SYSCONFIG_AUTOIDLE_ON BIT0
|
||||
|
||||
#define GPIO_SYSSTATUS_RESETDONE_MASK BIT0
|
||||
#define GPIO_SYSSTATUS_RESETDONE_ONGOING (0UL << 0)
|
||||
#define GPIO_SYSSTATUS_RESETDONE_COMPLETE BIT0
|
||||
|
||||
#define GPIO_IRQSTATUS_MASK(x) (1UL << (x))
|
||||
#define GPIO_IRQSTATUS_NOT_TRIGGERED(x) (0UL << (x))
|
||||
#define GPIO_IRQSTATUS_TRIGGERED(x) (1UL << (x))
|
||||
#define GPIO_IRQSTATUS_CLEAR(x) (1UL << (x))
|
||||
|
||||
#define GPIO_IRQENABLE_MASK(x) (1UL << (x))
|
||||
#define GPIO_IRQENABLE_DISABLE(x) (0UL << (x))
|
||||
#define GPIO_IRQENABLE_ENABLE(x) (1UL << (x))
|
||||
|
||||
#define GPIO_WAKEUPENABLE_MASK(x) (1UL << (x))
|
||||
#define GPIO_WAKEUPENABLE_DISABLE(x) (0UL << (x))
|
||||
#define GPIO_WAKEUPENABLE_ENABLE(x) (1UL << (x))
|
||||
|
||||
#define GPIO_CTRL_GATINGRATIO_MASK (3UL << 1)
|
||||
#define GPIO_CTRL_GATINGRATIO_DIV_1 (0UL << 1)
|
||||
#define GPIO_CTRL_GATINGRATIO_DIV_2 BIT1
|
||||
#define GPIO_CTRL_GATINGRATIO_DIV_4 (2UL << 1)
|
||||
#define GPIO_CTRL_GATINGRATIO_DIV_8 (3UL << 1)
|
||||
#define GPIO_CTRL_DISABLEMODULE_MASK BIT0
|
||||
#define GPIO_CTRL_DISABLEMODULE_ENABLE (0UL << 0)
|
||||
#define GPIO_CTRL_DISABLEMODULE_DISABLE BIT0
|
||||
|
||||
#define GPIO_OE_MASK(x) (1UL << (x))
|
||||
#define GPIO_OE_OUTPUT(x) (0UL << (x))
|
||||
#define GPIO_OE_INPUT(x) (1UL << (x))
|
||||
|
||||
#define GPIO_DATAIN_MASK(x) (1UL << (x))
|
||||
|
||||
#define GPIO_DATAOUT_MASK(x) (1UL << (x))
|
||||
|
||||
#define GPIO_LEVELDETECT_MASK(x) (1UL << (x))
|
||||
#define GPIO_LEVELDETECT_DISABLE(x) (0UL << (x))
|
||||
#define GPIO_LEVELDETECT_ENABLE(x) (1UL << (x))
|
||||
|
||||
#define GPIO_RISINGDETECT_MASK(x) (1UL << (x))
|
||||
#define GPIO_RISINGDETECT_DISABLE(x) (0UL << (x))
|
||||
#define GPIO_RISINGDETECT_ENABLE(x) (1UL << (x))
|
||||
|
||||
#define GPIO_FALLINGDETECT_MASK(x) (1UL << (x))
|
||||
#define GPIO_FALLINGDETECT_DISABLE(x) (0UL << (x))
|
||||
#define GPIO_FALLINGDETECT_ENABLE(x) (1UL << (x))
|
||||
|
||||
#define GPIO_DEBOUNCENABLE_MASK(x) (1UL << (x))
|
||||
#define GPIO_DEBOUNCENABLE_DISABLE(x) (0UL << (x))
|
||||
#define GPIO_DEBOUNCENABLE_ENABLE(x) (1UL << (x))
|
||||
|
||||
#define GPIO_DEBOUNCINGTIME_MASK (0xFF)
|
||||
#define GPIO_DEBOUNCINGTIME_US(x) ((((x) / 31) - 1) & GPIO_DEBOUNCINGTIME_MASK)
|
||||
|
||||
#define GPIO_CLEARIRQENABLE_BIT(x) (1UL << (x))
|
||||
|
||||
#define GPIO_SETIRQENABLE_BIT(x) (1UL << (x))
|
||||
|
||||
#define GPIO_CLEARWKUENA_BIT(x) (1UL << (x))
|
||||
|
||||
#define GPIO_SETWKUENA_BIT(x) (1UL << (x))
|
||||
|
||||
#define GPIO_CLEARDATAOUT_BIT(x) (1UL << (x))
|
||||
|
||||
#define GPIO_SETDATAOUT_BIT(x) (1UL << (x))
|
||||
|
||||
#endif // __OMAP3530GPIO_H__
|
||||
|
||||
|
||||
@@ -1,107 +1,107 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
||||
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __OMAP3530GPMC_H__
|
||||
#define __OMAP3530GPMC_H__
|
||||
|
||||
#define GPMC_BASE (0x6E000000)
|
||||
|
||||
//GPMC NAND definitions.
|
||||
#define GPMC_SYSCONFIG (GPMC_BASE + 0x10)
|
||||
#define SMARTIDLEMODE (0x2UL << 3)
|
||||
|
||||
#define GPMC_SYSSTATUS (GPMC_BASE + 0x14)
|
||||
#define GPMC_IRQSTATUS (GPMC_BASE + 0x18)
|
||||
#define GPMC_IRQENABLE (GPMC_BASE + 0x1C)
|
||||
|
||||
#define GPMC_TIMEOUT_CONTROL (GPMC_BASE + 0x40)
|
||||
#define TIMEOUTENABLE BIT0
|
||||
#define TIMEOUTDISABLE (0x0UL << 0)
|
||||
|
||||
#define GPMC_ERR_ADDRESS (GPMC_BASE + 0x44)
|
||||
#define GPMC_ERR_TYPE (GPMC_BASE + 0x48)
|
||||
|
||||
#define GPMC_CONFIG (GPMC_BASE + 0x50)
|
||||
#define WRITEPROTECT_HIGH BIT4
|
||||
#define WRITEPROTECT_LOW (0x0UL << 4)
|
||||
|
||||
#define GPMC_STATUS (GPMC_BASE + 0x54)
|
||||
|
||||
#define GPMC_CONFIG1_0 (GPMC_BASE + 0x60)
|
||||
#define DEVICETYPE_NOR (0x0UL << 10)
|
||||
#define DEVICETYPE_NAND (0x2UL << 10)
|
||||
#define DEVICESIZE_X8 (0x0UL << 12)
|
||||
#define DEVICESIZE_X16 BIT12
|
||||
|
||||
#define GPMC_CONFIG2_0 (GPMC_BASE + 0x64)
|
||||
#define CSONTIME (0x0UL << 0)
|
||||
#define CSRDOFFTIME (0x14UL << 8)
|
||||
#define CSWROFFTIME (0x14UL << 16)
|
||||
|
||||
#define GPMC_CONFIG3_0 (GPMC_BASE + 0x68)
|
||||
#define ADVRDOFFTIME (0x14UL << 8)
|
||||
#define ADVWROFFTIME (0x14UL << 16)
|
||||
|
||||
#define GPMC_CONFIG4_0 (GPMC_BASE + 0x6C)
|
||||
#define OEONTIME BIT0
|
||||
#define OEOFFTIME (0xFUL << 8)
|
||||
#define WEONTIME BIT16
|
||||
#define WEOFFTIME (0xFUL << 24)
|
||||
|
||||
#define GPMC_CONFIG5_0 (GPMC_BASE + 0x70)
|
||||
#define RDCYCLETIME (0x14UL << 0)
|
||||
#define WRCYCLETIME (0x14UL << 8)
|
||||
#define RDACCESSTIME (0xCUL << 16)
|
||||
#define PAGEBURSTACCESSTIME BIT24
|
||||
|
||||
#define GPMC_CONFIG6_0 (GPMC_BASE + 0x74)
|
||||
#define CYCLE2CYCLESAMECSEN BIT7
|
||||
#define CYCLE2CYCLEDELAY (0xAUL << 8)
|
||||
#define WRDATAONADMUXBUS (0xFUL << 16)
|
||||
#define WRACCESSTIME BIT24
|
||||
|
||||
#define GPMC_CONFIG7_0 (GPMC_BASE + 0x78)
|
||||
#define BASEADDRESS (0x30UL << 0)
|
||||
#define CSVALID BIT6
|
||||
#define MASKADDRESS_128MB (0x8UL << 8)
|
||||
|
||||
#define GPMC_NAND_COMMAND_0 (GPMC_BASE + 0x7C)
|
||||
#define GPMC_NAND_ADDRESS_0 (GPMC_BASE + 0x80)
|
||||
#define GPMC_NAND_DATA_0 (GPMC_BASE + 0x84)
|
||||
|
||||
#define GPMC_ECC_CONFIG (GPMC_BASE + 0x1F4)
|
||||
#define ECCENABLE BIT0
|
||||
#define ECCDISABLE (0x0UL << 0)
|
||||
#define ECCCS_0 (0x0UL << 1)
|
||||
#define ECC16B BIT7
|
||||
|
||||
#define GPMC_ECC_CONTROL (GPMC_BASE + 0x1F8)
|
||||
#define ECCPOINTER_REG1 BIT0
|
||||
#define ECCCLEAR BIT8
|
||||
|
||||
#define GPMC_ECC_SIZE_CONFIG (GPMC_BASE + 0x1FC)
|
||||
#define ECCSIZE0_512BYTES (0xFFUL << 12)
|
||||
#define ECCSIZE1_512BYTES (0xFFUL << 22)
|
||||
|
||||
#define GPMC_ECC1_RESULT (GPMC_BASE + 0x200)
|
||||
#define GPMC_ECC2_RESULT (GPMC_BASE + 0x204)
|
||||
#define GPMC_ECC3_RESULT (GPMC_BASE + 0x208)
|
||||
#define GPMC_ECC4_RESULT (GPMC_BASE + 0x20C)
|
||||
#define GPMC_ECC5_RESULT (GPMC_BASE + 0x210)
|
||||
#define GPMC_ECC6_RESULT (GPMC_BASE + 0x214)
|
||||
#define GPMC_ECC7_RESULT (GPMC_BASE + 0x218)
|
||||
#define GPMC_ECC8_RESULT (GPMC_BASE + 0x21C)
|
||||
#define GPMC_ECC9_RESULT (GPMC_BASE + 0x220)
|
||||
|
||||
#endif //__OMAP3530GPMC_H__
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
||||
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __OMAP3530GPMC_H__
|
||||
#define __OMAP3530GPMC_H__
|
||||
|
||||
#define GPMC_BASE (0x6E000000)
|
||||
|
||||
//GPMC NAND definitions.
|
||||
#define GPMC_SYSCONFIG (GPMC_BASE + 0x10)
|
||||
#define SMARTIDLEMODE (0x2UL << 3)
|
||||
|
||||
#define GPMC_SYSSTATUS (GPMC_BASE + 0x14)
|
||||
#define GPMC_IRQSTATUS (GPMC_BASE + 0x18)
|
||||
#define GPMC_IRQENABLE (GPMC_BASE + 0x1C)
|
||||
|
||||
#define GPMC_TIMEOUT_CONTROL (GPMC_BASE + 0x40)
|
||||
#define TIMEOUTENABLE BIT0
|
||||
#define TIMEOUTDISABLE (0x0UL << 0)
|
||||
|
||||
#define GPMC_ERR_ADDRESS (GPMC_BASE + 0x44)
|
||||
#define GPMC_ERR_TYPE (GPMC_BASE + 0x48)
|
||||
|
||||
#define GPMC_CONFIG (GPMC_BASE + 0x50)
|
||||
#define WRITEPROTECT_HIGH BIT4
|
||||
#define WRITEPROTECT_LOW (0x0UL << 4)
|
||||
|
||||
#define GPMC_STATUS (GPMC_BASE + 0x54)
|
||||
|
||||
#define GPMC_CONFIG1_0 (GPMC_BASE + 0x60)
|
||||
#define DEVICETYPE_NOR (0x0UL << 10)
|
||||
#define DEVICETYPE_NAND (0x2UL << 10)
|
||||
#define DEVICESIZE_X8 (0x0UL << 12)
|
||||
#define DEVICESIZE_X16 BIT12
|
||||
|
||||
#define GPMC_CONFIG2_0 (GPMC_BASE + 0x64)
|
||||
#define CSONTIME (0x0UL << 0)
|
||||
#define CSRDOFFTIME (0x14UL << 8)
|
||||
#define CSWROFFTIME (0x14UL << 16)
|
||||
|
||||
#define GPMC_CONFIG3_0 (GPMC_BASE + 0x68)
|
||||
#define ADVRDOFFTIME (0x14UL << 8)
|
||||
#define ADVWROFFTIME (0x14UL << 16)
|
||||
|
||||
#define GPMC_CONFIG4_0 (GPMC_BASE + 0x6C)
|
||||
#define OEONTIME BIT0
|
||||
#define OEOFFTIME (0xFUL << 8)
|
||||
#define WEONTIME BIT16
|
||||
#define WEOFFTIME (0xFUL << 24)
|
||||
|
||||
#define GPMC_CONFIG5_0 (GPMC_BASE + 0x70)
|
||||
#define RDCYCLETIME (0x14UL << 0)
|
||||
#define WRCYCLETIME (0x14UL << 8)
|
||||
#define RDACCESSTIME (0xCUL << 16)
|
||||
#define PAGEBURSTACCESSTIME BIT24
|
||||
|
||||
#define GPMC_CONFIG6_0 (GPMC_BASE + 0x74)
|
||||
#define CYCLE2CYCLESAMECSEN BIT7
|
||||
#define CYCLE2CYCLEDELAY (0xAUL << 8)
|
||||
#define WRDATAONADMUXBUS (0xFUL << 16)
|
||||
#define WRACCESSTIME BIT24
|
||||
|
||||
#define GPMC_CONFIG7_0 (GPMC_BASE + 0x78)
|
||||
#define BASEADDRESS (0x30UL << 0)
|
||||
#define CSVALID BIT6
|
||||
#define MASKADDRESS_128MB (0x8UL << 8)
|
||||
|
||||
#define GPMC_NAND_COMMAND_0 (GPMC_BASE + 0x7C)
|
||||
#define GPMC_NAND_ADDRESS_0 (GPMC_BASE + 0x80)
|
||||
#define GPMC_NAND_DATA_0 (GPMC_BASE + 0x84)
|
||||
|
||||
#define GPMC_ECC_CONFIG (GPMC_BASE + 0x1F4)
|
||||
#define ECCENABLE BIT0
|
||||
#define ECCDISABLE (0x0UL << 0)
|
||||
#define ECCCS_0 (0x0UL << 1)
|
||||
#define ECC16B BIT7
|
||||
|
||||
#define GPMC_ECC_CONTROL (GPMC_BASE + 0x1F8)
|
||||
#define ECCPOINTER_REG1 BIT0
|
||||
#define ECCCLEAR BIT8
|
||||
|
||||
#define GPMC_ECC_SIZE_CONFIG (GPMC_BASE + 0x1FC)
|
||||
#define ECCSIZE0_512BYTES (0xFFUL << 12)
|
||||
#define ECCSIZE1_512BYTES (0xFFUL << 22)
|
||||
|
||||
#define GPMC_ECC1_RESULT (GPMC_BASE + 0x200)
|
||||
#define GPMC_ECC2_RESULT (GPMC_BASE + 0x204)
|
||||
#define GPMC_ECC3_RESULT (GPMC_BASE + 0x208)
|
||||
#define GPMC_ECC4_RESULT (GPMC_BASE + 0x20C)
|
||||
#define GPMC_ECC5_RESULT (GPMC_BASE + 0x210)
|
||||
#define GPMC_ECC6_RESULT (GPMC_BASE + 0x214)
|
||||
#define GPMC_ECC7_RESULT (GPMC_BASE + 0x218)
|
||||
#define GPMC_ECC8_RESULT (GPMC_BASE + 0x21C)
|
||||
#define GPMC_ECC9_RESULT (GPMC_BASE + 0x220)
|
||||
|
||||
#endif //__OMAP3530GPMC_H__
|
||||
|
||||
@@ -1,62 +1,62 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
||||
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __OMAP3530I2C_H__
|
||||
#define __OMAP3530I2C_H__
|
||||
|
||||
//I2C register definitions.
|
||||
#define I2C1BASE 0x48070000
|
||||
|
||||
#define I2C_IE (I2C1BASE + 0x4)
|
||||
#define XRDY_IE BIT4
|
||||
#define RRDY_IE BIT3
|
||||
#define ARDY_IE BIT2
|
||||
#define NACK_IE BIT1
|
||||
|
||||
#define I2C_STAT (I2C1BASE + 0x8)
|
||||
#define BB BIT12
|
||||
#define XRDY BIT4
|
||||
#define RRDY BIT3
|
||||
#define ARDY BIT2
|
||||
#define NACK BIT1
|
||||
|
||||
#define I2C_WE (I2C1BASE + 0xC)
|
||||
#define I2C_SYSS (I2C1BASE + 0x10)
|
||||
#define I2C_BUF (I2C1BASE + 0x14)
|
||||
#define I2C_CNT (I2C1BASE + 0x18)
|
||||
#define I2C_DATA (I2C1BASE + 0x1C)
|
||||
#define I2C_SYSC (I2C1BASE + 0x20)
|
||||
|
||||
#define I2C_CON (I2C1BASE + 0x24)
|
||||
#define STT BIT0
|
||||
#define STP BIT1
|
||||
#define XSA BIT8
|
||||
#define TRX BIT9
|
||||
#define MST BIT10
|
||||
#define I2C_EN BIT15
|
||||
|
||||
#define I2C_OA0 (I2C1BASE + 0x28)
|
||||
#define I2C_SA (I2C1BASE + 0x2C)
|
||||
#define I2C_PSC (I2C1BASE + 0x30)
|
||||
#define I2C_SCLL (I2C1BASE + 0x34)
|
||||
#define I2C_SCLH (I2C1BASE + 0x38)
|
||||
#define I2C_SYSTEST (I2C1BASE + 0x3C)
|
||||
#define I2C_BUFSTAT (I2C1BASE + 0x40)
|
||||
#define I2C_OA1 (I2C1BASE + 0x44)
|
||||
#define I2C_OA2 (I2C1BASE + 0x48)
|
||||
#define I2C_OA3 (I2C1BASE + 0x4C)
|
||||
#define I2C_ACTOA (I2C1BASE + 0x50)
|
||||
#define I2C_SBLOCK (I2C1BASE + 0x54)
|
||||
|
||||
#endif //__OMAP3530I2C_H__
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
||||
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __OMAP3530I2C_H__
|
||||
#define __OMAP3530I2C_H__
|
||||
|
||||
//I2C register definitions.
|
||||
#define I2C1BASE 0x48070000
|
||||
|
||||
#define I2C_IE (I2C1BASE + 0x4)
|
||||
#define XRDY_IE BIT4
|
||||
#define RRDY_IE BIT3
|
||||
#define ARDY_IE BIT2
|
||||
#define NACK_IE BIT1
|
||||
|
||||
#define I2C_STAT (I2C1BASE + 0x8)
|
||||
#define BB BIT12
|
||||
#define XRDY BIT4
|
||||
#define RRDY BIT3
|
||||
#define ARDY BIT2
|
||||
#define NACK BIT1
|
||||
|
||||
#define I2C_WE (I2C1BASE + 0xC)
|
||||
#define I2C_SYSS (I2C1BASE + 0x10)
|
||||
#define I2C_BUF (I2C1BASE + 0x14)
|
||||
#define I2C_CNT (I2C1BASE + 0x18)
|
||||
#define I2C_DATA (I2C1BASE + 0x1C)
|
||||
#define I2C_SYSC (I2C1BASE + 0x20)
|
||||
|
||||
#define I2C_CON (I2C1BASE + 0x24)
|
||||
#define STT BIT0
|
||||
#define STP BIT1
|
||||
#define XSA BIT8
|
||||
#define TRX BIT9
|
||||
#define MST BIT10
|
||||
#define I2C_EN BIT15
|
||||
|
||||
#define I2C_OA0 (I2C1BASE + 0x28)
|
||||
#define I2C_SA (I2C1BASE + 0x2C)
|
||||
#define I2C_PSC (I2C1BASE + 0x30)
|
||||
#define I2C_SCLL (I2C1BASE + 0x34)
|
||||
#define I2C_SCLH (I2C1BASE + 0x38)
|
||||
#define I2C_SYSTEST (I2C1BASE + 0x3C)
|
||||
#define I2C_BUFSTAT (I2C1BASE + 0x40)
|
||||
#define I2C_OA1 (I2C1BASE + 0x44)
|
||||
#define I2C_OA2 (I2C1BASE + 0x48)
|
||||
#define I2C_OA3 (I2C1BASE + 0x4C)
|
||||
#define I2C_ACTOA (I2C1BASE + 0x50)
|
||||
#define I2C_SBLOCK (I2C1BASE + 0x54)
|
||||
|
||||
#endif //__OMAP3530I2C_H__
|
||||
|
||||
@@ -1,48 +1,48 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
||||
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __OMAP3530INTERRUPT_H__
|
||||
#define __OMAP3530INTERRUPT_H__
|
||||
|
||||
#define INTERRUPT_BASE (0x48200000)
|
||||
|
||||
#define INT_NROF_VECTORS (96)
|
||||
#define MAX_VECTOR (INT_NROF_VECTORS - 1)
|
||||
#define INTCPS_SYSCONFIG (INTERRUPT_BASE + 0x0010)
|
||||
#define INTCPS_SYSSTATUS (INTERRUPT_BASE + 0x0014)
|
||||
#define INTCPS_SIR_IRQ (INTERRUPT_BASE + 0x0040)
|
||||
#define INTCPS_SIR_IFQ (INTERRUPT_BASE + 0x0044)
|
||||
#define INTCPS_CONTROL (INTERRUPT_BASE + 0x0048)
|
||||
#define INTCPS_PROTECTION (INTERRUPT_BASE + 0x004C)
|
||||
#define INTCPS_IDLE (INTERRUPT_BASE + 0x0050)
|
||||
#define INTCPS_IRQ_PRIORITY (INTERRUPT_BASE + 0x0060)
|
||||
#define INTCPS_FIQ_PRIORITY (INTERRUPT_BASE + 0x0064)
|
||||
#define INTCPS_THRESHOLD (INTERRUPT_BASE + 0x0068)
|
||||
#define INTCPS_ITR(n) (INTERRUPT_BASE + 0x0080 + (0x20 * (n)))
|
||||
#define INTCPS_MIR(n) (INTERRUPT_BASE + 0x0084 + (0x20 * (n)))
|
||||
#define INTCPS_MIR_CLEAR(n) (INTERRUPT_BASE + 0x0088 + (0x20 * (n)))
|
||||
#define INTCPS_MIR_SET(n) (INTERRUPT_BASE + 0x008C + (0x20 * (n)))
|
||||
#define INTCPS_ISR_SET(n) (INTERRUPT_BASE + 0x0090 + (0x20 * (n)))
|
||||
#define INTCPS_ISR_CLEAR(n) (INTERRUPT_BASE + 0x0094 + (0x20 * (n)))
|
||||
#define INTCPS_PENDING_IRQ(n) (INTERRUPT_BASE + 0x0098 + (0x20 * (n)))
|
||||
#define INTCPS_PENDING_FIQ(n) (INTERRUPT_BASE + 0x009C + (0x20 * (n)))
|
||||
#define INTCPS_ILR(m) (INTERRUPT_BASE + 0x0100 + (0x04 * (m)))
|
||||
|
||||
#define INTCPS_ILR_FIQ BIT0
|
||||
#define INTCPS_SIR_IRQ_MASK (0x7F)
|
||||
#define INTCPS_CONTROL_NEWIRQAGR BIT0
|
||||
#define INTCPS_CONTROL_NEWFIQAGR BIT1
|
||||
|
||||
#endif // __OMAP3530INTERRUPT_H__
|
||||
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
||||
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __OMAP3530INTERRUPT_H__
|
||||
#define __OMAP3530INTERRUPT_H__
|
||||
|
||||
#define INTERRUPT_BASE (0x48200000)
|
||||
|
||||
#define INT_NROF_VECTORS (96)
|
||||
#define MAX_VECTOR (INT_NROF_VECTORS - 1)
|
||||
#define INTCPS_SYSCONFIG (INTERRUPT_BASE + 0x0010)
|
||||
#define INTCPS_SYSSTATUS (INTERRUPT_BASE + 0x0014)
|
||||
#define INTCPS_SIR_IRQ (INTERRUPT_BASE + 0x0040)
|
||||
#define INTCPS_SIR_IFQ (INTERRUPT_BASE + 0x0044)
|
||||
#define INTCPS_CONTROL (INTERRUPT_BASE + 0x0048)
|
||||
#define INTCPS_PROTECTION (INTERRUPT_BASE + 0x004C)
|
||||
#define INTCPS_IDLE (INTERRUPT_BASE + 0x0050)
|
||||
#define INTCPS_IRQ_PRIORITY (INTERRUPT_BASE + 0x0060)
|
||||
#define INTCPS_FIQ_PRIORITY (INTERRUPT_BASE + 0x0064)
|
||||
#define INTCPS_THRESHOLD (INTERRUPT_BASE + 0x0068)
|
||||
#define INTCPS_ITR(n) (INTERRUPT_BASE + 0x0080 + (0x20 * (n)))
|
||||
#define INTCPS_MIR(n) (INTERRUPT_BASE + 0x0084 + (0x20 * (n)))
|
||||
#define INTCPS_MIR_CLEAR(n) (INTERRUPT_BASE + 0x0088 + (0x20 * (n)))
|
||||
#define INTCPS_MIR_SET(n) (INTERRUPT_BASE + 0x008C + (0x20 * (n)))
|
||||
#define INTCPS_ISR_SET(n) (INTERRUPT_BASE + 0x0090 + (0x20 * (n)))
|
||||
#define INTCPS_ISR_CLEAR(n) (INTERRUPT_BASE + 0x0094 + (0x20 * (n)))
|
||||
#define INTCPS_PENDING_IRQ(n) (INTERRUPT_BASE + 0x0098 + (0x20 * (n)))
|
||||
#define INTCPS_PENDING_FIQ(n) (INTERRUPT_BASE + 0x009C + (0x20 * (n)))
|
||||
#define INTCPS_ILR(m) (INTERRUPT_BASE + 0x0100 + (0x04 * (m)))
|
||||
|
||||
#define INTCPS_ILR_FIQ BIT0
|
||||
#define INTCPS_SIR_IRQ_MASK (0x7F)
|
||||
#define INTCPS_CONTROL_NEWIRQAGR BIT0
|
||||
#define INTCPS_CONTROL_NEWFIQAGR BIT1
|
||||
|
||||
#endif // __OMAP3530INTERRUPT_H__
|
||||
|
||||
|
||||
@@ -1,214 +1,214 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
||||
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __OMAP3530SDIO_H__
|
||||
#define __OMAP3530SDIO_H__
|
||||
|
||||
//MMC/SD/SDIO1 register definitions.
|
||||
#define MMCHS1BASE 0x4809C000
|
||||
#define MMC_REFERENCE_CLK (96000000)
|
||||
|
||||
#define MMCHS_SYSCONFIG (MMCHS1BASE + 0x10)
|
||||
#define SOFTRESET BIT1
|
||||
#define ENAWAKEUP BIT2
|
||||
|
||||
#define MMCHS_SYSSTATUS (MMCHS1BASE + 0x14)
|
||||
#define RESETDONE_MASK BIT0
|
||||
#define RESETDONE BIT0
|
||||
|
||||
#define MMCHS_CSRE (MMCHS1BASE + 0x24)
|
||||
#define MMCHS_SYSTEST (MMCHS1BASE + 0x28)
|
||||
|
||||
#define MMCHS_CON (MMCHS1BASE + 0x2C)
|
||||
#define OD BIT0
|
||||
#define NOINIT (0x0UL << 1)
|
||||
#define INIT BIT1
|
||||
#define HR BIT2
|
||||
#define STR BIT3
|
||||
#define MODE BIT4
|
||||
#define DW8_1_4_BIT (0x0UL << 5)
|
||||
#define DW8_8_BIT BIT5
|
||||
#define MIT BIT6
|
||||
#define CDP BIT7
|
||||
#define WPP BIT8
|
||||
#define CTPL BIT11
|
||||
#define CEATA_OFF (0x0UL << 12)
|
||||
#define CEATA_ON BIT12
|
||||
|
||||
#define MMCHS_PWCNT (MMCHS1BASE + 0x30)
|
||||
|
||||
#define MMCHS_BLK (MMCHS1BASE + 0x104)
|
||||
#define BLEN_512BYTES (0x200UL << 0)
|
||||
|
||||
#define MMCHS_ARG (MMCHS1BASE + 0x108)
|
||||
|
||||
#define MMCHS_CMD (MMCHS1BASE + 0x10C)
|
||||
#define DE_ENABLE BIT0
|
||||
#define BCE_ENABLE BIT1
|
||||
#define ACEN_ENABLE BIT2
|
||||
#define DDIR_READ BIT4
|
||||
#define DDIR_WRITE (0x0UL << 4)
|
||||
#define MSBS_SGLEBLK (0x0UL << 5)
|
||||
#define MSBS_MULTBLK BIT5
|
||||
#define RSP_TYPE_MASK (0x3UL << 16)
|
||||
#define RSP_TYPE_136BITS BIT16
|
||||
#define RSP_TYPE_48BITS (0x2UL << 16)
|
||||
#define CCCE_ENABLE BIT19
|
||||
#define CICE_ENABLE BIT20
|
||||
#define DP_ENABLE BIT21
|
||||
#define INDX(CMD_INDX) ((CMD_INDX & 0x3F) << 24)
|
||||
|
||||
#define MMCHS_RSP10 (MMCHS1BASE + 0x110)
|
||||
#define MMCHS_RSP32 (MMCHS1BASE + 0x114)
|
||||
#define MMCHS_RSP54 (MMCHS1BASE + 0x118)
|
||||
#define MMCHS_RSP76 (MMCHS1BASE + 0x11C)
|
||||
#define MMCHS_DATA (MMCHS1BASE + 0x120)
|
||||
|
||||
#define MMCHS_PSTATE (MMCHS1BASE + 0x124)
|
||||
#define CMDI_MASK BIT0
|
||||
#define CMDI_ALLOWED (0x0UL << 0)
|
||||
#define CMDI_NOT_ALLOWED BIT0
|
||||
#define DATI_MASK BIT1
|
||||
#define DATI_ALLOWED (0x0UL << 1)
|
||||
#define DATI_NOT_ALLOWED BIT1
|
||||
|
||||
#define MMCHS_HCTL (MMCHS1BASE + 0x128)
|
||||
#define DTW_1_BIT (0x0UL << 1)
|
||||
#define DTW_4_BIT BIT1
|
||||
#define SDBP_MASK BIT8
|
||||
#define SDBP_OFF (0x0UL << 8)
|
||||
#define SDBP_ON BIT8
|
||||
#define SDVS_1_8_V (0x5UL << 9)
|
||||
#define SDVS_3_0_V (0x6UL << 9)
|
||||
#define IWE BIT24
|
||||
|
||||
#define MMCHS_SYSCTL (MMCHS1BASE + 0x12C)
|
||||
#define ICE BIT0
|
||||
#define ICS_MASK BIT1
|
||||
#define ICS BIT1
|
||||
#define CEN BIT2
|
||||
#define CLKD_MASK (0x3FFUL << 6)
|
||||
#define CLKD_80KHZ (0x258UL) //(96*1000/80)/2
|
||||
#define CLKD_400KHZ (0xF0UL)
|
||||
#define DTO_MASK (0xFUL << 16)
|
||||
#define DTO_VAL (0xEUL << 16)
|
||||
#define SRA BIT24
|
||||
#define SRC_MASK BIT25
|
||||
#define SRC BIT25
|
||||
#define SRD BIT26
|
||||
|
||||
#define MMCHS_STAT (MMCHS1BASE + 0x130)
|
||||
#define CC BIT0
|
||||
#define TC BIT1
|
||||
#define BWR BIT4
|
||||
#define BRR BIT5
|
||||
#define ERRI BIT15
|
||||
#define CTO BIT16
|
||||
#define DTO BIT20
|
||||
#define DCRC BIT21
|
||||
#define DEB BIT22
|
||||
|
||||
#define MMCHS_IE (MMCHS1BASE + 0x134)
|
||||
#define CC_EN BIT0
|
||||
#define TC_EN BIT1
|
||||
#define BWR_EN BIT4
|
||||
#define BRR_EN BIT5
|
||||
#define CTO_EN BIT16
|
||||
#define CCRC_EN BIT17
|
||||
#define CEB_EN BIT18
|
||||
#define CIE_EN BIT19
|
||||
#define DTO_EN BIT20
|
||||
#define DCRC_EN BIT21
|
||||
#define DEB_EN BIT22
|
||||
#define CERR_EN BIT28
|
||||
#define BADA_EN BIT29
|
||||
|
||||
#define MMCHS_ISE (MMCHS1BASE + 0x138)
|
||||
#define CC_SIGEN BIT0
|
||||
#define TC_SIGEN BIT1
|
||||
#define BWR_SIGEN BIT4
|
||||
#define BRR_SIGEN BIT5
|
||||
#define CTO_SIGEN BIT16
|
||||
#define CCRC_SIGEN BIT17
|
||||
#define CEB_SIGEN BIT18
|
||||
#define CIE_SIGEN BIT19
|
||||
#define DTO_SIGEN BIT20
|
||||
#define DCRC_SIGEN BIT21
|
||||
#define DEB_SIGEN BIT22
|
||||
#define CERR_SIGEN BIT28
|
||||
#define BADA_SIGEN BIT29
|
||||
|
||||
#define MMCHS_AC12 (MMCHS1BASE + 0x13C)
|
||||
|
||||
#define MMCHS_CAPA (MMCHS1BASE + 0x140)
|
||||
#define VS30 BIT25
|
||||
#define VS18 BIT26
|
||||
|
||||
#define MMCHS_CUR_CAPA (MMCHS1BASE + 0x148)
|
||||
#define MMCHS_REV (MMCHS1BASE + 0x1FC)
|
||||
|
||||
#define CMD0 INDX(0)
|
||||
#define CMD0_INT_EN (CC_EN | CEB_EN)
|
||||
|
||||
#define CMD1 (INDX(1) | RSP_TYPE_48BITS)
|
||||
#define CMD1_INT_EN (CC_EN | CEB_EN | CTO_EN)
|
||||
|
||||
#define CMD2 (INDX(2) | CCCE_ENABLE | RSP_TYPE_136BITS)
|
||||
#define CMD2_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
|
||||
|
||||
#define CMD3 (INDX(3) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
|
||||
#define CMD3_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
|
||||
|
||||
#define CMD5 (INDX(5) | RSP_TYPE_48BITS)
|
||||
#define CMD5_INT_EN (CC_EN | CEB_EN | CTO_EN)
|
||||
|
||||
#define CMD7 (INDX(7) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
|
||||
#define CMD7_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
|
||||
|
||||
#define CMD8 (INDX(8) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
|
||||
#define CMD8_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
|
||||
//Reserved(0)[12:31], Supply voltage(1)[11:8], check pattern(0xCE)[7:0] = 0x1CE
|
||||
#define CMD8_ARG (0x0UL << 12 | BIT8 | 0xCEUL << 0)
|
||||
|
||||
#define CMD9 (INDX(9) | CCCE_ENABLE | RSP_TYPE_136BITS)
|
||||
#define CMD9_INT_EN (CCRC_EN | CC_EN | CEB_EN | CTO_EN)
|
||||
|
||||
#define CMD16 (INDX(16) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
|
||||
#define CMD16_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
|
||||
|
||||
#define CMD17 (INDX(17) | DP_ENABLE | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS | DDIR_READ)
|
||||
#define CMD17_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | TC_EN | BRR_EN | CTO_EN | DTO_EN | DCRC_EN | DEB_EN | CEB_EN)
|
||||
|
||||
#define CMD18 (INDX(18) | DP_ENABLE | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS | MSBS_MULTBLK | DDIR_READ | BCE_ENABLE | DE_ENABLE)
|
||||
#define CMD18_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | TC_EN | BRR_EN | CTO_EN | DTO_EN | DCRC_EN | DEB_EN | CEB_EN)
|
||||
|
||||
#define CMD23 (INDX(23) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
|
||||
#define CMD23_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
|
||||
|
||||
#define CMD24 (INDX(24) | DP_ENABLE | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS | DDIR_WRITE)
|
||||
#define CMD24_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | TC_EN | BWR_EN | CTO_EN | DTO_EN | DCRC_EN | DEB_EN | CEB_EN)
|
||||
|
||||
#define CMD25 (INDX(25) | DP_ENABLE | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS | MSBS_MULTBLK | DDIR_READ | BCE_ENABLE | DE_ENABLE)
|
||||
#define CMD25_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | TC_EN | BRR_EN | CTO_EN | DTO_EN | DCRC_EN | DEB_EN | CEB_EN)
|
||||
|
||||
#define CMD55 (INDX(55) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
|
||||
#define CMD55_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
|
||||
|
||||
#define ACMD41 (INDX(41) | RSP_TYPE_48BITS)
|
||||
#define ACMD41_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
|
||||
|
||||
#define ACMD6 (INDX(6) | RSP_TYPE_48BITS)
|
||||
#define ACMD6_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
|
||||
|
||||
#endif //__OMAP3530SDIO_H__
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
||||
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __OMAP3530SDIO_H__
|
||||
#define __OMAP3530SDIO_H__
|
||||
|
||||
//MMC/SD/SDIO1 register definitions.
|
||||
#define MMCHS1BASE 0x4809C000
|
||||
#define MMC_REFERENCE_CLK (96000000)
|
||||
|
||||
#define MMCHS_SYSCONFIG (MMCHS1BASE + 0x10)
|
||||
#define SOFTRESET BIT1
|
||||
#define ENAWAKEUP BIT2
|
||||
|
||||
#define MMCHS_SYSSTATUS (MMCHS1BASE + 0x14)
|
||||
#define RESETDONE_MASK BIT0
|
||||
#define RESETDONE BIT0
|
||||
|
||||
#define MMCHS_CSRE (MMCHS1BASE + 0x24)
|
||||
#define MMCHS_SYSTEST (MMCHS1BASE + 0x28)
|
||||
|
||||
#define MMCHS_CON (MMCHS1BASE + 0x2C)
|
||||
#define OD BIT0
|
||||
#define NOINIT (0x0UL << 1)
|
||||
#define INIT BIT1
|
||||
#define HR BIT2
|
||||
#define STR BIT3
|
||||
#define MODE BIT4
|
||||
#define DW8_1_4_BIT (0x0UL << 5)
|
||||
#define DW8_8_BIT BIT5
|
||||
#define MIT BIT6
|
||||
#define CDP BIT7
|
||||
#define WPP BIT8
|
||||
#define CTPL BIT11
|
||||
#define CEATA_OFF (0x0UL << 12)
|
||||
#define CEATA_ON BIT12
|
||||
|
||||
#define MMCHS_PWCNT (MMCHS1BASE + 0x30)
|
||||
|
||||
#define MMCHS_BLK (MMCHS1BASE + 0x104)
|
||||
#define BLEN_512BYTES (0x200UL << 0)
|
||||
|
||||
#define MMCHS_ARG (MMCHS1BASE + 0x108)
|
||||
|
||||
#define MMCHS_CMD (MMCHS1BASE + 0x10C)
|
||||
#define DE_ENABLE BIT0
|
||||
#define BCE_ENABLE BIT1
|
||||
#define ACEN_ENABLE BIT2
|
||||
#define DDIR_READ BIT4
|
||||
#define DDIR_WRITE (0x0UL << 4)
|
||||
#define MSBS_SGLEBLK (0x0UL << 5)
|
||||
#define MSBS_MULTBLK BIT5
|
||||
#define RSP_TYPE_MASK (0x3UL << 16)
|
||||
#define RSP_TYPE_136BITS BIT16
|
||||
#define RSP_TYPE_48BITS (0x2UL << 16)
|
||||
#define CCCE_ENABLE BIT19
|
||||
#define CICE_ENABLE BIT20
|
||||
#define DP_ENABLE BIT21
|
||||
#define INDX(CMD_INDX) ((CMD_INDX & 0x3F) << 24)
|
||||
|
||||
#define MMCHS_RSP10 (MMCHS1BASE + 0x110)
|
||||
#define MMCHS_RSP32 (MMCHS1BASE + 0x114)
|
||||
#define MMCHS_RSP54 (MMCHS1BASE + 0x118)
|
||||
#define MMCHS_RSP76 (MMCHS1BASE + 0x11C)
|
||||
#define MMCHS_DATA (MMCHS1BASE + 0x120)
|
||||
|
||||
#define MMCHS_PSTATE (MMCHS1BASE + 0x124)
|
||||
#define CMDI_MASK BIT0
|
||||
#define CMDI_ALLOWED (0x0UL << 0)
|
||||
#define CMDI_NOT_ALLOWED BIT0
|
||||
#define DATI_MASK BIT1
|
||||
#define DATI_ALLOWED (0x0UL << 1)
|
||||
#define DATI_NOT_ALLOWED BIT1
|
||||
|
||||
#define MMCHS_HCTL (MMCHS1BASE + 0x128)
|
||||
#define DTW_1_BIT (0x0UL << 1)
|
||||
#define DTW_4_BIT BIT1
|
||||
#define SDBP_MASK BIT8
|
||||
#define SDBP_OFF (0x0UL << 8)
|
||||
#define SDBP_ON BIT8
|
||||
#define SDVS_1_8_V (0x5UL << 9)
|
||||
#define SDVS_3_0_V (0x6UL << 9)
|
||||
#define IWE BIT24
|
||||
|
||||
#define MMCHS_SYSCTL (MMCHS1BASE + 0x12C)
|
||||
#define ICE BIT0
|
||||
#define ICS_MASK BIT1
|
||||
#define ICS BIT1
|
||||
#define CEN BIT2
|
||||
#define CLKD_MASK (0x3FFUL << 6)
|
||||
#define CLKD_80KHZ (0x258UL) //(96*1000/80)/2
|
||||
#define CLKD_400KHZ (0xF0UL)
|
||||
#define DTO_MASK (0xFUL << 16)
|
||||
#define DTO_VAL (0xEUL << 16)
|
||||
#define SRA BIT24
|
||||
#define SRC_MASK BIT25
|
||||
#define SRC BIT25
|
||||
#define SRD BIT26
|
||||
|
||||
#define MMCHS_STAT (MMCHS1BASE + 0x130)
|
||||
#define CC BIT0
|
||||
#define TC BIT1
|
||||
#define BWR BIT4
|
||||
#define BRR BIT5
|
||||
#define ERRI BIT15
|
||||
#define CTO BIT16
|
||||
#define DTO BIT20
|
||||
#define DCRC BIT21
|
||||
#define DEB BIT22
|
||||
|
||||
#define MMCHS_IE (MMCHS1BASE + 0x134)
|
||||
#define CC_EN BIT0
|
||||
#define TC_EN BIT1
|
||||
#define BWR_EN BIT4
|
||||
#define BRR_EN BIT5
|
||||
#define CTO_EN BIT16
|
||||
#define CCRC_EN BIT17
|
||||
#define CEB_EN BIT18
|
||||
#define CIE_EN BIT19
|
||||
#define DTO_EN BIT20
|
||||
#define DCRC_EN BIT21
|
||||
#define DEB_EN BIT22
|
||||
#define CERR_EN BIT28
|
||||
#define BADA_EN BIT29
|
||||
|
||||
#define MMCHS_ISE (MMCHS1BASE + 0x138)
|
||||
#define CC_SIGEN BIT0
|
||||
#define TC_SIGEN BIT1
|
||||
#define BWR_SIGEN BIT4
|
||||
#define BRR_SIGEN BIT5
|
||||
#define CTO_SIGEN BIT16
|
||||
#define CCRC_SIGEN BIT17
|
||||
#define CEB_SIGEN BIT18
|
||||
#define CIE_SIGEN BIT19
|
||||
#define DTO_SIGEN BIT20
|
||||
#define DCRC_SIGEN BIT21
|
||||
#define DEB_SIGEN BIT22
|
||||
#define CERR_SIGEN BIT28
|
||||
#define BADA_SIGEN BIT29
|
||||
|
||||
#define MMCHS_AC12 (MMCHS1BASE + 0x13C)
|
||||
|
||||
#define MMCHS_CAPA (MMCHS1BASE + 0x140)
|
||||
#define VS30 BIT25
|
||||
#define VS18 BIT26
|
||||
|
||||
#define MMCHS_CUR_CAPA (MMCHS1BASE + 0x148)
|
||||
#define MMCHS_REV (MMCHS1BASE + 0x1FC)
|
||||
|
||||
#define CMD0 INDX(0)
|
||||
#define CMD0_INT_EN (CC_EN | CEB_EN)
|
||||
|
||||
#define CMD1 (INDX(1) | RSP_TYPE_48BITS)
|
||||
#define CMD1_INT_EN (CC_EN | CEB_EN | CTO_EN)
|
||||
|
||||
#define CMD2 (INDX(2) | CCCE_ENABLE | RSP_TYPE_136BITS)
|
||||
#define CMD2_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
|
||||
|
||||
#define CMD3 (INDX(3) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
|
||||
#define CMD3_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
|
||||
|
||||
#define CMD5 (INDX(5) | RSP_TYPE_48BITS)
|
||||
#define CMD5_INT_EN (CC_EN | CEB_EN | CTO_EN)
|
||||
|
||||
#define CMD7 (INDX(7) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
|
||||
#define CMD7_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
|
||||
|
||||
#define CMD8 (INDX(8) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
|
||||
#define CMD8_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
|
||||
//Reserved(0)[12:31], Supply voltage(1)[11:8], check pattern(0xCE)[7:0] = 0x1CE
|
||||
#define CMD8_ARG (0x0UL << 12 | BIT8 | 0xCEUL << 0)
|
||||
|
||||
#define CMD9 (INDX(9) | CCCE_ENABLE | RSP_TYPE_136BITS)
|
||||
#define CMD9_INT_EN (CCRC_EN | CC_EN | CEB_EN | CTO_EN)
|
||||
|
||||
#define CMD16 (INDX(16) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
|
||||
#define CMD16_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
|
||||
|
||||
#define CMD17 (INDX(17) | DP_ENABLE | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS | DDIR_READ)
|
||||
#define CMD17_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | TC_EN | BRR_EN | CTO_EN | DTO_EN | DCRC_EN | DEB_EN | CEB_EN)
|
||||
|
||||
#define CMD18 (INDX(18) | DP_ENABLE | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS | MSBS_MULTBLK | DDIR_READ | BCE_ENABLE | DE_ENABLE)
|
||||
#define CMD18_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | TC_EN | BRR_EN | CTO_EN | DTO_EN | DCRC_EN | DEB_EN | CEB_EN)
|
||||
|
||||
#define CMD23 (INDX(23) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
|
||||
#define CMD23_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
|
||||
|
||||
#define CMD24 (INDX(24) | DP_ENABLE | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS | DDIR_WRITE)
|
||||
#define CMD24_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | TC_EN | BWR_EN | CTO_EN | DTO_EN | DCRC_EN | DEB_EN | CEB_EN)
|
||||
|
||||
#define CMD25 (INDX(25) | DP_ENABLE | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS | MSBS_MULTBLK | DDIR_READ | BCE_ENABLE | DE_ENABLE)
|
||||
#define CMD25_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | TC_EN | BRR_EN | CTO_EN | DTO_EN | DCRC_EN | DEB_EN | CEB_EN)
|
||||
|
||||
#define CMD55 (INDX(55) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
|
||||
#define CMD55_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
|
||||
|
||||
#define ACMD41 (INDX(41) | RSP_TYPE_48BITS)
|
||||
#define ACMD41_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
|
||||
|
||||
#define ACMD6 (INDX(6) | RSP_TYPE_48BITS)
|
||||
#define ACMD6_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
|
||||
|
||||
#endif //__OMAP3530SDIO_H__
|
||||
|
||||
@@ -1,303 +1,303 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
||||
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __OMAP3530_PAD_CONFIGURATION_H__
|
||||
#define __OMAP3530_PAD_CONFIGURATION_H__
|
||||
|
||||
#define SYSTEM_CONTROL_MODULE_BASE 0x48002000
|
||||
|
||||
//Pin definition
|
||||
#define SDRC_D0 (SYSTEM_CONTROL_MODULE_BASE + 0x030)
|
||||
#define SDRC_D1 (SYSTEM_CONTROL_MODULE_BASE + 0x032)
|
||||
#define SDRC_D2 (SYSTEM_CONTROL_MODULE_BASE + 0x034)
|
||||
#define SDRC_D3 (SYSTEM_CONTROL_MODULE_BASE + 0x036)
|
||||
#define SDRC_D4 (SYSTEM_CONTROL_MODULE_BASE + 0x038)
|
||||
#define SDRC_D5 (SYSTEM_CONTROL_MODULE_BASE + 0x03A)
|
||||
#define SDRC_D6 (SYSTEM_CONTROL_MODULE_BASE + 0x03C)
|
||||
#define SDRC_D7 (SYSTEM_CONTROL_MODULE_BASE + 0x03E)
|
||||
#define SDRC_D8 (SYSTEM_CONTROL_MODULE_BASE + 0x040)
|
||||
#define SDRC_D9 (SYSTEM_CONTROL_MODULE_BASE + 0x042)
|
||||
#define SDRC_D10 (SYSTEM_CONTROL_MODULE_BASE + 0x044)
|
||||
#define SDRC_D11 (SYSTEM_CONTROL_MODULE_BASE + 0x046)
|
||||
#define SDRC_D12 (SYSTEM_CONTROL_MODULE_BASE + 0x048)
|
||||
#define SDRC_D13 (SYSTEM_CONTROL_MODULE_BASE + 0x04A)
|
||||
#define SDRC_D14 (SYSTEM_CONTROL_MODULE_BASE + 0x04C)
|
||||
#define SDRC_D15 (SYSTEM_CONTROL_MODULE_BASE + 0x04E)
|
||||
#define SDRC_D16 (SYSTEM_CONTROL_MODULE_BASE + 0x050)
|
||||
#define SDRC_D17 (SYSTEM_CONTROL_MODULE_BASE + 0x052)
|
||||
#define SDRC_D18 (SYSTEM_CONTROL_MODULE_BASE + 0x054)
|
||||
#define SDRC_D19 (SYSTEM_CONTROL_MODULE_BASE + 0x056)
|
||||
#define SDRC_D20 (SYSTEM_CONTROL_MODULE_BASE + 0x058)
|
||||
#define SDRC_D21 (SYSTEM_CONTROL_MODULE_BASE + 0x05A)
|
||||
#define SDRC_D22 (SYSTEM_CONTROL_MODULE_BASE + 0x05C)
|
||||
#define SDRC_D23 (SYSTEM_CONTROL_MODULE_BASE + 0x05E)
|
||||
#define SDRC_D24 (SYSTEM_CONTROL_MODULE_BASE + 0x060)
|
||||
#define SDRC_D25 (SYSTEM_CONTROL_MODULE_BASE + 0x062)
|
||||
#define SDRC_D26 (SYSTEM_CONTROL_MODULE_BASE + 0x064)
|
||||
#define SDRC_D27 (SYSTEM_CONTROL_MODULE_BASE + 0x066)
|
||||
#define SDRC_D28 (SYSTEM_CONTROL_MODULE_BASE + 0x068)
|
||||
#define SDRC_D29 (SYSTEM_CONTROL_MODULE_BASE + 0x06A)
|
||||
#define SDRC_D30 (SYSTEM_CONTROL_MODULE_BASE + 0x06C)
|
||||
#define SDRC_D31 (SYSTEM_CONTROL_MODULE_BASE + 0x06E)
|
||||
#define SDRC_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x070)
|
||||
#define SDRC_DQS0 (SYSTEM_CONTROL_MODULE_BASE + 0x072)
|
||||
#define SDRC_CKE0 (SYSTEM_CONTROL_MODULE_BASE + 0x262)
|
||||
#define SDRC_CKE1 (SYSTEM_CONTROL_MODULE_BASE + 0x264)
|
||||
#define SDRC_DQS1 (SYSTEM_CONTROL_MODULE_BASE + 0x074)
|
||||
#define SDRC_DQS2 (SYSTEM_CONTROL_MODULE_BASE + 0x076)
|
||||
#define SDRC_DQS3 (SYSTEM_CONTROL_MODULE_BASE + 0x078)
|
||||
#define GPMC_A1 (SYSTEM_CONTROL_MODULE_BASE + 0x07A)
|
||||
#define GPMC_A2 (SYSTEM_CONTROL_MODULE_BASE + 0x07C)
|
||||
#define GPMC_A3 (SYSTEM_CONTROL_MODULE_BASE + 0x07E)
|
||||
#define GPMC_A4 (SYSTEM_CONTROL_MODULE_BASE + 0x080)
|
||||
#define GPMC_A5 (SYSTEM_CONTROL_MODULE_BASE + 0x082)
|
||||
#define GPMC_A6 (SYSTEM_CONTROL_MODULE_BASE + 0x084)
|
||||
#define GPMC_A7 (SYSTEM_CONTROL_MODULE_BASE + 0x086)
|
||||
#define GPMC_A8 (SYSTEM_CONTROL_MODULE_BASE + 0x088)
|
||||
#define GPMC_A9 (SYSTEM_CONTROL_MODULE_BASE + 0x08A)
|
||||
#define GPMC_A10 (SYSTEM_CONTROL_MODULE_BASE + 0x08C)
|
||||
#define GPMC_D0 (SYSTEM_CONTROL_MODULE_BASE + 0x08E)
|
||||
#define GPMC_D1 (SYSTEM_CONTROL_MODULE_BASE + 0x090)
|
||||
#define GPMC_D2 (SYSTEM_CONTROL_MODULE_BASE + 0x092)
|
||||
#define GPMC_D3 (SYSTEM_CONTROL_MODULE_BASE + 0x094)
|
||||
#define GPMC_D4 (SYSTEM_CONTROL_MODULE_BASE + 0x096)
|
||||
#define GPMC_D5 (SYSTEM_CONTROL_MODULE_BASE + 0x098)
|
||||
#define GPMC_D6 (SYSTEM_CONTROL_MODULE_BASE + 0x09A)
|
||||
#define GPMC_D7 (SYSTEM_CONTROL_MODULE_BASE + 0x09C)
|
||||
#define GPMC_D8 (SYSTEM_CONTROL_MODULE_BASE + 0x09E)
|
||||
#define GPMC_D9 (SYSTEM_CONTROL_MODULE_BASE + 0x0A0)
|
||||
#define GPMC_D10 (SYSTEM_CONTROL_MODULE_BASE + 0x0A2)
|
||||
#define GPMC_D11 (SYSTEM_CONTROL_MODULE_BASE + 0x0A4)
|
||||
#define GPMC_D12 (SYSTEM_CONTROL_MODULE_BASE + 0x0A6)
|
||||
#define GPMC_D13 (SYSTEM_CONTROL_MODULE_BASE + 0x0A8)
|
||||
#define GPMC_D14 (SYSTEM_CONTROL_MODULE_BASE + 0x0AA)
|
||||
#define GPMC_D15 (SYSTEM_CONTROL_MODULE_BASE + 0x0AC)
|
||||
#define GPMC_NCS0 (SYSTEM_CONTROL_MODULE_BASE + 0x0AE)
|
||||
#define GPMC_NCS1 (SYSTEM_CONTROL_MODULE_BASE + 0x0B0)
|
||||
#define GPMC_NCS2 (SYSTEM_CONTROL_MODULE_BASE + 0x0B2)
|
||||
#define GPMC_NCS3 (SYSTEM_CONTROL_MODULE_BASE + 0x0B4)
|
||||
#define GPMC_NCS4 (SYSTEM_CONTROL_MODULE_BASE + 0x0B6)
|
||||
#define GPMC_NCS5 (SYSTEM_CONTROL_MODULE_BASE + 0x0B8)
|
||||
#define GPMC_NCS6 (SYSTEM_CONTROL_MODULE_BASE + 0x0BA)
|
||||
#define GPMC_NCS7 (SYSTEM_CONTROL_MODULE_BASE + 0x0BC)
|
||||
#define GPMC_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x0BE)
|
||||
#define GPMC_NADV_ALE (SYSTEM_CONTROL_MODULE_BASE + 0x0C0)
|
||||
#define GPMC_NOE (SYSTEM_CONTROL_MODULE_BASE + 0x0C2)
|
||||
#define GPMC_NWE (SYSTEM_CONTROL_MODULE_BASE + 0x0C4)
|
||||
#define GPMC_NBE0_CLE (SYSTEM_CONTROL_MODULE_BASE + 0x0C6)
|
||||
#define GPMC_NBE1 (SYSTEM_CONTROL_MODULE_BASE + 0x0C8)
|
||||
#define GPMC_NWP (SYSTEM_CONTROL_MODULE_BASE + 0x0CA)
|
||||
#define GPMC_WAIT0 (SYSTEM_CONTROL_MODULE_BASE + 0x0CC)
|
||||
#define GPMC_WAIT1 (SYSTEM_CONTROL_MODULE_BASE + 0x0CE)
|
||||
#define GPMC_WAIT2 (SYSTEM_CONTROL_MODULE_BASE + 0x0D0)
|
||||
#define GPMC_WAIT3 (SYSTEM_CONTROL_MODULE_BASE + 0x0D2)
|
||||
#define DSS_PCLK (SYSTEM_CONTROL_MODULE_BASE + 0x0D4)
|
||||
#define DSS_HSYNC (SYSTEM_CONTROL_MODULE_BASE + 0x0D6)
|
||||
#define DSS_PSYNC (SYSTEM_CONTROL_MODULE_BASE + 0x0D8)
|
||||
#define DSS_ACBIAS (SYSTEM_CONTROL_MODULE_BASE + 0x0DA)
|
||||
#define DSS_DATA0 (SYSTEM_CONTROL_MODULE_BASE + 0x0DC)
|
||||
#define DSS_DATA1 (SYSTEM_CONTROL_MODULE_BASE + 0x0DE)
|
||||
#define DSS_DATA2 (SYSTEM_CONTROL_MODULE_BASE + 0x0E0)
|
||||
#define DSS_DATA3 (SYSTEM_CONTROL_MODULE_BASE + 0x0E2)
|
||||
#define DSS_DATA4 (SYSTEM_CONTROL_MODULE_BASE + 0x0E4)
|
||||
#define DSS_DATA5 (SYSTEM_CONTROL_MODULE_BASE + 0x0E6)
|
||||
#define DSS_DATA6 (SYSTEM_CONTROL_MODULE_BASE + 0x0E8)
|
||||
#define DSS_DATA7 (SYSTEM_CONTROL_MODULE_BASE + 0x0EA)
|
||||
#define DSS_DATA8 (SYSTEM_CONTROL_MODULE_BASE + 0x0EC)
|
||||
#define DSS_DATA9 (SYSTEM_CONTROL_MODULE_BASE + 0x0EE)
|
||||
#define DSS_DATA10 (SYSTEM_CONTROL_MODULE_BASE + 0x0F0)
|
||||
#define DSS_DATA11 (SYSTEM_CONTROL_MODULE_BASE + 0x0F2)
|
||||
#define DSS_DATA12 (SYSTEM_CONTROL_MODULE_BASE + 0x0F4)
|
||||
#define DSS_DATA13 (SYSTEM_CONTROL_MODULE_BASE + 0x0F6)
|
||||
#define DSS_DATA14 (SYSTEM_CONTROL_MODULE_BASE + 0x0F8)
|
||||
#define DSS_DATA15 (SYSTEM_CONTROL_MODULE_BASE + 0x0FA)
|
||||
#define DSS_DATA16 (SYSTEM_CONTROL_MODULE_BASE + 0x0FC)
|
||||
#define DSS_DATA17 (SYSTEM_CONTROL_MODULE_BASE + 0x0FE)
|
||||
#define DSS_DATA18 (SYSTEM_CONTROL_MODULE_BASE + 0x100)
|
||||
#define DSS_DATA19 (SYSTEM_CONTROL_MODULE_BASE + 0x102)
|
||||
#define DSS_DATA20 (SYSTEM_CONTROL_MODULE_BASE + 0x104)
|
||||
#define DSS_DATA21 (SYSTEM_CONTROL_MODULE_BASE + 0x106)
|
||||
#define DSS_DATA22 (SYSTEM_CONTROL_MODULE_BASE + 0x108)
|
||||
#define DSS_DATA23 (SYSTEM_CONTROL_MODULE_BASE + 0x10A)
|
||||
#define CAM_HS (SYSTEM_CONTROL_MODULE_BASE + 0x10C)
|
||||
#define CAM_VS (SYSTEM_CONTROL_MODULE_BASE + 0x10E)
|
||||
#define CAM_XCLKA (SYSTEM_CONTROL_MODULE_BASE + 0x110)
|
||||
#define CAM_PCLK (SYSTEM_CONTROL_MODULE_BASE + 0x112)
|
||||
#define CAM_FLD (SYSTEM_CONTROL_MODULE_BASE + 0x114)
|
||||
#define CAM_D0 (SYSTEM_CONTROL_MODULE_BASE + 0x116)
|
||||
#define CAM_D1 (SYSTEM_CONTROL_MODULE_BASE + 0x118)
|
||||
#define CAM_D2 (SYSTEM_CONTROL_MODULE_BASE + 0x11A)
|
||||
#define CAM_D3 (SYSTEM_CONTROL_MODULE_BASE + 0x11C)
|
||||
#define CAM_D4 (SYSTEM_CONTROL_MODULE_BASE + 0x11E)
|
||||
#define CAM_D5 (SYSTEM_CONTROL_MODULE_BASE + 0x120)
|
||||
#define CAM_D6 (SYSTEM_CONTROL_MODULE_BASE + 0x122)
|
||||
#define CAM_D7 (SYSTEM_CONTROL_MODULE_BASE + 0x124)
|
||||
#define CAM_D8 (SYSTEM_CONTROL_MODULE_BASE + 0x126)
|
||||
#define CAM_D9 (SYSTEM_CONTROL_MODULE_BASE + 0x128)
|
||||
#define CAM_D10 (SYSTEM_CONTROL_MODULE_BASE + 0x12A)
|
||||
#define CAM_D11 (SYSTEM_CONTROL_MODULE_BASE + 0x12C)
|
||||
#define CAM_XCLKB (SYSTEM_CONTROL_MODULE_BASE + 0x12E)
|
||||
#define CAM_WEN (SYSTEM_CONTROL_MODULE_BASE + 0x130)
|
||||
#define CAM_STROBE (SYSTEM_CONTROL_MODULE_BASE + 0x132)
|
||||
#define CSI2_DX0 (SYSTEM_CONTROL_MODULE_BASE + 0x134)
|
||||
#define CSI2_DY0 (SYSTEM_CONTROL_MODULE_BASE + 0x136)
|
||||
#define CSI2_DX1 (SYSTEM_CONTROL_MODULE_BASE + 0x138)
|
||||
#define CSI2_DY1 (SYSTEM_CONTROL_MODULE_BASE + 0x13A)
|
||||
#define MCBSP2_FSX (SYSTEM_CONTROL_MODULE_BASE + 0x13C)
|
||||
#define MCBSP2_CLKX (SYSTEM_CONTROL_MODULE_BASE + 0x13E)
|
||||
#define MCBSP2_DR (SYSTEM_CONTROL_MODULE_BASE + 0x140)
|
||||
#define MCBSP2_DX (SYSTEM_CONTROL_MODULE_BASE + 0x142)
|
||||
#define MMC1_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x144)
|
||||
#define MMC1_CMD (SYSTEM_CONTROL_MODULE_BASE + 0x146)
|
||||
#define MMC1_DAT0 (SYSTEM_CONTROL_MODULE_BASE + 0x148)
|
||||
#define MMC1_DAT1 (SYSTEM_CONTROL_MODULE_BASE + 0x14A)
|
||||
#define MMC1_DAT2 (SYSTEM_CONTROL_MODULE_BASE + 0x14C)
|
||||
#define MMC1_DAT3 (SYSTEM_CONTROL_MODULE_BASE + 0x14E)
|
||||
#define MMC1_DAT4 (SYSTEM_CONTROL_MODULE_BASE + 0x150)
|
||||
#define MMC1_DAT5 (SYSTEM_CONTROL_MODULE_BASE + 0x152)
|
||||
#define MMC1_DAT6 (SYSTEM_CONTROL_MODULE_BASE + 0x154)
|
||||
#define MMC1_DAT7 (SYSTEM_CONTROL_MODULE_BASE + 0x156)
|
||||
#define MMC2_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x158)
|
||||
#define MMC2_CMD (SYSTEM_CONTROL_MODULE_BASE + 0x15A)
|
||||
#define MMC2_DAT0 (SYSTEM_CONTROL_MODULE_BASE + 0x15C)
|
||||
#define MMC2_DAT1 (SYSTEM_CONTROL_MODULE_BASE + 0x15E)
|
||||
#define MMC2_DAT2 (SYSTEM_CONTROL_MODULE_BASE + 0x160)
|
||||
#define MMC2_DAT3 (SYSTEM_CONTROL_MODULE_BASE + 0x162)
|
||||
#define MMC2_DAT4 (SYSTEM_CONTROL_MODULE_BASE + 0x164)
|
||||
#define MMC2_DAT5 (SYSTEM_CONTROL_MODULE_BASE + 0x166)
|
||||
#define MMC2_DAT6 (SYSTEM_CONTROL_MODULE_BASE + 0x168)
|
||||
#define MMC2_DAT7 (SYSTEM_CONTROL_MODULE_BASE + 0x16A)
|
||||
#define MCBSP3_DX (SYSTEM_CONTROL_MODULE_BASE + 0x16C)
|
||||
#define MCBSP3_DR (SYSTEM_CONTROL_MODULE_BASE + 0x16E)
|
||||
#define MCBSP3_CLKX (SYSTEM_CONTROL_MODULE_BASE + 0x170)
|
||||
#define MCBSP3_FSX (SYSTEM_CONTROL_MODULE_BASE + 0x172)
|
||||
#define UART2_CTS (SYSTEM_CONTROL_MODULE_BASE + 0x174)
|
||||
#define UART2_RTS (SYSTEM_CONTROL_MODULE_BASE + 0x176)
|
||||
#define UART2_TX (SYSTEM_CONTROL_MODULE_BASE + 0x178)
|
||||
#define UART2_RX (SYSTEM_CONTROL_MODULE_BASE + 0x17A)
|
||||
#define UART1_TX (SYSTEM_CONTROL_MODULE_BASE + 0x17C)
|
||||
#define UART1_RTS (SYSTEM_CONTROL_MODULE_BASE + 0x17E)
|
||||
#define UART1_CTS (SYSTEM_CONTROL_MODULE_BASE + 0x180)
|
||||
#define UART1_RX (SYSTEM_CONTROL_MODULE_BASE + 0x182)
|
||||
#define MCBSP4_CLKX (SYSTEM_CONTROL_MODULE_BASE + 0x184)
|
||||
#define MCBSP4_DR (SYSTEM_CONTROL_MODULE_BASE + 0x186)
|
||||
#define MCBSP4_DX (SYSTEM_CONTROL_MODULE_BASE + 0x188)
|
||||
#define MCBSP4_FSX (SYSTEM_CONTROL_MODULE_BASE + 0x18A)
|
||||
#define MCBSP1_CLKR (SYSTEM_CONTROL_MODULE_BASE + 0x18C)
|
||||
#define MCBSP1_FSR (SYSTEM_CONTROL_MODULE_BASE + 0x18E)
|
||||
#define MCBSP1_DX (SYSTEM_CONTROL_MODULE_BASE + 0x190)
|
||||
#define MCBSP1_DR (SYSTEM_CONTROL_MODULE_BASE + 0x192)
|
||||
#define MCBSP1_CLKS (SYSTEM_CONTROL_MODULE_BASE + 0x194)
|
||||
#define MCBSP1_FSX (SYSTEM_CONTROL_MODULE_BASE + 0x196)
|
||||
#define MCBSP1_CLKX (SYSTEM_CONTROL_MODULE_BASE + 0x198)
|
||||
#define UART3_CTS_RCTX (SYSTEM_CONTROL_MODULE_BASE + 0x19A)
|
||||
#define UART3_RTS_SD (SYSTEM_CONTROL_MODULE_BASE + 0x19C)
|
||||
#define UART3_RX_IRRX (SYSTEM_CONTROL_MODULE_BASE + 0x19E)
|
||||
#define UART3_TX_IRTX (SYSTEM_CONTROL_MODULE_BASE + 0x1A0)
|
||||
#define HSUSB0_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x1A2)
|
||||
#define HSUSB0_STP (SYSTEM_CONTROL_MODULE_BASE + 0x1A4)
|
||||
#define HSUSB0_DIR (SYSTEM_CONTROL_MODULE_BASE + 0x1A6)
|
||||
#define HSUSB0_NXT (SYSTEM_CONTROL_MODULE_BASE + 0x1A8)
|
||||
#define HSUSB0_DATA0 (SYSTEM_CONTROL_MODULE_BASE + 0x1AA)
|
||||
#define HSUSB0_DATA1 (SYSTEM_CONTROL_MODULE_BASE + 0x1AC)
|
||||
#define HSUSB0_DATA2 (SYSTEM_CONTROL_MODULE_BASE + 0x1AE)
|
||||
#define HSUSB0_DATA3 (SYSTEM_CONTROL_MODULE_BASE + 0x1B0)
|
||||
#define HSUSB0_DATA4 (SYSTEM_CONTROL_MODULE_BASE + 0x1B2)
|
||||
#define HSUSB0_DATA5 (SYSTEM_CONTROL_MODULE_BASE + 0x1B4)
|
||||
#define HSUSB0_DATA6 (SYSTEM_CONTROL_MODULE_BASE + 0x1B6)
|
||||
#define HSUSB0_DATA7 (SYSTEM_CONTROL_MODULE_BASE + 0x1B8)
|
||||
#define I2C1_SCL (SYSTEM_CONTROL_MODULE_BASE + 0x1BA)
|
||||
#define I2C1_SDA (SYSTEM_CONTROL_MODULE_BASE + 0x1BC)
|
||||
#define I2C2_SCL (SYSTEM_CONTROL_MODULE_BASE + 0x1BE)
|
||||
#define I2C2_SDA (SYSTEM_CONTROL_MODULE_BASE + 0x1C0)
|
||||
#define I2C3_SCL (SYSTEM_CONTROL_MODULE_BASE + 0x1C2)
|
||||
#define I2C3_SDA (SYSTEM_CONTROL_MODULE_BASE + 0x1C4)
|
||||
#define HDQ_SIO (SYSTEM_CONTROL_MODULE_BASE + 0x1C6)
|
||||
#define MCSPI1_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x1C8)
|
||||
#define MCSPI1_SIMO (SYSTEM_CONTROL_MODULE_BASE + 0x1CA)
|
||||
#define MCSPI1_SOMI (SYSTEM_CONTROL_MODULE_BASE + 0x1CC)
|
||||
#define MCSPI1_CS0 (SYSTEM_CONTROL_MODULE_BASE + 0x1CE)
|
||||
#define MCSPI1_CS1 (SYSTEM_CONTROL_MODULE_BASE + 0x1D0)
|
||||
#define MCSPI1_CS2 (SYSTEM_CONTROL_MODULE_BASE + 0x1D2)
|
||||
#define MCSPI1_CS3 (SYSTEM_CONTROL_MODULE_BASE + 0x1D4)
|
||||
#define MCSPI2_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x1D6)
|
||||
#define MCSPI2_SIMO (SYSTEM_CONTROL_MODULE_BASE + 0x1D8)
|
||||
#define MCSPI2_SOMI (SYSTEM_CONTROL_MODULE_BASE + 0x1DA)
|
||||
#define MCSPI2_CS0 (SYSTEM_CONTROL_MODULE_BASE + 0x1DC)
|
||||
#define MCSPI2_CS1 (SYSTEM_CONTROL_MODULE_BASE + 0x1DE)
|
||||
#define SYS_NIRQ (SYSTEM_CONTROL_MODULE_BASE + 0x1E0)
|
||||
#define SYS_CLKOUT2 (SYSTEM_CONTROL_MODULE_BASE + 0x1E2)
|
||||
#define ETK_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x5D8)
|
||||
#define ETK_CTL (SYSTEM_CONTROL_MODULE_BASE + 0x5DA)
|
||||
#define ETK_D0 (SYSTEM_CONTROL_MODULE_BASE + 0x5DC)
|
||||
#define ETK_D1 (SYSTEM_CONTROL_MODULE_BASE + 0x5DE)
|
||||
#define ETK_D2 (SYSTEM_CONTROL_MODULE_BASE + 0x5E0)
|
||||
#define ETK_D3 (SYSTEM_CONTROL_MODULE_BASE + 0x5E2)
|
||||
#define ETK_D4 (SYSTEM_CONTROL_MODULE_BASE + 0x5E4)
|
||||
#define ETK_D5 (SYSTEM_CONTROL_MODULE_BASE + 0x5E6)
|
||||
#define ETK_D6 (SYSTEM_CONTROL_MODULE_BASE + 0x5E8)
|
||||
#define ETK_D7 (SYSTEM_CONTROL_MODULE_BASE + 0x5EA)
|
||||
#define ETK_D8 (SYSTEM_CONTROL_MODULE_BASE + 0x5EC)
|
||||
#define ETK_D9 (SYSTEM_CONTROL_MODULE_BASE + 0x5EE)
|
||||
#define ETK_D10 (SYSTEM_CONTROL_MODULE_BASE + 0x5F0)
|
||||
#define ETK_D11 (SYSTEM_CONTROL_MODULE_BASE + 0x5F2)
|
||||
#define ETK_D12 (SYSTEM_CONTROL_MODULE_BASE + 0x5F4)
|
||||
#define ETK_D13 (SYSTEM_CONTROL_MODULE_BASE + 0x5F6)
|
||||
#define ETK_D14 (SYSTEM_CONTROL_MODULE_BASE + 0x5F8)
|
||||
#define ETK_D15 (SYSTEM_CONTROL_MODULE_BASE + 0x5FA)
|
||||
#define SYS_BOOT0 (SYSTEM_CONTROL_MODULE_BASE + 0xA0A)
|
||||
#define SYS_BOOT1 (SYSTEM_CONTROL_MODULE_BASE + 0xA0C)
|
||||
#define SYS_BOOT3 (SYSTEM_CONTROL_MODULE_BASE + 0xA10)
|
||||
#define SYS_BOOT4 (SYSTEM_CONTROL_MODULE_BASE + 0xA12)
|
||||
#define SYS_BOOT5 (SYSTEM_CONTROL_MODULE_BASE + 0xA14)
|
||||
#define SYS_BOOT6 (SYSTEM_CONTROL_MODULE_BASE + 0xA16)
|
||||
|
||||
//Mux modes
|
||||
#define MUXMODE0 (0x0UL)
|
||||
#define MUXMODE1 (0x1UL)
|
||||
#define MUXMODE2 (0x2UL)
|
||||
#define MUXMODE3 (0x3UL)
|
||||
#define MUXMODE4 (0x4UL)
|
||||
#define MUXMODE5 (0x5UL)
|
||||
#define MUXMODE6 (0x6UL)
|
||||
#define MUXMODE7 (0x7UL)
|
||||
|
||||
//Pad configuration register.
|
||||
#define PAD_CONFIG_MASK (0xFFFFUL)
|
||||
#define MUXMODE_OFFSET 0
|
||||
#define MUXMODE_MASK (0x7UL << MUXMODE_OFFSET)
|
||||
#define PULL_CONFIG_OFFSET 3
|
||||
#define PULL_CONFIG_MASK (0x3UL << PULL_CONFIG_OFFSET)
|
||||
#define INPUTENABLE_OFFSET 8
|
||||
#define INPUTENABLE_MASK (0x1UL << INPUTENABLE_OFFSET)
|
||||
#define OFFMODE_VALUE_OFFSET 9
|
||||
#define OFFMODE_VALUE_MASK (0x1FUL << OFFMODE_VALUE_OFFSET)
|
||||
#define WAKEUP_OFFSET 14
|
||||
#define WAKEUP_MASK (0x2UL << WAKEUP_OFFSET)
|
||||
|
||||
#define PULL_DOWN_SELECTED ((0x0UL << 1) | BIT0)
|
||||
#define PULL_UP_SELECTED (BIT1 | BIT0)
|
||||
#define PULL_DISABLED (0x0UL << 0)
|
||||
|
||||
#define OUTPUT (0x0UL) //Pin is configured in output only mode.
|
||||
#define INPUT (0x1UL) //Pin is configured in bi-directional mode.
|
||||
|
||||
typedef struct {
|
||||
UINTN Pin;
|
||||
UINTN MuxMode;
|
||||
UINTN PullConfig;
|
||||
UINTN InputEnable;
|
||||
} PAD_CONFIGURATION;
|
||||
|
||||
#endif //__OMAP3530_PAD_CONFIGURATION_H__
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
||||
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __OMAP3530_PAD_CONFIGURATION_H__
|
||||
#define __OMAP3530_PAD_CONFIGURATION_H__
|
||||
|
||||
#define SYSTEM_CONTROL_MODULE_BASE 0x48002000
|
||||
|
||||
//Pin definition
|
||||
#define SDRC_D0 (SYSTEM_CONTROL_MODULE_BASE + 0x030)
|
||||
#define SDRC_D1 (SYSTEM_CONTROL_MODULE_BASE + 0x032)
|
||||
#define SDRC_D2 (SYSTEM_CONTROL_MODULE_BASE + 0x034)
|
||||
#define SDRC_D3 (SYSTEM_CONTROL_MODULE_BASE + 0x036)
|
||||
#define SDRC_D4 (SYSTEM_CONTROL_MODULE_BASE + 0x038)
|
||||
#define SDRC_D5 (SYSTEM_CONTROL_MODULE_BASE + 0x03A)
|
||||
#define SDRC_D6 (SYSTEM_CONTROL_MODULE_BASE + 0x03C)
|
||||
#define SDRC_D7 (SYSTEM_CONTROL_MODULE_BASE + 0x03E)
|
||||
#define SDRC_D8 (SYSTEM_CONTROL_MODULE_BASE + 0x040)
|
||||
#define SDRC_D9 (SYSTEM_CONTROL_MODULE_BASE + 0x042)
|
||||
#define SDRC_D10 (SYSTEM_CONTROL_MODULE_BASE + 0x044)
|
||||
#define SDRC_D11 (SYSTEM_CONTROL_MODULE_BASE + 0x046)
|
||||
#define SDRC_D12 (SYSTEM_CONTROL_MODULE_BASE + 0x048)
|
||||
#define SDRC_D13 (SYSTEM_CONTROL_MODULE_BASE + 0x04A)
|
||||
#define SDRC_D14 (SYSTEM_CONTROL_MODULE_BASE + 0x04C)
|
||||
#define SDRC_D15 (SYSTEM_CONTROL_MODULE_BASE + 0x04E)
|
||||
#define SDRC_D16 (SYSTEM_CONTROL_MODULE_BASE + 0x050)
|
||||
#define SDRC_D17 (SYSTEM_CONTROL_MODULE_BASE + 0x052)
|
||||
#define SDRC_D18 (SYSTEM_CONTROL_MODULE_BASE + 0x054)
|
||||
#define SDRC_D19 (SYSTEM_CONTROL_MODULE_BASE + 0x056)
|
||||
#define SDRC_D20 (SYSTEM_CONTROL_MODULE_BASE + 0x058)
|
||||
#define SDRC_D21 (SYSTEM_CONTROL_MODULE_BASE + 0x05A)
|
||||
#define SDRC_D22 (SYSTEM_CONTROL_MODULE_BASE + 0x05C)
|
||||
#define SDRC_D23 (SYSTEM_CONTROL_MODULE_BASE + 0x05E)
|
||||
#define SDRC_D24 (SYSTEM_CONTROL_MODULE_BASE + 0x060)
|
||||
#define SDRC_D25 (SYSTEM_CONTROL_MODULE_BASE + 0x062)
|
||||
#define SDRC_D26 (SYSTEM_CONTROL_MODULE_BASE + 0x064)
|
||||
#define SDRC_D27 (SYSTEM_CONTROL_MODULE_BASE + 0x066)
|
||||
#define SDRC_D28 (SYSTEM_CONTROL_MODULE_BASE + 0x068)
|
||||
#define SDRC_D29 (SYSTEM_CONTROL_MODULE_BASE + 0x06A)
|
||||
#define SDRC_D30 (SYSTEM_CONTROL_MODULE_BASE + 0x06C)
|
||||
#define SDRC_D31 (SYSTEM_CONTROL_MODULE_BASE + 0x06E)
|
||||
#define SDRC_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x070)
|
||||
#define SDRC_DQS0 (SYSTEM_CONTROL_MODULE_BASE + 0x072)
|
||||
#define SDRC_CKE0 (SYSTEM_CONTROL_MODULE_BASE + 0x262)
|
||||
#define SDRC_CKE1 (SYSTEM_CONTROL_MODULE_BASE + 0x264)
|
||||
#define SDRC_DQS1 (SYSTEM_CONTROL_MODULE_BASE + 0x074)
|
||||
#define SDRC_DQS2 (SYSTEM_CONTROL_MODULE_BASE + 0x076)
|
||||
#define SDRC_DQS3 (SYSTEM_CONTROL_MODULE_BASE + 0x078)
|
||||
#define GPMC_A1 (SYSTEM_CONTROL_MODULE_BASE + 0x07A)
|
||||
#define GPMC_A2 (SYSTEM_CONTROL_MODULE_BASE + 0x07C)
|
||||
#define GPMC_A3 (SYSTEM_CONTROL_MODULE_BASE + 0x07E)
|
||||
#define GPMC_A4 (SYSTEM_CONTROL_MODULE_BASE + 0x080)
|
||||
#define GPMC_A5 (SYSTEM_CONTROL_MODULE_BASE + 0x082)
|
||||
#define GPMC_A6 (SYSTEM_CONTROL_MODULE_BASE + 0x084)
|
||||
#define GPMC_A7 (SYSTEM_CONTROL_MODULE_BASE + 0x086)
|
||||
#define GPMC_A8 (SYSTEM_CONTROL_MODULE_BASE + 0x088)
|
||||
#define GPMC_A9 (SYSTEM_CONTROL_MODULE_BASE + 0x08A)
|
||||
#define GPMC_A10 (SYSTEM_CONTROL_MODULE_BASE + 0x08C)
|
||||
#define GPMC_D0 (SYSTEM_CONTROL_MODULE_BASE + 0x08E)
|
||||
#define GPMC_D1 (SYSTEM_CONTROL_MODULE_BASE + 0x090)
|
||||
#define GPMC_D2 (SYSTEM_CONTROL_MODULE_BASE + 0x092)
|
||||
#define GPMC_D3 (SYSTEM_CONTROL_MODULE_BASE + 0x094)
|
||||
#define GPMC_D4 (SYSTEM_CONTROL_MODULE_BASE + 0x096)
|
||||
#define GPMC_D5 (SYSTEM_CONTROL_MODULE_BASE + 0x098)
|
||||
#define GPMC_D6 (SYSTEM_CONTROL_MODULE_BASE + 0x09A)
|
||||
#define GPMC_D7 (SYSTEM_CONTROL_MODULE_BASE + 0x09C)
|
||||
#define GPMC_D8 (SYSTEM_CONTROL_MODULE_BASE + 0x09E)
|
||||
#define GPMC_D9 (SYSTEM_CONTROL_MODULE_BASE + 0x0A0)
|
||||
#define GPMC_D10 (SYSTEM_CONTROL_MODULE_BASE + 0x0A2)
|
||||
#define GPMC_D11 (SYSTEM_CONTROL_MODULE_BASE + 0x0A4)
|
||||
#define GPMC_D12 (SYSTEM_CONTROL_MODULE_BASE + 0x0A6)
|
||||
#define GPMC_D13 (SYSTEM_CONTROL_MODULE_BASE + 0x0A8)
|
||||
#define GPMC_D14 (SYSTEM_CONTROL_MODULE_BASE + 0x0AA)
|
||||
#define GPMC_D15 (SYSTEM_CONTROL_MODULE_BASE + 0x0AC)
|
||||
#define GPMC_NCS0 (SYSTEM_CONTROL_MODULE_BASE + 0x0AE)
|
||||
#define GPMC_NCS1 (SYSTEM_CONTROL_MODULE_BASE + 0x0B0)
|
||||
#define GPMC_NCS2 (SYSTEM_CONTROL_MODULE_BASE + 0x0B2)
|
||||
#define GPMC_NCS3 (SYSTEM_CONTROL_MODULE_BASE + 0x0B4)
|
||||
#define GPMC_NCS4 (SYSTEM_CONTROL_MODULE_BASE + 0x0B6)
|
||||
#define GPMC_NCS5 (SYSTEM_CONTROL_MODULE_BASE + 0x0B8)
|
||||
#define GPMC_NCS6 (SYSTEM_CONTROL_MODULE_BASE + 0x0BA)
|
||||
#define GPMC_NCS7 (SYSTEM_CONTROL_MODULE_BASE + 0x0BC)
|
||||
#define GPMC_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x0BE)
|
||||
#define GPMC_NADV_ALE (SYSTEM_CONTROL_MODULE_BASE + 0x0C0)
|
||||
#define GPMC_NOE (SYSTEM_CONTROL_MODULE_BASE + 0x0C2)
|
||||
#define GPMC_NWE (SYSTEM_CONTROL_MODULE_BASE + 0x0C4)
|
||||
#define GPMC_NBE0_CLE (SYSTEM_CONTROL_MODULE_BASE + 0x0C6)
|
||||
#define GPMC_NBE1 (SYSTEM_CONTROL_MODULE_BASE + 0x0C8)
|
||||
#define GPMC_NWP (SYSTEM_CONTROL_MODULE_BASE + 0x0CA)
|
||||
#define GPMC_WAIT0 (SYSTEM_CONTROL_MODULE_BASE + 0x0CC)
|
||||
#define GPMC_WAIT1 (SYSTEM_CONTROL_MODULE_BASE + 0x0CE)
|
||||
#define GPMC_WAIT2 (SYSTEM_CONTROL_MODULE_BASE + 0x0D0)
|
||||
#define GPMC_WAIT3 (SYSTEM_CONTROL_MODULE_BASE + 0x0D2)
|
||||
#define DSS_PCLK (SYSTEM_CONTROL_MODULE_BASE + 0x0D4)
|
||||
#define DSS_HSYNC (SYSTEM_CONTROL_MODULE_BASE + 0x0D6)
|
||||
#define DSS_PSYNC (SYSTEM_CONTROL_MODULE_BASE + 0x0D8)
|
||||
#define DSS_ACBIAS (SYSTEM_CONTROL_MODULE_BASE + 0x0DA)
|
||||
#define DSS_DATA0 (SYSTEM_CONTROL_MODULE_BASE + 0x0DC)
|
||||
#define DSS_DATA1 (SYSTEM_CONTROL_MODULE_BASE + 0x0DE)
|
||||
#define DSS_DATA2 (SYSTEM_CONTROL_MODULE_BASE + 0x0E0)
|
||||
#define DSS_DATA3 (SYSTEM_CONTROL_MODULE_BASE + 0x0E2)
|
||||
#define DSS_DATA4 (SYSTEM_CONTROL_MODULE_BASE + 0x0E4)
|
||||
#define DSS_DATA5 (SYSTEM_CONTROL_MODULE_BASE + 0x0E6)
|
||||
#define DSS_DATA6 (SYSTEM_CONTROL_MODULE_BASE + 0x0E8)
|
||||
#define DSS_DATA7 (SYSTEM_CONTROL_MODULE_BASE + 0x0EA)
|
||||
#define DSS_DATA8 (SYSTEM_CONTROL_MODULE_BASE + 0x0EC)
|
||||
#define DSS_DATA9 (SYSTEM_CONTROL_MODULE_BASE + 0x0EE)
|
||||
#define DSS_DATA10 (SYSTEM_CONTROL_MODULE_BASE + 0x0F0)
|
||||
#define DSS_DATA11 (SYSTEM_CONTROL_MODULE_BASE + 0x0F2)
|
||||
#define DSS_DATA12 (SYSTEM_CONTROL_MODULE_BASE + 0x0F4)
|
||||
#define DSS_DATA13 (SYSTEM_CONTROL_MODULE_BASE + 0x0F6)
|
||||
#define DSS_DATA14 (SYSTEM_CONTROL_MODULE_BASE + 0x0F8)
|
||||
#define DSS_DATA15 (SYSTEM_CONTROL_MODULE_BASE + 0x0FA)
|
||||
#define DSS_DATA16 (SYSTEM_CONTROL_MODULE_BASE + 0x0FC)
|
||||
#define DSS_DATA17 (SYSTEM_CONTROL_MODULE_BASE + 0x0FE)
|
||||
#define DSS_DATA18 (SYSTEM_CONTROL_MODULE_BASE + 0x100)
|
||||
#define DSS_DATA19 (SYSTEM_CONTROL_MODULE_BASE + 0x102)
|
||||
#define DSS_DATA20 (SYSTEM_CONTROL_MODULE_BASE + 0x104)
|
||||
#define DSS_DATA21 (SYSTEM_CONTROL_MODULE_BASE + 0x106)
|
||||
#define DSS_DATA22 (SYSTEM_CONTROL_MODULE_BASE + 0x108)
|
||||
#define DSS_DATA23 (SYSTEM_CONTROL_MODULE_BASE + 0x10A)
|
||||
#define CAM_HS (SYSTEM_CONTROL_MODULE_BASE + 0x10C)
|
||||
#define CAM_VS (SYSTEM_CONTROL_MODULE_BASE + 0x10E)
|
||||
#define CAM_XCLKA (SYSTEM_CONTROL_MODULE_BASE + 0x110)
|
||||
#define CAM_PCLK (SYSTEM_CONTROL_MODULE_BASE + 0x112)
|
||||
#define CAM_FLD (SYSTEM_CONTROL_MODULE_BASE + 0x114)
|
||||
#define CAM_D0 (SYSTEM_CONTROL_MODULE_BASE + 0x116)
|
||||
#define CAM_D1 (SYSTEM_CONTROL_MODULE_BASE + 0x118)
|
||||
#define CAM_D2 (SYSTEM_CONTROL_MODULE_BASE + 0x11A)
|
||||
#define CAM_D3 (SYSTEM_CONTROL_MODULE_BASE + 0x11C)
|
||||
#define CAM_D4 (SYSTEM_CONTROL_MODULE_BASE + 0x11E)
|
||||
#define CAM_D5 (SYSTEM_CONTROL_MODULE_BASE + 0x120)
|
||||
#define CAM_D6 (SYSTEM_CONTROL_MODULE_BASE + 0x122)
|
||||
#define CAM_D7 (SYSTEM_CONTROL_MODULE_BASE + 0x124)
|
||||
#define CAM_D8 (SYSTEM_CONTROL_MODULE_BASE + 0x126)
|
||||
#define CAM_D9 (SYSTEM_CONTROL_MODULE_BASE + 0x128)
|
||||
#define CAM_D10 (SYSTEM_CONTROL_MODULE_BASE + 0x12A)
|
||||
#define CAM_D11 (SYSTEM_CONTROL_MODULE_BASE + 0x12C)
|
||||
#define CAM_XCLKB (SYSTEM_CONTROL_MODULE_BASE + 0x12E)
|
||||
#define CAM_WEN (SYSTEM_CONTROL_MODULE_BASE + 0x130)
|
||||
#define CAM_STROBE (SYSTEM_CONTROL_MODULE_BASE + 0x132)
|
||||
#define CSI2_DX0 (SYSTEM_CONTROL_MODULE_BASE + 0x134)
|
||||
#define CSI2_DY0 (SYSTEM_CONTROL_MODULE_BASE + 0x136)
|
||||
#define CSI2_DX1 (SYSTEM_CONTROL_MODULE_BASE + 0x138)
|
||||
#define CSI2_DY1 (SYSTEM_CONTROL_MODULE_BASE + 0x13A)
|
||||
#define MCBSP2_FSX (SYSTEM_CONTROL_MODULE_BASE + 0x13C)
|
||||
#define MCBSP2_CLKX (SYSTEM_CONTROL_MODULE_BASE + 0x13E)
|
||||
#define MCBSP2_DR (SYSTEM_CONTROL_MODULE_BASE + 0x140)
|
||||
#define MCBSP2_DX (SYSTEM_CONTROL_MODULE_BASE + 0x142)
|
||||
#define MMC1_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x144)
|
||||
#define MMC1_CMD (SYSTEM_CONTROL_MODULE_BASE + 0x146)
|
||||
#define MMC1_DAT0 (SYSTEM_CONTROL_MODULE_BASE + 0x148)
|
||||
#define MMC1_DAT1 (SYSTEM_CONTROL_MODULE_BASE + 0x14A)
|
||||
#define MMC1_DAT2 (SYSTEM_CONTROL_MODULE_BASE + 0x14C)
|
||||
#define MMC1_DAT3 (SYSTEM_CONTROL_MODULE_BASE + 0x14E)
|
||||
#define MMC1_DAT4 (SYSTEM_CONTROL_MODULE_BASE + 0x150)
|
||||
#define MMC1_DAT5 (SYSTEM_CONTROL_MODULE_BASE + 0x152)
|
||||
#define MMC1_DAT6 (SYSTEM_CONTROL_MODULE_BASE + 0x154)
|
||||
#define MMC1_DAT7 (SYSTEM_CONTROL_MODULE_BASE + 0x156)
|
||||
#define MMC2_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x158)
|
||||
#define MMC2_CMD (SYSTEM_CONTROL_MODULE_BASE + 0x15A)
|
||||
#define MMC2_DAT0 (SYSTEM_CONTROL_MODULE_BASE + 0x15C)
|
||||
#define MMC2_DAT1 (SYSTEM_CONTROL_MODULE_BASE + 0x15E)
|
||||
#define MMC2_DAT2 (SYSTEM_CONTROL_MODULE_BASE + 0x160)
|
||||
#define MMC2_DAT3 (SYSTEM_CONTROL_MODULE_BASE + 0x162)
|
||||
#define MMC2_DAT4 (SYSTEM_CONTROL_MODULE_BASE + 0x164)
|
||||
#define MMC2_DAT5 (SYSTEM_CONTROL_MODULE_BASE + 0x166)
|
||||
#define MMC2_DAT6 (SYSTEM_CONTROL_MODULE_BASE + 0x168)
|
||||
#define MMC2_DAT7 (SYSTEM_CONTROL_MODULE_BASE + 0x16A)
|
||||
#define MCBSP3_DX (SYSTEM_CONTROL_MODULE_BASE + 0x16C)
|
||||
#define MCBSP3_DR (SYSTEM_CONTROL_MODULE_BASE + 0x16E)
|
||||
#define MCBSP3_CLKX (SYSTEM_CONTROL_MODULE_BASE + 0x170)
|
||||
#define MCBSP3_FSX (SYSTEM_CONTROL_MODULE_BASE + 0x172)
|
||||
#define UART2_CTS (SYSTEM_CONTROL_MODULE_BASE + 0x174)
|
||||
#define UART2_RTS (SYSTEM_CONTROL_MODULE_BASE + 0x176)
|
||||
#define UART2_TX (SYSTEM_CONTROL_MODULE_BASE + 0x178)
|
||||
#define UART2_RX (SYSTEM_CONTROL_MODULE_BASE + 0x17A)
|
||||
#define UART1_TX (SYSTEM_CONTROL_MODULE_BASE + 0x17C)
|
||||
#define UART1_RTS (SYSTEM_CONTROL_MODULE_BASE + 0x17E)
|
||||
#define UART1_CTS (SYSTEM_CONTROL_MODULE_BASE + 0x180)
|
||||
#define UART1_RX (SYSTEM_CONTROL_MODULE_BASE + 0x182)
|
||||
#define MCBSP4_CLKX (SYSTEM_CONTROL_MODULE_BASE + 0x184)
|
||||
#define MCBSP4_DR (SYSTEM_CONTROL_MODULE_BASE + 0x186)
|
||||
#define MCBSP4_DX (SYSTEM_CONTROL_MODULE_BASE + 0x188)
|
||||
#define MCBSP4_FSX (SYSTEM_CONTROL_MODULE_BASE + 0x18A)
|
||||
#define MCBSP1_CLKR (SYSTEM_CONTROL_MODULE_BASE + 0x18C)
|
||||
#define MCBSP1_FSR (SYSTEM_CONTROL_MODULE_BASE + 0x18E)
|
||||
#define MCBSP1_DX (SYSTEM_CONTROL_MODULE_BASE + 0x190)
|
||||
#define MCBSP1_DR (SYSTEM_CONTROL_MODULE_BASE + 0x192)
|
||||
#define MCBSP1_CLKS (SYSTEM_CONTROL_MODULE_BASE + 0x194)
|
||||
#define MCBSP1_FSX (SYSTEM_CONTROL_MODULE_BASE + 0x196)
|
||||
#define MCBSP1_CLKX (SYSTEM_CONTROL_MODULE_BASE + 0x198)
|
||||
#define UART3_CTS_RCTX (SYSTEM_CONTROL_MODULE_BASE + 0x19A)
|
||||
#define UART3_RTS_SD (SYSTEM_CONTROL_MODULE_BASE + 0x19C)
|
||||
#define UART3_RX_IRRX (SYSTEM_CONTROL_MODULE_BASE + 0x19E)
|
||||
#define UART3_TX_IRTX (SYSTEM_CONTROL_MODULE_BASE + 0x1A0)
|
||||
#define HSUSB0_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x1A2)
|
||||
#define HSUSB0_STP (SYSTEM_CONTROL_MODULE_BASE + 0x1A4)
|
||||
#define HSUSB0_DIR (SYSTEM_CONTROL_MODULE_BASE + 0x1A6)
|
||||
#define HSUSB0_NXT (SYSTEM_CONTROL_MODULE_BASE + 0x1A8)
|
||||
#define HSUSB0_DATA0 (SYSTEM_CONTROL_MODULE_BASE + 0x1AA)
|
||||
#define HSUSB0_DATA1 (SYSTEM_CONTROL_MODULE_BASE + 0x1AC)
|
||||
#define HSUSB0_DATA2 (SYSTEM_CONTROL_MODULE_BASE + 0x1AE)
|
||||
#define HSUSB0_DATA3 (SYSTEM_CONTROL_MODULE_BASE + 0x1B0)
|
||||
#define HSUSB0_DATA4 (SYSTEM_CONTROL_MODULE_BASE + 0x1B2)
|
||||
#define HSUSB0_DATA5 (SYSTEM_CONTROL_MODULE_BASE + 0x1B4)
|
||||
#define HSUSB0_DATA6 (SYSTEM_CONTROL_MODULE_BASE + 0x1B6)
|
||||
#define HSUSB0_DATA7 (SYSTEM_CONTROL_MODULE_BASE + 0x1B8)
|
||||
#define I2C1_SCL (SYSTEM_CONTROL_MODULE_BASE + 0x1BA)
|
||||
#define I2C1_SDA (SYSTEM_CONTROL_MODULE_BASE + 0x1BC)
|
||||
#define I2C2_SCL (SYSTEM_CONTROL_MODULE_BASE + 0x1BE)
|
||||
#define I2C2_SDA (SYSTEM_CONTROL_MODULE_BASE + 0x1C0)
|
||||
#define I2C3_SCL (SYSTEM_CONTROL_MODULE_BASE + 0x1C2)
|
||||
#define I2C3_SDA (SYSTEM_CONTROL_MODULE_BASE + 0x1C4)
|
||||
#define HDQ_SIO (SYSTEM_CONTROL_MODULE_BASE + 0x1C6)
|
||||
#define MCSPI1_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x1C8)
|
||||
#define MCSPI1_SIMO (SYSTEM_CONTROL_MODULE_BASE + 0x1CA)
|
||||
#define MCSPI1_SOMI (SYSTEM_CONTROL_MODULE_BASE + 0x1CC)
|
||||
#define MCSPI1_CS0 (SYSTEM_CONTROL_MODULE_BASE + 0x1CE)
|
||||
#define MCSPI1_CS1 (SYSTEM_CONTROL_MODULE_BASE + 0x1D0)
|
||||
#define MCSPI1_CS2 (SYSTEM_CONTROL_MODULE_BASE + 0x1D2)
|
||||
#define MCSPI1_CS3 (SYSTEM_CONTROL_MODULE_BASE + 0x1D4)
|
||||
#define MCSPI2_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x1D6)
|
||||
#define MCSPI2_SIMO (SYSTEM_CONTROL_MODULE_BASE + 0x1D8)
|
||||
#define MCSPI2_SOMI (SYSTEM_CONTROL_MODULE_BASE + 0x1DA)
|
||||
#define MCSPI2_CS0 (SYSTEM_CONTROL_MODULE_BASE + 0x1DC)
|
||||
#define MCSPI2_CS1 (SYSTEM_CONTROL_MODULE_BASE + 0x1DE)
|
||||
#define SYS_NIRQ (SYSTEM_CONTROL_MODULE_BASE + 0x1E0)
|
||||
#define SYS_CLKOUT2 (SYSTEM_CONTROL_MODULE_BASE + 0x1E2)
|
||||
#define ETK_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x5D8)
|
||||
#define ETK_CTL (SYSTEM_CONTROL_MODULE_BASE + 0x5DA)
|
||||
#define ETK_D0 (SYSTEM_CONTROL_MODULE_BASE + 0x5DC)
|
||||
#define ETK_D1 (SYSTEM_CONTROL_MODULE_BASE + 0x5DE)
|
||||
#define ETK_D2 (SYSTEM_CONTROL_MODULE_BASE + 0x5E0)
|
||||
#define ETK_D3 (SYSTEM_CONTROL_MODULE_BASE + 0x5E2)
|
||||
#define ETK_D4 (SYSTEM_CONTROL_MODULE_BASE + 0x5E4)
|
||||
#define ETK_D5 (SYSTEM_CONTROL_MODULE_BASE + 0x5E6)
|
||||
#define ETK_D6 (SYSTEM_CONTROL_MODULE_BASE + 0x5E8)
|
||||
#define ETK_D7 (SYSTEM_CONTROL_MODULE_BASE + 0x5EA)
|
||||
#define ETK_D8 (SYSTEM_CONTROL_MODULE_BASE + 0x5EC)
|
||||
#define ETK_D9 (SYSTEM_CONTROL_MODULE_BASE + 0x5EE)
|
||||
#define ETK_D10 (SYSTEM_CONTROL_MODULE_BASE + 0x5F0)
|
||||
#define ETK_D11 (SYSTEM_CONTROL_MODULE_BASE + 0x5F2)
|
||||
#define ETK_D12 (SYSTEM_CONTROL_MODULE_BASE + 0x5F4)
|
||||
#define ETK_D13 (SYSTEM_CONTROL_MODULE_BASE + 0x5F6)
|
||||
#define ETK_D14 (SYSTEM_CONTROL_MODULE_BASE + 0x5F8)
|
||||
#define ETK_D15 (SYSTEM_CONTROL_MODULE_BASE + 0x5FA)
|
||||
#define SYS_BOOT0 (SYSTEM_CONTROL_MODULE_BASE + 0xA0A)
|
||||
#define SYS_BOOT1 (SYSTEM_CONTROL_MODULE_BASE + 0xA0C)
|
||||
#define SYS_BOOT3 (SYSTEM_CONTROL_MODULE_BASE + 0xA10)
|
||||
#define SYS_BOOT4 (SYSTEM_CONTROL_MODULE_BASE + 0xA12)
|
||||
#define SYS_BOOT5 (SYSTEM_CONTROL_MODULE_BASE + 0xA14)
|
||||
#define SYS_BOOT6 (SYSTEM_CONTROL_MODULE_BASE + 0xA16)
|
||||
|
||||
//Mux modes
|
||||
#define MUXMODE0 (0x0UL)
|
||||
#define MUXMODE1 (0x1UL)
|
||||
#define MUXMODE2 (0x2UL)
|
||||
#define MUXMODE3 (0x3UL)
|
||||
#define MUXMODE4 (0x4UL)
|
||||
#define MUXMODE5 (0x5UL)
|
||||
#define MUXMODE6 (0x6UL)
|
||||
#define MUXMODE7 (0x7UL)
|
||||
|
||||
//Pad configuration register.
|
||||
#define PAD_CONFIG_MASK (0xFFFFUL)
|
||||
#define MUXMODE_OFFSET 0
|
||||
#define MUXMODE_MASK (0x7UL << MUXMODE_OFFSET)
|
||||
#define PULL_CONFIG_OFFSET 3
|
||||
#define PULL_CONFIG_MASK (0x3UL << PULL_CONFIG_OFFSET)
|
||||
#define INPUTENABLE_OFFSET 8
|
||||
#define INPUTENABLE_MASK (0x1UL << INPUTENABLE_OFFSET)
|
||||
#define OFFMODE_VALUE_OFFSET 9
|
||||
#define OFFMODE_VALUE_MASK (0x1FUL << OFFMODE_VALUE_OFFSET)
|
||||
#define WAKEUP_OFFSET 14
|
||||
#define WAKEUP_MASK (0x2UL << WAKEUP_OFFSET)
|
||||
|
||||
#define PULL_DOWN_SELECTED ((0x0UL << 1) | BIT0)
|
||||
#define PULL_UP_SELECTED (BIT1 | BIT0)
|
||||
#define PULL_DISABLED (0x0UL << 0)
|
||||
|
||||
#define OUTPUT (0x0UL) //Pin is configured in output only mode.
|
||||
#define INPUT (0x1UL) //Pin is configured in bi-directional mode.
|
||||
|
||||
typedef struct {
|
||||
UINTN Pin;
|
||||
UINTN MuxMode;
|
||||
UINTN PullConfig;
|
||||
UINTN InputEnable;
|
||||
} PAD_CONFIGURATION;
|
||||
|
||||
#endif //__OMAP3530_PAD_CONFIGURATION_H__
|
||||
|
||||
@@ -1,165 +1,165 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
||||
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __OMAP3530PRCM_H__
|
||||
#define __OMAP3530PRCM_H__
|
||||
|
||||
#define CM_FCLKEN1_CORE (0x48004A00)
|
||||
#define CM_FCLKEN3_CORE (0x48004A08)
|
||||
#define CM_ICLKEN1_CORE (0x48004A10)
|
||||
#define CM_ICLKEN3_CORE (0x48004A18)
|
||||
#define CM_CLKEN2_PLL (0x48004D04)
|
||||
#define CM_CLKSEL4_PLL (0x48004D4C)
|
||||
#define CM_CLKSEL5_PLL (0x48004D50)
|
||||
#define CM_FCLKEN_USBHOST (0x48005400)
|
||||
#define CM_ICLKEN_USBHOST (0x48005410)
|
||||
#define CM_CLKSTST_USBHOST (0x4800544c)
|
||||
|
||||
//Wakeup clock defintion
|
||||
#define CM_FCLKEN_WKUP (0x48004C00)
|
||||
#define CM_ICLKEN_WKUP (0x48004C10)
|
||||
|
||||
//Peripheral clock definition
|
||||
#define CM_FCLKEN_PER (0x48005000)
|
||||
#define CM_ICLKEN_PER (0x48005010)
|
||||
#define CM_CLKSEL_PER (0x48005040)
|
||||
|
||||
//Reset management definition
|
||||
#define PRM_RSTCTRL (0x48307250)
|
||||
#define PRM_RSTST (0x48307258)
|
||||
|
||||
//CORE clock
|
||||
#define CM_FCLKEN1_CORE_EN_I2C1_MASK BIT15
|
||||
#define CM_FCLKEN1_CORE_EN_I2C1_DISABLE (0UL << 15)
|
||||
#define CM_FCLKEN1_CORE_EN_I2C1_ENABLE BIT15
|
||||
|
||||
#define CM_ICLKEN1_CORE_EN_I2C1_MASK BIT15
|
||||
#define CM_ICLKEN1_CORE_EN_I2C1_DISABLE (0UL << 15)
|
||||
#define CM_ICLKEN1_CORE_EN_I2C1_ENABLE BIT15
|
||||
|
||||
#define CM_FCLKEN1_CORE_EN_MMC1_MASK BIT24
|
||||
#define CM_FCLKEN1_CORE_EN_MMC1_DISABLE (0UL << 24)
|
||||
#define CM_FCLKEN1_CORE_EN_MMC1_ENABLE BIT24
|
||||
|
||||
#define CM_FCLKEN3_CORE_EN_USBTLL_MASK BIT2
|
||||
#define CM_FCLKEN3_CORE_EN_USBTLL_DISABLE (0UL << 2)
|
||||
#define CM_FCLKEN3_CORE_EN_USBTLL_ENABLE BIT2
|
||||
|
||||
#define CM_ICLKEN1_CORE_EN_MMC1_MASK BIT24
|
||||
#define CM_ICLKEN1_CORE_EN_MMC1_DISABLE (0UL << 24)
|
||||
#define CM_ICLKEN1_CORE_EN_MMC1_ENABLE BIT24
|
||||
|
||||
#define CM_ICLKEN3_CORE_EN_USBTLL_MASK BIT2
|
||||
#define CM_ICLKEN3_CORE_EN_USBTLL_DISABLE (0UL << 2)
|
||||
#define CM_ICLKEN3_CORE_EN_USBTLL_ENABLE BIT2
|
||||
|
||||
#define CM_CLKEN_FREQSEL_075_100 (0x03UL << 4)
|
||||
#define CM_CLKEN_ENABLE (7UL << 0)
|
||||
|
||||
#define CM_CLKSEL_PLL_MULT(x) (((x) & 0x07FF) << 8)
|
||||
#define CM_CLKSEL_PLL_DIV(x) ((((x) - 1) & 0x7F) << 0)
|
||||
|
||||
#define CM_CLKSEL_DIV_120M(x) (((x) & 0x1F) << 0)
|
||||
|
||||
#define CM_FCLKEN_USBHOST_EN_USBHOST2_MASK BIT1
|
||||
#define CM_FCLKEN_USBHOST_EN_USBHOST2_DISABLE (0UL << 1)
|
||||
#define CM_FCLKEN_USBHOST_EN_USBHOST2_ENABLE BIT1
|
||||
|
||||
#define CM_FCLKEN_USBHOST_EN_USBHOST1_MASK BIT0
|
||||
#define CM_FCLKEN_USBHOST_EN_USBHOST1_DISABLE (0UL << 0)
|
||||
#define CM_FCLKEN_USBHOST_EN_USBHOST1_ENABLE BIT0
|
||||
|
||||
#define CM_ICLKEN_USBHOST_EN_USBHOST_MASK BIT0
|
||||
#define CM_ICLKEN_USBHOST_EN_USBHOST_DISABLE (0UL << 0)
|
||||
#define CM_ICLKEN_USBHOST_EN_USBHOST_ENABLE BIT0
|
||||
|
||||
//Wakeup functional clock
|
||||
#define CM_FCLKEN_WKUP_EN_GPIO1_DISABLE (0UL << 3)
|
||||
#define CM_FCLKEN_WKUP_EN_GPIO1_ENABLE BIT3
|
||||
|
||||
#define CM_FCLKEN_WKUP_EN_WDT2_DISABLE (0UL << 5)
|
||||
#define CM_FCLKEN_WKUP_EN_WDT2_ENABLE BIT5
|
||||
|
||||
//Wakeup interface clock
|
||||
#define CM_ICLKEN_WKUP_EN_GPIO1_DISABLE (0UL << 3)
|
||||
#define CM_ICLKEN_WKUP_EN_GPIO1_ENABLE BIT3
|
||||
|
||||
#define CM_ICLKEN_WKUP_EN_WDT2_DISABLE (0UL << 5)
|
||||
#define CM_ICLKEN_WKUP_EN_WDT2_ENABLE BIT5
|
||||
|
||||
//Peripheral functional clock
|
||||
#define CM_FCLKEN_PER_EN_GPT3_DISABLE (0UL << 4)
|
||||
#define CM_FCLKEN_PER_EN_GPT3_ENABLE BIT4
|
||||
|
||||
#define CM_FCLKEN_PER_EN_GPT4_DISABLE (0UL << 5)
|
||||
#define CM_FCLKEN_PER_EN_GPT4_ENABLE BIT5
|
||||
|
||||
#define CM_FCLKEN_PER_EN_UART3_DISABLE (0UL << 11)
|
||||
#define CM_FCLKEN_PER_EN_UART3_ENABLE BIT11
|
||||
|
||||
#define CM_FCLKEN_PER_EN_GPIO2_DISABLE (0UL << 13)
|
||||
#define CM_FCLKEN_PER_EN_GPIO2_ENABLE BIT13
|
||||
|
||||
#define CM_FCLKEN_PER_EN_GPIO3_DISABLE (0UL << 14)
|
||||
#define CM_FCLKEN_PER_EN_GPIO3_ENABLE BIT14
|
||||
|
||||
#define CM_FCLKEN_PER_EN_GPIO4_DISABLE (0UL << 15)
|
||||
#define CM_FCLKEN_PER_EN_GPIO4_ENABLE BIT15
|
||||
|
||||
#define CM_FCLKEN_PER_EN_GPIO5_DISABLE (0UL << 16)
|
||||
#define CM_FCLKEN_PER_EN_GPIO5_ENABLE BIT16
|
||||
|
||||
#define CM_FCLKEN_PER_EN_GPIO6_DISABLE (0UL << 17)
|
||||
#define CM_FCLKEN_PER_EN_GPIO6_ENABLE BIT17
|
||||
|
||||
//Peripheral interface clock
|
||||
#define CM_ICLKEN_PER_EN_GPT3_DISABLE (0UL << 4)
|
||||
#define CM_ICLKEN_PER_EN_GPT3_ENABLE BIT4
|
||||
|
||||
#define CM_ICLKEN_PER_EN_GPT4_DISABLE (0UL << 5)
|
||||
#define CM_ICLKEN_PER_EN_GPT4_ENABLE BIT5
|
||||
|
||||
#define CM_ICLKEN_PER_EN_UART3_DISABLE (0UL << 11)
|
||||
#define CM_ICLKEN_PER_EN_UART3_ENABLE BIT11
|
||||
|
||||
#define CM_ICLKEN_PER_EN_GPIO2_DISABLE (0UL << 13)
|
||||
#define CM_ICLKEN_PER_EN_GPIO2_ENABLE BIT13
|
||||
|
||||
#define CM_ICLKEN_PER_EN_GPIO3_DISABLE (0UL << 14)
|
||||
#define CM_ICLKEN_PER_EN_GPIO3_ENABLE BIT14
|
||||
|
||||
#define CM_ICLKEN_PER_EN_GPIO4_DISABLE (0UL << 15)
|
||||
#define CM_ICLKEN_PER_EN_GPIO4_ENABLE BIT15
|
||||
|
||||
#define CM_ICLKEN_PER_EN_GPIO5_DISABLE (0UL << 16)
|
||||
#define CM_ICLKEN_PER_EN_GPIO5_ENABLE BIT16
|
||||
|
||||
#define CM_ICLKEN_PER_EN_GPIO6_DISABLE (0UL << 17)
|
||||
#define CM_ICLKEN_PER_EN_GPIO6_ENABLE BIT17
|
||||
|
||||
//Timer source clock selection
|
||||
#define CM_CLKSEL_PER_CLKSEL_GPT3_32K (0UL << 1)
|
||||
#define CM_CLKSEL_PER_CLKSEL_GPT3_SYS BIT1
|
||||
|
||||
#define CM_CLKSEL_PER_CLKSEL_GPT4_32K (0UL << 2)
|
||||
#define CM_CLKSEL_PER_CLKSEL_GPT4_SYS BIT2
|
||||
|
||||
//Reset management (Global and Cold reset)
|
||||
#define RST_GS BIT1
|
||||
#define RST_DPLL3 BIT2
|
||||
#define GLOBAL_SW_RST BIT1
|
||||
#define GLOBAL_COLD_RST (0x0UL << 0)
|
||||
|
||||
#endif // __OMAP3530PRCM_H__
|
||||
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
||||
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __OMAP3530PRCM_H__
|
||||
#define __OMAP3530PRCM_H__
|
||||
|
||||
#define CM_FCLKEN1_CORE (0x48004A00)
|
||||
#define CM_FCLKEN3_CORE (0x48004A08)
|
||||
#define CM_ICLKEN1_CORE (0x48004A10)
|
||||
#define CM_ICLKEN3_CORE (0x48004A18)
|
||||
#define CM_CLKEN2_PLL (0x48004D04)
|
||||
#define CM_CLKSEL4_PLL (0x48004D4C)
|
||||
#define CM_CLKSEL5_PLL (0x48004D50)
|
||||
#define CM_FCLKEN_USBHOST (0x48005400)
|
||||
#define CM_ICLKEN_USBHOST (0x48005410)
|
||||
#define CM_CLKSTST_USBHOST (0x4800544c)
|
||||
|
||||
//Wakeup clock defintion
|
||||
#define CM_FCLKEN_WKUP (0x48004C00)
|
||||
#define CM_ICLKEN_WKUP (0x48004C10)
|
||||
|
||||
//Peripheral clock definition
|
||||
#define CM_FCLKEN_PER (0x48005000)
|
||||
#define CM_ICLKEN_PER (0x48005010)
|
||||
#define CM_CLKSEL_PER (0x48005040)
|
||||
|
||||
//Reset management definition
|
||||
#define PRM_RSTCTRL (0x48307250)
|
||||
#define PRM_RSTST (0x48307258)
|
||||
|
||||
//CORE clock
|
||||
#define CM_FCLKEN1_CORE_EN_I2C1_MASK BIT15
|
||||
#define CM_FCLKEN1_CORE_EN_I2C1_DISABLE (0UL << 15)
|
||||
#define CM_FCLKEN1_CORE_EN_I2C1_ENABLE BIT15
|
||||
|
||||
#define CM_ICLKEN1_CORE_EN_I2C1_MASK BIT15
|
||||
#define CM_ICLKEN1_CORE_EN_I2C1_DISABLE (0UL << 15)
|
||||
#define CM_ICLKEN1_CORE_EN_I2C1_ENABLE BIT15
|
||||
|
||||
#define CM_FCLKEN1_CORE_EN_MMC1_MASK BIT24
|
||||
#define CM_FCLKEN1_CORE_EN_MMC1_DISABLE (0UL << 24)
|
||||
#define CM_FCLKEN1_CORE_EN_MMC1_ENABLE BIT24
|
||||
|
||||
#define CM_FCLKEN3_CORE_EN_USBTLL_MASK BIT2
|
||||
#define CM_FCLKEN3_CORE_EN_USBTLL_DISABLE (0UL << 2)
|
||||
#define CM_FCLKEN3_CORE_EN_USBTLL_ENABLE BIT2
|
||||
|
||||
#define CM_ICLKEN1_CORE_EN_MMC1_MASK BIT24
|
||||
#define CM_ICLKEN1_CORE_EN_MMC1_DISABLE (0UL << 24)
|
||||
#define CM_ICLKEN1_CORE_EN_MMC1_ENABLE BIT24
|
||||
|
||||
#define CM_ICLKEN3_CORE_EN_USBTLL_MASK BIT2
|
||||
#define CM_ICLKEN3_CORE_EN_USBTLL_DISABLE (0UL << 2)
|
||||
#define CM_ICLKEN3_CORE_EN_USBTLL_ENABLE BIT2
|
||||
|
||||
#define CM_CLKEN_FREQSEL_075_100 (0x03UL << 4)
|
||||
#define CM_CLKEN_ENABLE (7UL << 0)
|
||||
|
||||
#define CM_CLKSEL_PLL_MULT(x) (((x) & 0x07FF) << 8)
|
||||
#define CM_CLKSEL_PLL_DIV(x) ((((x) - 1) & 0x7F) << 0)
|
||||
|
||||
#define CM_CLKSEL_DIV_120M(x) (((x) & 0x1F) << 0)
|
||||
|
||||
#define CM_FCLKEN_USBHOST_EN_USBHOST2_MASK BIT1
|
||||
#define CM_FCLKEN_USBHOST_EN_USBHOST2_DISABLE (0UL << 1)
|
||||
#define CM_FCLKEN_USBHOST_EN_USBHOST2_ENABLE BIT1
|
||||
|
||||
#define CM_FCLKEN_USBHOST_EN_USBHOST1_MASK BIT0
|
||||
#define CM_FCLKEN_USBHOST_EN_USBHOST1_DISABLE (0UL << 0)
|
||||
#define CM_FCLKEN_USBHOST_EN_USBHOST1_ENABLE BIT0
|
||||
|
||||
#define CM_ICLKEN_USBHOST_EN_USBHOST_MASK BIT0
|
||||
#define CM_ICLKEN_USBHOST_EN_USBHOST_DISABLE (0UL << 0)
|
||||
#define CM_ICLKEN_USBHOST_EN_USBHOST_ENABLE BIT0
|
||||
|
||||
//Wakeup functional clock
|
||||
#define CM_FCLKEN_WKUP_EN_GPIO1_DISABLE (0UL << 3)
|
||||
#define CM_FCLKEN_WKUP_EN_GPIO1_ENABLE BIT3
|
||||
|
||||
#define CM_FCLKEN_WKUP_EN_WDT2_DISABLE (0UL << 5)
|
||||
#define CM_FCLKEN_WKUP_EN_WDT2_ENABLE BIT5
|
||||
|
||||
//Wakeup interface clock
|
||||
#define CM_ICLKEN_WKUP_EN_GPIO1_DISABLE (0UL << 3)
|
||||
#define CM_ICLKEN_WKUP_EN_GPIO1_ENABLE BIT3
|
||||
|
||||
#define CM_ICLKEN_WKUP_EN_WDT2_DISABLE (0UL << 5)
|
||||
#define CM_ICLKEN_WKUP_EN_WDT2_ENABLE BIT5
|
||||
|
||||
//Peripheral functional clock
|
||||
#define CM_FCLKEN_PER_EN_GPT3_DISABLE (0UL << 4)
|
||||
#define CM_FCLKEN_PER_EN_GPT3_ENABLE BIT4
|
||||
|
||||
#define CM_FCLKEN_PER_EN_GPT4_DISABLE (0UL << 5)
|
||||
#define CM_FCLKEN_PER_EN_GPT4_ENABLE BIT5
|
||||
|
||||
#define CM_FCLKEN_PER_EN_UART3_DISABLE (0UL << 11)
|
||||
#define CM_FCLKEN_PER_EN_UART3_ENABLE BIT11
|
||||
|
||||
#define CM_FCLKEN_PER_EN_GPIO2_DISABLE (0UL << 13)
|
||||
#define CM_FCLKEN_PER_EN_GPIO2_ENABLE BIT13
|
||||
|
||||
#define CM_FCLKEN_PER_EN_GPIO3_DISABLE (0UL << 14)
|
||||
#define CM_FCLKEN_PER_EN_GPIO3_ENABLE BIT14
|
||||
|
||||
#define CM_FCLKEN_PER_EN_GPIO4_DISABLE (0UL << 15)
|
||||
#define CM_FCLKEN_PER_EN_GPIO4_ENABLE BIT15
|
||||
|
||||
#define CM_FCLKEN_PER_EN_GPIO5_DISABLE (0UL << 16)
|
||||
#define CM_FCLKEN_PER_EN_GPIO5_ENABLE BIT16
|
||||
|
||||
#define CM_FCLKEN_PER_EN_GPIO6_DISABLE (0UL << 17)
|
||||
#define CM_FCLKEN_PER_EN_GPIO6_ENABLE BIT17
|
||||
|
||||
//Peripheral interface clock
|
||||
#define CM_ICLKEN_PER_EN_GPT3_DISABLE (0UL << 4)
|
||||
#define CM_ICLKEN_PER_EN_GPT3_ENABLE BIT4
|
||||
|
||||
#define CM_ICLKEN_PER_EN_GPT4_DISABLE (0UL << 5)
|
||||
#define CM_ICLKEN_PER_EN_GPT4_ENABLE BIT5
|
||||
|
||||
#define CM_ICLKEN_PER_EN_UART3_DISABLE (0UL << 11)
|
||||
#define CM_ICLKEN_PER_EN_UART3_ENABLE BIT11
|
||||
|
||||
#define CM_ICLKEN_PER_EN_GPIO2_DISABLE (0UL << 13)
|
||||
#define CM_ICLKEN_PER_EN_GPIO2_ENABLE BIT13
|
||||
|
||||
#define CM_ICLKEN_PER_EN_GPIO3_DISABLE (0UL << 14)
|
||||
#define CM_ICLKEN_PER_EN_GPIO3_ENABLE BIT14
|
||||
|
||||
#define CM_ICLKEN_PER_EN_GPIO4_DISABLE (0UL << 15)
|
||||
#define CM_ICLKEN_PER_EN_GPIO4_ENABLE BIT15
|
||||
|
||||
#define CM_ICLKEN_PER_EN_GPIO5_DISABLE (0UL << 16)
|
||||
#define CM_ICLKEN_PER_EN_GPIO5_ENABLE BIT16
|
||||
|
||||
#define CM_ICLKEN_PER_EN_GPIO6_DISABLE (0UL << 17)
|
||||
#define CM_ICLKEN_PER_EN_GPIO6_ENABLE BIT17
|
||||
|
||||
//Timer source clock selection
|
||||
#define CM_CLKSEL_PER_CLKSEL_GPT3_32K (0UL << 1)
|
||||
#define CM_CLKSEL_PER_CLKSEL_GPT3_SYS BIT1
|
||||
|
||||
#define CM_CLKSEL_PER_CLKSEL_GPT4_32K (0UL << 2)
|
||||
#define CM_CLKSEL_PER_CLKSEL_GPT4_SYS BIT2
|
||||
|
||||
//Reset management (Global and Cold reset)
|
||||
#define RST_GS BIT1
|
||||
#define RST_DPLL3 BIT2
|
||||
#define GLOBAL_SW_RST BIT1
|
||||
#define GLOBAL_COLD_RST (0x0UL << 0)
|
||||
|
||||
#endif // __OMAP3530PRCM_H__
|
||||
|
||||
|
||||
@@ -1,82 +1,82 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
||||
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __OMAP3530TIMER_H__
|
||||
#define __OMAP3530TIMER_H__
|
||||
|
||||
#define GPTIMER1_BASE (0x48313000)
|
||||
#define GPTIMER2_BASE (0x49032000)
|
||||
#define GPTIMER3_BASE (0x49034000)
|
||||
#define GPTIMER4_BASE (0x49036000)
|
||||
#define GPTIMER5_BASE (0x49038000)
|
||||
#define GPTIMER6_BASE (0x4903A000)
|
||||
#define GPTIMER7_BASE (0x4903C000)
|
||||
#define GPTIMER8_BASE (0x4903E000)
|
||||
#define GPTIMER9_BASE (0x49040000)
|
||||
#define GPTIMER10_BASE (0x48086000)
|
||||
#define GPTIMER11_BASE (0x48088000)
|
||||
#define GPTIMER12_BASE (0x48304000)
|
||||
#define WDTIMER2_BASE (0x48314000)
|
||||
|
||||
#define GPTIMER_TIOCP_CFG (0x0010)
|
||||
#define GPTIMER_TISTAT (0x0014)
|
||||
#define GPTIMER_TISR (0x0018)
|
||||
#define GPTIMER_TIER (0x001C)
|
||||
#define GPTIMER_TWER (0x0020)
|
||||
#define GPTIMER_TCLR (0x0024)
|
||||
#define GPTIMER_TCRR (0x0028)
|
||||
#define GPTIMER_TLDR (0x002C)
|
||||
#define GPTIMER_TTGR (0x0030)
|
||||
#define GPTIMER_TWPS (0x0034)
|
||||
#define GPTIMER_TMAR (0x0038)
|
||||
#define GPTIMER_TCAR1 (0x003C)
|
||||
#define GPTIMER_TSICR (0x0040)
|
||||
#define GPTIMER_TCAR2 (0x0044)
|
||||
#define GPTIMER_TPIR (0x0048)
|
||||
#define GPTIMER_TNIR (0x004C)
|
||||
#define GPTIMER_TCVR (0x0050)
|
||||
#define GPTIMER_TOCR (0x0054)
|
||||
#define GPTIMER_TOWR (0x0058)
|
||||
|
||||
#define WSPR (0x048)
|
||||
|
||||
#define TISR_TCAR_IT_FLAG_MASK BIT2
|
||||
#define TISR_OVF_IT_FLAG_MASK BIT1
|
||||
#define TISR_MAT_IT_FLAG_MASK BIT0
|
||||
#define TISR_ALL_INTERRUPT_MASK (TISR_TCAR_IT_FLAG_MASK | TISR_OVF_IT_FLAG_MASK | TISR_MAT_IT_FLAG_MASK)
|
||||
|
||||
#define TISR_TCAR_IT_FLAG_NOT_PENDING (0UL << 2)
|
||||
#define TISR_OVF_IT_FLAG_NOT_PENDING (0UL << 1)
|
||||
#define TISR_MAT_IT_FLAG_NOT_PENDING (0UL << 0)
|
||||
#define TISR_NO_INTERRUPTS_PENDING (TISR_TCAR_IT_FLAG_NOT_PENDING | TISR_OVF_IT_FLAG_NOT_PENDING | TISR_MAT_IT_FLAG_NOT_PENDING)
|
||||
|
||||
#define TISR_TCAR_IT_FLAG_CLEAR BIT2
|
||||
#define TISR_OVF_IT_FLAG_CLEAR BIT1
|
||||
#define TISR_MAT_IT_FLAG_CLEAR BIT0
|
||||
#define TISR_CLEAR_ALL (TISR_TCAR_IT_FLAG_CLEAR | TISR_OVF_IT_FLAG_CLEAR | TISR_MAT_IT_FLAG_CLEAR)
|
||||
|
||||
#define TCLR_AR_AUTORELOAD BIT1
|
||||
#define TCLR_AR_ONESHOT (0UL << 1)
|
||||
#define TCLR_ST_ON BIT0
|
||||
#define TCLR_ST_OFF (0UL << 0)
|
||||
|
||||
#define TIER_TCAR_IT_ENABLE (BIT2
|
||||
#define TIER_TCAR_IT_DISABLE (0UL << 2)
|
||||
#define TIER_OVF_IT_ENABLE BIT1
|
||||
#define TIER_OVF_IT_DISABLE (0UL << 1)
|
||||
#define TIER_MAT_IT_ENABLE BIT0
|
||||
#define TIER_MAT_IT_DISABLE (0UL << 0)
|
||||
|
||||
#endif // __OMAP3530TIMER_H__
|
||||
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
||||
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __OMAP3530TIMER_H__
|
||||
#define __OMAP3530TIMER_H__
|
||||
|
||||
#define GPTIMER1_BASE (0x48313000)
|
||||
#define GPTIMER2_BASE (0x49032000)
|
||||
#define GPTIMER3_BASE (0x49034000)
|
||||
#define GPTIMER4_BASE (0x49036000)
|
||||
#define GPTIMER5_BASE (0x49038000)
|
||||
#define GPTIMER6_BASE (0x4903A000)
|
||||
#define GPTIMER7_BASE (0x4903C000)
|
||||
#define GPTIMER8_BASE (0x4903E000)
|
||||
#define GPTIMER9_BASE (0x49040000)
|
||||
#define GPTIMER10_BASE (0x48086000)
|
||||
#define GPTIMER11_BASE (0x48088000)
|
||||
#define GPTIMER12_BASE (0x48304000)
|
||||
#define WDTIMER2_BASE (0x48314000)
|
||||
|
||||
#define GPTIMER_TIOCP_CFG (0x0010)
|
||||
#define GPTIMER_TISTAT (0x0014)
|
||||
#define GPTIMER_TISR (0x0018)
|
||||
#define GPTIMER_TIER (0x001C)
|
||||
#define GPTIMER_TWER (0x0020)
|
||||
#define GPTIMER_TCLR (0x0024)
|
||||
#define GPTIMER_TCRR (0x0028)
|
||||
#define GPTIMER_TLDR (0x002C)
|
||||
#define GPTIMER_TTGR (0x0030)
|
||||
#define GPTIMER_TWPS (0x0034)
|
||||
#define GPTIMER_TMAR (0x0038)
|
||||
#define GPTIMER_TCAR1 (0x003C)
|
||||
#define GPTIMER_TSICR (0x0040)
|
||||
#define GPTIMER_TCAR2 (0x0044)
|
||||
#define GPTIMER_TPIR (0x0048)
|
||||
#define GPTIMER_TNIR (0x004C)
|
||||
#define GPTIMER_TCVR (0x0050)
|
||||
#define GPTIMER_TOCR (0x0054)
|
||||
#define GPTIMER_TOWR (0x0058)
|
||||
|
||||
#define WSPR (0x048)
|
||||
|
||||
#define TISR_TCAR_IT_FLAG_MASK BIT2
|
||||
#define TISR_OVF_IT_FLAG_MASK BIT1
|
||||
#define TISR_MAT_IT_FLAG_MASK BIT0
|
||||
#define TISR_ALL_INTERRUPT_MASK (TISR_TCAR_IT_FLAG_MASK | TISR_OVF_IT_FLAG_MASK | TISR_MAT_IT_FLAG_MASK)
|
||||
|
||||
#define TISR_TCAR_IT_FLAG_NOT_PENDING (0UL << 2)
|
||||
#define TISR_OVF_IT_FLAG_NOT_PENDING (0UL << 1)
|
||||
#define TISR_MAT_IT_FLAG_NOT_PENDING (0UL << 0)
|
||||
#define TISR_NO_INTERRUPTS_PENDING (TISR_TCAR_IT_FLAG_NOT_PENDING | TISR_OVF_IT_FLAG_NOT_PENDING | TISR_MAT_IT_FLAG_NOT_PENDING)
|
||||
|
||||
#define TISR_TCAR_IT_FLAG_CLEAR BIT2
|
||||
#define TISR_OVF_IT_FLAG_CLEAR BIT1
|
||||
#define TISR_MAT_IT_FLAG_CLEAR BIT0
|
||||
#define TISR_CLEAR_ALL (TISR_TCAR_IT_FLAG_CLEAR | TISR_OVF_IT_FLAG_CLEAR | TISR_MAT_IT_FLAG_CLEAR)
|
||||
|
||||
#define TCLR_AR_AUTORELOAD BIT1
|
||||
#define TCLR_AR_ONESHOT (0UL << 1)
|
||||
#define TCLR_ST_ON BIT0
|
||||
#define TCLR_ST_OFF (0UL << 0)
|
||||
|
||||
#define TIER_TCAR_IT_ENABLE (BIT2
|
||||
#define TIER_TCAR_IT_DISABLE (0UL << 2)
|
||||
#define TIER_OVF_IT_ENABLE BIT1
|
||||
#define TIER_OVF_IT_DISABLE (0UL << 1)
|
||||
#define TIER_MAT_IT_ENABLE BIT0
|
||||
#define TIER_MAT_IT_DISABLE (0UL << 0)
|
||||
|
||||
#endif // __OMAP3530TIMER_H__
|
||||
|
||||
|
||||
@@ -1,48 +1,48 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
||||
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __OMAP3530USB_H__
|
||||
#define __OMAP3530USB_H__
|
||||
|
||||
#define USB_BASE (0x48060000)
|
||||
|
||||
#define UHH_SYSCONFIG (USB_BASE + 0x4010)
|
||||
#define UHH_HOSTCONFIG (USB_BASE + 0x4040)
|
||||
#define UHH_SYSSTATUS (USB_BASE + 0x4014)
|
||||
|
||||
#define USB_EHCI_HCCAPBASE (USB_BASE + 0x4800)
|
||||
|
||||
#define UHH_SYSCONFIG_MIDLEMODE_NO_STANDBY BIT12
|
||||
#define UHH_SYSCONFIG_CLOCKACTIVITY_ON BIT8
|
||||
#define UHH_SYSCONFIG_SIDLEMODE_NO_STANDBY BIT3
|
||||
#define UHH_SYSCONFIG_ENAWAKEUP_ENABLE BIT2
|
||||
#define UHH_SYSCONFIG_SOFTRESET BIT1
|
||||
#define UHH_SYSCONFIG_AUTOIDLE_ALWAYS_RUN (0UL << 0)
|
||||
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
||||
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __OMAP3530USB_H__
|
||||
#define __OMAP3530USB_H__
|
||||
|
||||
#define USB_BASE (0x48060000)
|
||||
|
||||
#define UHH_SYSCONFIG (USB_BASE + 0x4010)
|
||||
#define UHH_HOSTCONFIG (USB_BASE + 0x4040)
|
||||
#define UHH_SYSSTATUS (USB_BASE + 0x4014)
|
||||
|
||||
#define USB_EHCI_HCCAPBASE (USB_BASE + 0x4800)
|
||||
|
||||
#define UHH_SYSCONFIG_MIDLEMODE_NO_STANDBY BIT12
|
||||
#define UHH_SYSCONFIG_CLOCKACTIVITY_ON BIT8
|
||||
#define UHH_SYSCONFIG_SIDLEMODE_NO_STANDBY BIT3
|
||||
#define UHH_SYSCONFIG_ENAWAKEUP_ENABLE BIT2
|
||||
#define UHH_SYSCONFIG_SOFTRESET BIT1
|
||||
#define UHH_SYSCONFIG_AUTOIDLE_ALWAYS_RUN (0UL << 0)
|
||||
|
||||
#define UHH_HOSTCONFIG_P3_CONNECT_STATUS_DISCONNECT (0UL << 10)
|
||||
#define UHH_HOSTCONFIG_P2_CONNECT_STATUS_DISCONNECT (0UL << 9)
|
||||
#define UHH_HOSTCONFIG_P1_CONNECT_STATUS_DISCONNECT (0UL << 8)
|
||||
#define UHH_HOSTCONFIG_ENA_INCR_ALIGN_DISABLE (0UL << 5)
|
||||
#define UHH_HOSTCONFIG_ENA_INCR16_ENABLE BIT4
|
||||
#define UHH_HOSTCONFIG_ENA_INCR8_ENABLE BIT3
|
||||
#define UHH_HOSTCONFIG_ENA_INCR4_ENABLE BIT2
|
||||
#define UHH_HOSTCONFIG_ENA_INCR16_ENABLE BIT4
|
||||
#define UHH_HOSTCONFIG_ENA_INCR8_ENABLE BIT3
|
||||
#define UHH_HOSTCONFIG_ENA_INCR4_ENABLE BIT2
|
||||
#define UHH_HOSTCONFIG_AUTOPPD_ON_OVERCUR_EN_ON (0UL << 1)
|
||||
#define UHH_HOSTCONFIG_P1_ULPI_BYPASS_ULPI_MODE (0UL << 0)
|
||||
|
||||
#define UHH_SYSSTATUS_RESETDONE (BIT0 | BIT1 | BIT2)
|
||||
|
||||
#endif // __OMAP3530USB_H__
|
||||
|
||||
|
||||
|
||||
#define UHH_HOSTCONFIG_P1_ULPI_BYPASS_ULPI_MODE (0UL << 0)
|
||||
|
||||
#define UHH_SYSSTATUS_RESETDONE (BIT0 | BIT1 | BIT2)
|
||||
|
||||
#endif // __OMAP3530USB_H__
|
||||
|
||||
|
||||
|
||||
|
||||
Reference in New Issue
Block a user