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ARM Packages: Fixed line endings

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This large code change only modifies the line endings to be CRLF to be
compliant with the EDK2 coding convention document.



git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14088 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin
2013-01-25 11:28:06 +00:00
parent 5767f22fca
commit 1e57a46299
280 changed files with 48862 additions and 48862 deletions
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706
ArmPkg/Application/LinuxLoader/LinuxConfig.c
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@ -1,353 +1,353 @@
/** @file
*
* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
* which accompanies this distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#include "LinuxInternal.h"
#define DEFAULT_BOOT_ENTRY_DESCRIPTION L"Linux"
#define MAX_STR_INPUT 300
#define MAX_ASCII_INPUT 300
typedef enum {
LINUX_LOADER_NEW = 1,
LINUX_LOADER_UPDATE
} LINUX_LOADER_ACTION;
STATIC
EFI_STATUS
EditHIInputStr (
IN OUT CHAR16 *CmdLine,
IN UINTN MaxCmdLine
)
{
UINTN CmdLineIndex;
UINTN WaitIndex;
CHAR8 Char;
EFI_INPUT_KEY Key;
EFI_STATUS Status;
Print (CmdLine);
for (CmdLineIndex = StrLen (CmdLine); CmdLineIndex < MaxCmdLine; ) {
Status = gBS->WaitForEvent (1, &gST->ConIn->WaitForKey, &WaitIndex);
ASSERT_EFI_ERROR (Status);
Status = gST->ConIn->ReadKeyStroke (gST->ConIn, &Key);
ASSERT_EFI_ERROR (Status);
// Unicode character is valid when Scancode is NUll
if (Key.ScanCode == SCAN_NULL) {
// Scan code is NUll, hence read Unicode character
Char = (CHAR8)Key.UnicodeChar;
} else {
Char = CHAR_NULL;
}
if ((Char == CHAR_LINEFEED) || (Char == CHAR_CARRIAGE_RETURN) || (Char == 0x7f)) {
CmdLine[CmdLineIndex] = '\0';
Print (L"\n\r");
return EFI_SUCCESS;
} else if ((Key.UnicodeChar == L'\b') || (Key.ScanCode == SCAN_LEFT) || (Key.ScanCode == SCAN_DELETE)){
if (CmdLineIndex != 0) {
CmdLineIndex--;
Print (L"\b \b");
}
} else if ((Key.ScanCode == SCAN_ESC) || (Char == 0x1B) || (Char == 0x0)) {
return EFI_INVALID_PARAMETER;
} else {
CmdLine[CmdLineIndex++] = Key.UnicodeChar;
Print (L"%c", Key.UnicodeChar);
}
}
return EFI_SUCCESS;
}
STATIC
EFI_STATUS
EditHIInputAscii (
IN OUT CHAR8 *CmdLine,
IN UINTN MaxCmdLine
)
{
CHAR16* Str;
EFI_STATUS Status;
Str = (CHAR16*)AllocatePool (MaxCmdLine * sizeof(CHAR16));
AsciiStrToUnicodeStr (CmdLine, Str);
Status = EditHIInputStr (Str, MaxCmdLine);
UnicodeStrToAsciiStr (Str, CmdLine);
FreePool (Str);
return Status;
}
STATIC
EFI_STATUS
GetHIInputInteger (
OUT UINTN *Integer
)
{
CHAR16 CmdLine[255];
EFI_STATUS Status;
CmdLine[0] = '\0';
Status = EditHIInputStr (CmdLine, 255);
if (!EFI_ERROR(Status)) {
*Integer = StrDecimalToUintn (CmdLine);
}
return Status;
}
#if 0
EFI_STATUS
GenerateDeviceDescriptionName (
IN EFI_HANDLE Handle,
IN OUT CHAR16* Description
)
{
EFI_STATUS Status;
EFI_COMPONENT_NAME_PROTOCOL* ComponentName2Protocol;
EFI_DEVICE_PATH_TO_TEXT_PROTOCOL* DevicePathToTextProtocol;
EFI_DEVICE_PATH_PROTOCOL* DevicePathProtocol;
CHAR16* DriverName;
CHAR16* DevicePathTxt;
EFI_DEVICE_PATH* DevicePathNode;
ComponentName2Protocol = NULL;
Status = gBS->HandleProtocol (Handle, &gEfiComponentName2ProtocolGuid, (VOID **)&ComponentName2Protocol);
if (!EFI_ERROR(Status)) {
//TODO: Fixme. we must find the best langague
Status = ComponentName2Protocol->GetDriverName (ComponentName2Protocol,"en",&DriverName);
if (!EFI_ERROR(Status)) {
StrnCpy (Description,DriverName,BOOT_DEVICE_DESCRIPTION_MAX);
}
}
if (EFI_ERROR(Status)) {
// Use the lastest non null entry of the Device path as a description
Status = gBS->HandleProtocol (Handle, &gEfiDevicePathProtocolGuid, (VOID **)&DevicePathProtocol);
if (EFI_ERROR(Status)) {
return Status;
}
// Convert the last non end-type Device Path Node in text for the description
DevicePathNode = GetLastDevicePathNode (DevicePathProtocol);
Status = gBS->LocateProtocol (&gEfiDevicePathToTextProtocolGuid, NULL, (VOID **)&DevicePathToTextProtocol);
ASSERT_EFI_ERROR(Status);
DevicePathTxt = DevicePathToTextProtocol->ConvertDevicePathToText(DevicePathNode,TRUE,TRUE);
StrnCpy (Description, DevicePathTxt, BOOT_DEVICE_DESCRIPTION_MAX);
FreePool (DevicePathTxt);
}
return EFI_SUCCESS;
}
#endif
EFI_STATUS
LinuxLoaderConfig (
IN EFI_LOADED_IMAGE_PROTOCOL *LoadedImage
)
{
EFI_STATUS Status;
LINUX_LOADER_ACTION Choice;
UINTN BootOrderSize;
UINT16* BootOrder;
UINTN BootOrderCount;
UINTN Index;
CHAR16 Description[MAX_ASCII_INPUT];
CHAR8 CmdLine[MAX_ASCII_INPUT];
CHAR16 Initrd[MAX_STR_INPUT];
UINT16 InitrdPathListLength;
UINT16 CmdLineLength;
BDS_LOAD_OPTION* BdsLoadOption;
BDS_LOAD_OPTION** SupportedBdsLoadOptions;
UINTN SupportedBdsLoadOptionCount;
LINUX_LOADER_OPTIONAL_DATA* LinuxOptionalData;
EFI_DEVICE_PATH* DevicePathRoot;
SupportedBdsLoadOptions = NULL;
SupportedBdsLoadOptionCount = 0;
do {
Print (L"[%d] Create new Linux Boot Entry\n",LINUX_LOADER_NEW);
Print (L"[%d] Update Linux Boot Entry\n",LINUX_LOADER_UPDATE);
Print (L"Option: ");
Status = GetHIInputInteger (&Choice);
if (Status == EFI_INVALID_PARAMETER) {
Print (L"\n");
return Status;
} else if ((Choice != LINUX_LOADER_NEW) && (Choice != LINUX_LOADER_UPDATE)) {
Print (L"Error: the option should be either '%d' or '%d'\n",LINUX_LOADER_NEW,LINUX_LOADER_UPDATE);
Status = EFI_INVALID_PARAMETER;
}
} while (EFI_ERROR(Status));
if (Choice == LINUX_LOADER_UPDATE) {
// If no compatible entry then we just create a new entry
Choice = LINUX_LOADER_NEW;
// Scan the OptionalData of every entry for the correct signature
Status = GetEnvironmentVariable (L"BootOrder", NULL, &BootOrderSize, (VOID**)&BootOrder);
if (!EFI_ERROR(Status)) {
BootOrderCount = BootOrderSize / sizeof(UINT16);
// Allocate an array to handle maximum number of supported Boot Entry
SupportedBdsLoadOptions = (BDS_LOAD_OPTION**)AllocatePool(sizeof(BDS_LOAD_OPTION*) * BootOrderCount);
SupportedBdsLoadOptionCount = 0;
// Check if the signature is present in the list of the current Boot entries
for (Index = 0; Index < BootOrderCount; Index++) {
Status = BootOptionFromLoadOptionIndex (BootOrder[Index], &BdsLoadOption);
if (!EFI_ERROR(Status)) {
if ((BdsLoadOption->OptionalDataSize >= sizeof(UINT32)) &&
(*(UINT32*)BdsLoadOption->OptionalData == LINUX_LOADER_SIGNATURE)) {
SupportedBdsLoadOptions[SupportedBdsLoadOptionCount++] = BdsLoadOption;
Choice = LINUX_LOADER_UPDATE;
}
}
}
}
FreePool (BootOrder);
}
if (Choice == LINUX_LOADER_NEW) {
Description[0] = '\0';
CmdLine[0] = '\0';
Initrd[0] = '\0';
BdsLoadOption = (BDS_LOAD_OPTION*)AllocateZeroPool (sizeof(BDS_LOAD_OPTION));
DEBUG_CODE_BEGIN();
CHAR16* DevicePathTxt;
EFI_DEVICE_PATH_TO_TEXT_PROTOCOL* DevicePathToTextProtocol;
Status = gBS->LocateProtocol (&gEfiDevicePathToTextProtocolGuid, NULL, (VOID **)&DevicePathToTextProtocol);
ASSERT_EFI_ERROR(Status);
DevicePathTxt = DevicePathToTextProtocol->ConvertDevicePathToText (LoadedImage->FilePath, TRUE, TRUE);
Print(L"EFI OS Loader: %s\n",DevicePathTxt);
FreePool(DevicePathTxt);
DEBUG_CODE_END();
//
// Fill the known fields of BdsLoadOption
//
BdsLoadOption->Attributes = LOAD_OPTION_ACTIVE | LOAD_OPTION_CATEGORY_BOOT;
// Get the full Device Path for this file
Status = gBS->HandleProtocol (LoadedImage->DeviceHandle, &gEfiDevicePathProtocolGuid, (VOID **)&DevicePathRoot);
ASSERT_EFI_ERROR(Status);
BdsLoadOption->FilePathList = AppendDevicePath (DevicePathRoot, LoadedImage->FilePath);
BdsLoadOption->FilePathListLength = GetDevicePathSize (BdsLoadOption->FilePathList);
} else {
if (SupportedBdsLoadOptionCount > 1) {
for (Index = 0; Index < SupportedBdsLoadOptionCount; Index++) {
Print (L"[%d] %s\n",Index + 1,SupportedBdsLoadOptions[Index]->Description);
}
do {
Print (L"Update Boot Entry: ");
Status = GetHIInputInteger (&Choice);
if (Status == EFI_INVALID_PARAMETER) {
Print (L"\n");
return Status;
} else if ((Choice < 1) && (Choice > SupportedBdsLoadOptionCount)) {
Print (L"Choose entry from 1 to %d\n",SupportedBdsLoadOptionCount);
Status = EFI_INVALID_PARAMETER;
}
} while (EFI_ERROR(Status));
BdsLoadOption = SupportedBdsLoadOptions[Choice-1];
}
StrnCpy (Description, BdsLoadOption->Description, MAX_STR_INPUT);
LinuxOptionalData = (LINUX_LOADER_OPTIONAL_DATA*)BdsLoadOption->OptionalData;
if (LinuxOptionalData->CmdLineLength > 0) {
CopyMem (CmdLine, (CHAR8*)LinuxOptionalData + sizeof(LINUX_LOADER_OPTIONAL_DATA), LinuxOptionalData->CmdLineLength);
} else {
CmdLine[0] = '\0';
}
if (LinuxOptionalData->InitrdPathListLength > 0) {
CopyMem (Initrd, (CHAR8*)LinuxOptionalData + sizeof(LINUX_LOADER_OPTIONAL_DATA) + LinuxOptionalData->CmdLineLength, LinuxOptionalData->InitrdPathListLength);
} else {
Initrd[0] = L'\0';
}
DEBUG((EFI_D_ERROR,"L\n"));
}
// Description
Print (L"Description: ");
Status = EditHIInputStr (Description, MAX_STR_INPUT);
if (EFI_ERROR(Status)) {
return Status;
}
if (StrLen (Description) == 0) {
StrnCpy (Description, DEFAULT_BOOT_ENTRY_DESCRIPTION, MAX_STR_INPUT);
}
BdsLoadOption->Description = Description;
// CmdLine
Print (L"Command Line: ");
Status = EditHIInputAscii (CmdLine, MAX_ASCII_INPUT);
if (EFI_ERROR(Status)) {
return Status;
}
// Initrd
Print (L"Initrd name: ");
Status = EditHIInputStr (Initrd, MAX_STR_INPUT);
if (EFI_ERROR(Status)) {
return Status;
}
CmdLineLength = AsciiStrLen (CmdLine);
if (CmdLineLength > 0) {
CmdLineLength += sizeof(CHAR8);
}
InitrdPathListLength = StrLen (Initrd) * sizeof(CHAR16);
if (InitrdPathListLength > 0) {
InitrdPathListLength += sizeof(CHAR16);
}
BdsLoadOption->OptionalDataSize = sizeof(LINUX_LOADER_OPTIONAL_DATA) + CmdLineLength + InitrdPathListLength;
LinuxOptionalData = (LINUX_LOADER_OPTIONAL_DATA*)AllocatePool (BdsLoadOption->OptionalDataSize);
BdsLoadOption->OptionalData = LinuxOptionalData;
LinuxOptionalData->Signature = LINUX_LOADER_SIGNATURE;
LinuxOptionalData->CmdLineLength = CmdLineLength;
LinuxOptionalData->InitrdPathListLength = InitrdPathListLength;
if (CmdLineLength > 0) {
CopyMem (LinuxOptionalData + 1, CmdLine, CmdLineLength);
}
if (InitrdPathListLength > 0) {
CopyMem ((UINT8*)(LinuxOptionalData + 1) + CmdLineLength, Initrd, InitrdPathListLength);
}
// Create or Update the boot entry
Status = BootOptionToLoadOptionVariable (BdsLoadOption);
return Status;
}
/** @file
*
* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
* which accompanies this distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#include "LinuxInternal.h"
#define DEFAULT_BOOT_ENTRY_DESCRIPTION L"Linux"
#define MAX_STR_INPUT 300
#define MAX_ASCII_INPUT 300
typedef enum {
LINUX_LOADER_NEW = 1,
LINUX_LOADER_UPDATE
} LINUX_LOADER_ACTION;
STATIC
EFI_STATUS
EditHIInputStr (
IN OUT CHAR16 *CmdLine,
IN UINTN MaxCmdLine
)
{
UINTN CmdLineIndex;
UINTN WaitIndex;
CHAR8 Char;
EFI_INPUT_KEY Key;
EFI_STATUS Status;
Print (CmdLine);
for (CmdLineIndex = StrLen (CmdLine); CmdLineIndex < MaxCmdLine; ) {
Status = gBS->WaitForEvent (1, &gST->ConIn->WaitForKey, &WaitIndex);
ASSERT_EFI_ERROR (Status);
Status = gST->ConIn->ReadKeyStroke (gST->ConIn, &Key);
ASSERT_EFI_ERROR (Status);
// Unicode character is valid when Scancode is NUll
if (Key.ScanCode == SCAN_NULL) {
// Scan code is NUll, hence read Unicode character
Char = (CHAR8)Key.UnicodeChar;
} else {
Char = CHAR_NULL;
}
if ((Char == CHAR_LINEFEED) || (Char == CHAR_CARRIAGE_RETURN) || (Char == 0x7f)) {
CmdLine[CmdLineIndex] = '\0';
Print (L"\n\r");
return EFI_SUCCESS;
} else if ((Key.UnicodeChar == L'\b') || (Key.ScanCode == SCAN_LEFT) || (Key.ScanCode == SCAN_DELETE)){
if (CmdLineIndex != 0) {
CmdLineIndex--;
Print (L"\b \b");
}
} else if ((Key.ScanCode == SCAN_ESC) || (Char == 0x1B) || (Char == 0x0)) {
return EFI_INVALID_PARAMETER;
} else {
CmdLine[CmdLineIndex++] = Key.UnicodeChar;
Print (L"%c", Key.UnicodeChar);
}
}
return EFI_SUCCESS;
}
STATIC
EFI_STATUS
EditHIInputAscii (
IN OUT CHAR8 *CmdLine,
IN UINTN MaxCmdLine
)
{
CHAR16* Str;
EFI_STATUS Status;
Str = (CHAR16*)AllocatePool (MaxCmdLine * sizeof(CHAR16));
AsciiStrToUnicodeStr (CmdLine, Str);
Status = EditHIInputStr (Str, MaxCmdLine);
UnicodeStrToAsciiStr (Str, CmdLine);
FreePool (Str);
return Status;
}
STATIC
EFI_STATUS
GetHIInputInteger (
OUT UINTN *Integer
)
{
CHAR16 CmdLine[255];
EFI_STATUS Status;
CmdLine[0] = '\0';
Status = EditHIInputStr (CmdLine, 255);
if (!EFI_ERROR(Status)) {
*Integer = StrDecimalToUintn (CmdLine);
}
return Status;
}
#if 0
EFI_STATUS
GenerateDeviceDescriptionName (
IN EFI_HANDLE Handle,
IN OUT CHAR16* Description
)
{
EFI_STATUS Status;
EFI_COMPONENT_NAME_PROTOCOL* ComponentName2Protocol;
EFI_DEVICE_PATH_TO_TEXT_PROTOCOL* DevicePathToTextProtocol;
EFI_DEVICE_PATH_PROTOCOL* DevicePathProtocol;
CHAR16* DriverName;
CHAR16* DevicePathTxt;
EFI_DEVICE_PATH* DevicePathNode;
ComponentName2Protocol = NULL;
Status = gBS->HandleProtocol (Handle, &gEfiComponentName2ProtocolGuid, (VOID **)&ComponentName2Protocol);
if (!EFI_ERROR(Status)) {
//TODO: Fixme. we must find the best langague
Status = ComponentName2Protocol->GetDriverName (ComponentName2Protocol,"en",&DriverName);
if (!EFI_ERROR(Status)) {
StrnCpy (Description,DriverName,BOOT_DEVICE_DESCRIPTION_MAX);
}
}
if (EFI_ERROR(Status)) {
// Use the lastest non null entry of the Device path as a description
Status = gBS->HandleProtocol (Handle, &gEfiDevicePathProtocolGuid, (VOID **)&DevicePathProtocol);
if (EFI_ERROR(Status)) {
return Status;
}
// Convert the last non end-type Device Path Node in text for the description
DevicePathNode = GetLastDevicePathNode (DevicePathProtocol);
Status = gBS->LocateProtocol (&gEfiDevicePathToTextProtocolGuid, NULL, (VOID **)&DevicePathToTextProtocol);
ASSERT_EFI_ERROR(Status);
DevicePathTxt = DevicePathToTextProtocol->ConvertDevicePathToText(DevicePathNode,TRUE,TRUE);
StrnCpy (Description, DevicePathTxt, BOOT_DEVICE_DESCRIPTION_MAX);
FreePool (DevicePathTxt);
}
return EFI_SUCCESS;
}
#endif
EFI_STATUS
LinuxLoaderConfig (
IN EFI_LOADED_IMAGE_PROTOCOL *LoadedImage
)
{
EFI_STATUS Status;
LINUX_LOADER_ACTION Choice;
UINTN BootOrderSize;
UINT16* BootOrder;
UINTN BootOrderCount;
UINTN Index;
CHAR16 Description[MAX_ASCII_INPUT];
CHAR8 CmdLine[MAX_ASCII_INPUT];
CHAR16 Initrd[MAX_STR_INPUT];
UINT16 InitrdPathListLength;
UINT16 CmdLineLength;
BDS_LOAD_OPTION* BdsLoadOption;
BDS_LOAD_OPTION** SupportedBdsLoadOptions;
UINTN SupportedBdsLoadOptionCount;
LINUX_LOADER_OPTIONAL_DATA* LinuxOptionalData;
EFI_DEVICE_PATH* DevicePathRoot;
SupportedBdsLoadOptions = NULL;
SupportedBdsLoadOptionCount = 0;
do {
Print (L"[%d] Create new Linux Boot Entry\n",LINUX_LOADER_NEW);
Print (L"[%d] Update Linux Boot Entry\n",LINUX_LOADER_UPDATE);
Print (L"Option: ");
Status = GetHIInputInteger (&Choice);
if (Status == EFI_INVALID_PARAMETER) {
Print (L"\n");
return Status;
} else if ((Choice != LINUX_LOADER_NEW) && (Choice != LINUX_LOADER_UPDATE)) {
Print (L"Error: the option should be either '%d' or '%d'\n",LINUX_LOADER_NEW,LINUX_LOADER_UPDATE);
Status = EFI_INVALID_PARAMETER;
}
} while (EFI_ERROR(Status));
if (Choice == LINUX_LOADER_UPDATE) {
// If no compatible entry then we just create a new entry
Choice = LINUX_LOADER_NEW;
// Scan the OptionalData of every entry for the correct signature
Status = GetEnvironmentVariable (L"BootOrder", NULL, &BootOrderSize, (VOID**)&BootOrder);
if (!EFI_ERROR(Status)) {
BootOrderCount = BootOrderSize / sizeof(UINT16);
// Allocate an array to handle maximum number of supported Boot Entry
SupportedBdsLoadOptions = (BDS_LOAD_OPTION**)AllocatePool(sizeof(BDS_LOAD_OPTION*) * BootOrderCount);
SupportedBdsLoadOptionCount = 0;
// Check if the signature is present in the list of the current Boot entries
for (Index = 0; Index < BootOrderCount; Index++) {
Status = BootOptionFromLoadOptionIndex (BootOrder[Index], &BdsLoadOption);
if (!EFI_ERROR(Status)) {
if ((BdsLoadOption->OptionalDataSize >= sizeof(UINT32)) &&
(*(UINT32*)BdsLoadOption->OptionalData == LINUX_LOADER_SIGNATURE)) {
SupportedBdsLoadOptions[SupportedBdsLoadOptionCount++] = BdsLoadOption;
Choice = LINUX_LOADER_UPDATE;
}
}
}
}
FreePool (BootOrder);
}
if (Choice == LINUX_LOADER_NEW) {
Description[0] = '\0';
CmdLine[0] = '\0';
Initrd[0] = '\0';
BdsLoadOption = (BDS_LOAD_OPTION*)AllocateZeroPool (sizeof(BDS_LOAD_OPTION));
DEBUG_CODE_BEGIN();
CHAR16* DevicePathTxt;
EFI_DEVICE_PATH_TO_TEXT_PROTOCOL* DevicePathToTextProtocol;
Status = gBS->LocateProtocol (&gEfiDevicePathToTextProtocolGuid, NULL, (VOID **)&DevicePathToTextProtocol);
ASSERT_EFI_ERROR(Status);
DevicePathTxt = DevicePathToTextProtocol->ConvertDevicePathToText (LoadedImage->FilePath, TRUE, TRUE);
Print(L"EFI OS Loader: %s\n",DevicePathTxt);
FreePool(DevicePathTxt);
DEBUG_CODE_END();
//
// Fill the known fields of BdsLoadOption
//
BdsLoadOption->Attributes = LOAD_OPTION_ACTIVE | LOAD_OPTION_CATEGORY_BOOT;
// Get the full Device Path for this file
Status = gBS->HandleProtocol (LoadedImage->DeviceHandle, &gEfiDevicePathProtocolGuid, (VOID **)&DevicePathRoot);
ASSERT_EFI_ERROR(Status);
BdsLoadOption->FilePathList = AppendDevicePath (DevicePathRoot, LoadedImage->FilePath);
BdsLoadOption->FilePathListLength = GetDevicePathSize (BdsLoadOption->FilePathList);
} else {
if (SupportedBdsLoadOptionCount > 1) {
for (Index = 0; Index < SupportedBdsLoadOptionCount; Index++) {
Print (L"[%d] %s\n",Index + 1,SupportedBdsLoadOptions[Index]->Description);
}
do {
Print (L"Update Boot Entry: ");
Status = GetHIInputInteger (&Choice);
if (Status == EFI_INVALID_PARAMETER) {
Print (L"\n");
return Status;
} else if ((Choice < 1) && (Choice > SupportedBdsLoadOptionCount)) {
Print (L"Choose entry from 1 to %d\n",SupportedBdsLoadOptionCount);
Status = EFI_INVALID_PARAMETER;
}
} while (EFI_ERROR(Status));
BdsLoadOption = SupportedBdsLoadOptions[Choice-1];
}
StrnCpy (Description, BdsLoadOption->Description, MAX_STR_INPUT);
LinuxOptionalData = (LINUX_LOADER_OPTIONAL_DATA*)BdsLoadOption->OptionalData;
if (LinuxOptionalData->CmdLineLength > 0) {
CopyMem (CmdLine, (CHAR8*)LinuxOptionalData + sizeof(LINUX_LOADER_OPTIONAL_DATA), LinuxOptionalData->CmdLineLength);
} else {
CmdLine[0] = '\0';
}
if (LinuxOptionalData->InitrdPathListLength > 0) {
CopyMem (Initrd, (CHAR8*)LinuxOptionalData + sizeof(LINUX_LOADER_OPTIONAL_DATA) + LinuxOptionalData->CmdLineLength, LinuxOptionalData->InitrdPathListLength);
} else {
Initrd[0] = L'\0';
}
DEBUG((EFI_D_ERROR,"L\n"));
}
// Description
Print (L"Description: ");
Status = EditHIInputStr (Description, MAX_STR_INPUT);
if (EFI_ERROR(Status)) {
return Status;
}
if (StrLen (Description) == 0) {
StrnCpy (Description, DEFAULT_BOOT_ENTRY_DESCRIPTION, MAX_STR_INPUT);
}
BdsLoadOption->Description = Description;
// CmdLine
Print (L"Command Line: ");
Status = EditHIInputAscii (CmdLine, MAX_ASCII_INPUT);
if (EFI_ERROR(Status)) {
return Status;
}
// Initrd
Print (L"Initrd name: ");
Status = EditHIInputStr (Initrd, MAX_STR_INPUT);
if (EFI_ERROR(Status)) {
return Status;
}
CmdLineLength = AsciiStrLen (CmdLine);
if (CmdLineLength > 0) {
CmdLineLength += sizeof(CHAR8);
}
InitrdPathListLength = StrLen (Initrd) * sizeof(CHAR16);
if (InitrdPathListLength > 0) {
InitrdPathListLength += sizeof(CHAR16);
}
BdsLoadOption->OptionalDataSize = sizeof(LINUX_LOADER_OPTIONAL_DATA) + CmdLineLength + InitrdPathListLength;
LinuxOptionalData = (LINUX_LOADER_OPTIONAL_DATA*)AllocatePool (BdsLoadOption->OptionalDataSize);
BdsLoadOption->OptionalData = LinuxOptionalData;
LinuxOptionalData->Signature = LINUX_LOADER_SIGNATURE;
LinuxOptionalData->CmdLineLength = CmdLineLength;
LinuxOptionalData->InitrdPathListLength = InitrdPathListLength;
if (CmdLineLength > 0) {
CopyMem (LinuxOptionalData + 1, CmdLine, CmdLineLength);
}
if (InitrdPathListLength > 0) {
CopyMem ((UINT8*)(LinuxOptionalData + 1) + CmdLineLength, Initrd, InitrdPathListLength);
}
// Create or Update the boot entry
Status = BootOptionToLoadOptionVariable (BdsLoadOption);
return Status;
}

98
ArmPkg/Application/LinuxLoader/LinuxInternal.h
View File

@ -1,49 +1,49 @@
/** @file
*
* Copyright (c) 2011, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
* which accompanies this distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#ifndef __LOADER_INTERNAL_H
#define __LOADER_INTERNAL_H
#include <Uefi.h>
#include <Library/BaseMemoryLib.h>
#include <Library/BdsLib.h>
#include <Library/DebugLib.h>
#include <Library/DevicePathLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiLib.h>
#include <Protocol/LoadedImage.h>
#define LINUX_KERNEL_NAME L"zImage"
#define FDT_NAME L"platform.dtb"
#define LINUX_LOADER_SIGNATURE SIGNATURE_32('l', 'i', 'l', 'o')
typedef struct {
UINT32 Signature;
UINT16 CmdLineLength;
UINT16 InitrdPathListLength;
// These following fields have variable length:
//CHAR8* CmdLine;
//CHAR16* Initrd;
} LINUX_LOADER_OPTIONAL_DATA;
EFI_STATUS
LinuxLoaderConfig (
IN EFI_LOADED_IMAGE_PROTOCOL *LoadedImage
);
#endif
/** @file
*
* Copyright (c) 2011, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
* which accompanies this distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#ifndef __LOADER_INTERNAL_H
#define __LOADER_INTERNAL_H
#include <Uefi.h>
#include <Library/BaseMemoryLib.h>
#include <Library/BdsLib.h>
#include <Library/DebugLib.h>
#include <Library/DevicePathLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiLib.h>
#include <Protocol/LoadedImage.h>
#define LINUX_KERNEL_NAME L"zImage"
#define FDT_NAME L"platform.dtb"
#define LINUX_LOADER_SIGNATURE SIGNATURE_32('l', 'i', 'l', 'o')
typedef struct {
UINT32 Signature;
UINT16 CmdLineLength;
UINT16 InitrdPathListLength;
// These following fields have variable length:
//CHAR8* CmdLine;
//CHAR16* Initrd;
} LINUX_LOADER_OPTIONAL_DATA;
EFI_STATUS
LinuxLoaderConfig (
IN EFI_LOADED_IMAGE_PROTOCOL *LoadedImage
);
#endif

262
ArmPkg/ArmPkg.dsc
View File

@ -1,131 +1,131 @@
#/** @file
# ARM processor package.
#
# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#**/
################################################################################
#
# Defines Section - statements that will be processed to create a Makefile.
#
################################################################################
[Defines]
PLATFORM_NAME = ArmPkg
PLATFORM_GUID = 5CFBD99E-3C43-4E7F-8054-9CDEAFF7710F
PLATFORM_VERSION = 0.1
DSC_SPECIFICATION = 0x00010005
OUTPUT_DIRECTORY = Build/Arm
SUPPORTED_ARCHITECTURES = ARM
BUILD_TARGETS = DEBUG|RELEASE
SKUID_IDENTIFIER = DEFAULT
[BuildOptions]
XCODE:*_*_ARM_PLATFORM_FLAGS == -arch armv7
XCODE:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
GCC:*_*_ARM_PLATFORM_FLAGS == -march=armv7-a -mfpu=neon
GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu Cortex-A8
RVCT:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
[LibraryClasses.common]
BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
TimerLib|MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplate.inf
UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
SemihostLib|ArmPkg/Library/SemihostLib/SemihostLib.inf
UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf
ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf
CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf
DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf
ArmTrustZoneLib|ArmPkg/Library/ArmTrustZoneLib/ArmTrustZoneLib.inf
UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
# TODO: Check if we cannot remove this dependancy (Mayve using the SerialLibNull implementation makes the EFI application do not print)
SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf
BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf
FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
[LibraryClasses.common.PEIM]
HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
[LibraryClasses.common.DXE_DRIVER]
ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/Dxe/DxeArmPlatformGlobalVariableLib.inf
[LibraryClasses.ARM]
NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
[Components.common]
ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf
ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf
# ArmPkg/Library/ArmLib/Arm11/Arm11ArmLib.inf
# ArmPkg/Library/ArmLib/Arm11/Arm11ArmLibPrePi.inf
# ArmPkg/Library/ArmLib/Arm9/Arm9ArmLib.inf
# ArmPkg/Library/ArmLib/Arm9/Arm9ArmLibPrePi.inf
ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf
ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf
ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf
ArmPkg/Library/ArmLib/Null/NullArmLib.inf
ArmPkg/Library/BaseMemoryLibStm/BaseMemoryLibStm.inf
ArmPkg/Library/BaseMemoryLibVstm/BaseMemoryLibVstm.inf
ArmPkg/Library/BasePeCoffLib/BasePeCoffLib.inf
ArmPkg/Library/BdsLib/BdsLib.inf
ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf
ArmPkg/Library/DebugUncachedMemoryAllocationLib/DebugUncachedMemoryAllocationLib.inf
ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf
ArmPkg/Library/RvdPeCoffExtraActionLib/RvdPeCoffExtraActionLib.inf
ArmPkg/Library/SemiHostingDebugLib/SemiHostingDebugLib.inf
ArmPkg/Library/SemiHostingSerialPortLib/SemiHostingSerialPortLib.inf
ArmPkg/Library/SemihostLib/SemihostLib.inf
ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
ArmPkg/Drivers/ArmCpuLib/ArmCortexA8Lib/ArmCortexA8Lib.inf
ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.inf
ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Lib.inf
ArmPkg/Drivers/CpuDxe/CpuDxe.inf
ArmPkg/Drivers/CpuPei/CpuPei.inf
ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf
ArmPkg/Drivers/PL390Gic/PL390GicLib.inf
ArmPkg/Drivers/PL390Gic/PL390GicSecLib.inf
ArmPkg/Drivers/TimerDxe/TimerDxe.inf
ArmPkg/Filesystem/SemihostFs/SemihostFs.inf
ArmPkg/Application/LinuxLoader/LinuxAtagLoader.inf
ArmPkg/Application/LinuxLoader/LinuxFdtLoader.inf
#/** @file
# ARM processor package.
#
# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#**/
################################################################################
#
# Defines Section - statements that will be processed to create a Makefile.
#
################################################################################
[Defines]
PLATFORM_NAME = ArmPkg
PLATFORM_GUID = 5CFBD99E-3C43-4E7F-8054-9CDEAFF7710F
PLATFORM_VERSION = 0.1
DSC_SPECIFICATION = 0x00010005
OUTPUT_DIRECTORY = Build/Arm
SUPPORTED_ARCHITECTURES = ARM
BUILD_TARGETS = DEBUG|RELEASE
SKUID_IDENTIFIER = DEFAULT
[BuildOptions]
XCODE:*_*_ARM_PLATFORM_FLAGS == -arch armv7
XCODE:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
GCC:*_*_ARM_PLATFORM_FLAGS == -march=armv7-a -mfpu=neon
GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu Cortex-A8
RVCT:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
[LibraryClasses.common]
BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
TimerLib|MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplate.inf
UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
SemihostLib|ArmPkg/Library/SemihostLib/SemihostLib.inf
UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf
ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf
CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf
DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf
ArmTrustZoneLib|ArmPkg/Library/ArmTrustZoneLib/ArmTrustZoneLib.inf
UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
# TODO: Check if we cannot remove this dependancy (Mayve using the SerialLibNull implementation makes the EFI application do not print)
SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf
BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf
FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
[LibraryClasses.common.PEIM]
HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
[LibraryClasses.common.DXE_DRIVER]
ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/Dxe/DxeArmPlatformGlobalVariableLib.inf
[LibraryClasses.ARM]
NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
[Components.common]
ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf
ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf
# ArmPkg/Library/ArmLib/Arm11/Arm11ArmLib.inf
# ArmPkg/Library/ArmLib/Arm11/Arm11ArmLibPrePi.inf
# ArmPkg/Library/ArmLib/Arm9/Arm9ArmLib.inf
# ArmPkg/Library/ArmLib/Arm9/Arm9ArmLibPrePi.inf
ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf
ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf
ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf
ArmPkg/Library/ArmLib/Null/NullArmLib.inf
ArmPkg/Library/BaseMemoryLibStm/BaseMemoryLibStm.inf
ArmPkg/Library/BaseMemoryLibVstm/BaseMemoryLibVstm.inf
ArmPkg/Library/BasePeCoffLib/BasePeCoffLib.inf
ArmPkg/Library/BdsLib/BdsLib.inf
ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf
ArmPkg/Library/DebugUncachedMemoryAllocationLib/DebugUncachedMemoryAllocationLib.inf
ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf
ArmPkg/Library/RvdPeCoffExtraActionLib/RvdPeCoffExtraActionLib.inf
ArmPkg/Library/SemiHostingDebugLib/SemiHostingDebugLib.inf
ArmPkg/Library/SemiHostingSerialPortLib/SemiHostingSerialPortLib.inf
ArmPkg/Library/SemihostLib/SemihostLib.inf
ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
ArmPkg/Drivers/ArmCpuLib/ArmCortexA8Lib/ArmCortexA8Lib.inf
ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.inf
ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Lib.inf
ArmPkg/Drivers/CpuDxe/CpuDxe.inf
ArmPkg/Drivers/CpuPei/CpuPei.inf
ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf
ArmPkg/Drivers/PL390Gic/PL390GicLib.inf
ArmPkg/Drivers/PL390Gic/PL390GicSecLib.inf
ArmPkg/Drivers/TimerDxe/TimerDxe.inf
ArmPkg/Filesystem/SemihostFs/SemihostFs.inf
ArmPkg/Application/LinuxLoader/LinuxAtagLoader.inf
ArmPkg/Application/LinuxLoader/LinuxFdtLoader.inf

382
ArmPkg/Drivers/CpuDxe/ArmV4/ExceptionSupport.S
View File

@ -1,191 +1,191 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
.text
.align 3
GCC_ASM_EXPORT(ExceptionHandlersStart)
GCC_ASM_EXPORT(ExceptionHandlersEnd)
GCC_ASM_EXPORT(CommonExceptionEntry)
GCC_ASM_EXPORT(AsmCommonExceptionEntry)
GCC_ASM_EXPORT(CommonCExceptionHandler)
ASM_PFX(ExceptionHandlersStart):
ASM_PFX(Reset):
b ASM_PFX(ResetEntry)
ASM_PFX(UndefinedInstruction):
b ASM_PFX(UndefinedInstructionEntry)
ASM_PFX(SoftwareInterrupt):
b ASM_PFX(SoftwareInterruptEntry)
ASM_PFX(PrefetchAbort):
b ASM_PFX(PrefetchAbortEntry)
ASM_PFX(DataAbort):
b ASM_PFX(DataAbortEntry)
ASM_PFX(ReservedException):
b ASM_PFX(ReservedExceptionEntry)
ASM_PFX(Irq):
b ASM_PFX(IrqEntry)
ASM_PFX(Fiq):
b ASM_PFX(FiqEntry)
ASM_PFX(ResetEntry):
srsdb #0x13! @ Store return state on SVC stack
stmfd SP!,{LR} @ Store the link register for the current mode
sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
stmfd SP!,{R0-R12} @ Store the register state
mov R0,#0
ldr R1,ASM_PFX(CommonExceptionEntry)
bx R1
ASM_PFX(UndefinedInstructionEntry):
srsdb #0x13! @ Store return state on SVC stack
cps #0x13 @ Switch to SVC for common stack
stmfd SP!,{LR} @ Store the link register for the current mode
sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
stmfd SP!,{R0-R12} @ Store the register state
mov r0,#1
ldr r1,ASM_PFX(CommonExceptionEntry)
bx r1
ASM_PFX(SoftwareInterruptEntry):
srsdb #0x13! @ Store return state on SVC stack
stmfd SP!,{LR} @ Store the link register for the current mode
sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
stmfd SP!,{R0-R12} @ Store the register state
mov r0,#2
ldr r1,ASM_PFX(CommonExceptionEntry)
bx r1
ASM_PFX(PrefetchAbortEntry):
sub LR,LR,#4
srsdb #0x13! @ Store return state on SVC stack
cps #0x13 @ Switch to SVC for common stack
stmfd SP!,{LR} @ Store the link register for the current mode
sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
stmfd SP!,{R0-R12} @ Store the register state
mov r0,#3
ldr r1,ASM_PFX(CommonExceptionEntry)
bx r1
ASM_PFX(DataAbortEntry):
sub LR,LR,#8
srsdb #0x13! @ Store return state on SVC stack
cps #0x13 @ Switch to SVC for common stack
stmfd SP!,{LR} @ Store the link register for the current mode
sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
stmfd SP!,{R0-R12} @ Store the register state
mov r0,#4
ldr r1,ASM_PFX(CommonExceptionEntry)
bx r1
ASM_PFX(ReservedExceptionEntry):
srsdb #0x13! @ Store return state on SVC stack
cps #0x13 @ Switch to SVC for common stack
stmfd SP!,{LR} @ Store the link register for the current mode
sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
stmfd SP!,{R0-R12} @ Store the register state
mov r0,#5
ldr r1,ASM_PFX(CommonExceptionEntry)
bx r1
ASM_PFX(IrqEntry):
sub LR,LR,#4
srsdb #0x13! @ Store return state on SVC stack
cps #0x13 @ Switch to SVC for common stack
stmfd SP!,{LR} @ Store the link register for the current mode
sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
stmfd SP!,{R0-R12} @ Store the register state
mov r0,#6
ldr r1,ASM_PFX(CommonExceptionEntry)
bx r1
ASM_PFX(FiqEntry):
sub LR,LR,#4
srsdb #0x13! @ Store return state on SVC stack
cps #0x13 @ Switch to SVC for common stack
stmfd SP!,{LR} @ Store the link register for the current mode
sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
stmfd SP!,{R0-R12} @ Store the register state
mov r0,#7
ldr r1,ASM_PFX(CommonExceptionEntry)
bx r1
ASM_PFX(CommonExceptionEntry):
.byte 0x12
.byte 0x34
.byte 0x56
.byte 0x78
ASM_PFX(ExceptionHandlersEnd):
ASM_PFX(AsmCommonExceptionEntry):
mrc p15, 0, R1, c6, c0, 2 @ Read IFAR
str R1, [SP, #0x50] @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFAR
mrc p15, 0, R1, c5, c0, 1 @ Read IFSR
str R1, [SP, #0x4c] @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFSR
mrc p15, 0, R1, c6, c0, 0 @ Read DFAR
str R1, [SP, #0x48] @ Store it in EFI_SYSTEM_CONTEXT_ARM.DFAR
mrc p15, 0, R1, c5, c0, 0 @ Read DFSR
str R1, [SP, #0x44] @ Store it in EFI_SYSTEM_CONTEXT_ARM.DFSR
ldr R1, [SP, #0x5c] @ srsdb saved pre-exception CPSR on the stack
str R1, [SP, #0x40] @ Store it in EFI_SYSTEM_CONTEXT_ARM.CPSR
and r1, r1, #0x1f @ Check to see if User or System Mode
cmp r1, #0x1f
cmpne r1, #0x10
add R2, SP, #0x38 @ Store it in EFI_SYSTEM_CONTEXT_ARM.LR
ldmneed r2, {lr}^ @ User or System mode, use unbanked register
ldmneed r2, {lr} @ All other modes used banked register
ldr R1, [SP, #0x58] @ PC is the LR pushed by srsdb
str R1, [SP, #0x3c] @ Store it in EFI_SYSTEM_CONTEXT_ARM.PC
sub R1, SP, #0x60 @ We pused 0x60 bytes on the stack
str R1, [SP, #0x34] @ Store it in EFI_SYSTEM_CONTEXT_ARM.SP
@ R0 is exception type
mov R1,SP @ Prepare System Context pointer as an argument for the exception handler
blx ASM_PFX(CommonCExceptionHandler) @ Call exception handler
ldr R2,[SP,#0x40] @ EFI_SYSTEM_CONTEXT_ARM.CPSR
str R2,[SP,#0x5c] @ Store it back to srsdb stack slot so it can be restored
ldr R2,[SP,#0x3c] @ EFI_SYSTEM_CONTEXT_ARM.PC
str R2,[SP,#0x58] @ Store it back to srsdb stack slot so it can be restored
ldmfd SP!,{R0-R12} @ Restore general purpose registers
@ Exception handler can not change SP or LR as we would blow chunks
add SP,SP,#0x20 @ Clear out the remaining stack space
ldmfd SP!,{LR} @ restore the link register for this context
rfefd SP! @ return from exception via srsdb stack slot
#------------------------------------------------------------------------------
#
# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
.text
.align 3
GCC_ASM_EXPORT(ExceptionHandlersStart)
GCC_ASM_EXPORT(ExceptionHandlersEnd)
GCC_ASM_EXPORT(CommonExceptionEntry)
GCC_ASM_EXPORT(AsmCommonExceptionEntry)
GCC_ASM_EXPORT(CommonCExceptionHandler)
ASM_PFX(ExceptionHandlersStart):
ASM_PFX(Reset):
b ASM_PFX(ResetEntry)
ASM_PFX(UndefinedInstruction):
b ASM_PFX(UndefinedInstructionEntry)
ASM_PFX(SoftwareInterrupt):
b ASM_PFX(SoftwareInterruptEntry)
ASM_PFX(PrefetchAbort):
b ASM_PFX(PrefetchAbortEntry)
ASM_PFX(DataAbort):
b ASM_PFX(DataAbortEntry)
ASM_PFX(ReservedException):
b ASM_PFX(ReservedExceptionEntry)
ASM_PFX(Irq):
b ASM_PFX(IrqEntry)
ASM_PFX(Fiq):
b ASM_PFX(FiqEntry)
ASM_PFX(ResetEntry):
srsdb #0x13! @ Store return state on SVC stack
stmfd SP!,{LR} @ Store the link register for the current mode
sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
stmfd SP!,{R0-R12} @ Store the register state
mov R0,#0
ldr R1,ASM_PFX(CommonExceptionEntry)
bx R1
ASM_PFX(UndefinedInstructionEntry):
srsdb #0x13! @ Store return state on SVC stack
cps #0x13 @ Switch to SVC for common stack
stmfd SP!,{LR} @ Store the link register for the current mode
sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
stmfd SP!,{R0-R12} @ Store the register state
mov r0,#1
ldr r1,ASM_PFX(CommonExceptionEntry)
bx r1
ASM_PFX(SoftwareInterruptEntry):
srsdb #0x13! @ Store return state on SVC stack
stmfd SP!,{LR} @ Store the link register for the current mode
sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
stmfd SP!,{R0-R12} @ Store the register state
mov r0,#2
ldr r1,ASM_PFX(CommonExceptionEntry)
bx r1
ASM_PFX(PrefetchAbortEntry):
sub LR,LR,#4
srsdb #0x13! @ Store return state on SVC stack
cps #0x13 @ Switch to SVC for common stack
stmfd SP!,{LR} @ Store the link register for the current mode
sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
stmfd SP!,{R0-R12} @ Store the register state
mov r0,#3
ldr r1,ASM_PFX(CommonExceptionEntry)
bx r1
ASM_PFX(DataAbortEntry):
sub LR,LR,#8
srsdb #0x13! @ Store return state on SVC stack
cps #0x13 @ Switch to SVC for common stack
stmfd SP!,{LR} @ Store the link register for the current mode
sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
stmfd SP!,{R0-R12} @ Store the register state
mov r0,#4
ldr r1,ASM_PFX(CommonExceptionEntry)
bx r1
ASM_PFX(ReservedExceptionEntry):
srsdb #0x13! @ Store return state on SVC stack
cps #0x13 @ Switch to SVC for common stack
stmfd SP!,{LR} @ Store the link register for the current mode
sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
stmfd SP!,{R0-R12} @ Store the register state
mov r0,#5
ldr r1,ASM_PFX(CommonExceptionEntry)
bx r1
ASM_PFX(IrqEntry):
sub LR,LR,#4
srsdb #0x13! @ Store return state on SVC stack
cps #0x13 @ Switch to SVC for common stack
stmfd SP!,{LR} @ Store the link register for the current mode
sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
stmfd SP!,{R0-R12} @ Store the register state
mov r0,#6
ldr r1,ASM_PFX(CommonExceptionEntry)
bx r1
ASM_PFX(FiqEntry):
sub LR,LR,#4
srsdb #0x13! @ Store return state on SVC stack
cps #0x13 @ Switch to SVC for common stack
stmfd SP!,{LR} @ Store the link register for the current mode
sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
stmfd SP!,{R0-R12} @ Store the register state
mov r0,#7
ldr r1,ASM_PFX(CommonExceptionEntry)
bx r1
ASM_PFX(CommonExceptionEntry):
.byte 0x12
.byte 0x34
.byte 0x56
.byte 0x78
ASM_PFX(ExceptionHandlersEnd):
ASM_PFX(AsmCommonExceptionEntry):
mrc p15, 0, R1, c6, c0, 2 @ Read IFAR
str R1, [SP, #0x50] @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFAR
mrc p15, 0, R1, c5, c0, 1 @ Read IFSR
str R1, [SP, #0x4c] @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFSR
mrc p15, 0, R1, c6, c0, 0 @ Read DFAR
str R1, [SP, #0x48] @ Store it in EFI_SYSTEM_CONTEXT_ARM.DFAR
mrc p15, 0, R1, c5, c0, 0 @ Read DFSR
str R1, [SP, #0x44] @ Store it in EFI_SYSTEM_CONTEXT_ARM.DFSR
ldr R1, [SP, #0x5c] @ srsdb saved pre-exception CPSR on the stack
str R1, [SP, #0x40] @ Store it in EFI_SYSTEM_CONTEXT_ARM.CPSR
and r1, r1, #0x1f @ Check to see if User or System Mode
cmp r1, #0x1f
cmpne r1, #0x10
add R2, SP, #0x38 @ Store it in EFI_SYSTEM_CONTEXT_ARM.LR
ldmneed r2, {lr}^ @ User or System mode, use unbanked register
ldmneed r2, {lr} @ All other modes used banked register
ldr R1, [SP, #0x58] @ PC is the LR pushed by srsdb
str R1, [SP, #0x3c] @ Store it in EFI_SYSTEM_CONTEXT_ARM.PC
sub R1, SP, #0x60 @ We pused 0x60 bytes on the stack
str R1, [SP, #0x34] @ Store it in EFI_SYSTEM_CONTEXT_ARM.SP
@ R0 is exception type
mov R1,SP @ Prepare System Context pointer as an argument for the exception handler
blx ASM_PFX(CommonCExceptionHandler) @ Call exception handler
ldr R2,[SP,#0x40] @ EFI_SYSTEM_CONTEXT_ARM.CPSR
str R2,[SP,#0x5c] @ Store it back to srsdb stack slot so it can be restored
ldr R2,[SP,#0x3c] @ EFI_SYSTEM_CONTEXT_ARM.PC
str R2,[SP,#0x58] @ Store it back to srsdb stack slot so it can be restored
ldmfd SP!,{R0-R12} @ Restore general purpose registers
@ Exception handler can not change SP or LR as we would blow chunks
add SP,SP,#0x20 @ Clear out the remaining stack space
ldmfd SP!,{LR} @ restore the link register for this context
rfefd SP! @ return from exception via srsdb stack slot

304
ArmPkg/Drivers/CpuDxe/ArmV4/ExceptionSupport.asm
View File

@ -1,152 +1,152 @@
//------------------------------------------------------------------------------
//
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
//------------------------------------------------------------------------------
EXPORT ExceptionHandlersStart
EXPORT ExceptionHandlersEnd
EXPORT CommonExceptionEntry
EXPORT AsmCommonExceptionEntry
IMPORT CommonCExceptionHandler
PRESERVE8
AREA DxeExceptionHandlers, CODE, READONLY
ExceptionHandlersStart
Reset
b ResetEntry
UndefinedInstruction
b UndefinedInstructionEntry
SoftwareInterrupt
b SoftwareInterruptEntry
PrefetchAbort
b PrefetchAbortEntry
DataAbort
b DataAbortEntry
ReservedException
b ReservedExceptionEntry
Irq
b IrqEntry
Fiq
b FiqEntry
ResetEntry
stmfd SP!,{R0-R1}
mov R0,#0
ldr R1,CommonExceptionEntry
bx R1
UndefinedInstructionEntry
stmfd SP!,{R0-R1}
mov R0,#1
ldr R1,CommonExceptionEntry
bx R1
SoftwareInterruptEntry
stmfd SP!,{R0-R1}
mov R0,#2
ldr R1,CommonExceptionEntry
bx R1
PrefetchAbortEntry
stmfd SP!,{R0-R1}
mov R0,#3
SUB LR,LR,#4
ldr R1,CommonExceptionEntry
bx R1
DataAbortEntry
stmfd SP!,{R0-R1}
mov R0,#4
SUB LR,LR,#8
ldr R1,CommonExceptionEntry
bx R1
ReservedExceptionEntry
stmfd SP!,{R0-R1}
mov R0,#5
ldr R1,CommonExceptionEntry
bx R1
IrqEntry
stmfd SP!,{R0-R1}
mov R0,#6
SUB LR,LR,#4
ldr R1,CommonExceptionEntry
bx R1
FiqEntry
stmfd SP!,{R0-R1}
mov R0,#7
SUB LR,LR,#4
ldr R1,CommonExceptionEntry
bx R1
CommonExceptionEntry
dcd 0x12345678
ExceptionHandlersEnd
AsmCommonExceptionEntry
mrc p15, 0, r1, c6, c0, 2 ; Read IFAR
stmfd SP!,{R1} ; Store the IFAR
mrc p15, 0, r1, c5, c0, 1 ; Read IFSR
stmfd SP!,{R1} ; Store the IFSR
mrc p15, 0, r1, c6, c0, 0 ; Read DFAR
stmfd SP!,{R1} ; Store the DFAR
mrc p15, 0, r1, c5, c0, 0 ; Read DFSR
stmfd SP!,{R1} ; Store the DFSR
mrs R1,SPSR ; Read SPSR (which is the pre-exception CPSR)
stmfd SP!,{R1} ; Store the SPSR
stmfd SP!,{LR} ; Store the link register (which is the pre-exception PC)
stmfd SP,{SP,LR}^ ; Store user/system mode stack pointer and link register
nop ; Required by ARM architecture
SUB SP,SP,#0x08 ; Adjust stack pointer
stmfd SP!,{R2-R12} ; Store general purpose registers
ldr R3,[SP,#0x50] ; Read saved R1 from the stack (it was saved by the exception entry routine)
ldr R2,[SP,#0x4C] ; Read saved R0 from the stack (it was saved by the exception entry routine)
stmfd SP!,{R2-R3} ; Store general purpose registers R0 and R1
mov R1,SP ; Prepare System Context pointer as an argument for the exception handler
sub SP,SP,#4 ; Adjust SP to preserve 8-byte alignment
blx CommonCExceptionHandler ; Call exception handler
add SP,SP,#4 ; Adjust SP back to where we were
ldr R2,[SP,#0x40] ; Load CPSR from context, in case it has changed
MSR SPSR_cxsf,R2 ; Store it back to the SPSR to be restored when exiting this handler
ldmfd SP!,{R0-R12} ; Restore general purpose registers
ldm SP,{SP,LR}^ ; Restore user/system mode stack pointer and link register
nop ; Required by ARM architecture
add SP,SP,#0x08 ; Adjust stack pointer
ldmfd SP!,{LR} ; Restore the link register (which is the pre-exception PC)
add SP,SP,#0x1C ; Clear out the remaining stack space
movs PC,LR ; Return from exception
END
//------------------------------------------------------------------------------
//
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
//------------------------------------------------------------------------------
EXPORT ExceptionHandlersStart
EXPORT ExceptionHandlersEnd
EXPORT CommonExceptionEntry
EXPORT AsmCommonExceptionEntry
IMPORT CommonCExceptionHandler
PRESERVE8
AREA DxeExceptionHandlers, CODE, READONLY
ExceptionHandlersStart
Reset
b ResetEntry
UndefinedInstruction
b UndefinedInstructionEntry
SoftwareInterrupt
b SoftwareInterruptEntry
PrefetchAbort
b PrefetchAbortEntry
DataAbort
b DataAbortEntry
ReservedException
b ReservedExceptionEntry
Irq
b IrqEntry
Fiq
b FiqEntry
ResetEntry
stmfd SP!,{R0-R1}
mov R0,#0
ldr R1,CommonExceptionEntry
bx R1
UndefinedInstructionEntry
stmfd SP!,{R0-R1}
mov R0,#1
ldr R1,CommonExceptionEntry
bx R1
SoftwareInterruptEntry
stmfd SP!,{R0-R1}
mov R0,#2
ldr R1,CommonExceptionEntry
bx R1
PrefetchAbortEntry
stmfd SP!,{R0-R1}
mov R0,#3
SUB LR,LR,#4
ldr R1,CommonExceptionEntry
bx R1
DataAbortEntry
stmfd SP!,{R0-R1}
mov R0,#4
SUB LR,LR,#8
ldr R1,CommonExceptionEntry
bx R1
ReservedExceptionEntry
stmfd SP!,{R0-R1}
mov R0,#5
ldr R1,CommonExceptionEntry
bx R1
IrqEntry
stmfd SP!,{R0-R1}
mov R0,#6
SUB LR,LR,#4
ldr R1,CommonExceptionEntry
bx R1
FiqEntry
stmfd SP!,{R0-R1}
mov R0,#7
SUB LR,LR,#4
ldr R1,CommonExceptionEntry
bx R1
CommonExceptionEntry
dcd 0x12345678
ExceptionHandlersEnd
AsmCommonExceptionEntry
mrc p15, 0, r1, c6, c0, 2 ; Read IFAR
stmfd SP!,{R1} ; Store the IFAR
mrc p15, 0, r1, c5, c0, 1 ; Read IFSR
stmfd SP!,{R1} ; Store the IFSR
mrc p15, 0, r1, c6, c0, 0 ; Read DFAR
stmfd SP!,{R1} ; Store the DFAR
mrc p15, 0, r1, c5, c0, 0 ; Read DFSR
stmfd SP!,{R1} ; Store the DFSR
mrs R1,SPSR ; Read SPSR (which is the pre-exception CPSR)
stmfd SP!,{R1} ; Store the SPSR
stmfd SP!,{LR} ; Store the link register (which is the pre-exception PC)
stmfd SP,{SP,LR}^ ; Store user/system mode stack pointer and link register
nop ; Required by ARM architecture
SUB SP,SP,#0x08 ; Adjust stack pointer
stmfd SP!,{R2-R12} ; Store general purpose registers
ldr R3,[SP,#0x50] ; Read saved R1 from the stack (it was saved by the exception entry routine)
ldr R2,[SP,#0x4C] ; Read saved R0 from the stack (it was saved by the exception entry routine)
stmfd SP!,{R2-R3} ; Store general purpose registers R0 and R1
mov R1,SP ; Prepare System Context pointer as an argument for the exception handler
sub SP,SP,#4 ; Adjust SP to preserve 8-byte alignment
blx CommonCExceptionHandler ; Call exception handler
add SP,SP,#4 ; Adjust SP back to where we were
ldr R2,[SP,#0x40] ; Load CPSR from context, in case it has changed
MSR SPSR_cxsf,R2 ; Store it back to the SPSR to be restored when exiting this handler
ldmfd SP!,{R0-R12} ; Restore general purpose registers
ldm SP,{SP,LR}^ ; Restore user/system mode stack pointer and link register
nop ; Required by ARM architecture
add SP,SP,#0x08 ; Adjust stack pointer
ldmfd SP!,{LR} ; Restore the link register (which is the pre-exception PC)
add SP,SP,#0x1C ; Clear out the remaining stack space
movs PC,LR ; Return from exception
END

594
ArmPkg/Drivers/CpuDxe/ArmV6/ExceptionSupport.S
View File

@ -1,297 +1,297 @@
#------------------------------------------------------------------------------
#
# Use ARMv6 instruction to operate on a single stack
#
# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
#include <Library/PcdLib.h>
/*
This is the stack constructed by the exception handler (low address to high address)
# R0 - IFAR is EFI_SYSTEM_CONTEXT for ARM
Reg Offset
=== ======
R0 0x00 # stmfd SP!,{R0-R12}
R1 0x04
R2 0x08
R3 0x0c
R4 0x10
R5 0x14
R6 0x18
R7 0x1c
R8 0x20
R9 0x24
R10 0x28
R11 0x2c
R12 0x30
SP 0x34 # reserved via adding 0x20 (32) to the SP
LR 0x38
PC 0x3c
CPSR 0x40
DFSR 0x44
DFAR 0x48
IFSR 0x4c
IFAR 0x50
LR 0x54 # SVC Link register (we need to restore it)
LR 0x58 # pushed by srsfd
CPSR 0x5c
*/
GCC_ASM_EXPORT(ExceptionHandlersStart)
GCC_ASM_EXPORT(ExceptionHandlersEnd)
GCC_ASM_EXPORT(CommonExceptionEntry)
GCC_ASM_EXPORT(AsmCommonExceptionEntry)
GCC_ASM_EXPORT(CommonCExceptionHandler)
.text
#if !defined(__APPLE__)
.fpu neon @ makes vpush/vpop assemble
#endif
.align 5
//
// This code gets copied to the ARM vector table
// ExceptionHandlersStart - ExceptionHandlersEnd gets copied
//
ASM_PFX(ExceptionHandlersStart):
ASM_PFX(Reset):
b ASM_PFX(ResetEntry)
ASM_PFX(UndefinedInstruction):
b ASM_PFX(UndefinedInstructionEntry)
ASM_PFX(SoftwareInterrupt):
b ASM_PFX(SoftwareInterruptEntry)
ASM_PFX(PrefetchAbort):
b ASM_PFX(PrefetchAbortEntry)
ASM_PFX(DataAbort):
b ASM_PFX(DataAbortEntry)
ASM_PFX(ReservedException):
b ASM_PFX(ReservedExceptionEntry)
ASM_PFX(Irq):
b ASM_PFX(IrqEntry)
ASM_PFX(Fiq):
b ASM_PFX(FiqEntry)
ASM_PFX(ResetEntry):
srsdb #0x13! @ Store return state on SVC stack
@ We are already in SVC mode
stmfd SP!,{LR} @ Store the link register for the current mode
sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
stmfd SP!,{R0-R12} @ Store the register state
mov R0,#0 @ ExceptionType
ldr R1,ASM_PFX(CommonExceptionEntry)
bx R1
ASM_PFX(UndefinedInstructionEntry):
sub LR, LR, #4 @ Only -2 for Thumb, adjust in CommonExceptionEntry
srsdb #0x13! @ Store return state on SVC stack
cps #0x13 @ Switch to SVC for common stack
stmfd SP!,{LR} @ Store the link register for the current mode
sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
stmfd SP!,{R0-R12} @ Store the register state
mov R0,#1 @ ExceptionType
ldr R1,ASM_PFX(CommonExceptionEntry)
bx R1
ASM_PFX(SoftwareInterruptEntry):
sub LR, LR, #4 @ Only -2 for Thumb, adjust in CommonExceptionEntry
srsdb #0x13! @ Store return state on SVC stack
@ We are already in SVC mode
stmfd SP!,{LR} @ Store the link register for the current mode
sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
stmfd SP!,{R0-R12} @ Store the register state
mov R0,#2 @ ExceptionType
ldr R1,ASM_PFX(CommonExceptionEntry)
bx R1
ASM_PFX(PrefetchAbortEntry):
sub LR,LR,#4
srsdb #0x13! @ Store return state on SVC stack
cps #0x13 @ Switch to SVC for common stack
stmfd SP!,{LR} @ Store the link register for the current mode
sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
stmfd SP!,{R0-R12} @ Store the register state
mov R0,#3 @ ExceptionType
ldr R1,ASM_PFX(CommonExceptionEntry)
bx R1
ASM_PFX(DataAbortEntry):
sub LR,LR,#8
srsdb #0x13! @ Store return state on SVC stack
cps #0x13 @ Switch to SVC for common stack
stmfd SP!,{LR} @ Store the link register for the current mode
sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
stmfd SP!,{R0-R12} @ Store the register state
mov R0,#4
ldr R1,ASM_PFX(CommonExceptionEntry)
bx R1
ASM_PFX(ReservedExceptionEntry):
srsdb #0x13! @ Store return state on SVC stack
cps #0x13 @ Switch to SVC for common stack
stmfd SP!,{LR} @ Store the link register for the current mode
sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
stmfd SP!,{R0-R12} @ Store the register state
mov R0,#5
ldr R1,ASM_PFX(CommonExceptionEntry)
bx R1
ASM_PFX(IrqEntry):
sub LR,LR,#4
srsdb #0x13! @ Store return state on SVC stack
cps #0x13 @ Switch to SVC for common stack
stmfd SP!,{LR} @ Store the link register for the current mode
sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
stmfd SP!,{R0-R12} @ Store the register state
mov R0,#6 @ ExceptionType
ldr R1,ASM_PFX(CommonExceptionEntry)
bx R1
ASM_PFX(FiqEntry):
sub LR,LR,#4
srsdb #0x13! @ Store return state on SVC stack
cps #0x13 @ Switch to SVC for common stack
stmfd SP!,{LR} @ Store the link register for the current mode
sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
stmfd SP!,{R0-R12} @ Store the register state
@ Since we have already switch to SVC R8_fiq - R12_fiq
@ never get used or saved
mov R0,#7 @ ExceptionType
ldr R1,ASM_PFX(CommonExceptionEntry)
bx R1
//
// This gets patched by the C code that patches in the vector table
//
ASM_PFX(CommonExceptionEntry):
.word ASM_PFX(AsmCommonExceptionEntry)
ASM_PFX(ExceptionHandlersEnd):
//
// This code runs from CpuDxe driver loaded address. It is patched into
// CommonExceptionEntry.
//
ASM_PFX(AsmCommonExceptionEntry):
mrc p15, 0, R1, c6, c0, 2 @ Read IFAR
str R1, [SP, #0x50] @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFAR
mrc p15, 0, R1, c5, c0, 1 @ Read IFSR
str R1, [SP, #0x4c] @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFSR
mrc p15, 0, R1, c6, c0, 0 @ Read DFAR
str R1, [SP, #0x48] @ Store it in EFI_SYSTEM_CONTEXT_ARM.DFAR
mrc p15, 0, R1, c5, c0, 0 @ Read DFSR
str R1, [SP, #0x44] @ Store it in EFI_SYSTEM_CONTEXT_ARM.DFSR
ldr R1, [SP, #0x5c] @ srsdb saved pre-exception CPSR on the stack
str R1, [SP, #0x40] @ Store it in EFI_SYSTEM_CONTEXT_ARM.CPSR
add R2, SP, #0x38 @ Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR
and R3, R1, #0x1f @ Check CPSR to see if User or System Mode
cmp R3, #0x1f @ if ((CPSR == 0x10) || (CPSR == 0x1df))
cmpne R3, #0x10 @
stmeqed R2, {lr}^ @ save unbanked lr
@ else
stmneed R2, {lr} @ save SVC lr
ldr R5, [SP, #0x58] @ PC is the LR pushed by srsfd
@ Check to see if we have to adjust for Thumb entry
sub r4, r0, #1 @ if (ExceptionType == 1 || ExceptionType ==2)) {
cmp r4, #1 @ // UND & SVC have differnt LR adjust for Thumb
bhi NoAdjustNeeded
tst r1, #0x20 @ if ((CPSR & T)) == T) { // Thumb Mode on entry
addne R5, R5, #2 @ PC += 2@
str R5,[SP,#0x58] @ Update LR value pused by srsfd
NoAdjustNeeded:
str R5, [SP, #0x3c] @ Store it in EFI_SYSTEM_CONTEXT_ARM.PC
sub R1, SP, #0x60 @ We pused 0x60 bytes on the stack
str R1, [SP, #0x34] @ Store it in EFI_SYSTEM_CONTEXT_ARM.SP
@ R0 is ExceptionType
mov R1,SP @ R1 is SystemContext
#if (FixedPcdGet32(PcdVFPEnabled))
vpush {d0-d15} @ save vstm registers in case they are used in optimizations
#endif
/*
VOID
EFIAPI
CommonCExceptionHandler (
IN EFI_EXCEPTION_TYPE ExceptionType, R0
IN OUT EFI_SYSTEM_CONTEXT SystemContext R1
)
*/
blx ASM_PFX(CommonCExceptionHandler) @ Call exception handler
#if (FixedPcdGet32(PcdVFPEnabled))
vpop {d0-d15}
#endif
ldr R1, [SP, #0x4c] @ Restore EFI_SYSTEM_CONTEXT_ARM.IFSR
mcr p15, 0, R1, c5, c0, 1 @ Write IFSR
ldr R1, [SP, #0x44] @ sRestore EFI_SYSTEM_CONTEXT_ARM.DFSR
mcr p15, 0, R1, c5, c0, 0 @ Write DFSR
ldr R1,[SP,#0x3c] @ EFI_SYSTEM_CONTEXT_ARM.PC
str R1,[SP,#0x58] @ Store it back to srsfd stack slot so it can be restored
ldr R1,[SP,#0x40] @ EFI_SYSTEM_CONTEXT_ARM.CPSR
str R1,[SP,#0x5c] @ Store it back to srsfd stack slot so it can be restored
add R3, SP, #0x54 @ Make R3 point to SVC LR saved on entry
add R2, SP, #0x38 @ Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR
and R1, R1, #0x1f @ Check to see if User or System Mode
cmp R1, #0x1f @ if ((CPSR == 0x10) || (CPSR == 0x1f))
cmpne R1, #0x10 @
ldmeqed R2, {lr}^ @ restore unbanked lr
@ else
ldmneed R3, {lr} @ restore SVC lr, via ldmfd SP!, {LR}
ldmfd SP!,{R0-R12} @ Restore general purpose registers
@ Exception handler can not change SP
add SP,SP,#0x20 @ Clear out the remaining stack space
ldmfd SP!,{LR} @ restore the link register for this context
rfefd SP! @ return from exception via srsfd stack slot
#------------------------------------------------------------------------------
#
# Use ARMv6 instruction to operate on a single stack
#
# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
#include <Library/PcdLib.h>
/*
This is the stack constructed by the exception handler (low address to high address)
# R0 - IFAR is EFI_SYSTEM_CONTEXT for ARM
Reg Offset
=== ======
R0 0x00 # stmfd SP!,{R0-R12}
R1 0x04
R2 0x08
R3 0x0c
R4 0x10
R5 0x14
R6 0x18
R7 0x1c
R8 0x20
R9 0x24
R10 0x28
R11 0x2c
R12 0x30
SP 0x34 # reserved via adding 0x20 (32) to the SP
LR 0x38
PC 0x3c
CPSR 0x40
DFSR 0x44
DFAR 0x48
IFSR 0x4c
IFAR 0x50
LR 0x54 # SVC Link register (we need to restore it)
LR 0x58 # pushed by srsfd
CPSR 0x5c
*/
GCC_ASM_EXPORT(ExceptionHandlersStart)
GCC_ASM_EXPORT(ExceptionHandlersEnd)
GCC_ASM_EXPORT(CommonExceptionEntry)
GCC_ASM_EXPORT(AsmCommonExceptionEntry)
GCC_ASM_EXPORT(CommonCExceptionHandler)
.text
#if !defined(__APPLE__)
.fpu neon @ makes vpush/vpop assemble
#endif
.align 5
//
// This code gets copied to the ARM vector table
// ExceptionHandlersStart - ExceptionHandlersEnd gets copied
//
ASM_PFX(ExceptionHandlersStart):
ASM_PFX(Reset):
b ASM_PFX(ResetEntry)
ASM_PFX(UndefinedInstruction):
b ASM_PFX(UndefinedInstructionEntry)
ASM_PFX(SoftwareInterrupt):
b ASM_PFX(SoftwareInterruptEntry)
ASM_PFX(PrefetchAbort):
b ASM_PFX(PrefetchAbortEntry)
ASM_PFX(DataAbort):
b ASM_PFX(DataAbortEntry)
ASM_PFX(ReservedException):
b ASM_PFX(ReservedExceptionEntry)
ASM_PFX(Irq):
b ASM_PFX(IrqEntry)
ASM_PFX(Fiq):
b ASM_PFX(FiqEntry)
ASM_PFX(ResetEntry):
srsdb #0x13! @ Store return state on SVC stack
@ We are already in SVC mode
stmfd SP!,{LR} @ Store the link register for the current mode
sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
stmfd SP!,{R0-R12} @ Store the register state
mov R0,#0 @ ExceptionType
ldr R1,ASM_PFX(CommonExceptionEntry)
bx R1
ASM_PFX(UndefinedInstructionEntry):
sub LR, LR, #4 @ Only -2 for Thumb, adjust in CommonExceptionEntry
srsdb #0x13! @ Store return state on SVC stack
cps #0x13 @ Switch to SVC for common stack
stmfd SP!,{LR} @ Store the link register for the current mode
sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
stmfd SP!,{R0-R12} @ Store the register state
mov R0,#1 @ ExceptionType
ldr R1,ASM_PFX(CommonExceptionEntry)
bx R1
ASM_PFX(SoftwareInterruptEntry):
sub LR, LR, #4 @ Only -2 for Thumb, adjust in CommonExceptionEntry
srsdb #0x13! @ Store return state on SVC stack
@ We are already in SVC mode
stmfd SP!,{LR} @ Store the link register for the current mode
sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
stmfd SP!,{R0-R12} @ Store the register state
mov R0,#2 @ ExceptionType
ldr R1,ASM_PFX(CommonExceptionEntry)
bx R1
ASM_PFX(PrefetchAbortEntry):
sub LR,LR,#4
srsdb #0x13! @ Store return state on SVC stack
cps #0x13 @ Switch to SVC for common stack
stmfd SP!,{LR} @ Store the link register for the current mode
sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
stmfd SP!,{R0-R12} @ Store the register state
mov R0,#3 @ ExceptionType
ldr R1,ASM_PFX(CommonExceptionEntry)
bx R1
ASM_PFX(DataAbortEntry):
sub LR,LR,#8
srsdb #0x13! @ Store return state on SVC stack
cps #0x13 @ Switch to SVC for common stack
stmfd SP!,{LR} @ Store the link register for the current mode
sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
stmfd SP!,{R0-R12} @ Store the register state
mov R0,#4
ldr R1,ASM_PFX(CommonExceptionEntry)
bx R1
ASM_PFX(ReservedExceptionEntry):
srsdb #0x13! @ Store return state on SVC stack
cps #0x13 @ Switch to SVC for common stack
stmfd SP!,{LR} @ Store the link register for the current mode
sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
stmfd SP!,{R0-R12} @ Store the register state
mov R0,#5
ldr R1,ASM_PFX(CommonExceptionEntry)
bx R1
ASM_PFX(IrqEntry):
sub LR,LR,#4
srsdb #0x13! @ Store return state on SVC stack
cps #0x13 @ Switch to SVC for common stack
stmfd SP!,{LR} @ Store the link register for the current mode
sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
stmfd SP!,{R0-R12} @ Store the register state
mov R0,#6 @ ExceptionType
ldr R1,ASM_PFX(CommonExceptionEntry)
bx R1
ASM_PFX(FiqEntry):
sub LR,LR,#4
srsdb #0x13! @ Store return state on SVC stack
cps #0x13 @ Switch to SVC for common stack
stmfd SP!,{LR} @ Store the link register for the current mode
sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
stmfd SP!,{R0-R12} @ Store the register state
@ Since we have already switch to SVC R8_fiq - R12_fiq
@ never get used or saved
mov R0,#7 @ ExceptionType
ldr R1,ASM_PFX(CommonExceptionEntry)
bx R1
//
// This gets patched by the C code that patches in the vector table
//
ASM_PFX(CommonExceptionEntry):
.word ASM_PFX(AsmCommonExceptionEntry)
ASM_PFX(ExceptionHandlersEnd):
//
// This code runs from CpuDxe driver loaded address. It is patched into
// CommonExceptionEntry.
//
ASM_PFX(AsmCommonExceptionEntry):
mrc p15, 0, R1, c6, c0, 2 @ Read IFAR
str R1, [SP, #0x50] @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFAR
mrc p15, 0, R1, c5, c0, 1 @ Read IFSR
str R1, [SP, #0x4c] @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFSR
mrc p15, 0, R1, c6, c0, 0 @ Read DFAR
str R1, [SP, #0x48] @ Store it in EFI_SYSTEM_CONTEXT_ARM.DFAR
mrc p15, 0, R1, c5, c0, 0 @ Read DFSR
str R1, [SP, #0x44] @ Store it in EFI_SYSTEM_CONTEXT_ARM.DFSR
ldr R1, [SP, #0x5c] @ srsdb saved pre-exception CPSR on the stack
str R1, [SP, #0x40] @ Store it in EFI_SYSTEM_CONTEXT_ARM.CPSR
add R2, SP, #0x38 @ Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR
and R3, R1, #0x1f @ Check CPSR to see if User or System Mode
cmp R3, #0x1f @ if ((CPSR == 0x10) || (CPSR == 0x1df))
cmpne R3, #0x10 @
stmeqed R2, {lr}^ @ save unbanked lr
@ else
stmneed R2, {lr} @ save SVC lr
ldr R5, [SP, #0x58] @ PC is the LR pushed by srsfd
@ Check to see if we have to adjust for Thumb entry
sub r4, r0, #1 @ if (ExceptionType == 1 || ExceptionType ==2)) {
cmp r4, #1 @ // UND & SVC have differnt LR adjust for Thumb
bhi NoAdjustNeeded
tst r1, #0x20 @ if ((CPSR & T)) == T) { // Thumb Mode on entry
addne R5, R5, #2 @ PC += 2@
str R5,[SP,#0x58] @ Update LR value pused by srsfd
NoAdjustNeeded:
str R5, [SP, #0x3c] @ Store it in EFI_SYSTEM_CONTEXT_ARM.PC
sub R1, SP, #0x60 @ We pused 0x60 bytes on the stack
str R1, [SP, #0x34] @ Store it in EFI_SYSTEM_CONTEXT_ARM.SP
@ R0 is ExceptionType
mov R1,SP @ R1 is SystemContext
#if (FixedPcdGet32(PcdVFPEnabled))
vpush {d0-d15} @ save vstm registers in case they are used in optimizations
#endif
/*
VOID
EFIAPI
CommonCExceptionHandler (
IN EFI_EXCEPTION_TYPE ExceptionType, R0
IN OUT EFI_SYSTEM_CONTEXT SystemContext R1
)
*/
blx ASM_PFX(CommonCExceptionHandler) @ Call exception handler
#if (FixedPcdGet32(PcdVFPEnabled))
vpop {d0-d15}
#endif
ldr R1, [SP, #0x4c] @ Restore EFI_SYSTEM_CONTEXT_ARM.IFSR
mcr p15, 0, R1, c5, c0, 1 @ Write IFSR
ldr R1, [SP, #0x44] @ sRestore EFI_SYSTEM_CONTEXT_ARM.DFSR
mcr p15, 0, R1, c5, c0, 0 @ Write DFSR
ldr R1,[SP,#0x3c] @ EFI_SYSTEM_CONTEXT_ARM.PC
str R1,[SP,#0x58] @ Store it back to srsfd stack slot so it can be restored
ldr R1,[SP,#0x40] @ EFI_SYSTEM_CONTEXT_ARM.CPSR
str R1,[SP,#0x5c] @ Store it back to srsfd stack slot so it can be restored
add R3, SP, #0x54 @ Make R3 point to SVC LR saved on entry
add R2, SP, #0x38 @ Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR
and R1, R1, #0x1f @ Check to see if User or System Mode
cmp R1, #0x1f @ if ((CPSR == 0x10) || (CPSR == 0x1f))
cmpne R1, #0x10 @
ldmeqed R2, {lr}^ @ restore unbanked lr
@ else
ldmneed R3, {lr} @ restore SVC lr, via ldmfd SP!, {LR}
ldmfd SP!,{R0-R12} @ Restore general purpose registers
@ Exception handler can not change SP
add SP,SP,#0x20 @ Clear out the remaining stack space
ldmfd SP!,{LR} @ restore the link register for this context
rfefd SP! @ return from exception via srsfd stack slot

2
ArmPkg/Drivers/CpuPei/CpuPei.inf
View File

@ -53,7 +53,7 @@
gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize
gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize
[FeaturePcd]
[FeaturePcd]
gEmbeddedTokenSpaceGuid.PcdCacheEnable
[depex]

850
ArmPkg/Drivers/PL390Gic/PL390GicDxe.c
View File

@ -1,425 +1,425 @@
/*++
Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.<BR>
Portions copyright (c) 2010, Apple Inc. All rights reserved.<BR>
Portions copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
Gic.c
Abstract:
Driver implementing the GIC interrupt controller protocol
--*/
#include <PiDxe.h>
#include <Library/BaseLib.h>
#include <Library/DebugLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiLib.h>
#include <Library/PcdLib.h>
#include <Library/IoLib.h>
#include <Library/ArmGicLib.h>
#include <Protocol/Cpu.h>
#include <Protocol/HardwareInterrupt.h>
#define ARM_GIC_DEFAULT_PRIORITY 0x80
extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptProtocol;
//
// Notifications
//
EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL;
// Maximum Number of Interrupts
UINTN mGicNumInterrupts = 0;
HARDWARE_INTERRUPT_HANDLER *gRegisteredInterruptHandlers = NULL;
/**
Register Handler for the specified interrupt source.
@param This Instance pointer for this protocol
@param Source Hardware source of the interrupt
@param Handler Callback for interrupt. NULL to unregister
@retval EFI_SUCCESS Source was updated to support Handler.
@retval EFI_DEVICE_ERROR Hardware could not be programmed.
**/
EFI_STATUS
EFIAPI
RegisterInterruptSource (
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source,
IN HARDWARE_INTERRUPT_HANDLER Handler
)
{
if (Source > mGicNumInterrupts) {
ASSERT(FALSE);
return EFI_UNSUPPORTED;
}
if ((Handler == NULL) && (gRegisteredInterruptHandlers[Source] == NULL)) {
return EFI_INVALID_PARAMETER;
}
if ((Handler != NULL) && (gRegisteredInterruptHandlers[Source] != NULL)) {
return EFI_ALREADY_STARTED;
}
gRegisteredInterruptHandlers[Source] = Handler;
// If the interrupt handler is unregistered then disable the interrupt
if (NULL == Handler){
return This->DisableInterruptSource (This, Source);
} else {
return This->EnableInterruptSource (This, Source);
}
}
/**
Enable interrupt source Source.
@param This Instance pointer for this protocol
@param Source Hardware source of the interrupt
@retval EFI_SUCCESS Source interrupt enabled.
@retval EFI_DEVICE_ERROR Hardware could not be programmed.
**/
EFI_STATUS
EFIAPI
EnableInterruptSource (
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source
)
{
UINT32 RegOffset;
UINTN RegShift;
if (Source > mGicNumInterrupts) {
ASSERT(FALSE);
return EFI_UNSUPPORTED;
}
// Calculate enable register offset and bit position
RegOffset = Source / 32;
RegShift = Source % 32;
// Write set-enable register
MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDISER + (4*RegOffset), 1 << RegShift);
return EFI_SUCCESS;
}
/**
Disable interrupt source Source.
@param This Instance pointer for this protocol
@param Source Hardware source of the interrupt
@retval EFI_SUCCESS Source interrupt disabled.
@retval EFI_DEVICE_ERROR Hardware could not be programmed.
**/
EFI_STATUS
EFIAPI
DisableInterruptSource (
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source
)
{
UINT32 RegOffset;
UINTN RegShift;
if (Source > mGicNumInterrupts) {
ASSERT(FALSE);
return EFI_UNSUPPORTED;
}
// Calculate enable register offset and bit position
RegOffset = Source / 32;
RegShift = Source % 32;
// Write set-enable register
MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDICER + (4*RegOffset), 1 << RegShift);
return EFI_SUCCESS;
}
/**
Return current state of interrupt source Source.
@param This Instance pointer for this protocol
@param Source Hardware source of the interrupt
@param InterruptState TRUE: source enabled, FALSE: source disabled.
@retval EFI_SUCCESS InterruptState is valid
@retval EFI_DEVICE_ERROR InterruptState is not valid
**/
EFI_STATUS
EFIAPI
GetInterruptSourceState (
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source,
IN BOOLEAN *InterruptState
)
{
UINT32 RegOffset;
UINTN RegShift;
if (Source > mGicNumInterrupts) {
ASSERT(FALSE);
return EFI_UNSUPPORTED;
}
// calculate enable register offset and bit position
RegOffset = Source / 32;
RegShift = Source % 32;
if ((MmioRead32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDISER + (4*RegOffset)) & (1<<RegShift)) == 0) {
*InterruptState = FALSE;
} else {
*InterruptState = TRUE;
}
return EFI_SUCCESS;
}
/**
Signal to the hardware that the End Of Intrrupt state
has been reached.
@param This Instance pointer for this protocol
@param Source Hardware source of the interrupt
@retval EFI_SUCCESS Source interrupt EOI'ed.
@retval EFI_DEVICE_ERROR Hardware could not be programmed.
**/
EFI_STATUS
EFIAPI
EndOfInterrupt (
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source
)
{
if (Source > mGicNumInterrupts) {
ASSERT(FALSE);
return EFI_UNSUPPORTED;
}
MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCEIOR, Source);
return EFI_SUCCESS;
}
/**
EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs.
@param InterruptType Defines the type of interrupt or exception that
occurred on the processor.This parameter is processor architecture specific.
@param SystemContext A pointer to the processor context when
the interrupt occurred on the processor.
@return None
**/
VOID
EFIAPI
IrqInterruptHandler (
IN EFI_EXCEPTION_TYPE InterruptType,
IN EFI_SYSTEM_CONTEXT SystemContext
)
{
UINT32 GicInterrupt;
HARDWARE_INTERRUPT_HANDLER InterruptHandler;
GicInterrupt = MmioRead32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCIAR);
// Special Interrupts (ID1020-ID1023) have an Interrupt ID greater than the number of interrupt (ie: Spurious interrupt).
if (GicInterrupt >= mGicNumInterrupts) {
// The special interrupt do not need to be acknowledge
return;
}
InterruptHandler = gRegisteredInterruptHandlers[GicInterrupt];
if (InterruptHandler != NULL) {
// Call the registered interrupt handler.
InterruptHandler (GicInterrupt, SystemContext);
} else {
DEBUG ((EFI_D_ERROR, "Spurious GIC interrupt: 0x%x\n", GicInterrupt));
}
EndOfInterrupt (&gHardwareInterruptProtocol, GicInterrupt);
}
//
// Making this global saves a few bytes in image size
//
EFI_HANDLE gHardwareInterruptHandle = NULL;
//
// The protocol instance produced by this driver
//
EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptProtocol = {
RegisterInterruptSource,
EnableInterruptSource,
DisableInterruptSource,
GetInterruptSourceState,
EndOfInterrupt
};
/**
Shutdown our hardware
DXE Core will disable interrupts and turn off the timer and disable interrupts
after all the event handlers have run.
@param[in] Event The Event that is being processed
@param[in] Context Event Context
**/
VOID
EFIAPI
ExitBootServicesEvent (
IN EFI_EVENT Event,
IN VOID *Context
)
{
UINTN Index;
// Acknowledge all pending interrupts
for (Index = 0; Index < mGicNumInterrupts; Index++) {
DisableInterruptSource (&gHardwareInterruptProtocol, Index);
}
for (Index = 0; Index < mGicNumInterrupts; Index++) {
EndOfInterrupt (&gHardwareInterruptProtocol, Index);
}
// Disable Gic Interface
MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCICR, 0x0);
MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCPMR, 0x0);
// Disable Gic Distributor
MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDDCR, 0x0);
}
/**
Initialize the state information for the CPU Architectural Protocol
@param ImageHandle of the loaded driver
@param SystemTable Pointer to the System Table
@retval EFI_SUCCESS Protocol registered
@retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
@retval EFI_DEVICE_ERROR Hardware problems
**/
EFI_STATUS
InterruptDxeInitialize (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
UINTN Index;
UINT32 RegOffset;
UINTN RegShift;
EFI_CPU_ARCH_PROTOCOL *Cpu;
UINT32 CpuTarget;
// Check PcdGicPrimaryCoreId has been set in case the Primary Core is not the core 0 of Cluster 0
DEBUG_CODE_BEGIN();
if ((PcdGet32(PcdArmPrimaryCore) != 0) && (PcdGet32 (PcdGicPrimaryCoreId) == 0)) {
DEBUG((EFI_D_WARN,"Warning: the PCD PcdGicPrimaryCoreId does not seem to be set up for the configuration.\n"));
}
DEBUG_CODE_END();
// Make sure the Interrupt Controller Protocol is not already installed in the system.
ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);
mGicNumInterrupts = ArmGicGetMaxNumInterrupts (PcdGet32(PcdGicDistributorBase));
for (Index = 0; Index < mGicNumInterrupts; Index++) {
DisableInterruptSource (&gHardwareInterruptProtocol, Index);
// Set Priority
RegOffset = Index / 4;
RegShift = (Index % 4) * 8;
MmioAndThenOr32 (
PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDIPR + (4*RegOffset),
~(0xff << RegShift),
ARM_GIC_DEFAULT_PRIORITY << RegShift
);
}
// Configure interrupts for Primary Cpu
CpuTarget = (1 << PcdGet32 (PcdGicPrimaryCoreId));
CpuTarget |= (CpuTarget << 24) | (CpuTarget << 16) | (CpuTarget << 8);
for (Index = 0; Index < (mGicNumInterrupts / 4); Index++) {
MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDIPTR + (Index*4), CpuTarget);
}
// Set binary point reg to 0x7 (no preemption)
MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCBPR, 0x7);
// Set priority mask reg to 0xff to allow all priorities through
MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCPMR, 0xff);
// Enable gic cpu interface
MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCICR, 0x1);
// Enable gic distributor
MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDDCR, 0x1);
// Initialize the array for the Interrupt Handlers
gRegisteredInterruptHandlers = (HARDWARE_INTERRUPT_HANDLER*)AllocateZeroPool (sizeof(HARDWARE_INTERRUPT_HANDLER) * mGicNumInterrupts);
Status = gBS->InstallMultipleProtocolInterfaces (
&gHardwareInterruptHandle,
&gHardwareInterruptProtocolGuid, &gHardwareInterruptProtocol,
NULL
);
ASSERT_EFI_ERROR (Status);
//
// Get the CPU protocol that this driver requires.
//
Status = gBS->LocateProtocol(&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu);
ASSERT_EFI_ERROR(Status);
//
// Unregister the default exception handler.
//
Status = Cpu->RegisterInterruptHandler(Cpu, EXCEPT_ARM_IRQ, NULL);
ASSERT_EFI_ERROR(Status);
//
// Register to receive interrupts
//
Status = Cpu->RegisterInterruptHandler(Cpu, EXCEPT_ARM_IRQ, IrqInterruptHandler);
ASSERT_EFI_ERROR(Status);
// Register for an ExitBootServicesEvent
Status = gBS->CreateEvent (EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY, ExitBootServicesEvent, NULL, &EfiExitBootServicesEvent);
ASSERT_EFI_ERROR (Status);
return Status;
}
/*++
Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.<BR>
Portions copyright (c) 2010, Apple Inc. All rights reserved.<BR>
Portions copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
Gic.c
Abstract:
Driver implementing the GIC interrupt controller protocol
--*/
#include <PiDxe.h>
#include <Library/BaseLib.h>
#include <Library/DebugLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiLib.h>
#include <Library/PcdLib.h>
#include <Library/IoLib.h>
#include <Library/ArmGicLib.h>
#include <Protocol/Cpu.h>
#include <Protocol/HardwareInterrupt.h>
#define ARM_GIC_DEFAULT_PRIORITY 0x80
extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptProtocol;
//
// Notifications
//
EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL;
// Maximum Number of Interrupts
UINTN mGicNumInterrupts = 0;
HARDWARE_INTERRUPT_HANDLER *gRegisteredInterruptHandlers = NULL;
/**
Register Handler for the specified interrupt source.
@param This Instance pointer for this protocol
@param Source Hardware source of the interrupt
@param Handler Callback for interrupt. NULL to unregister
@retval EFI_SUCCESS Source was updated to support Handler.
@retval EFI_DEVICE_ERROR Hardware could not be programmed.
**/
EFI_STATUS
EFIAPI
RegisterInterruptSource (
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source,
IN HARDWARE_INTERRUPT_HANDLER Handler
)
{
if (Source > mGicNumInterrupts) {
ASSERT(FALSE);
return EFI_UNSUPPORTED;
}
if ((Handler == NULL) && (gRegisteredInterruptHandlers[Source] == NULL)) {
return EFI_INVALID_PARAMETER;
}
if ((Handler != NULL) && (gRegisteredInterruptHandlers[Source] != NULL)) {
return EFI_ALREADY_STARTED;
}
gRegisteredInterruptHandlers[Source] = Handler;
// If the interrupt handler is unregistered then disable the interrupt
if (NULL == Handler){
return This->DisableInterruptSource (This, Source);
} else {
return This->EnableInterruptSource (This, Source);
}
}
/**
Enable interrupt source Source.
@param This Instance pointer for this protocol
@param Source Hardware source of the interrupt
@retval EFI_SUCCESS Source interrupt enabled.
@retval EFI_DEVICE_ERROR Hardware could not be programmed.
**/
EFI_STATUS
EFIAPI
EnableInterruptSource (
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source
)
{
UINT32 RegOffset;
UINTN RegShift;
if (Source > mGicNumInterrupts) {
ASSERT(FALSE);
return EFI_UNSUPPORTED;
}
// Calculate enable register offset and bit position
RegOffset = Source / 32;
RegShift = Source % 32;
// Write set-enable register
MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDISER + (4*RegOffset), 1 << RegShift);
return EFI_SUCCESS;
}
/**
Disable interrupt source Source.
@param This Instance pointer for this protocol
@param Source Hardware source of the interrupt
@retval EFI_SUCCESS Source interrupt disabled.
@retval EFI_DEVICE_ERROR Hardware could not be programmed.
**/
EFI_STATUS
EFIAPI
DisableInterruptSource (
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source
)
{
UINT32 RegOffset;
UINTN RegShift;
if (Source > mGicNumInterrupts) {
ASSERT(FALSE);
return EFI_UNSUPPORTED;
}
// Calculate enable register offset and bit position
RegOffset = Source / 32;
RegShift = Source % 32;
// Write set-enable register
MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDICER + (4*RegOffset), 1 << RegShift);
return EFI_SUCCESS;
}
/**
Return current state of interrupt source Source.
@param This Instance pointer for this protocol
@param Source Hardware source of the interrupt
@param InterruptState TRUE: source enabled, FALSE: source disabled.
@retval EFI_SUCCESS InterruptState is valid
@retval EFI_DEVICE_ERROR InterruptState is not valid
**/
EFI_STATUS
EFIAPI
GetInterruptSourceState (
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source,
IN BOOLEAN *InterruptState
)
{
UINT32 RegOffset;
UINTN RegShift;
if (Source > mGicNumInterrupts) {
ASSERT(FALSE);
return EFI_UNSUPPORTED;
}
// calculate enable register offset and bit position
RegOffset = Source / 32;
RegShift = Source % 32;
if ((MmioRead32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDISER + (4*RegOffset)) & (1<<RegShift)) == 0) {
*InterruptState = FALSE;
} else {
*InterruptState = TRUE;
}
return EFI_SUCCESS;
}
/**
Signal to the hardware that the End Of Intrrupt state
has been reached.
@param This Instance pointer for this protocol
@param Source Hardware source of the interrupt
@retval EFI_SUCCESS Source interrupt EOI'ed.
@retval EFI_DEVICE_ERROR Hardware could not be programmed.
**/
EFI_STATUS
EFIAPI
EndOfInterrupt (
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source
)
{
if (Source > mGicNumInterrupts) {
ASSERT(FALSE);
return EFI_UNSUPPORTED;
}
MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCEIOR, Source);
return EFI_SUCCESS;
}
/**
EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs.
@param InterruptType Defines the type of interrupt or exception that
occurred on the processor.This parameter is processor architecture specific.
@param SystemContext A pointer to the processor context when
the interrupt occurred on the processor.
@return None
**/
VOID
EFIAPI
IrqInterruptHandler (
IN EFI_EXCEPTION_TYPE InterruptType,
IN EFI_SYSTEM_CONTEXT SystemContext
)
{
UINT32 GicInterrupt;
HARDWARE_INTERRUPT_HANDLER InterruptHandler;
GicInterrupt = MmioRead32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCIAR);
// Special Interrupts (ID1020-ID1023) have an Interrupt ID greater than the number of interrupt (ie: Spurious interrupt).
if (GicInterrupt >= mGicNumInterrupts) {
// The special interrupt do not need to be acknowledge
return;
}
InterruptHandler = gRegisteredInterruptHandlers[GicInterrupt];
if (InterruptHandler != NULL) {
// Call the registered interrupt handler.
InterruptHandler (GicInterrupt, SystemContext);
} else {
DEBUG ((EFI_D_ERROR, "Spurious GIC interrupt: 0x%x\n", GicInterrupt));
}
EndOfInterrupt (&gHardwareInterruptProtocol, GicInterrupt);
}
//
// Making this global saves a few bytes in image size
//
EFI_HANDLE gHardwareInterruptHandle = NULL;
//
// The protocol instance produced by this driver
//
EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptProtocol = {
RegisterInterruptSource,
EnableInterruptSource,
DisableInterruptSource,
GetInterruptSourceState,
EndOfInterrupt
};
/**
Shutdown our hardware
DXE Core will disable interrupts and turn off the timer and disable interrupts
after all the event handlers have run.
@param[in] Event The Event that is being processed
@param[in] Context Event Context
**/
VOID
EFIAPI
ExitBootServicesEvent (
IN EFI_EVENT Event,
IN VOID *Context
)
{
UINTN Index;
// Acknowledge all pending interrupts
for (Index = 0; Index < mGicNumInterrupts; Index++) {
DisableInterruptSource (&gHardwareInterruptProtocol, Index);
}
for (Index = 0; Index < mGicNumInterrupts; Index++) {
EndOfInterrupt (&gHardwareInterruptProtocol, Index);
}
// Disable Gic Interface
MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCICR, 0x0);
MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCPMR, 0x0);
// Disable Gic Distributor
MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDDCR, 0x0);
}
/**
Initialize the state information for the CPU Architectural Protocol
@param ImageHandle of the loaded driver
@param SystemTable Pointer to the System Table
@retval EFI_SUCCESS Protocol registered
@retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
@retval EFI_DEVICE_ERROR Hardware problems
**/
EFI_STATUS
InterruptDxeInitialize (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
UINTN Index;
UINT32 RegOffset;
UINTN RegShift;
EFI_CPU_ARCH_PROTOCOL *Cpu;
UINT32 CpuTarget;
// Check PcdGicPrimaryCoreId has been set in case the Primary Core is not the core 0 of Cluster 0
DEBUG_CODE_BEGIN();
if ((PcdGet32(PcdArmPrimaryCore) != 0) && (PcdGet32 (PcdGicPrimaryCoreId) == 0)) {
DEBUG((EFI_D_WARN,"Warning: the PCD PcdGicPrimaryCoreId does not seem to be set up for the configuration.\n"));
}
DEBUG_CODE_END();
// Make sure the Interrupt Controller Protocol is not already installed in the system.
ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);
mGicNumInterrupts = ArmGicGetMaxNumInterrupts (PcdGet32(PcdGicDistributorBase));
for (Index = 0; Index < mGicNumInterrupts; Index++) {
DisableInterruptSource (&gHardwareInterruptProtocol, Index);
// Set Priority
RegOffset = Index / 4;
RegShift = (Index % 4) * 8;
MmioAndThenOr32 (
PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDIPR + (4*RegOffset),
~(0xff << RegShift),
ARM_GIC_DEFAULT_PRIORITY << RegShift
);
}
// Configure interrupts for Primary Cpu
CpuTarget = (1 << PcdGet32 (PcdGicPrimaryCoreId));
CpuTarget |= (CpuTarget << 24) | (CpuTarget << 16) | (CpuTarget << 8);
for (Index = 0; Index < (mGicNumInterrupts / 4); Index++) {
MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDIPTR + (Index*4), CpuTarget);
}
// Set binary point reg to 0x7 (no preemption)
MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCBPR, 0x7);
// Set priority mask reg to 0xff to allow all priorities through
MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCPMR, 0xff);
// Enable gic cpu interface
MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCICR, 0x1);
// Enable gic distributor
MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDDCR, 0x1);
// Initialize the array for the Interrupt Handlers
gRegisteredInterruptHandlers = (HARDWARE_INTERRUPT_HANDLER*)AllocateZeroPool (sizeof(HARDWARE_INTERRUPT_HANDLER) * mGicNumInterrupts);
Status = gBS->InstallMultipleProtocolInterfaces (
&gHardwareInterruptHandle,
&gHardwareInterruptProtocolGuid, &gHardwareInterruptProtocol,
NULL
);
ASSERT_EFI_ERROR (Status);
//
// Get the CPU protocol that this driver requires.
//
Status = gBS->LocateProtocol(&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu);
ASSERT_EFI_ERROR(Status);
//
// Unregister the default exception handler.
//
Status = Cpu->RegisterInterruptHandler(Cpu, EXCEPT_ARM_IRQ, NULL);
ASSERT_EFI_ERROR(Status);
//
// Register to receive interrupts
//
Status = Cpu->RegisterInterruptHandler(Cpu, EXCEPT_ARM_IRQ, IrqInterruptHandler);
ASSERT_EFI_ERROR(Status);
// Register for an ExitBootServicesEvent
Status = gBS->CreateEvent (EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY, ExitBootServicesEvent, NULL, &EfiExitBootServicesEvent);
ASSERT_EFI_ERROR (Status);
return Status;
}

114
ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf
View File

@ -1,57 +1,57 @@
#/** @file
#
# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
# Copyright (c) 2012, ARM Ltd. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = PL390GicDxe
FILE_GUID = DE371F7C-DEC4-4D21-ADF1-593ABCC15882
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
ENTRY_POINT = InterruptDxeInitialize
[Sources.common]
PL390Gic.c
PL390GicDxe.c
[Packages]
MdePkg/MdePkg.dec
EmbeddedPkg/EmbeddedPkg.dec
ArmPkg/ArmPkg.dec
[LibraryClasses]
BaseLib
UefiLib
UefiBootServicesTableLib
DebugLib
PrintLib
MemoryAllocationLib
UefiDriverEntryPoint
IoLib
[Protocols]
gHardwareInterruptProtocolGuid
gEfiCpuArchProtocolGuid
[FixedPcd.common]
gArmTokenSpaceGuid.PcdGicDistributorBase
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
gArmTokenSpaceGuid.PcdArmPrimaryCore
gArmTokenSpaceGuid.PcdGicPrimaryCoreId
[Depex]
gEfiCpuArchProtocolGuid
#/** @file
#
# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
# Copyright (c) 2012, ARM Ltd. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = PL390GicDxe
FILE_GUID = DE371F7C-DEC4-4D21-ADF1-593ABCC15882
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
ENTRY_POINT = InterruptDxeInitialize
[Sources.common]
PL390Gic.c
PL390GicDxe.c
[Packages]
MdePkg/MdePkg.dec
EmbeddedPkg/EmbeddedPkg.dec
ArmPkg/ArmPkg.dec
[LibraryClasses]
BaseLib
UefiLib
UefiBootServicesTableLib
DebugLib
PrintLib
MemoryAllocationLib
UefiDriverEntryPoint
IoLib
[Protocols]
gHardwareInterruptProtocolGuid
gEfiCpuArchProtocolGuid
[FixedPcd.common]
gArmTokenSpaceGuid.PcdGicDistributorBase
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
gArmTokenSpaceGuid.PcdArmPrimaryCore
gArmTokenSpaceGuid.PcdGicPrimaryCoreId
[Depex]
gEfiCpuArchProtocolGuid

760
ArmPkg/Drivers/TimerDxe/TimerDxe.c
View File

@ -1,380 +1,380 @@
/** @file
Timer Architecture Protocol driver of the ARM flavor
Copyright (c) 2011 ARM Ltd. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <PiDxe.h>
#include <Library/ArmLib.h>
#include <Library/BaseLib.h>
#include <Library/DebugLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiLib.h>
#include <Library/PcdLib.h>
#include <Library/IoLib.h>
#include <Library/ArmV7ArchTimerLib.h>
#include <Protocol/Timer.h>
#include <Protocol/HardwareInterrupt.h>
// The notification function to call on every timer interrupt.
EFI_TIMER_NOTIFY mTimerNotifyFunction = (EFI_TIMER_NOTIFY)NULL;
EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL;
// The current period of the timer interrupt
UINT64 mTimerPeriod = 0;
// Cached copy of the Hardware Interrupt protocol instance
EFI_HARDWARE_INTERRUPT_PROTOCOL *gInterrupt = NULL;
/**
This function registers the handler NotifyFunction so it is called every time
the timer interrupt fires. It also passes the amount of time since the last
handler call to the NotifyFunction. If NotifyFunction is NULL, then the
handler is unregistered. If the handler is registered, then EFI_SUCCESS is
returned. If the CPU does not support registering a timer interrupt handler,
then EFI_UNSUPPORTED is returned. If an attempt is made to register a handler
when a handler is already registered, then EFI_ALREADY_STARTED is returned.
If an attempt is made to unregister a handler when a handler is not registered,
then EFI_INVALID_PARAMETER is returned. If an error occurs attempting to
register the NotifyFunction with the timer interrupt, then EFI_DEVICE_ERROR
is returned.
@param This The EFI_TIMER_ARCH_PROTOCOL instance.
@param NotifyFunction The function to call when a timer interrupt fires. This
function executes at TPL_HIGH_LEVEL. The DXE Core will
register a handler for the timer interrupt, so it can know
how much time has passed. This information is used to
signal timer based events. NULL will unregister the handler.
@retval EFI_SUCCESS The timer handler was registered.
@retval EFI_UNSUPPORTED The platform does not support timer interrupts.
@retval EFI_ALREADY_STARTED NotifyFunction is not NULL, and a handler is already
registered.
@retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a handler was not
previously registered.
@retval EFI_DEVICE_ERROR The timer handler could not be registered.
**/
EFI_STATUS
EFIAPI
TimerDriverRegisterHandler (
IN EFI_TIMER_ARCH_PROTOCOL *This,
IN EFI_TIMER_NOTIFY NotifyFunction
)
{
if ((NotifyFunction == NULL) && (mTimerNotifyFunction == NULL)) {
return EFI_INVALID_PARAMETER;
}
if ((NotifyFunction != NULL) && (mTimerNotifyFunction != NULL)) {
return EFI_ALREADY_STARTED;
}
mTimerNotifyFunction = NotifyFunction;
return EFI_SUCCESS;
}
/**
Disable the timer
**/
VOID
EFIAPI
ExitBootServicesEvent (
IN EFI_EVENT Event,
IN VOID *Context
)
{
ArmArchTimerDisableTimer ();
}
/**
This function adjusts the period of timer interrupts to the value specified
by TimerPeriod. If the timer period is updated, then the selected timer
period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. If
the timer hardware is not programmable, then EFI_UNSUPPORTED is returned.
If an error occurs while attempting to update the timer period, then the
timer hardware will be put back in its state prior to this call, and
EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer interrupt
is disabled. This is not the same as disabling the CPU's interrupts.
Instead, it must either turn off the timer hardware, or it must adjust the
interrupt controller so that a CPU interrupt is not generated when the timer
interrupt fires.
@param This The EFI_TIMER_ARCH_PROTOCOL instance.
@param TimerPeriod The rate to program the timer interrupt in 100 nS units. If
the timer hardware is not programmable, then EFI_UNSUPPORTED is
returned. If the timer is programmable, then the timer period
will be rounded up to the nearest timer period that is supported
by the timer hardware. If TimerPeriod is set to 0, then the
timer interrupts will be disabled.
@retval EFI_SUCCESS The timer period was changed.
@retval EFI_UNSUPPORTED The platform cannot change the period of the timer interrupt.
@retval EFI_DEVICE_ERROR The timer period could not be changed due to a device error.
**/
EFI_STATUS
EFIAPI
TimerDriverSetTimerPeriod (
IN EFI_TIMER_ARCH_PROTOCOL *This,
IN UINT64 TimerPeriod
)
{
UINT64 TimerTicks;
// Always disable the timer
ArmArchTimerDisableTimer ();
if (TimerPeriod != 0) {
// Convert TimerPeriod to micro sec units
TimerTicks = DivU64x32 (TimerPeriod, 10);
TimerTicks = MultU64x32 (TimerTicks, (PcdGet32(PcdArmArchTimerFreqInHz)/1000000));
ArmArchTimerSetTimerVal((UINTN)TimerTicks);
// Enable the timer
ArmArchTimerEnableTimer ();
}
// Save the new timer period
mTimerPeriod = TimerPeriod;
return EFI_SUCCESS;
}
/**
This function retrieves the period of timer interrupts in 100 ns units,
returns that value in TimerPeriod, and returns EFI_SUCCESS. If TimerPeriod
is NULL, then EFI_INVALID_PARAMETER is returned. If a TimerPeriod of 0 is
returned, then the timer is currently disabled.
@param This The EFI_TIMER_ARCH_PROTOCOL instance.
@param TimerPeriod A pointer to the timer period to retrieve in 100 ns units. If
0 is returned, then the timer is currently disabled.
@retval EFI_SUCCESS The timer period was returned in TimerPeriod.
@retval EFI_INVALID_PARAMETER TimerPeriod is NULL.
**/
EFI_STATUS
EFIAPI
TimerDriverGetTimerPeriod (
IN EFI_TIMER_ARCH_PROTOCOL *This,
OUT UINT64 *TimerPeriod
)
{
if (TimerPeriod == NULL) {
return EFI_INVALID_PARAMETER;
}
*TimerPeriod = mTimerPeriod;
return EFI_SUCCESS;
}
/**
This function generates a soft timer interrupt. If the platform does not support soft
timer interrupts, then EFI_UNSUPPORTED is returned. Otherwise, EFI_SUCCESS is returned.
If a handler has been registered through the EFI_TIMER_ARCH_PROTOCOL.RegisterHandler()
service, then a soft timer interrupt will be generated. If the timer interrupt is
enabled when this service is called, then the registered handler will be invoked. The
registered handler should not be able to distinguish a hardware-generated timer
interrupt from a software-generated timer interrupt.
@param This The EFI_TIMER_ARCH_PROTOCOL instance.
@retval EFI_SUCCESS The soft timer interrupt was generated.
@retval EFI_UNSUPPORTED The platform does not support the generation of soft timer interrupts.
**/
EFI_STATUS
EFIAPI
TimerDriverGenerateSoftInterrupt (
IN EFI_TIMER_ARCH_PROTOCOL *This
)
{
return EFI_UNSUPPORTED;
}
/**
Interface structure for the Timer Architectural Protocol.
@par Protocol Description:
This protocol provides the services to initialize a periodic timer
interrupt, and to register a handler that is called each time the timer
interrupt fires. It may also provide a service to adjust the rate of the
periodic timer interrupt. When a timer interrupt occurs, the handler is
passed the amount of time that has passed since the previous timer
interrupt.
@param RegisterHandler
Registers a handler that will be called each time the
timer interrupt fires. TimerPeriod defines the minimum
time between timer interrupts, so TimerPeriod will also
be the minimum time between calls to the registered
handler.
@param SetTimerPeriod
Sets the period of the timer interrupt in 100 nS units.
This function is optional, and may return EFI_UNSUPPORTED.
If this function is supported, then the timer period will
be rounded up to the nearest supported timer period.
@param GetTimerPeriod
Retrieves the period of the timer interrupt in 100 nS units.
@param GenerateSoftInterrupt
Generates a soft timer interrupt that simulates the firing of
the timer interrupt. This service can be used to invoke the registered handler if the timer interrupt has been masked for
a period of time.
**/
EFI_TIMER_ARCH_PROTOCOL gTimer = {
TimerDriverRegisterHandler,
TimerDriverSetTimerPeriod,
TimerDriverGetTimerPeriod,
TimerDriverGenerateSoftInterrupt
};
/**
C Interrupt Handler called in the interrupt context when Source interrupt is active.
@param Source Source of the interrupt. Hardware routing off a specific platform defines
what source means.
@param SystemContext Pointer to system register context. Mostly used by debuggers and will
update the system context after the return from the interrupt if
modified. Don't change these values unless you know what you are doing
**/
VOID
EFIAPI
TimerInterruptHandler (
IN HARDWARE_INTERRUPT_SOURCE Source,
IN EFI_SYSTEM_CONTEXT SystemContext
)
{
EFI_TPL OriginalTPL;
//
// DXE core uses this callback for the EFI timer tick. The DXE core uses locks
// that raise to TPL_HIGH and then restore back to current level. Thus we need
// to make sure TPL level is set to TPL_HIGH while we are handling the timer tick.
//
OriginalTPL = gBS->RaiseTPL (TPL_HIGH_LEVEL);
// Check if the timer interrupt is active
if ((ArmArchTimerGetTimerCtrlReg () ) & ARM_ARCH_TIMER_ISTATUS) {
// Signal end of interrupt early to help avoid losing subsequent ticks from long duration handlers
gInterrupt->EndOfInterrupt (gInterrupt, Source);
if (mTimerNotifyFunction) {
mTimerNotifyFunction (mTimerPeriod);
}
// Reload the Timer
TimerDriverSetTimerPeriod (&gTimer, FixedPcdGet32(PcdTimerPeriod));
}
// Enable timer interrupts
gInterrupt->EnableInterruptSource (gInterrupt, Source);
gBS->RestoreTPL (OriginalTPL);
}
/**
Initialize the state information for the Timer Architectural Protocol and
the Timer Debug support protocol that allows the debugger to break into a
running program.
@param ImageHandle of the loaded driver
@param SystemTable Pointer to the System Table
@retval EFI_SUCCESS Protocol registered
@retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
@retval EFI_DEVICE_ERROR Hardware problems
**/
EFI_STATUS
EFIAPI
TimerInitialize (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_HANDLE Handle = NULL;
EFI_STATUS Status;
UINTN TimerCtrlReg;
if (ArmIsArchTimerImplemented () == 0) {
DEBUG ((EFI_D_ERROR, "ARM Architectural Timer is not available in the CPU, hence cann't use this Driver \n"));
ASSERT (0);
}
// Find the interrupt controller protocol. ASSERT if not found.
Status = gBS->LocateProtocol (&gHardwareInterruptProtocolGuid, NULL, (VOID **)&gInterrupt);
ASSERT_EFI_ERROR (Status);
// Disable the timer
Status = TimerDriverSetTimerPeriod (&gTimer, 0);
ASSERT_EFI_ERROR (Status);
// Install secure and Non-secure interrupt handlers
// Note: Because it is not possible to determine the security state of the
// CPU dynamically, we just install interrupt handler for both sec and non-sec
// timer PPI
Status = gInterrupt->RegisterInterruptSource (gInterrupt, PcdGet32 (PcdArmArchTimerSecIntrNum), TimerInterruptHandler);
ASSERT_EFI_ERROR (Status);
Status = gInterrupt->RegisterInterruptSource (gInterrupt, PcdGet32 (PcdArmArchTimerIntrNum), TimerInterruptHandler);
ASSERT_EFI_ERROR (Status);
// Unmask timer interrupts
TimerCtrlReg = ArmArchTimerGetTimerCtrlReg ();
TimerCtrlReg &= ~ARM_ARCH_TIMER_IMASK;
ArmArchTimerSetTimerCtrlReg (TimerCtrlReg);
// Set up default timer
Status = TimerDriverSetTimerPeriod (&gTimer, FixedPcdGet32(PcdTimerPeriod)); // TIMER_DEFAULT_PERIOD
ASSERT_EFI_ERROR (Status);
// Install the Timer Architectural Protocol onto a new handle
Status = gBS->InstallMultipleProtocolInterfaces(
&Handle,
&gEfiTimerArchProtocolGuid, &gTimer,
NULL
);
ASSERT_EFI_ERROR(Status);
// enable Secure timer interrupts
Status = gInterrupt->EnableInterruptSource (gInterrupt, PcdGet32 (PcdArmArchTimerSecIntrNum));
// enable NonSecure timer interrupts
Status = gInterrupt->EnableInterruptSource (gInterrupt, PcdGet32 (PcdArmArchTimerIntrNum));
// Register for an ExitBootServicesEvent
Status = gBS->CreateEvent (EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY, ExitBootServicesEvent, NULL, &EfiExitBootServicesEvent);
ASSERT_EFI_ERROR (Status);
return Status;
}
/** @file
Timer Architecture Protocol driver of the ARM flavor
Copyright (c) 2011 ARM Ltd. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <PiDxe.h>
#include <Library/ArmLib.h>
#include <Library/BaseLib.h>
#include <Library/DebugLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiLib.h>
#include <Library/PcdLib.h>
#include <Library/IoLib.h>
#include <Library/ArmV7ArchTimerLib.h>
#include <Protocol/Timer.h>
#include <Protocol/HardwareInterrupt.h>
// The notification function to call on every timer interrupt.
EFI_TIMER_NOTIFY mTimerNotifyFunction = (EFI_TIMER_NOTIFY)NULL;
EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL;
// The current period of the timer interrupt
UINT64 mTimerPeriod = 0;
// Cached copy of the Hardware Interrupt protocol instance
EFI_HARDWARE_INTERRUPT_PROTOCOL *gInterrupt = NULL;
/**
This function registers the handler NotifyFunction so it is called every time
the timer interrupt fires. It also passes the amount of time since the last
handler call to the NotifyFunction. If NotifyFunction is NULL, then the
handler is unregistered. If the handler is registered, then EFI_SUCCESS is
returned. If the CPU does not support registering a timer interrupt handler,
then EFI_UNSUPPORTED is returned. If an attempt is made to register a handler
when a handler is already registered, then EFI_ALREADY_STARTED is returned.
If an attempt is made to unregister a handler when a handler is not registered,
then EFI_INVALID_PARAMETER is returned. If an error occurs attempting to
register the NotifyFunction with the timer interrupt, then EFI_DEVICE_ERROR
is returned.
@param This The EFI_TIMER_ARCH_PROTOCOL instance.
@param NotifyFunction The function to call when a timer interrupt fires. This
function executes at TPL_HIGH_LEVEL. The DXE Core will
register a handler for the timer interrupt, so it can know
how much time has passed. This information is used to
signal timer based events. NULL will unregister the handler.
@retval EFI_SUCCESS The timer handler was registered.
@retval EFI_UNSUPPORTED The platform does not support timer interrupts.
@retval EFI_ALREADY_STARTED NotifyFunction is not NULL, and a handler is already
registered.
@retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a handler was not
previously registered.
@retval EFI_DEVICE_ERROR The timer handler could not be registered.
**/
EFI_STATUS
EFIAPI
TimerDriverRegisterHandler (
IN EFI_TIMER_ARCH_PROTOCOL *This,
IN EFI_TIMER_NOTIFY NotifyFunction
)
{
if ((NotifyFunction == NULL) && (mTimerNotifyFunction == NULL)) {
return EFI_INVALID_PARAMETER;
}
if ((NotifyFunction != NULL) && (mTimerNotifyFunction != NULL)) {
return EFI_ALREADY_STARTED;
}
mTimerNotifyFunction = NotifyFunction;
return EFI_SUCCESS;
}
/**
Disable the timer
**/
VOID
EFIAPI
ExitBootServicesEvent (
IN EFI_EVENT Event,
IN VOID *Context
)
{
ArmArchTimerDisableTimer ();
}
/**
This function adjusts the period of timer interrupts to the value specified
by TimerPeriod. If the timer period is updated, then the selected timer
period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. If
the timer hardware is not programmable, then EFI_UNSUPPORTED is returned.
If an error occurs while attempting to update the timer period, then the
timer hardware will be put back in its state prior to this call, and
EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer interrupt
is disabled. This is not the same as disabling the CPU's interrupts.
Instead, it must either turn off the timer hardware, or it must adjust the
interrupt controller so that a CPU interrupt is not generated when the timer
interrupt fires.
@param This The EFI_TIMER_ARCH_PROTOCOL instance.
@param TimerPeriod The rate to program the timer interrupt in 100 nS units. If
the timer hardware is not programmable, then EFI_UNSUPPORTED is
returned. If the timer is programmable, then the timer period
will be rounded up to the nearest timer period that is supported
by the timer hardware. If TimerPeriod is set to 0, then the
timer interrupts will be disabled.
@retval EFI_SUCCESS The timer period was changed.
@retval EFI_UNSUPPORTED The platform cannot change the period of the timer interrupt.
@retval EFI_DEVICE_ERROR The timer period could not be changed due to a device error.
**/
EFI_STATUS
EFIAPI
TimerDriverSetTimerPeriod (
IN EFI_TIMER_ARCH_PROTOCOL *This,
IN UINT64 TimerPeriod
)
{
UINT64 TimerTicks;
// Always disable the timer
ArmArchTimerDisableTimer ();
if (TimerPeriod != 0) {
// Convert TimerPeriod to micro sec units
TimerTicks = DivU64x32 (TimerPeriod, 10);
TimerTicks = MultU64x32 (TimerTicks, (PcdGet32(PcdArmArchTimerFreqInHz)/1000000));
ArmArchTimerSetTimerVal((UINTN)TimerTicks);
// Enable the timer
ArmArchTimerEnableTimer ();
}
// Save the new timer period
mTimerPeriod = TimerPeriod;
return EFI_SUCCESS;
}
/**
This function retrieves the period of timer interrupts in 100 ns units,
returns that value in TimerPeriod, and returns EFI_SUCCESS. If TimerPeriod
is NULL, then EFI_INVALID_PARAMETER is returned. If a TimerPeriod of 0 is
returned, then the timer is currently disabled.
@param This The EFI_TIMER_ARCH_PROTOCOL instance.
@param TimerPeriod A pointer to the timer period to retrieve in 100 ns units. If
0 is returned, then the timer is currently disabled.
@retval EFI_SUCCESS The timer period was returned in TimerPeriod.
@retval EFI_INVALID_PARAMETER TimerPeriod is NULL.
**/
EFI_STATUS
EFIAPI
TimerDriverGetTimerPeriod (
IN EFI_TIMER_ARCH_PROTOCOL *This,
OUT UINT64 *TimerPeriod
)
{
if (TimerPeriod == NULL) {
return EFI_INVALID_PARAMETER;
}
*TimerPeriod = mTimerPeriod;
return EFI_SUCCESS;
}
/**
This function generates a soft timer interrupt. If the platform does not support soft
timer interrupts, then EFI_UNSUPPORTED is returned. Otherwise, EFI_SUCCESS is returned.
If a handler has been registered through the EFI_TIMER_ARCH_PROTOCOL.RegisterHandler()
service, then a soft timer interrupt will be generated. If the timer interrupt is
enabled when this service is called, then the registered handler will be invoked. The
registered handler should not be able to distinguish a hardware-generated timer
interrupt from a software-generated timer interrupt.
@param This The EFI_TIMER_ARCH_PROTOCOL instance.
@retval EFI_SUCCESS The soft timer interrupt was generated.
@retval EFI_UNSUPPORTED The platform does not support the generation of soft timer interrupts.
**/
EFI_STATUS
EFIAPI
TimerDriverGenerateSoftInterrupt (
IN EFI_TIMER_ARCH_PROTOCOL *This
)
{
return EFI_UNSUPPORTED;
}
/**
Interface structure for the Timer Architectural Protocol.
@par Protocol Description:
This protocol provides the services to initialize a periodic timer
interrupt, and to register a handler that is called each time the timer
interrupt fires. It may also provide a service to adjust the rate of the
periodic timer interrupt. When a timer interrupt occurs, the handler is
passed the amount of time that has passed since the previous timer
interrupt.
@param RegisterHandler
Registers a handler that will be called each time the
timer interrupt fires. TimerPeriod defines the minimum
time between timer interrupts, so TimerPeriod will also
be the minimum time between calls to the registered
handler.
@param SetTimerPeriod
Sets the period of the timer interrupt in 100 nS units.
This function is optional, and may return EFI_UNSUPPORTED.
If this function is supported, then the timer period will
be rounded up to the nearest supported timer period.
@param GetTimerPeriod
Retrieves the period of the timer interrupt in 100 nS units.
@param GenerateSoftInterrupt
Generates a soft timer interrupt that simulates the firing of
the timer interrupt. This service can be used to invoke the registered handler if the timer interrupt has been masked for
a period of time.
**/
EFI_TIMER_ARCH_PROTOCOL gTimer = {
TimerDriverRegisterHandler,
TimerDriverSetTimerPeriod,
TimerDriverGetTimerPeriod,
TimerDriverGenerateSoftInterrupt
};
/**
C Interrupt Handler called in the interrupt context when Source interrupt is active.
@param Source Source of the interrupt. Hardware routing off a specific platform defines
what source means.
@param SystemContext Pointer to system register context. Mostly used by debuggers and will
update the system context after the return from the interrupt if
modified. Don't change these values unless you know what you are doing
**/
VOID
EFIAPI
TimerInterruptHandler (
IN HARDWARE_INTERRUPT_SOURCE Source,
IN EFI_SYSTEM_CONTEXT SystemContext
)
{
EFI_TPL OriginalTPL;
//
// DXE core uses this callback for the EFI timer tick. The DXE core uses locks
// that raise to TPL_HIGH and then restore back to current level. Thus we need
// to make sure TPL level is set to TPL_HIGH while we are handling the timer tick.
//
OriginalTPL = gBS->RaiseTPL (TPL_HIGH_LEVEL);
// Check if the timer interrupt is active
if ((ArmArchTimerGetTimerCtrlReg () ) & ARM_ARCH_TIMER_ISTATUS) {
// Signal end of interrupt early to help avoid losing subsequent ticks from long duration handlers
gInterrupt->EndOfInterrupt (gInterrupt, Source);
if (mTimerNotifyFunction) {
mTimerNotifyFunction (mTimerPeriod);
}
// Reload the Timer
TimerDriverSetTimerPeriod (&gTimer, FixedPcdGet32(PcdTimerPeriod));
}
// Enable timer interrupts
gInterrupt->EnableInterruptSource (gInterrupt, Source);
gBS->RestoreTPL (OriginalTPL);
}
/**
Initialize the state information for the Timer Architectural Protocol and
the Timer Debug support protocol that allows the debugger to break into a
running program.
@param ImageHandle of the loaded driver
@param SystemTable Pointer to the System Table
@retval EFI_SUCCESS Protocol registered
@retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
@retval EFI_DEVICE_ERROR Hardware problems
**/
EFI_STATUS
EFIAPI
TimerInitialize (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_HANDLE Handle = NULL;
EFI_STATUS Status;
UINTN TimerCtrlReg;
if (ArmIsArchTimerImplemented () == 0) {
DEBUG ((EFI_D_ERROR, "ARM Architectural Timer is not available in the CPU, hence cann't use this Driver \n"));
ASSERT (0);
}
// Find the interrupt controller protocol. ASSERT if not found.
Status = gBS->LocateProtocol (&gHardwareInterruptProtocolGuid, NULL, (VOID **)&gInterrupt);
ASSERT_EFI_ERROR (Status);
// Disable the timer
Status = TimerDriverSetTimerPeriod (&gTimer, 0);
ASSERT_EFI_ERROR (Status);
// Install secure and Non-secure interrupt handlers
// Note: Because it is not possible to determine the security state of the
// CPU dynamically, we just install interrupt handler for both sec and non-sec
// timer PPI
Status = gInterrupt->RegisterInterruptSource (gInterrupt, PcdGet32 (PcdArmArchTimerSecIntrNum), TimerInterruptHandler);
ASSERT_EFI_ERROR (Status);
Status = gInterrupt->RegisterInterruptSource (gInterrupt, PcdGet32 (PcdArmArchTimerIntrNum), TimerInterruptHandler);
ASSERT_EFI_ERROR (Status);
// Unmask timer interrupts
TimerCtrlReg = ArmArchTimerGetTimerCtrlReg ();
TimerCtrlReg &= ~ARM_ARCH_TIMER_IMASK;
ArmArchTimerSetTimerCtrlReg (TimerCtrlReg);
// Set up default timer
Status = TimerDriverSetTimerPeriod (&gTimer, FixedPcdGet32(PcdTimerPeriod)); // TIMER_DEFAULT_PERIOD
ASSERT_EFI_ERROR (Status);
// Install the Timer Architectural Protocol onto a new handle
Status = gBS->InstallMultipleProtocolInterfaces(
&Handle,
&gEfiTimerArchProtocolGuid, &gTimer,
NULL
);
ASSERT_EFI_ERROR(Status);
// enable Secure timer interrupts
Status = gInterrupt->EnableInterruptSource (gInterrupt, PcdGet32 (PcdArmArchTimerSecIntrNum));
// enable NonSecure timer interrupts
Status = gInterrupt->EnableInterruptSource (gInterrupt, PcdGet32 (PcdArmArchTimerIntrNum));
// Register for an ExitBootServicesEvent
Status = gBS->CreateEvent (EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY, ExitBootServicesEvent, NULL, &EfiExitBootServicesEvent);
ASSERT_EFI_ERROR (Status);
return Status;
}

118
ArmPkg/Drivers/TimerDxe/TimerDxe.inf
View File

@ -1,59 +1,59 @@
#/** @file
#
# Component description file for Timer DXE module
#
# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = ArmTimerDxe
FILE_GUID = 49ea041e-6752-42ca-b0b1-7344fe2546b7
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
ENTRY_POINT = TimerInitialize
[Sources.common]
TimerDxe.c
[Packages]
MdePkg/MdePkg.dec
EmbeddedPkg/EmbeddedPkg.dec
ArmPkg/ArmPkg.dec
ArmPlatformPkg/ArmPlatformPkg.dec
[LibraryClasses]
ArmLib
BaseLib
UefiRuntimeServicesTableLib
UefiLib
UefiBootServicesTableLib
BaseMemoryLib
DebugLib
UefiDriverEntryPoint
IoLib
[Guids]
[Protocols]
gEfiTimerArchProtocolGuid
gHardwareInterruptProtocolGuid
[Pcd.common]
gEmbeddedTokenSpaceGuid.PcdTimerPeriod
gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz
[Depex]
gHardwareInterruptProtocolGuid
#/** @file
#
# Component description file for Timer DXE module
#
# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = ArmTimerDxe
FILE_GUID = 49ea041e-6752-42ca-b0b1-7344fe2546b7
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
ENTRY_POINT = TimerInitialize
[Sources.common]
TimerDxe.c
[Packages]
MdePkg/MdePkg.dec
EmbeddedPkg/EmbeddedPkg.dec
ArmPkg/ArmPkg.dec
ArmPlatformPkg/ArmPlatformPkg.dec
[LibraryClasses]
ArmLib
BaseLib
UefiRuntimeServicesTableLib
UefiLib
UefiBootServicesTableLib
BaseMemoryLib
DebugLib
UefiDriverEntryPoint
IoLib
[Guids]
[Protocols]
gEfiTimerArchProtocolGuid
gHardwareInterruptProtocolGuid
[Pcd.common]
gEmbeddedTokenSpaceGuid.PcdTimerPeriod
gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz
[Depex]
gHardwareInterruptProtocolGuid

92
ArmPkg/Filesystem/SemihostFs/SemihostFs.inf
View File

@ -1,46 +1,46 @@
#/** @file
# Support a Semi Host file system over a debuggers JTAG
#
# Copyright (c) 2009, Apple Inc. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = SemihostFs
FILE_GUID = C5B9C74A-6D72-4719-99AB-C59F199091EB
MODULE_TYPE = UEFI_DRIVER
VERSION_STRING = 1.0
ENTRY_POINT = SemihostFsEntryPoint
[Sources.ARM]
Arm/SemihostFs.c
[Packages]
MdePkg/MdePkg.dec
ArmPkg/ArmPkg.dec
[LibraryClasses]
BaseLib
MemoryAllocationLib
SemihostLib
UefiDriverEntryPoint
UefiLib
[Guids]
gEfiFileSystemInfoGuid
gEfiFileInfoGuid
gEfiFileSystemVolumeLabelInfoIdGuid
[Protocols]
gEfiSimpleFileSystemProtocolGuid
gEfiDevicePathProtocolGuid
#/** @file
# Support a Semi Host file system over a debuggers JTAG
#
# Copyright (c) 2009, Apple Inc. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = SemihostFs
FILE_GUID = C5B9C74A-6D72-4719-99AB-C59F199091EB
MODULE_TYPE = UEFI_DRIVER
VERSION_STRING = 1.0
ENTRY_POINT = SemihostFsEntryPoint
[Sources.ARM]
Arm/SemihostFs.c
[Packages]
MdePkg/MdePkg.dec
ArmPkg/ArmPkg.dec
[LibraryClasses]
BaseLib
MemoryAllocationLib
SemihostLib
UefiDriverEntryPoint
UefiLib
[Guids]
gEfiFileSystemInfoGuid
gEfiFileInfoGuid
gEfiFileSystemVolumeLabelInfoIdGuid
[Protocols]
gEfiSimpleFileSystemProtocolGuid
gEfiDevicePathProtocolGuid

56
ArmPkg/Include/Library/ArmCpuLib.h
View File

@ -1,28 +1,28 @@
/** @file
Copyright (c) 2011-2012, ARM Limited. All rights reserved.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __ARMCPU_LIB__
#define __ARMCPU_LIB__
VOID
ArmCpuSetup (
IN UINTN MpId
);
VOID
ArmCpuSetupSmpNonSecure (
IN UINTN MpId
);
#endif // __ARMCPU_LIB__
/** @file
Copyright (c) 2011-2012, ARM Limited. All rights reserved.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __ARMCPU_LIB__
#define __ARMCPU_LIB__
VOID
ArmCpuSetup (
IN UINTN MpId
);
VOID
ArmCpuSetupSmpNonSecure (
IN UINTN MpId
);
#endif // __ARMCPU_LIB__

82
ArmPkg/Include/Library/ArmDisassemblerLib.h
View File

@ -1,43 +1,43 @@
/** @file
Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __ARM_DISASSEBLER_LIB_H__
#define __ARM_DISASSEBLER_LIB_H__
/**
Place a dissasembly of of **OpCodePtr into buffer, and update OpCodePtr to
point to next instructin.
We cheat and only decode instructions that access
memory. If the instruction is not found we dump the instruction in hex.
@param OpCodePtrPtr Pointer to pointer of ARM Thumb instruction to disassemble.
@param Thumb TRUE for Thumb(2), FALSE for ARM instruction stream
@param Extended TRUE dump hex for instruction too.
/** @file
Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __ARM_DISASSEBLER_LIB_H__
#define __ARM_DISASSEBLER_LIB_H__
/**
Place a dissasembly of of **OpCodePtr into buffer, and update OpCodePtr to
point to next instructin.
We cheat and only decode instructions that access
memory. If the instruction is not found we dump the instruction in hex.
@param OpCodePtrPtr Pointer to pointer of ARM Thumb instruction to disassemble.
@param Thumb TRUE for Thumb(2), FALSE for ARM instruction stream
@param Extended TRUE dump hex for instruction too.
@param ItBlock Size of IT Block
@param Buf Buffer to sprintf disassembly into.
@param Size Size of Buf in bytes.
**/
VOID
DisassembleInstruction (
IN UINT8 **OpCodePtr,
IN BOOLEAN Thumb,
IN BOOLEAN Extended,
@param Buf Buffer to sprintf disassembly into.
@param Size Size of Buf in bytes.
**/
VOID
DisassembleInstruction (
IN UINT8 **OpCodePtr,
IN BOOLEAN Thumb,
IN BOOLEAN Extended,
IN OUT UINT32 *ItBlock,
OUT CHAR8 *Buf,
OUT UINTN Size
);
#endif
OUT CHAR8 *Buf,
OUT UINTN Size
);
#endif

1122
ArmPkg/Include/Library/ArmLib.h
View File

File diff suppressed because it is too large Load Diff

230
ArmPkg/Include/Library/ArmV7ArchTimerLib.h
View File

@ -1,115 +1,115 @@
/** @file
Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __ARM_V7_ARCH_TIMER_LIB_H__
#define __ARM_V7_ARCH_TIMER_LIB_H__
#define ARM_ARCH_TIMER_ENABLE (1 << 0)
#define ARM_ARCH_TIMER_IMASK (1 << 1)
#define ARM_ARCH_TIMER_ISTATUS (1 << 2)
typedef enum {
CntFrq = 0,
CntPct,
CntkCtl,
CntpTval,
CntpCtl,
CntvTval,
CntvCtl,
CntvCt,
CntpCval,
CntvCval,
CntvOff,
CnthCtl,
CnthpTval,
CnthpCtl,
CnthpCval,
RegMaximum
}ARM_ARCH_TIMER_REGS;
VOID
EFIAPI
ArmArchTimerReadReg (
IN ARM_ARCH_TIMER_REGS Reg,
OUT VOID *DstBuf
);
VOID
EFIAPI
ArmArchTimerWriteReg (
IN ARM_ARCH_TIMER_REGS Reg,
IN VOID *SrcBuf
);
VOID
EFIAPI
ArmArchTimerEnableTimer (
VOID
);
VOID
EFIAPI
ArmArchTimerDisableTimer (
VOID
);
VOID
EFIAPI
ArmArchTimerSetTimerFreq (
IN UINTN FreqInHz
);
UINTN
EFIAPI
ArmArchTimerGetTimerFreq (
VOID
);
VOID
EFIAPI
ArmArchTimerSetTimerVal (
IN UINTN Val
);
UINTN
EFIAPI
ArmArchTimerGetTimerVal (
VOID
);
UINT64
EFIAPI
ArmArchTimerGetSystemCount (
VOID
);
UINTN
EFIAPI
ArmArchTimerGetTimerCtrlReg (
VOID
);
VOID
EFIAPI
ArmArchTimerSetTimerCtrlReg (
UINTN Val
);
VOID
EFIAPI
ArmArchTimerSetCompareVal (
IN UINT64 Val
);
#endif // __ARM_V7_ARCH_TIMER_LIB_H__
/** @file
Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __ARM_V7_ARCH_TIMER_LIB_H__
#define __ARM_V7_ARCH_TIMER_LIB_H__
#define ARM_ARCH_TIMER_ENABLE (1 << 0)
#define ARM_ARCH_TIMER_IMASK (1 << 1)
#define ARM_ARCH_TIMER_ISTATUS (1 << 2)
typedef enum {
CntFrq = 0,
CntPct,
CntkCtl,
CntpTval,
CntpCtl,
CntvTval,
CntvCtl,
CntvCt,
CntpCval,
CntvCval,
CntvOff,
CnthCtl,
CnthpTval,
CnthpCtl,
CnthpCval,
RegMaximum
}ARM_ARCH_TIMER_REGS;
VOID
EFIAPI
ArmArchTimerReadReg (
IN ARM_ARCH_TIMER_REGS Reg,
OUT VOID *DstBuf
);
VOID
EFIAPI
ArmArchTimerWriteReg (
IN ARM_ARCH_TIMER_REGS Reg,
IN VOID *SrcBuf
);
VOID
EFIAPI
ArmArchTimerEnableTimer (
VOID
);
VOID
EFIAPI
ArmArchTimerDisableTimer (
VOID
);
VOID
EFIAPI
ArmArchTimerSetTimerFreq (
IN UINTN FreqInHz
);
UINTN
EFIAPI
ArmArchTimerGetTimerFreq (
VOID
);
VOID
EFIAPI
ArmArchTimerSetTimerVal (
IN UINTN Val
);
UINTN
EFIAPI
ArmArchTimerGetTimerVal (
VOID
);
UINT64
EFIAPI
ArmArchTimerGetSystemCount (
VOID
);
UINTN
EFIAPI
ArmArchTimerGetTimerCtrlReg (
VOID
);
VOID
EFIAPI
ArmArchTimerSetTimerCtrlReg (
UINTN Val
);
VOID
EFIAPI
ArmArchTimerSetCompareVal (
IN UINT64 Val
);
#endif // __ARM_V7_ARCH_TIMER_LIB_H__

62
ArmPkg/Include/Library/DefaultExceptionHandlerLib.h
View File

@ -1,31 +1,31 @@
/** @file
Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __DEFAULT_EXCEPTION_HANDLER_LIB_H__
#define __DEFAULT_EXCEPTION_HANDLER_LIB_H__
/**
This is the default action to take on an unexpected exception
@param ExceptionType Type of the exception
@param SystemContext Register state at the time of the Exception
**/
VOID
DefaultExceptionHandler (
IN EFI_EXCEPTION_TYPE ExceptionType,
IN OUT EFI_SYSTEM_CONTEXT SystemContext
);
#endif
/** @file
Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __DEFAULT_EXCEPTION_HANDLER_LIB_H__
#define __DEFAULT_EXCEPTION_HANDLER_LIB_H__
/**
This is the default action to take on an unexpected exception
@param ExceptionType Type of the exception
@param SystemContext Register state at the time of the Exception
**/
VOID
DefaultExceptionHandler (
IN EFI_EXCEPTION_TYPE ExceptionType,
IN OUT EFI_SYSTEM_CONTEXT SystemContext
);
#endif

200
ArmPkg/Include/Library/SemihostLib.h
View File

@ -1,100 +1,100 @@
/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __SEMIHOSTING_H__
#define __SEMIHOSTING_H__
/*
*
* Please refer to ARM RVDS 3.0 Compiler and Libraries Guide for more information
* about the semihosting interface.
*
*/
#define SEMIHOST_FILE_MODE_READ (0 << 2)
#define SEMIHOST_FILE_MODE_WRITE (1 << 2)
#define SEMIHOST_FILE_MODE_APPEND (2 << 2)
#define SEMIHOST_FILE_MODE_CREATE (1 << 1)
#define SEMIHOST_FILE_MODE_BINARY (1 << 0)
#define SEMIHOST_FILE_MODE_ASCII (0 << 0)
BOOLEAN
SemihostConnectionSupported (
VOID
);
RETURN_STATUS
SemihostFileOpen (
IN CHAR8 *FileName,
IN UINT32 Mode,
OUT UINT32 *FileHandle
);
RETURN_STATUS
SemihostFileSeek (
IN UINT32 FileHandle,
IN UINT32 Offset
);
RETURN_STATUS
SemihostFileRead (
IN UINT32 FileHandle,
IN OUT UINT32 *Length,
OUT VOID *Buffer
);
RETURN_STATUS
SemihostFileWrite (
IN UINT32 FileHandle,
IN OUT UINT32 *Length,
IN VOID *Buffer
);
RETURN_STATUS
SemihostFileClose (
IN UINT32 FileHandle
);
RETURN_STATUS
SemihostFileLength (
IN UINT32 FileHandle,
OUT UINT32 *Length
);
RETURN_STATUS
SemihostFileRemove (
IN CHAR8 *FileName
);
CHAR8
SemihostReadCharacter (
VOID
);
VOID
SemihostWriteCharacter (
IN CHAR8 Character
);
VOID
SemihostWriteString (
IN CHAR8 *String
);
UINT32
SemihostSystem (
IN CHAR8 *CommandLine
);
#endif // __SEMIHOSTING_H__
/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __SEMIHOSTING_H__
#define __SEMIHOSTING_H__
/*
*
* Please refer to ARM RVDS 3.0 Compiler and Libraries Guide for more information
* about the semihosting interface.
*
*/
#define SEMIHOST_FILE_MODE_READ (0 << 2)
#define SEMIHOST_FILE_MODE_WRITE (1 << 2)
#define SEMIHOST_FILE_MODE_APPEND (2 << 2)
#define SEMIHOST_FILE_MODE_CREATE (1 << 1)
#define SEMIHOST_FILE_MODE_BINARY (1 << 0)
#define SEMIHOST_FILE_MODE_ASCII (0 << 0)
BOOLEAN
SemihostConnectionSupported (
VOID
);
RETURN_STATUS
SemihostFileOpen (
IN CHAR8 *FileName,
IN UINT32 Mode,
OUT UINT32 *FileHandle
);
RETURN_STATUS
SemihostFileSeek (
IN UINT32 FileHandle,
IN UINT32 Offset
);
RETURN_STATUS
SemihostFileRead (
IN UINT32 FileHandle,
IN OUT UINT32 *Length,
OUT VOID *Buffer
);
RETURN_STATUS
SemihostFileWrite (
IN UINT32 FileHandle,
IN OUT UINT32 *Length,
IN VOID *Buffer
);
RETURN_STATUS
SemihostFileClose (
IN UINT32 FileHandle
);
RETURN_STATUS
SemihostFileLength (
IN UINT32 FileHandle,
OUT UINT32 *Length
);
RETURN_STATUS
SemihostFileRemove (
IN CHAR8 *FileName
);
CHAR8
SemihostReadCharacter (
VOID
);
VOID
SemihostWriteCharacter (
IN CHAR8 Character
);
VOID
SemihostWriteString (
IN CHAR8 *String
);
UINT32
SemihostSystem (
IN CHAR8 *CommandLine
);
#endif // __SEMIHOSTING_H__

1330
ArmPkg/Include/Library/UncachedMemoryAllocationLib.h
View File

File diff suppressed because it is too large Load Diff

250
ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c
View File

@ -1,125 +1,125 @@
/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <Base.h>
#include <Library/ArmLib.h>
#include <Library/PcdLib.h>
VOID
CacheRangeOperation (
IN VOID *Start,
IN UINTN Length,
IN CACHE_OPERATION CacheOperation,
IN LINE_OPERATION LineOperation
)
{
UINTN ArmCacheLineLength = ArmDataCacheLineLength();
UINTN ArmCacheLineAlignmentMask = ArmCacheLineLength - 1;
UINTN ArmCacheOperationThreshold = PcdGet32(PcdArmCacheOperationThreshold);
if ((CacheOperation != NULL) && (Length >= ArmCacheOperationThreshold)) {
CacheOperation ();
} else {
// Align address (rounding down)
UINTN AlignedAddress = (UINTN)Start - ((UINTN)Start & ArmCacheLineAlignmentMask);
UINTN EndAddress = (UINTN)Start + Length;
// Perform the line operation on an address in each cache line
while (AlignedAddress < EndAddress) {
LineOperation(AlignedAddress);
AlignedAddress += ArmCacheLineLength;
}
}
}
VOID
EFIAPI
InvalidateInstructionCache (
VOID
)
{
ArmCleanDataCache();
ArmInvalidateInstructionCache();
}
VOID
EFIAPI
InvalidateDataCache (
VOID
)
{
ArmInvalidateDataCache();
}
VOID *
EFIAPI
InvalidateInstructionCacheRange (
IN VOID *Address,
IN UINTN Length
)
{
CacheRangeOperation (Address, Length, ArmCleanDataCacheToPoU, ArmCleanDataCacheEntryByMVA);
ArmInvalidateInstructionCache ();
return Address;
}
VOID
EFIAPI
WriteBackInvalidateDataCache (
VOID
)
{
ArmCleanInvalidateDataCache();
}
VOID *
EFIAPI
WriteBackInvalidateDataCacheRange (
IN VOID *Address,
IN UINTN Length
)
{
CacheRangeOperation(Address, Length, ArmCleanInvalidateDataCache, ArmCleanInvalidateDataCacheEntryByMVA);
return Address;
}
VOID
EFIAPI
WriteBackDataCache (
VOID
)
{
ArmCleanDataCache();
}
VOID *
EFIAPI
WriteBackDataCacheRange (
IN VOID *Address,
IN UINTN Length
)
{
CacheRangeOperation(Address, Length, ArmCleanDataCache, ArmCleanDataCacheEntryByMVA);
return Address;
}
VOID *
EFIAPI
InvalidateDataCacheRange (
IN VOID *Address,
IN UINTN Length
)
{
CacheRangeOperation(Address, Length, NULL, ArmInvalidateDataCacheEntryByMVA);
return Address;
}
/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <Base.h>
#include <Library/ArmLib.h>
#include <Library/PcdLib.h>
VOID
CacheRangeOperation (
IN VOID *Start,
IN UINTN Length,
IN CACHE_OPERATION CacheOperation,
IN LINE_OPERATION LineOperation
)
{
UINTN ArmCacheLineLength = ArmDataCacheLineLength();
UINTN ArmCacheLineAlignmentMask = ArmCacheLineLength - 1;
UINTN ArmCacheOperationThreshold = PcdGet32(PcdArmCacheOperationThreshold);
if ((CacheOperation != NULL) && (Length >= ArmCacheOperationThreshold)) {
CacheOperation ();
} else {
// Align address (rounding down)
UINTN AlignedAddress = (UINTN)Start - ((UINTN)Start & ArmCacheLineAlignmentMask);
UINTN EndAddress = (UINTN)Start + Length;
// Perform the line operation on an address in each cache line
while (AlignedAddress < EndAddress) {
LineOperation(AlignedAddress);
AlignedAddress += ArmCacheLineLength;
}
}
}
VOID
EFIAPI
InvalidateInstructionCache (
VOID
)
{
ArmCleanDataCache();
ArmInvalidateInstructionCache();
}
VOID
EFIAPI
InvalidateDataCache (
VOID
)
{
ArmInvalidateDataCache();
}
VOID *
EFIAPI
InvalidateInstructionCacheRange (
IN VOID *Address,
IN UINTN Length
)
{
CacheRangeOperation (Address, Length, ArmCleanDataCacheToPoU, ArmCleanDataCacheEntryByMVA);
ArmInvalidateInstructionCache ();
return Address;
}
VOID
EFIAPI
WriteBackInvalidateDataCache (
VOID
)
{
ArmCleanInvalidateDataCache();
}
VOID *
EFIAPI
WriteBackInvalidateDataCacheRange (
IN VOID *Address,
IN UINTN Length
)
{
CacheRangeOperation(Address, Length, ArmCleanInvalidateDataCache, ArmCleanInvalidateDataCacheEntryByMVA);
return Address;
}
VOID
EFIAPI
WriteBackDataCache (
VOID
)
{
ArmCleanDataCache();
}
VOID *
EFIAPI
WriteBackDataCacheRange (
IN VOID *Address,
IN UINTN Length
)
{
CacheRangeOperation(Address, Length, ArmCleanDataCache, ArmCleanDataCacheEntryByMVA);
return Address;
}
VOID *
EFIAPI
InvalidateDataCacheRange (
IN VOID *Address,
IN UINTN Length
)
{
CacheRangeOperation(Address, Length, NULL, ArmInvalidateDataCacheEntryByMVA);
return Address;
}

74
ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
View File

@ -1,37 +1,37 @@
#/** @file
# Semihosting serail port lib
#
# Copyright (c) 2008, Apple Inc. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = ArmCacheMaintenanceLib
FILE_GUID = 1A20BE1F-33AD-450C-B49A-7123FCA8B7F9
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = CacheMaintenanceLib
[Sources.common]
ArmCacheMaintenanceLib.c
[Packages]
ArmPkg/ArmPkg.dec
MdePkg/MdePkg.dec
[LibraryClasses]
ArmLib
BaseLib
[FixedPcd]
gArmTokenSpaceGuid.PcdArmCacheOperationThreshold
#/** @file
# Semihosting serail port lib
#
# Copyright (c) 2008, Apple Inc. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = ArmCacheMaintenanceLib
FILE_GUID = 1A20BE1F-33AD-450C-B49A-7123FCA8B7F9
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = CacheMaintenanceLib
[Sources.common]
ArmCacheMaintenanceLib.c
[Packages]
ArmPkg/ArmPkg.dec
MdePkg/MdePkg.dec
[LibraryClasses]
ArmLib
BaseLib
[FixedPcd]
gArmTokenSpaceGuid.PcdArmCacheOperationThreshold

2
ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf
View File

@ -47,4 +47,4 @@
[Pcd]
[Depex]
gEfiCpuArchProtocolGuid
gEfiCpuArchProtocolGuid

266
ArmPkg/Library/ArmLib/Arm11/Arm11LibMem.c
View File

@ -1,133 +1,133 @@
/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <Chipset/ARM1176JZ-S.h>
#include <Library/ArmLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/MemoryAllocationLib.h>
VOID
FillTranslationTable (
IN UINT32 *TranslationTable,
IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryRegion
)
{
UINT32 *Entry;
UINTN Sections;
UINTN Index;
UINT32 Attributes;
UINT32 PhysicalBase = MemoryRegion->PhysicalBase;
switch (MemoryRegion->Attributes) {
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(0);
break;
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0);
break;
case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);
break;
case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:
Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(1);
break;
case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:
Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(1);
break;
case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:
Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(1);
break;
default:
Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);
break;
}
Entry = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);
Sections = ((( MemoryRegion->Length - 1 ) / TT_DESCRIPTOR_SECTION_SIZE ) + 1 );
for (Index = 0; Index < Sections; Index++)
{
*Entry++ = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;
PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;
}
}
VOID
EFIAPI
ArmConfigureMmu (
IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,
OUT VOID **TranslationTableBase OPTIONAL,
OUT UINTN *TranslationTableSize OPTIONAL
)
{
VOID *TranslationTable;
// Allocate pages for translation table.
TranslationTable = AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_SIZE + TRANSLATION_TABLE_ALIGNMENT));
TranslationTable = (VOID *)(((UINTN)TranslationTable + TRANSLATION_TABLE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_ALIGNMENT_MASK);
if (TranslationTableBase != NULL) {
*TranslationTableBase = TranslationTable;
}
if (TranslationTableBase != NULL) {
*TranslationTableSize = TRANSLATION_TABLE_SIZE;
}
ZeroMem(TranslationTable, TRANSLATION_TABLE_SIZE);
ArmCleanInvalidateDataCache();
ArmInvalidateInstructionCache();
ArmInvalidateTlb();
ArmDisableDataCache();
ArmDisableInstructionCache();
ArmDisableMmu();
// Make sure nothing sneaked into the cache
ArmCleanInvalidateDataCache();
ArmInvalidateInstructionCache();
while (MemoryTable->Length != 0) {
FillTranslationTable(TranslationTable, MemoryTable);
MemoryTable++;
}
ArmSetTTBR0(TranslationTable);
ArmSetDomainAccessControl(DOMAIN_ACCESS_CONTROL_NONE(15) |
DOMAIN_ACCESS_CONTROL_NONE(14) |
DOMAIN_ACCESS_CONTROL_NONE(13) |
DOMAIN_ACCESS_CONTROL_NONE(12) |
DOMAIN_ACCESS_CONTROL_NONE(11) |
DOMAIN_ACCESS_CONTROL_NONE(10) |
DOMAIN_ACCESS_CONTROL_NONE( 9) |
DOMAIN_ACCESS_CONTROL_NONE( 8) |
DOMAIN_ACCESS_CONTROL_NONE( 7) |
DOMAIN_ACCESS_CONTROL_NONE( 6) |
DOMAIN_ACCESS_CONTROL_NONE( 5) |
DOMAIN_ACCESS_CONTROL_NONE( 4) |
DOMAIN_ACCESS_CONTROL_NONE( 3) |
DOMAIN_ACCESS_CONTROL_NONE( 2) |
DOMAIN_ACCESS_CONTROL_NONE( 1) |
DOMAIN_ACCESS_CONTROL_MANAGER(0));
ArmEnableInstructionCache();
ArmEnableDataCache();
ArmEnableMmu();
}
/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <Chipset/ARM1176JZ-S.h>
#include <Library/ArmLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/MemoryAllocationLib.h>
VOID
FillTranslationTable (
IN UINT32 *TranslationTable,
IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryRegion
)
{
UINT32 *Entry;
UINTN Sections;
UINTN Index;
UINT32 Attributes;
UINT32 PhysicalBase = MemoryRegion->PhysicalBase;
switch (MemoryRegion->Attributes) {
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(0);
break;
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0);
break;
case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);
break;
case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:
Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(1);
break;
case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:
Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(1);
break;
case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:
Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(1);
break;
default:
Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);
break;
}
Entry = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);
Sections = ((( MemoryRegion->Length - 1 ) / TT_DESCRIPTOR_SECTION_SIZE ) + 1 );
for (Index = 0; Index < Sections; Index++)
{
*Entry++ = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;
PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;
}
}
VOID
EFIAPI
ArmConfigureMmu (
IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,
OUT VOID **TranslationTableBase OPTIONAL,
OUT UINTN *TranslationTableSize OPTIONAL
)
{
VOID *TranslationTable;
// Allocate pages for translation table.
TranslationTable = AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_SIZE + TRANSLATION_TABLE_ALIGNMENT));
TranslationTable = (VOID *)(((UINTN)TranslationTable + TRANSLATION_TABLE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_ALIGNMENT_MASK);
if (TranslationTableBase != NULL) {
*TranslationTableBase = TranslationTable;
}
if (TranslationTableBase != NULL) {
*TranslationTableSize = TRANSLATION_TABLE_SIZE;
}
ZeroMem(TranslationTable, TRANSLATION_TABLE_SIZE);
ArmCleanInvalidateDataCache();
ArmInvalidateInstructionCache();
ArmInvalidateTlb();
ArmDisableDataCache();
ArmDisableInstructionCache();
ArmDisableMmu();
// Make sure nothing sneaked into the cache
ArmCleanInvalidateDataCache();
ArmInvalidateInstructionCache();
while (MemoryTable->Length != 0) {
FillTranslationTable(TranslationTable, MemoryTable);
MemoryTable++;
}
ArmSetTTBR0(TranslationTable);
ArmSetDomainAccessControl(DOMAIN_ACCESS_CONTROL_NONE(15) |
DOMAIN_ACCESS_CONTROL_NONE(14) |
DOMAIN_ACCESS_CONTROL_NONE(13) |
DOMAIN_ACCESS_CONTROL_NONE(12) |
DOMAIN_ACCESS_CONTROL_NONE(11) |
DOMAIN_ACCESS_CONTROL_NONE(10) |
DOMAIN_ACCESS_CONTROL_NONE( 9) |
DOMAIN_ACCESS_CONTROL_NONE( 8) |
DOMAIN_ACCESS_CONTROL_NONE( 7) |
DOMAIN_ACCESS_CONTROL_NONE( 6) |
DOMAIN_ACCESS_CONTROL_NONE( 5) |
DOMAIN_ACCESS_CONTROL_NONE( 4) |
DOMAIN_ACCESS_CONTROL_NONE( 3) |
DOMAIN_ACCESS_CONTROL_NONE( 2) |
DOMAIN_ACCESS_CONTROL_NONE( 1) |
DOMAIN_ACCESS_CONTROL_MANAGER(0));
ArmEnableInstructionCache();
ArmEnableDataCache();
ArmEnableMmu();
}

524
ArmPkg/Library/ArmLib/Arm11/Arm11Support.S
View File

@ -1,262 +1,262 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
# Copyright (c) 2011, ARM Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
#include <AsmMacroIoLib.h>
.text
.align 2
GCC_ASM_EXPORT(ArmDisableCachesAndMmu)
GCC_ASM_EXPORT(ArmInvalidateInstructionAndDataTlb)
GCC_ASM_EXPORT(ArmCleanInvalidateDataCache)
GCC_ASM_EXPORT(ArmCleanDataCache)
GCC_ASM_EXPORT(ArmInvalidateDataCache)
GCC_ASM_EXPORT(ArmInvalidateInstructionCache)
GCC_ASM_EXPORT(ArmInvalidateDataCacheEntryByMVA)
GCC_ASM_EXPORT(ArmCleanDataCacheEntryByMVA)
GCC_ASM_EXPORT(ArmCleanInvalidateDataCacheEntryByMVA)
GCC_ASM_EXPORT(ArmEnableMmu)
GCC_ASM_EXPORT(ArmDisableMmu)
GCC_ASM_EXPORT(ArmMmuEnabled)
GCC_ASM_EXPORT(ArmEnableDataCache)
GCC_ASM_EXPORT(ArmDisableDataCache)
GCC_ASM_EXPORT(ArmEnableInstructionCache)
GCC_ASM_EXPORT(ArmDisableInstructionCache)
GCC_ASM_EXPORT(ArmEnableBranchPrediction)
GCC_ASM_EXPORT(ArmDisableBranchPrediction)
GCC_ASM_EXPORT(ArmDataMemoryBarrier)
GCC_ASM_EXPORT(ArmDataSyncronizationBarrier)
GCC_ASM_EXPORT(ArmInstructionSynchronizationBarrier)
GCC_ASM_EXPORT(ArmSetLowVectors)
GCC_ASM_EXPORT(ArmSetHighVectors)
GCC_ASM_EXPORT(ArmIsMpCore)
GCC_ASM_EXPORT(ArmCallWFI)
GCC_ASM_EXPORT(ArmReadMpidr)
GCC_ASM_EXPORT(ArmUpdateTranslationTableEntry)
GCC_ASM_EXPORT(ArmEnableFiq)
GCC_ASM_EXPORT(ArmDisableFiq)
GCC_ASM_EXPORT(ArmEnableInterrupts)
GCC_ASM_EXPORT(ArmDisableInterrupts)
GCC_ASM_EXPORT (ArmEnableVFP)
Arm11PartNumberMask: .word 0xFFF0
Arm11PartNumber: .word 0xB020
.set DC_ON, (0x1<<2)
.set IC_ON, (0x1<<12)
.set XP_ON, (0x1<<23)
.set CTRL_M_BIT, (1 << 0)
.set CTRL_C_BIT, (1 << 2)
.set CTRL_I_BIT, (1 << 12)
ASM_PFX(ArmDisableCachesAndMmu):
mrc p15, 0, r0, c1, c0, 0 @ Get control register
bic r0, r0, #CTRL_M_BIT @ Disable MMU
bic r0, r0, #CTRL_C_BIT @ Disable D Cache
bic r0, r0, #CTRL_I_BIT @ Disable I Cache
mcr p15, 0, r0, c1, c0, 0 @ Write control register
bx LR
ASM_PFX(ArmInvalidateInstructionAndDataTlb):
mcr p15, 0, r0, c8, c7, 0 @ Invalidate Inst TLB and Data TLB
bx lr
ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line
bx lr
ASM_PFX(ArmCleanDataCacheEntryByMVA):
mcr p15, 0, r0, c7, c10, 1 @clean single data cache line
bx lr
ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
mcr p15, 0, r0, c7, c14, 1 @clean and invalidate single data cache line
bx lr
ASM_PFX(ArmCleanDataCache):
mcr p15, 0, r0, c7, c10, 0 @ clean entire data cache
bx lr
ASM_PFX(ArmCleanInvalidateDataCache):
mcr p15, 0, r0, c7, c14, 0 @ clean and invalidate entire data cache
bx lr
ASM_PFX(ArmInvalidateDataCache):
mcr p15, 0, r0, c7, c6, 0 @ invalidate entire data cache
bx lr
ASM_PFX(ArmInvalidateInstructionCache):
mcr p15, 0, r0, c7, c5, 0 @invalidate entire instruction cache
mov R0,#0
mcr p15,0,R0,c7,c5,4 @Flush Prefetch buffer
bx lr
ASM_PFX(ArmEnableMmu):
mrc p15,0,R0,c1,c0,0
orr R0,R0,#1
mcr p15,0,R0,c1,c0,0
bx LR
ASM_PFX(ArmMmuEnabled):
mrc p15,0,R0,c1,c0,0
and R0,R0,#1
bx LR
ASM_PFX(ArmDisableMmu):
mrc p15,0,R0,c1,c0,0
bic R0,R0,#1
mcr p15,0,R0,c1,c0,0
mov R0,#0
mcr p15,0,R0,c7,c10,4 @Data synchronization barrier
mov R0,#0
mcr p15,0,R0,c7,c5,4 @Flush Prefetch buffer
bx LR
ASM_PFX(ArmEnableDataCache):
LoadConstantToReg(DC_ON, R1) @ldr R1,=DC_ON
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
orr R0,R0,R1 @Set C bit
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
bx LR
ASM_PFX(ArmDisableDataCache):
LoadConstantToReg(DC_ON, R1) @ldr R1,=DC_ON
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
bic R0,R0,R1 @Clear C bit
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
bx LR
ASM_PFX(ArmEnableInstructionCache):
ldr R1,=IC_ON
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
orr R0,R0,R1 @Set I bit
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
bx LR
ASM_PFX(ArmDisableInstructionCache):
ldr R1,=IC_ON
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
bic R0,R0,R1 @Clear I bit.
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
bx LR
ASM_PFX(ArmEnableBranchPrediction):
mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #0x00000800
mcr p15, 0, r0, c1, c0, 0
bx LR
ASM_PFX(ArmDisableBranchPrediction):
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x00000800
mcr p15, 0, r0, c1, c0, 0
bx LR
ASM_PFX(ArmDataMemoryBarrier):
mov R0, #0
mcr P15, #0, R0, C7, C10, #5
bx LR
ASM_PFX(ArmDataSyncronizationBarrier):
mov R0, #0
mcr P15, #0, R0, C7, C10, #4
bx LR
ASM_PFX(ArmInstructionSynchronizationBarrier):
mov R0, #0
mcr P15, #0, R0, C7, C5, #4
bx LR
ASM_PFX(ArmSetLowVectors):
mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
bic r0, r0, #0x00002000 @ clear V bit
mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
bx LR
ASM_PFX(ArmSetHighVectors):
mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
orr r0, r0, #0x00002000 @ clear V bit
mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
bx LR
ASM_PFX(ArmIsMpCore):
push { r1 }
mrc p15, 0, r0, c0, c0, 0
# Extract Part Number to check it is an ARM11MP core (0xB02)
LoadConstantToReg (Arm11PartNumberMask, r1)
and r0, r0, r1
LoadConstantToReg (Arm11PartNumber, r1)
cmp r0, r1
movne r0, #0
pop { r1 }
bx lr
ASM_PFX(ArmCallWFI):
wfi
bx lr
ASM_PFX(ArmReadMpidr):
mrc p15, 0, r0, c0, c0, 5 @ read MPIDR
bx lr
ASM_PFX(ArmEnableFiq):
mrs R0,CPSR
bic R0,R0,#0x40 @Enable FIQ interrupts
msr CPSR_c,R0
bx LR
ASM_PFX(ArmDisableFiq):
mrs R0,CPSR
orr R1,R0,#0x40 @Disable FIQ interrupts
msr CPSR_c,R1
tst R0,#0x80
moveq R0,#1
movne R0,#0
bx LR
ASM_PFX(ArmEnableInterrupts):
mrs R0,CPSR
bic R0,R0,#0x80 @Enable IRQ interrupts
msr CPSR_c,R0
bx LR
ASM_PFX(ArmDisableInterrupts):
mrs R0,CPSR
orr R1,R0,#0x80 @Disable IRQ interrupts
msr CPSR_c,R1
tst R0,#0x80
moveq R0,#1
movne R0,#0
bx LR
ASM_PFX(ArmEnableVFP):
# Read CPACR (Coprocessor Access Control Register)
mrc p15, 0, r0, c1, c0, 2
# Enable VPF access (Full Access to CP10, CP11) (V* instructions)
orr r0, r0, #0x00f00000
# Write back CPACR (Coprocessor Access Control Register)
mcr p15, 0, r0, c1, c0, 2
# Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
mov r0, #0x40000000
#TODO: Fixme - need compilation flag
#fmxr FPEXC, r0
bx lr
ASM_FUNCTION_REMOVE_IF_UNREFERENCED
#------------------------------------------------------------------------------
#
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
# Copyright (c) 2011, ARM Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
#include <AsmMacroIoLib.h>
.text
.align 2
GCC_ASM_EXPORT(ArmDisableCachesAndMmu)
GCC_ASM_EXPORT(ArmInvalidateInstructionAndDataTlb)
GCC_ASM_EXPORT(ArmCleanInvalidateDataCache)
GCC_ASM_EXPORT(ArmCleanDataCache)
GCC_ASM_EXPORT(ArmInvalidateDataCache)
GCC_ASM_EXPORT(ArmInvalidateInstructionCache)
GCC_ASM_EXPORT(ArmInvalidateDataCacheEntryByMVA)
GCC_ASM_EXPORT(ArmCleanDataCacheEntryByMVA)
GCC_ASM_EXPORT(ArmCleanInvalidateDataCacheEntryByMVA)
GCC_ASM_EXPORT(ArmEnableMmu)
GCC_ASM_EXPORT(ArmDisableMmu)
GCC_ASM_EXPORT(ArmMmuEnabled)
GCC_ASM_EXPORT(ArmEnableDataCache)
GCC_ASM_EXPORT(ArmDisableDataCache)
GCC_ASM_EXPORT(ArmEnableInstructionCache)
GCC_ASM_EXPORT(ArmDisableInstructionCache)
GCC_ASM_EXPORT(ArmEnableBranchPrediction)
GCC_ASM_EXPORT(ArmDisableBranchPrediction)
GCC_ASM_EXPORT(ArmDataMemoryBarrier)
GCC_ASM_EXPORT(ArmDataSyncronizationBarrier)
GCC_ASM_EXPORT(ArmInstructionSynchronizationBarrier)
GCC_ASM_EXPORT(ArmSetLowVectors)
GCC_ASM_EXPORT(ArmSetHighVectors)
GCC_ASM_EXPORT(ArmIsMpCore)
GCC_ASM_EXPORT(ArmCallWFI)
GCC_ASM_EXPORT(ArmReadMpidr)
GCC_ASM_EXPORT(ArmUpdateTranslationTableEntry)
GCC_ASM_EXPORT(ArmEnableFiq)
GCC_ASM_EXPORT(ArmDisableFiq)
GCC_ASM_EXPORT(ArmEnableInterrupts)
GCC_ASM_EXPORT(ArmDisableInterrupts)
GCC_ASM_EXPORT (ArmEnableVFP)
Arm11PartNumberMask: .word 0xFFF0
Arm11PartNumber: .word 0xB020
.set DC_ON, (0x1<<2)
.set IC_ON, (0x1<<12)
.set XP_ON, (0x1<<23)
.set CTRL_M_BIT, (1 << 0)
.set CTRL_C_BIT, (1 << 2)
.set CTRL_I_BIT, (1 << 12)
ASM_PFX(ArmDisableCachesAndMmu):
mrc p15, 0, r0, c1, c0, 0 @ Get control register
bic r0, r0, #CTRL_M_BIT @ Disable MMU
bic r0, r0, #CTRL_C_BIT @ Disable D Cache
bic r0, r0, #CTRL_I_BIT @ Disable I Cache
mcr p15, 0, r0, c1, c0, 0 @ Write control register
bx LR
ASM_PFX(ArmInvalidateInstructionAndDataTlb):
mcr p15, 0, r0, c8, c7, 0 @ Invalidate Inst TLB and Data TLB
bx lr
ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line
bx lr
ASM_PFX(ArmCleanDataCacheEntryByMVA):
mcr p15, 0, r0, c7, c10, 1 @clean single data cache line
bx lr
ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
mcr p15, 0, r0, c7, c14, 1 @clean and invalidate single data cache line
bx lr
ASM_PFX(ArmCleanDataCache):
mcr p15, 0, r0, c7, c10, 0 @ clean entire data cache
bx lr
ASM_PFX(ArmCleanInvalidateDataCache):
mcr p15, 0, r0, c7, c14, 0 @ clean and invalidate entire data cache
bx lr
ASM_PFX(ArmInvalidateDataCache):
mcr p15, 0, r0, c7, c6, 0 @ invalidate entire data cache
bx lr
ASM_PFX(ArmInvalidateInstructionCache):
mcr p15, 0, r0, c7, c5, 0 @invalidate entire instruction cache
mov R0,#0
mcr p15,0,R0,c7,c5,4 @Flush Prefetch buffer
bx lr
ASM_PFX(ArmEnableMmu):
mrc p15,0,R0,c1,c0,0
orr R0,R0,#1
mcr p15,0,R0,c1,c0,0
bx LR
ASM_PFX(ArmMmuEnabled):
mrc p15,0,R0,c1,c0,0
and R0,R0,#1
bx LR
ASM_PFX(ArmDisableMmu):
mrc p15,0,R0,c1,c0,0
bic R0,R0,#1
mcr p15,0,R0,c1,c0,0
mov R0,#0
mcr p15,0,R0,c7,c10,4 @Data synchronization barrier
mov R0,#0
mcr p15,0,R0,c7,c5,4 @Flush Prefetch buffer
bx LR
ASM_PFX(ArmEnableDataCache):
LoadConstantToReg(DC_ON, R1) @ldr R1,=DC_ON
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
orr R0,R0,R1 @Set C bit
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
bx LR
ASM_PFX(ArmDisableDataCache):
LoadConstantToReg(DC_ON, R1) @ldr R1,=DC_ON
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
bic R0,R0,R1 @Clear C bit
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
bx LR
ASM_PFX(ArmEnableInstructionCache):
ldr R1,=IC_ON
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
orr R0,R0,R1 @Set I bit
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
bx LR
ASM_PFX(ArmDisableInstructionCache):
ldr R1,=IC_ON
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
bic R0,R0,R1 @Clear I bit.
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
bx LR
ASM_PFX(ArmEnableBranchPrediction):
mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #0x00000800
mcr p15, 0, r0, c1, c0, 0
bx LR
ASM_PFX(ArmDisableBranchPrediction):
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x00000800
mcr p15, 0, r0, c1, c0, 0
bx LR
ASM_PFX(ArmDataMemoryBarrier):
mov R0, #0
mcr P15, #0, R0, C7, C10, #5
bx LR
ASM_PFX(ArmDataSyncronizationBarrier):
mov R0, #0
mcr P15, #0, R0, C7, C10, #4
bx LR
ASM_PFX(ArmInstructionSynchronizationBarrier):
mov R0, #0
mcr P15, #0, R0, C7, C5, #4
bx LR
ASM_PFX(ArmSetLowVectors):
mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
bic r0, r0, #0x00002000 @ clear V bit
mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
bx LR
ASM_PFX(ArmSetHighVectors):
mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
orr r0, r0, #0x00002000 @ clear V bit
mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
bx LR
ASM_PFX(ArmIsMpCore):
push { r1 }
mrc p15, 0, r0, c0, c0, 0
# Extract Part Number to check it is an ARM11MP core (0xB02)
LoadConstantToReg (Arm11PartNumberMask, r1)
and r0, r0, r1
LoadConstantToReg (Arm11PartNumber, r1)
cmp r0, r1
movne r0, #0
pop { r1 }
bx lr
ASM_PFX(ArmCallWFI):
wfi
bx lr
ASM_PFX(ArmReadMpidr):
mrc p15, 0, r0, c0, c0, 5 @ read MPIDR
bx lr
ASM_PFX(ArmEnableFiq):
mrs R0,CPSR
bic R0,R0,#0x40 @Enable FIQ interrupts
msr CPSR_c,R0
bx LR
ASM_PFX(ArmDisableFiq):
mrs R0,CPSR
orr R1,R0,#0x40 @Disable FIQ interrupts
msr CPSR_c,R1
tst R0,#0x80
moveq R0,#1
movne R0,#0
bx LR
ASM_PFX(ArmEnableInterrupts):
mrs R0,CPSR
bic R0,R0,#0x80 @Enable IRQ interrupts
msr CPSR_c,R0
bx LR
ASM_PFX(ArmDisableInterrupts):
mrs R0,CPSR
orr R1,R0,#0x80 @Disable IRQ interrupts
msr CPSR_c,R1
tst R0,#0x80
moveq R0,#1
movne R0,#0
bx LR
ASM_PFX(ArmEnableVFP):
# Read CPACR (Coprocessor Access Control Register)
mrc p15, 0, r0, c1, c0, 2
# Enable VPF access (Full Access to CP10, CP11) (V* instructions)
orr r0, r0, #0x00f00000
# Write back CPACR (Coprocessor Access Control Register)
mcr p15, 0, r0, c1, c0, 2
# Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
mov r0, #0x40000000
#TODO: Fixme - need compilation flag
#fmxr FPEXC, r0
bx lr
ASM_FUNCTION_REMOVE_IF_UNREFERENCED

314
ArmPkg/Library/ArmLib/Arm11/Arm11Support.asm
View File

@ -1,157 +1,157 @@
//------------------------------------------------------------------------------
//
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
//------------------------------------------------------------------------------
EXPORT ArmCleanInvalidateDataCache
EXPORT ArmCleanDataCache
EXPORT ArmInvalidateDataCache
EXPORT ArmInvalidateInstructionCache
EXPORT ArmInvalidateDataCacheEntryByMVA
EXPORT ArmCleanDataCacheEntryByMVA
EXPORT ArmCleanInvalidateDataCacheEntryByMVA
EXPORT ArmEnableMmu
EXPORT ArmDisableMmu
EXPORT ArmMmuEnabled
EXPORT ArmEnableDataCache
EXPORT ArmDisableDataCache
EXPORT ArmEnableInstructionCache
EXPORT ArmDisableInstructionCache
EXPORT ArmEnableBranchPrediction
EXPORT ArmDisableBranchPrediction
EXPORT ArmDataMemoryBarrier
EXPORT ArmDataSyncronizationBarrier
EXPORT ArmInstructionSynchronizationBarrier
DC_ON EQU ( 0x1:SHL:2 )
IC_ON EQU ( 0x1:SHL:12 )
XP_ON EQU ( 0x1:SHL:23 )
AREA ArmCacheLib, CODE, READONLY
PRESERVE8
ArmInvalidateDataCacheEntryByMVA
mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
bx lr
ArmCleanDataCacheEntryByMVA
mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line
bx lr
ArmCleanInvalidateDataCacheEntryByMVA
mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
bx lr
ArmCleanDataCache
mcr p15, 0, r0, c7, c10, 0 ; clean entire data cache
bx lr
ArmCleanInvalidateDataCache
mcr p15, 0, r0, c7, c14, 0 ; clean and invalidate entire data cache
bx lr
ArmInvalidateDataCache
mcr p15, 0, r0, c7, c6, 0 ; invalidate entire data cache
bx lr
ArmInvalidateInstructionCache
mcr p15, 0, r0, c7, c5, 0 ;invalidate entire instruction cache
mov R0,#0
mcr p15,0,R0,c7,c5,4 ;Flush Prefetch buffer
bx lr
ArmEnableMmu
mrc p15,0,R0,c1,c0,0
orr R0,R0,#1
mcr p15,0,R0,c1,c0,0
bx LR
ArmMmuEnabled
mrc p15,0,R0,c1,c0,0
and R0,R0,#1
bx LR
ArmDisableMmu
mrc p15,0,R0,c1,c0,0
bic R0,R0,#1
mcr p15,0,R0,c1,c0,0
mov R0,#0
mcr p15,0,R0,c7,c10,4 ;Data synchronization barrier
mov R0,#0
mcr p15,0,R0,c7,c5,4 ;Flush Prefetch buffer
bx LR
ArmEnableDataCache
LDR R1,=DC_ON
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
ORR R0,R0,R1 ;Set C bit
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
BX LR
ArmDisableDataCache
LDR R1,=DC_ON
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
BIC R0,R0,R1 ;Clear C bit
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
BX LR
ArmEnableInstructionCache
LDR R1,=IC_ON
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
ORR R0,R0,R1 ;Set I bit
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
BX LR
ArmDisableInstructionCache
LDR R1,=IC_ON
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
BIC R0,R0,R1 ;Clear I bit.
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
BX LR
ArmEnableBranchPrediction
mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #0x00000800
mcr p15, 0, r0, c1, c0, 0
bx LR
ArmDisableBranchPrediction
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x00000800
mcr p15, 0, r0, c1, c0, 0
bx LR
ASM_PFX(ArmDataMemoryBarrier):
mov R0, #0
mcr P15, #0, R0, C7, C10, #5
bx LR
ASM_PFX(ArmDataSyncronizationBarrier):
mov R0, #0
mcr P15, #0, R0, C7, C10, #4
bx LR
ASM_PFX(ArmInstructionSynchronizationBarrier):
MOV R0, #0
MCR P15, #0, R0, C7, C5, #4
bx LR
END
//------------------------------------------------------------------------------
//
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
//------------------------------------------------------------------------------
EXPORT ArmCleanInvalidateDataCache
EXPORT ArmCleanDataCache
EXPORT ArmInvalidateDataCache
EXPORT ArmInvalidateInstructionCache
EXPORT ArmInvalidateDataCacheEntryByMVA
EXPORT ArmCleanDataCacheEntryByMVA
EXPORT ArmCleanInvalidateDataCacheEntryByMVA
EXPORT ArmEnableMmu
EXPORT ArmDisableMmu
EXPORT ArmMmuEnabled
EXPORT ArmEnableDataCache
EXPORT ArmDisableDataCache
EXPORT ArmEnableInstructionCache
EXPORT ArmDisableInstructionCache
EXPORT ArmEnableBranchPrediction
EXPORT ArmDisableBranchPrediction
EXPORT ArmDataMemoryBarrier
EXPORT ArmDataSyncronizationBarrier
EXPORT ArmInstructionSynchronizationBarrier
DC_ON EQU ( 0x1:SHL:2 )
IC_ON EQU ( 0x1:SHL:12 )
XP_ON EQU ( 0x1:SHL:23 )
AREA ArmCacheLib, CODE, READONLY
PRESERVE8
ArmInvalidateDataCacheEntryByMVA
mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
bx lr
ArmCleanDataCacheEntryByMVA
mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line
bx lr
ArmCleanInvalidateDataCacheEntryByMVA
mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
bx lr
ArmCleanDataCache
mcr p15, 0, r0, c7, c10, 0 ; clean entire data cache
bx lr
ArmCleanInvalidateDataCache
mcr p15, 0, r0, c7, c14, 0 ; clean and invalidate entire data cache
bx lr
ArmInvalidateDataCache
mcr p15, 0, r0, c7, c6, 0 ; invalidate entire data cache
bx lr
ArmInvalidateInstructionCache
mcr p15, 0, r0, c7, c5, 0 ;invalidate entire instruction cache
mov R0,#0
mcr p15,0,R0,c7,c5,4 ;Flush Prefetch buffer
bx lr
ArmEnableMmu
mrc p15,0,R0,c1,c0,0
orr R0,R0,#1
mcr p15,0,R0,c1,c0,0
bx LR
ArmMmuEnabled
mrc p15,0,R0,c1,c0,0
and R0,R0,#1
bx LR
ArmDisableMmu
mrc p15,0,R0,c1,c0,0
bic R0,R0,#1
mcr p15,0,R0,c1,c0,0
mov R0,#0
mcr p15,0,R0,c7,c10,4 ;Data synchronization barrier
mov R0,#0
mcr p15,0,R0,c7,c5,4 ;Flush Prefetch buffer
bx LR
ArmEnableDataCache
LDR R1,=DC_ON
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
ORR R0,R0,R1 ;Set C bit
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
BX LR
ArmDisableDataCache
LDR R1,=DC_ON
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
BIC R0,R0,R1 ;Clear C bit
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
BX LR
ArmEnableInstructionCache
LDR R1,=IC_ON
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
ORR R0,R0,R1 ;Set I bit
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
BX LR
ArmDisableInstructionCache
LDR R1,=IC_ON
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
BIC R0,R0,R1 ;Clear I bit.
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
BX LR
ArmEnableBranchPrediction
mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #0x00000800
mcr p15, 0, r0, c1, c0, 0
bx LR
ArmDisableBranchPrediction
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x00000800
mcr p15, 0, r0, c1, c0, 0
bx LR
ASM_PFX(ArmDataMemoryBarrier):
mov R0, #0
mcr P15, #0, R0, C7, C10, #5
bx LR
ASM_PFX(ArmDataSyncronizationBarrier):
mov R0, #0
mcr P15, #0, R0, C7, C10, #4
bx LR
ASM_PFX(ArmInstructionSynchronizationBarrier):
MOV R0, #0
MCR P15, #0, R0, C7, C5, #4
bx LR
END

262
ArmPkg/Library/ArmLib/Arm9/Arm9Lib.c
View File

@ -1,131 +1,131 @@
/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <Chipset/ARM926EJ-S.h>
#include <Library/ArmLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/DebugLib.h>
VOID
FillTranslationTable (
IN UINT32 *TranslationTable,
IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryRegion
)
{
UINT32 *Entry;
UINTN Sections;
UINTN Index;
UINT32 Attributes;
UINT32 PhysicalBase = MemoryRegion->PhysicalBase;
switch (MemoryRegion->Attributes) {
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK;
break;
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH;
break;
case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
Attributes = TT_DESCRIPTOR_SECTION_UNCACHED_UNBUFFERED;
break;
case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:
case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:
case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:
ASSERT(0); // Trustzone is not supported on ARMv5
default:
Attributes = TT_DESCRIPTOR_SECTION_UNCACHED_UNBUFFERED;
break;
}
Entry = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);
Sections = MemoryRegion->Length / TT_DESCRIPTOR_SECTION_SIZE;
// The current code does not support memory region size that is not aligned on TT_DESCRIPTOR_SECTION_SIZE boundary
ASSERT (MemoryRegion->Length % TT_DESCRIPTOR_SECTION_SIZE == 0);
for (Index = 0; Index < Sections; Index++)
{
*Entry++ = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;
PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;
}
}
VOID
EFIAPI
ArmConfigureMmu (
IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,
OUT VOID **TranslationTableBase OPTIONAL,
OUT UINTN *TranslationTableSize OPTIONAL
)
{
VOID *TranslationTable;
// Allocate pages for translation table.
TranslationTable = AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_SIZE + TRANSLATION_TABLE_ALIGNMENT));
TranslationTable = (VOID *)(((UINTN)TranslationTable + TRANSLATION_TABLE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_ALIGNMENT_MASK);
if (TranslationTableBase != NULL) {
*TranslationTableBase = TranslationTable;
}
if (TranslationTableBase != NULL) {
*TranslationTableSize = TRANSLATION_TABLE_SIZE;
}
ZeroMem(TranslationTable, TRANSLATION_TABLE_SIZE);
ArmCleanInvalidateDataCache();
ArmInvalidateInstructionCache();
ArmInvalidateTlb();
ArmDisableDataCache();
ArmDisableInstructionCache();
ArmDisableMmu();
// Make sure nothing sneaked into the cache
ArmCleanInvalidateDataCache();
ArmInvalidateInstructionCache();
while (MemoryTable->Length != 0) {
FillTranslationTable(TranslationTable, MemoryTable);
MemoryTable++;
}
ArmSetTTBR0(TranslationTable);
ArmSetDomainAccessControl(DOMAIN_ACCESS_CONTROL_NONE(15) |
DOMAIN_ACCESS_CONTROL_NONE(14) |
DOMAIN_ACCESS_CONTROL_NONE(13) |
DOMAIN_ACCESS_CONTROL_NONE(12) |
DOMAIN_ACCESS_CONTROL_NONE(11) |
DOMAIN_ACCESS_CONTROL_NONE(10) |
DOMAIN_ACCESS_CONTROL_NONE( 9) |
DOMAIN_ACCESS_CONTROL_NONE( 8) |
DOMAIN_ACCESS_CONTROL_NONE( 7) |
DOMAIN_ACCESS_CONTROL_NONE( 6) |
DOMAIN_ACCESS_CONTROL_NONE( 5) |
DOMAIN_ACCESS_CONTROL_NONE( 4) |
DOMAIN_ACCESS_CONTROL_NONE( 3) |
DOMAIN_ACCESS_CONTROL_NONE( 2) |
DOMAIN_ACCESS_CONTROL_NONE( 1) |
DOMAIN_ACCESS_CONTROL_MANAGER(0));
ArmEnableInstructionCache();
ArmEnableDataCache();
ArmEnableMmu();
}
/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <Chipset/ARM926EJ-S.h>
#include <Library/ArmLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/DebugLib.h>
VOID
FillTranslationTable (
IN UINT32 *TranslationTable,
IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryRegion
)
{
UINT32 *Entry;
UINTN Sections;
UINTN Index;
UINT32 Attributes;
UINT32 PhysicalBase = MemoryRegion->PhysicalBase;
switch (MemoryRegion->Attributes) {
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK;
break;
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH;
break;
case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
Attributes = TT_DESCRIPTOR_SECTION_UNCACHED_UNBUFFERED;
break;
case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:
case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:
case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:
ASSERT(0); // Trustzone is not supported on ARMv5
default:
Attributes = TT_DESCRIPTOR_SECTION_UNCACHED_UNBUFFERED;
break;
}
Entry = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);
Sections = MemoryRegion->Length / TT_DESCRIPTOR_SECTION_SIZE;
// The current code does not support memory region size that is not aligned on TT_DESCRIPTOR_SECTION_SIZE boundary
ASSERT (MemoryRegion->Length % TT_DESCRIPTOR_SECTION_SIZE == 0);
for (Index = 0; Index < Sections; Index++)
{
*Entry++ = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;
PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;
}
}
VOID
EFIAPI
ArmConfigureMmu (
IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,
OUT VOID **TranslationTableBase OPTIONAL,
OUT UINTN *TranslationTableSize OPTIONAL
)
{
VOID *TranslationTable;
// Allocate pages for translation table.
TranslationTable = AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_SIZE + TRANSLATION_TABLE_ALIGNMENT));
TranslationTable = (VOID *)(((UINTN)TranslationTable + TRANSLATION_TABLE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_ALIGNMENT_MASK);
if (TranslationTableBase != NULL) {
*TranslationTableBase = TranslationTable;
}
if (TranslationTableBase != NULL) {
*TranslationTableSize = TRANSLATION_TABLE_SIZE;
}
ZeroMem(TranslationTable, TRANSLATION_TABLE_SIZE);
ArmCleanInvalidateDataCache();
ArmInvalidateInstructionCache();
ArmInvalidateTlb();
ArmDisableDataCache();
ArmDisableInstructionCache();
ArmDisableMmu();
// Make sure nothing sneaked into the cache
ArmCleanInvalidateDataCache();
ArmInvalidateInstructionCache();
while (MemoryTable->Length != 0) {
FillTranslationTable(TranslationTable, MemoryTable);
MemoryTable++;
}
ArmSetTTBR0(TranslationTable);
ArmSetDomainAccessControl(DOMAIN_ACCESS_CONTROL_NONE(15) |
DOMAIN_ACCESS_CONTROL_NONE(14) |
DOMAIN_ACCESS_CONTROL_NONE(13) |
DOMAIN_ACCESS_CONTROL_NONE(12) |
DOMAIN_ACCESS_CONTROL_NONE(11) |
DOMAIN_ACCESS_CONTROL_NONE(10) |
DOMAIN_ACCESS_CONTROL_NONE( 9) |
DOMAIN_ACCESS_CONTROL_NONE( 8) |
DOMAIN_ACCESS_CONTROL_NONE( 7) |
DOMAIN_ACCESS_CONTROL_NONE( 6) |
DOMAIN_ACCESS_CONTROL_NONE( 5) |
DOMAIN_ACCESS_CONTROL_NONE( 4) |
DOMAIN_ACCESS_CONTROL_NONE( 3) |
DOMAIN_ACCESS_CONTROL_NONE( 2) |
DOMAIN_ACCESS_CONTROL_NONE( 1) |
DOMAIN_ACCESS_CONTROL_MANAGER(0));
ArmEnableInstructionCache();
ArmEnableDataCache();
ArmEnableMmu();
}

306
ArmPkg/Library/ArmLib/Arm9/Arm9Support.S
View File

@ -1,153 +1,153 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
.text
.align 2
GCC_ASM_EXPORT(ArmCleanInvalidateDataCache)
GCC_ASM_EXPORT(ArmCleanDataCache)
GCC_ASM_EXPORT(ArmInvalidateDataCache)
GCC_ASM_EXPORT(ArmInvalidateInstructionCache)
GCC_ASM_EXPORT(ArmInvalidateDataCacheEntryByMVA)
GCC_ASM_EXPORT(ArmCleanDataCacheEntryByMVA)
GCC_ASM_EXPORT(ArmCleanInvalidateDataCacheEntryByMVA)
GCC_ASM_EXPORT(ArmEnableMmu)
GCC_ASM_EXPORT(ArmDisableMmu)
GCC_ASM_EXPORT(ArmMmuEnabled)
GCC_ASM_EXPORT(ArmEnableDataCache)
GCC_ASM_EXPORT(ArmDisableDataCache)
GCC_ASM_EXPORT(ArmEnableInstructionCache)
GCC_ASM_EXPORT(ArmDisableInstructionCache)
GCC_ASM_EXPORT(ArmEnableBranchPrediction)
GCC_ASM_EXPORT(ArmDisableBranchPrediction)
GCC_ASM_EXPORT(ArmDataMemoryBarrier)
GCC_ASM_EXPORT(ArmDataSyncronizationBarrier)
GCC_ASM_EXPORT(ArmInstructionSynchronizationBarrier)
.set DC_ON, (1<<2)
.set IC_ON, (1<<12)
#------------------------------------------------------------------------------
ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
mcr p15, 0, r0, c7, c6, 1 @ invalidate single data cache line
bx lr
ASM_PFX(ArmCleanDataCacheEntryByMVA):
mcr p15, 0, r0, c7, c10, 1 @ clean single data cache line
bx lr
ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate single data cache line
bx lr
ASM_PFX(ArmEnableInstructionCache):
ldr r1,=IC_ON
mrc p15,0,r0,c1,c0,0 @Read control register configuration data
orr r0,r0,r1 @Set I bit
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
bx LR
ASM_PFX(ArmDisableInstructionCache):
ldr r1,=IC_ON
mrc p15,0,r0,c1,c0,0 @Read control register configuration data
bic r0,r0,r1 @Clear I bit.
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
bx LR
ASM_PFX(ArmInvalidateInstructionCache):
mov r0,#0
mcr p15,0,r0,c7,c5,0 @Invalidate entire Instruction cache.
@Also flushes the branch target cache.
mov r0,#0
mcr p15,0,r0,c7,c10,4 @Data write buffer
bx LR
ASM_PFX(ArmEnableMmu):
mrc p15,0,R0,c1,c0,0
orr R0,R0,#1
mcr p15,0,R0,c1,c0,0
bx LR
ASM_PFX(ArmMmuEnabled):
mrc p15,0,R0,c1,c0,0
and R0,R0,#1
bx LR
ASM_PFX(ArmDisableMmu):
mrc p15,0,R0,c1,c0,0
bic R0,R0,#1
mcr p15,0,R0,c1,c0,0
mov R0,#0
mcr p15,0,R0,c7,c10,4 @Drain write buffer
bx LR
ASM_PFX(ArmEnableDataCache):
ldr R1,=DC_ON
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
orr R0,R0,R1 @Set C bit
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
bx LR
ASM_PFX(ArmDisableDataCache):
ldr R1,=DC_ON
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
bic R0,R0,R1 @Clear C bit
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
bx LR
ASM_PFX(ArmCleanDataCache):
mrc p15,0,r15,c7,c10,3
bne ASM_PFX(ArmCleanDataCache)
mov R0,#0
mcr p15,0,R0,c7,c10,4 @Drain write buffer
bx LR
ASM_PFX(ArmInvalidateDataCache):
mov R0,#0
mcr p15,0,R0,c7,c6,0 @Invalidate entire data cache
mov R0,#0
mcr p15,0,R0,c7,c10,4 @Drain write buffer
bx LR
ASM_PFX(ArmCleanInvalidateDataCache):
mrc p15,0,r15,c7,c14,3
bne ASM_PFX(ArmCleanInvalidateDataCache)
mov R0,#0
mcr p15,0,R0,c7,c10,4 @Drain write buffer
bx LR
ASM_PFX(ArmEnableBranchPrediction):
bx LR @Branch prediction is not supported.
ASM_PFX(ArmDisableBranchPrediction):
bx LR @Branch prediction is not supported.
ASM_PFX(ArmDataMemoryBarrier):
mov R0, #0
mcr P15, #0, R0, C7, C10, #5 @ check if this is OK?
bx LR
ASM_PFX(ArmDataSyncronizationBarrier):
mov R0, #0
mcr P15, #0, R0, C7, C10, #4 @ check if this is OK?
bx LR
ASM_PFX(ArmInstructionSynchronizationBarrier):
mov R0, #0
mcr P15, #0, R0, C7, C5, #4 @ check if this is OK?
bx LR
ASM_FUNCTION_REMOVE_IF_UNREFERENCED
#------------------------------------------------------------------------------
#
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
.text
.align 2
GCC_ASM_EXPORT(ArmCleanInvalidateDataCache)
GCC_ASM_EXPORT(ArmCleanDataCache)
GCC_ASM_EXPORT(ArmInvalidateDataCache)
GCC_ASM_EXPORT(ArmInvalidateInstructionCache)
GCC_ASM_EXPORT(ArmInvalidateDataCacheEntryByMVA)
GCC_ASM_EXPORT(ArmCleanDataCacheEntryByMVA)
GCC_ASM_EXPORT(ArmCleanInvalidateDataCacheEntryByMVA)
GCC_ASM_EXPORT(ArmEnableMmu)
GCC_ASM_EXPORT(ArmDisableMmu)
GCC_ASM_EXPORT(ArmMmuEnabled)
GCC_ASM_EXPORT(ArmEnableDataCache)
GCC_ASM_EXPORT(ArmDisableDataCache)
GCC_ASM_EXPORT(ArmEnableInstructionCache)
GCC_ASM_EXPORT(ArmDisableInstructionCache)
GCC_ASM_EXPORT(ArmEnableBranchPrediction)
GCC_ASM_EXPORT(ArmDisableBranchPrediction)
GCC_ASM_EXPORT(ArmDataMemoryBarrier)
GCC_ASM_EXPORT(ArmDataSyncronizationBarrier)
GCC_ASM_EXPORT(ArmInstructionSynchronizationBarrier)
.set DC_ON, (1<<2)
.set IC_ON, (1<<12)
#------------------------------------------------------------------------------
ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
mcr p15, 0, r0, c7, c6, 1 @ invalidate single data cache line
bx lr
ASM_PFX(ArmCleanDataCacheEntryByMVA):
mcr p15, 0, r0, c7, c10, 1 @ clean single data cache line
bx lr
ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate single data cache line
bx lr
ASM_PFX(ArmEnableInstructionCache):
ldr r1,=IC_ON
mrc p15,0,r0,c1,c0,0 @Read control register configuration data
orr r0,r0,r1 @Set I bit
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
bx LR
ASM_PFX(ArmDisableInstructionCache):
ldr r1,=IC_ON
mrc p15,0,r0,c1,c0,0 @Read control register configuration data
bic r0,r0,r1 @Clear I bit.
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
bx LR
ASM_PFX(ArmInvalidateInstructionCache):
mov r0,#0
mcr p15,0,r0,c7,c5,0 @Invalidate entire Instruction cache.
@Also flushes the branch target cache.
mov r0,#0
mcr p15,0,r0,c7,c10,4 @Data write buffer
bx LR
ASM_PFX(ArmEnableMmu):
mrc p15,0,R0,c1,c0,0
orr R0,R0,#1
mcr p15,0,R0,c1,c0,0
bx LR
ASM_PFX(ArmMmuEnabled):
mrc p15,0,R0,c1,c0,0
and R0,R0,#1
bx LR
ASM_PFX(ArmDisableMmu):
mrc p15,0,R0,c1,c0,0
bic R0,R0,#1
mcr p15,0,R0,c1,c0,0
mov R0,#0
mcr p15,0,R0,c7,c10,4 @Drain write buffer
bx LR
ASM_PFX(ArmEnableDataCache):
ldr R1,=DC_ON
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
orr R0,R0,R1 @Set C bit
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
bx LR
ASM_PFX(ArmDisableDataCache):
ldr R1,=DC_ON
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
bic R0,R0,R1 @Clear C bit
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
bx LR
ASM_PFX(ArmCleanDataCache):
mrc p15,0,r15,c7,c10,3
bne ASM_PFX(ArmCleanDataCache)
mov R0,#0
mcr p15,0,R0,c7,c10,4 @Drain write buffer
bx LR
ASM_PFX(ArmInvalidateDataCache):
mov R0,#0
mcr p15,0,R0,c7,c6,0 @Invalidate entire data cache
mov R0,#0
mcr p15,0,R0,c7,c10,4 @Drain write buffer
bx LR
ASM_PFX(ArmCleanInvalidateDataCache):
mrc p15,0,r15,c7,c14,3
bne ASM_PFX(ArmCleanInvalidateDataCache)
mov R0,#0
mcr p15,0,R0,c7,c10,4 @Drain write buffer
bx LR
ASM_PFX(ArmEnableBranchPrediction):
bx LR @Branch prediction is not supported.
ASM_PFX(ArmDisableBranchPrediction):
bx LR @Branch prediction is not supported.
ASM_PFX(ArmDataMemoryBarrier):
mov R0, #0
mcr P15, #0, R0, C7, C10, #5 @ check if this is OK?
bx LR
ASM_PFX(ArmDataSyncronizationBarrier):
mov R0, #0
mcr P15, #0, R0, C7, C10, #4 @ check if this is OK?
bx LR
ASM_PFX(ArmInstructionSynchronizationBarrier):
mov R0, #0
mcr P15, #0, R0, C7, C5, #4 @ check if this is OK?
bx LR
ASM_FUNCTION_REMOVE_IF_UNREFERENCED

306
ArmPkg/Library/ArmLib/Arm9/Arm9Support.asm
View File

@ -1,153 +1,153 @@
//------------------------------------------------------------------------------
//
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
//------------------------------------------------------------------------------
EXPORT ArmCleanInvalidateDataCache
EXPORT ArmCleanDataCache
EXPORT ArmInvalidateDataCache
EXPORT ArmInvalidateInstructionCache
EXPORT ArmInvalidateDataCacheEntryByMVA
EXPORT ArmCleanDataCacheEntryByMVA
EXPORT ArmCleanInvalidateDataCacheEntryByMVA
EXPORT ArmEnableMmu
EXPORT ArmDisableMmu
EXPORT ArmMmuEnabled
EXPORT ArmEnableDataCache
EXPORT ArmDisableDataCache
EXPORT ArmEnableInstructionCache
EXPORT ArmDisableInstructionCache
EXPORT ArmEnableBranchPrediction
EXPORT ArmDisableBranchPrediction
EXPORT ArmDataMemoryBarrier
EXPORT ArmDataSyncronizationBarrier
EXPORT ArmInstructionSynchronizationBarrier
DC_ON EQU ( 0x1:SHL:2 )
IC_ON EQU ( 0x1:SHL:12 )
AREA ArmCacheLib, CODE, READONLY
PRESERVE8
ArmInvalidateDataCacheEntryByMVA
MCR p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
BX lr
ArmCleanDataCacheEntryByMVA
MCR p15, 0, r0, c7, c10, 1 ; clean single data cache line
BX lr
ArmCleanInvalidateDataCacheEntryByMVA
MCR p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
BX lr
ArmEnableInstructionCache
LDR R1,=IC_ON
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
ORR R0,R0,R1 ;Set I bit
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
BX LR
ArmDisableInstructionCache
LDR R1,=IC_ON
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
BIC R0,R0,R1 ;Clear I bit.
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
BX LR
ArmInvalidateInstructionCache
MOV R0,#0
MCR p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache
MOV R0,#0
MCR p15,0,R0,c7,c10,4 ;Drain write buffer
BX LR
ArmEnableMmu
mrc p15,0,R0,c1,c0,0
orr R0,R0,#1
mcr p15,0,R0,c1,c0,0
bx LR
ArmMmuEnabled
mrc p15,0,R0,c1,c0,0
and R0,R0,#1
bx LR
ArmDisableMmu
mrc p15,0,R0,c1,c0,0
bic R0,R0,#1
mcr p15,0,R0,c1,c0,0
mov R0,#0
mcr p15,0,R0,c7,c10,4 ;Drain write buffer
bx LR
ArmEnableDataCache
LDR R1,=DC_ON
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
ORR R0,R0,R1 ;Set C bit
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
BX LR
ArmDisableDataCache
LDR R1,=DC_ON
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
BIC R0,R0,R1 ;Clear C bit
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
BX LR
ArmCleanDataCache
MRC p15,0,r15,c7,c10,3
BNE ArmCleanDataCache
MOV R0,#0
MCR p15,0,R0,c7,c10,4 ;Drain write buffer
BX LR
ArmInvalidateDataCache
MOV R0,#0
MCR p15,0,R0,c7,c6,0 ;Invalidate entire data cache
MOV R0,#0
MCR p15,0,R0,c7,c10,4 ;Drain write buffer
BX LR
ArmCleanInvalidateDataCache
MRC p15,0,r15,c7,c14,3
BNE ArmCleanInvalidateDataCache
MOV R0,#0
MCR p15,0,R0,c7,c10,4 ;Drain write buffer
BX LR
ArmEnableBranchPrediction
bx LR ;Branch prediction is not supported.
ArmDisableBranchPrediction
bx LR ;Branch prediction is not supported.
ASM_PFX(ArmDataMemoryBarrier):
mov R0, #0
mcr P15, #0, R0, C7, C10, #5 ; Check to see if this is correct
bx LR
ASM_PFX(ArmDataSyncronizationBarrier):
mov R0, #0
mcr P15, #0, R0, C7, C10, #4 ; Check to see if this is correct
bx LR
ASM_PFX(ArmInstructionSynchronizationBarrier):
MOV R0, #0
MCR P15, #0, R0, C7, C5, #4 ; Check to see if this is correct
bx LR
END
//------------------------------------------------------------------------------
//
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
//------------------------------------------------------------------------------
EXPORT ArmCleanInvalidateDataCache
EXPORT ArmCleanDataCache
EXPORT ArmInvalidateDataCache
EXPORT ArmInvalidateInstructionCache
EXPORT ArmInvalidateDataCacheEntryByMVA
EXPORT ArmCleanDataCacheEntryByMVA
EXPORT ArmCleanInvalidateDataCacheEntryByMVA
EXPORT ArmEnableMmu
EXPORT ArmDisableMmu
EXPORT ArmMmuEnabled
EXPORT ArmEnableDataCache
EXPORT ArmDisableDataCache
EXPORT ArmEnableInstructionCache
EXPORT ArmDisableInstructionCache
EXPORT ArmEnableBranchPrediction
EXPORT ArmDisableBranchPrediction
EXPORT ArmDataMemoryBarrier
EXPORT ArmDataSyncronizationBarrier
EXPORT ArmInstructionSynchronizationBarrier
DC_ON EQU ( 0x1:SHL:2 )
IC_ON EQU ( 0x1:SHL:12 )
AREA ArmCacheLib, CODE, READONLY
PRESERVE8
ArmInvalidateDataCacheEntryByMVA
MCR p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
BX lr
ArmCleanDataCacheEntryByMVA
MCR p15, 0, r0, c7, c10, 1 ; clean single data cache line
BX lr
ArmCleanInvalidateDataCacheEntryByMVA
MCR p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
BX lr
ArmEnableInstructionCache
LDR R1,=IC_ON
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
ORR R0,R0,R1 ;Set I bit
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
BX LR
ArmDisableInstructionCache
LDR R1,=IC_ON
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
BIC R0,R0,R1 ;Clear I bit.
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
BX LR
ArmInvalidateInstructionCache
MOV R0,#0
MCR p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache
MOV R0,#0
MCR p15,0,R0,c7,c10,4 ;Drain write buffer
BX LR
ArmEnableMmu
mrc p15,0,R0,c1,c0,0
orr R0,R0,#1
mcr p15,0,R0,c1,c0,0
bx LR
ArmMmuEnabled
mrc p15,0,R0,c1,c0,0
and R0,R0,#1
bx LR
ArmDisableMmu
mrc p15,0,R0,c1,c0,0
bic R0,R0,#1
mcr p15,0,R0,c1,c0,0
mov R0,#0
mcr p15,0,R0,c7,c10,4 ;Drain write buffer
bx LR
ArmEnableDataCache
LDR R1,=DC_ON
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
ORR R0,R0,R1 ;Set C bit
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
BX LR
ArmDisableDataCache
LDR R1,=DC_ON
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
BIC R0,R0,R1 ;Clear C bit
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
BX LR
ArmCleanDataCache
MRC p15,0,r15,c7,c10,3
BNE ArmCleanDataCache
MOV R0,#0
MCR p15,0,R0,c7,c10,4 ;Drain write buffer
BX LR
ArmInvalidateDataCache
MOV R0,#0
MCR p15,0,R0,c7,c6,0 ;Invalidate entire data cache
MOV R0,#0
MCR p15,0,R0,c7,c10,4 ;Drain write buffer
BX LR
ArmCleanInvalidateDataCache
MRC p15,0,r15,c7,c14,3
BNE ArmCleanInvalidateDataCache
MOV R0,#0
MCR p15,0,R0,c7,c10,4 ;Drain write buffer
BX LR
ArmEnableBranchPrediction
bx LR ;Branch prediction is not supported.
ArmDisableBranchPrediction
bx LR ;Branch prediction is not supported.
ASM_PFX(ArmDataMemoryBarrier):
mov R0, #0
mcr P15, #0, R0, C7, C10, #5 ; Check to see if this is correct
bx LR
ASM_PFX(ArmDataSyncronizationBarrier):
mov R0, #0
mcr P15, #0, R0, C7, C10, #4 ; Check to see if this is correct
bx LR
ASM_PFX(ArmInstructionSynchronizationBarrier):
MOV R0, #0
MCR P15, #0, R0, C7, C5, #4 ; Check to see if this is correct
bx LR
END

550
ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimer.c
View File

@ -1,275 +1,275 @@
/** @file
*
* Copyright (c) 2011, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
* which accompanies this distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#include <Uefi.h>
#include <Chipset/ArmV7.h>
#include <Library/BaseMemoryLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/ArmLib.h>
#include <Library/BaseLib.h>
#include <Library/DebugLib.h>
#include "ArmV7Lib.h"
#include "ArmLibPrivate.h"
#include <Library/ArmV7ArchTimerLib.h>
VOID
EFIAPI
ArmArchTimerReadReg (
IN ARM_ARCH_TIMER_REGS Reg,
OUT VOID *DstBuf
)
{
// Check if the Generic/Architecture timer is implemented
if (ArmIsArchTimerImplemented ()) {
switch (Reg) {
case CntFrq:
*((UINTN *)DstBuf) = ArmReadCntFrq ();
break;
case CntPct:
*((UINT64 *)DstBuf) = ArmReadCntPct ();
break;
case CntkCtl:
*((UINTN *)DstBuf) = ArmReadCntkCtl();
break;
case CntpTval:
*((UINTN *)DstBuf) = ArmReadCntpTval ();
break;
case CntpCtl:
*((UINTN *)DstBuf) = ArmReadCntpCtl ();
break;
case CntvTval:
*((UINTN *)DstBuf) = ArmReadCntvTval ();
break;
case CntvCtl:
*((UINTN *)DstBuf) = ArmReadCntvCtl ();
break;
case CntvCt:
*((UINT64 *)DstBuf) = ArmReadCntvCt ();
break;
case CntpCval:
*((UINT64 *)DstBuf) = ArmReadCntpCval ();
break;
case CntvCval:
*((UINT64 *)DstBuf) = ArmReadCntvCval ();
break;
case CntvOff:
*((UINT64 *)DstBuf) = ArmReadCntvOff ();
break;
case CnthCtl:
case CnthpTval:
case CnthpCtl:
case CnthpCval:
DEBUG ((EFI_D_ERROR, "The register is related to Hypervisor Mode. Can't perform requested operation\n "));
break;
default:
DEBUG ((EFI_D_ERROR, "Unknown ARM Generic Timer register %x. \n ", Reg));
}
} else {
DEBUG ((EFI_D_ERROR, "Attempt to read ARM Generic Timer registers. But ARM Generic Timer extension is not implemented \n "));
ASSERT (0);
}
}
VOID
EFIAPI
ArmArchTimerWriteReg (
IN ARM_ARCH_TIMER_REGS Reg,
IN VOID *SrcBuf
)
{
// Check if the Generic/Architecture timer is implemented
if (ArmIsArchTimerImplemented ()) {
switch (Reg) {
case CntFrq:
ArmWriteCntFrq (*((UINTN *)SrcBuf));
break;
case CntPct:
DEBUG ((EFI_D_ERROR, "Can't write to Read Only Register: CNTPCT \n"));
break;
case CntkCtl:
ArmWriteCntkCtl (*((UINTN *)SrcBuf));
break;
case CntpTval:
ArmWriteCntpTval (*((UINTN *)SrcBuf));
break;
case CntpCtl:
ArmWriteCntpCtl (*((UINTN *)SrcBuf));
break;
case CntvTval:
ArmWriteCntvTval (*((UINTN *)SrcBuf));
break;
case CntvCtl:
ArmWriteCntvCtl (*((UINTN *)SrcBuf));
break;
case CntvCt:
DEBUG ((EFI_D_ERROR, "Can't write to Read Only Register: CNTVCT \n"));
break;
case CntpCval:
ArmWriteCntpCval (*((UINT64 *)SrcBuf) );
break;
case CntvCval:
ArmWriteCntvCval (*((UINT64 *)SrcBuf) );
break;
case CntvOff:
ArmWriteCntvOff (*((UINT64 *)SrcBuf));
break;
case CnthCtl:
case CnthpTval:
case CnthpCtl:
case CnthpCval:
DEBUG ((EFI_D_ERROR, "The register is related to Hypervisor Mode. Can't perform requested operation\n "));
break;
default:
DEBUG ((EFI_D_ERROR, "Unknown ARM Generic Timer register %x. \n ", Reg));
}
} else {
DEBUG ((EFI_D_ERROR, "Attempt to write to ARM Generic Timer registers. But ARM Generic Timer extension is not implemented \n "));
ASSERT (0);
}
}
VOID
EFIAPI
ArmArchTimerEnableTimer (
VOID
)
{
UINTN TimerCtrlReg;
ArmArchTimerReadReg (CntpCtl, (VOID *)&TimerCtrlReg);
TimerCtrlReg |= ARM_ARCH_TIMER_ENABLE;
ArmArchTimerWriteReg (CntpCtl, (VOID *)&TimerCtrlReg);
}
VOID
EFIAPI
ArmArchTimerDisableTimer (
VOID
)
{
UINTN TimerCtrlReg;
ArmArchTimerReadReg (CntpCtl, (VOID *)&TimerCtrlReg);
TimerCtrlReg &= ~ARM_ARCH_TIMER_ENABLE;
ArmArchTimerWriteReg (CntpCtl, (VOID *)&TimerCtrlReg);
}
VOID
EFIAPI
ArmArchTimerSetTimerFreq (
IN UINTN FreqInHz
)
{
ArmArchTimerWriteReg (CntFrq, (VOID *)&FreqInHz);
}
UINTN
EFIAPI
ArmArchTimerGetTimerFreq (
VOID
)
{
UINTN ArchTimerFreq = 0;
ArmArchTimerReadReg (CntFrq, (VOID *)&ArchTimerFreq);
return ArchTimerFreq;
}
UINTN
EFIAPI
ArmArchTimerGetTimerVal (
VOID
)
{
UINTN ArchTimerVal;
ArmArchTimerReadReg (CntpTval, (VOID *)&ArchTimerVal);
return ArchTimerVal;
}
VOID
EFIAPI
ArmArchTimerSetTimerVal (
IN UINTN Val
)
{
ArmArchTimerWriteReg (CntpTval, (VOID *)&Val);
}
UINT64
EFIAPI
ArmArchTimerGetSystemCount (
VOID
)
{
UINT64 SystemCount;
ArmArchTimerReadReg (CntPct, (VOID *)&SystemCount);
return SystemCount;
}
UINTN
EFIAPI
ArmArchTimerGetTimerCtrlReg (
VOID
)
{
UINTN Val;
ArmArchTimerReadReg (CntpCtl, (VOID *)&Val);
return Val;
}
VOID
EFIAPI
ArmArchTimerSetTimerCtrlReg (
UINTN Val
)
{
ArmArchTimerWriteReg (CntpCtl, (VOID *)&Val);
}
VOID
EFIAPI
ArmArchTimerSetCompareVal (
IN UINT64 Val
)
{
ArmArchTimerWriteReg (CntpCval, (VOID *)&Val);
}
/** @file
*
* Copyright (c) 2011, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
* which accompanies this distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#include <Uefi.h>
#include <Chipset/ArmV7.h>
#include <Library/BaseMemoryLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/ArmLib.h>
#include <Library/BaseLib.h>
#include <Library/DebugLib.h>
#include "ArmV7Lib.h"
#include "ArmLibPrivate.h"
#include <Library/ArmV7ArchTimerLib.h>
VOID
EFIAPI
ArmArchTimerReadReg (
IN ARM_ARCH_TIMER_REGS Reg,
OUT VOID *DstBuf
)
{
// Check if the Generic/Architecture timer is implemented
if (ArmIsArchTimerImplemented ()) {
switch (Reg) {
case CntFrq:
*((UINTN *)DstBuf) = ArmReadCntFrq ();
break;
case CntPct:
*((UINT64 *)DstBuf) = ArmReadCntPct ();
break;
case CntkCtl:
*((UINTN *)DstBuf) = ArmReadCntkCtl();
break;
case CntpTval:
*((UINTN *)DstBuf) = ArmReadCntpTval ();
break;
case CntpCtl:
*((UINTN *)DstBuf) = ArmReadCntpCtl ();
break;
case CntvTval:
*((UINTN *)DstBuf) = ArmReadCntvTval ();
break;
case CntvCtl:
*((UINTN *)DstBuf) = ArmReadCntvCtl ();
break;
case CntvCt:
*((UINT64 *)DstBuf) = ArmReadCntvCt ();
break;
case CntpCval:
*((UINT64 *)DstBuf) = ArmReadCntpCval ();
break;
case CntvCval:
*((UINT64 *)DstBuf) = ArmReadCntvCval ();
break;
case CntvOff:
*((UINT64 *)DstBuf) = ArmReadCntvOff ();
break;
case CnthCtl:
case CnthpTval:
case CnthpCtl:
case CnthpCval:
DEBUG ((EFI_D_ERROR, "The register is related to Hypervisor Mode. Can't perform requested operation\n "));
break;
default:
DEBUG ((EFI_D_ERROR, "Unknown ARM Generic Timer register %x. \n ", Reg));
}
} else {
DEBUG ((EFI_D_ERROR, "Attempt to read ARM Generic Timer registers. But ARM Generic Timer extension is not implemented \n "));
ASSERT (0);
}
}
VOID
EFIAPI
ArmArchTimerWriteReg (
IN ARM_ARCH_TIMER_REGS Reg,
IN VOID *SrcBuf
)
{
// Check if the Generic/Architecture timer is implemented
if (ArmIsArchTimerImplemented ()) {
switch (Reg) {
case CntFrq:
ArmWriteCntFrq (*((UINTN *)SrcBuf));
break;
case CntPct:
DEBUG ((EFI_D_ERROR, "Can't write to Read Only Register: CNTPCT \n"));
break;
case CntkCtl:
ArmWriteCntkCtl (*((UINTN *)SrcBuf));
break;
case CntpTval:
ArmWriteCntpTval (*((UINTN *)SrcBuf));
break;
case CntpCtl:
ArmWriteCntpCtl (*((UINTN *)SrcBuf));
break;
case CntvTval:
ArmWriteCntvTval (*((UINTN *)SrcBuf));
break;
case CntvCtl:
ArmWriteCntvCtl (*((UINTN *)SrcBuf));
break;
case CntvCt:
DEBUG ((EFI_D_ERROR, "Can't write to Read Only Register: CNTVCT \n"));
break;
case CntpCval:
ArmWriteCntpCval (*((UINT64 *)SrcBuf) );
break;
case CntvCval:
ArmWriteCntvCval (*((UINT64 *)SrcBuf) );
break;
case CntvOff:
ArmWriteCntvOff (*((UINT64 *)SrcBuf));
break;
case CnthCtl:
case CnthpTval:
case CnthpCtl:
case CnthpCval:
DEBUG ((EFI_D_ERROR, "The register is related to Hypervisor Mode. Can't perform requested operation\n "));
break;
default:
DEBUG ((EFI_D_ERROR, "Unknown ARM Generic Timer register %x. \n ", Reg));
}
} else {
DEBUG ((EFI_D_ERROR, "Attempt to write to ARM Generic Timer registers. But ARM Generic Timer extension is not implemented \n "));
ASSERT (0);
}
}
VOID
EFIAPI
ArmArchTimerEnableTimer (
VOID
)
{
UINTN TimerCtrlReg;
ArmArchTimerReadReg (CntpCtl, (VOID *)&TimerCtrlReg);
TimerCtrlReg |= ARM_ARCH_TIMER_ENABLE;
ArmArchTimerWriteReg (CntpCtl, (VOID *)&TimerCtrlReg);
}
VOID
EFIAPI
ArmArchTimerDisableTimer (
VOID
)
{
UINTN TimerCtrlReg;
ArmArchTimerReadReg (CntpCtl, (VOID *)&TimerCtrlReg);
TimerCtrlReg &= ~ARM_ARCH_TIMER_ENABLE;
ArmArchTimerWriteReg (CntpCtl, (VOID *)&TimerCtrlReg);
}
VOID
EFIAPI
ArmArchTimerSetTimerFreq (
IN UINTN FreqInHz
)
{
ArmArchTimerWriteReg (CntFrq, (VOID *)&FreqInHz);
}
UINTN
EFIAPI
ArmArchTimerGetTimerFreq (
VOID
)
{
UINTN ArchTimerFreq = 0;
ArmArchTimerReadReg (CntFrq, (VOID *)&ArchTimerFreq);
return ArchTimerFreq;
}
UINTN
EFIAPI
ArmArchTimerGetTimerVal (
VOID
)
{
UINTN ArchTimerVal;
ArmArchTimerReadReg (CntpTval, (VOID *)&ArchTimerVal);
return ArchTimerVal;
}
VOID
EFIAPI
ArmArchTimerSetTimerVal (
IN UINTN Val
)
{
ArmArchTimerWriteReg (CntpTval, (VOID *)&Val);
}
UINT64
EFIAPI
ArmArchTimerGetSystemCount (
VOID
)
{
UINT64 SystemCount;
ArmArchTimerReadReg (CntPct, (VOID *)&SystemCount);
return SystemCount;
}
UINTN
EFIAPI
ArmArchTimerGetTimerCtrlReg (
VOID
)
{
UINTN Val;
ArmArchTimerReadReg (CntpCtl, (VOID *)&Val);
return Val;
}
VOID
EFIAPI
ArmArchTimerSetTimerCtrlReg (
UINTN Val
)
{
ArmArchTimerWriteReg (CntpCtl, (VOID *)&Val);
}
VOID
EFIAPI
ArmArchTimerSetCompareVal (
IN UINT64 Val
)
{
ArmArchTimerWriteReg (CntpCval, (VOID *)&Val);
}

528
ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.c
View File

@ -1,264 +1,264 @@
/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <Uefi.h>
#include <Chipset/ArmV7.h>
#include <Library/ArmLib.h>
#include <Library/BaseLib.h>
#include <Library/IoLib.h>
#include "ArmV7Lib.h"
#include "ArmLibPrivate.h"
ARM_CACHE_TYPE
EFIAPI
ArmCacheType (
VOID
)
{
return ARM_CACHE_TYPE_WRITE_BACK;
}
ARM_CACHE_ARCHITECTURE
EFIAPI
ArmCacheArchitecture (
VOID
)
{
UINT32 CLIDR = ReadCLIDR ();
return (ARM_CACHE_ARCHITECTURE)CLIDR; // BugBug Fix Me
}
BOOLEAN
EFIAPI
ArmDataCachePresent (
VOID
)
{
UINT32 CLIDR = ReadCLIDR ();
if ((CLIDR & 0x2) == 0x2) {
// Instruction cache exists
return TRUE;
}
if ((CLIDR & 0x7) == 0x4) {
// Unified cache
return TRUE;
}
return FALSE;
}
UINTN
EFIAPI
ArmDataCacheSize (
VOID
)
{
UINT32 NumSets;
UINT32 Associativity;
UINT32 LineSize;
UINT32 CCSIDR = ReadCCSIDR (0);
LineSize = (1 << ((CCSIDR & 0x7) + 2));
Associativity = ((CCSIDR >> 3) & 0x3ff) + 1;
NumSets = ((CCSIDR >> 13) & 0x7fff) + 1;
// LineSize is in words (4 byte chunks)
return NumSets * Associativity * LineSize * 4;
}
UINTN
EFIAPI
ArmDataCacheAssociativity (
VOID
)
{
UINT32 CCSIDR = ReadCCSIDR (0);
return ((CCSIDR >> 3) & 0x3ff) + 1;
}
UINTN
ArmDataCacheSets (
VOID
)
{
UINT32 CCSIDR = ReadCCSIDR (0);
return ((CCSIDR >> 13) & 0x7fff) + 1;
}
UINTN
EFIAPI
ArmDataCacheLineLength (
VOID
)
{
UINT32 CCSIDR = ReadCCSIDR (0) & 7;
// * 4 converts to bytes
return (1 << (CCSIDR + 2)) * 4;
}
BOOLEAN
EFIAPI
ArmInstructionCachePresent (
VOID
)
{
UINT32 CLIDR = ReadCLIDR ();
if ((CLIDR & 1) == 1) {
// Instruction cache exists
return TRUE;
}
if ((CLIDR & 0x7) == 0x4) {
// Unified cache
return TRUE;
}
return FALSE;
}
UINTN
EFIAPI
ArmInstructionCacheSize (
VOID
)
{
UINT32 NumSets;
UINT32 Associativity;
UINT32 LineSize;
UINT32 CCSIDR = ReadCCSIDR (1);
LineSize = (1 << ((CCSIDR & 0x7) + 2));
Associativity = ((CCSIDR >> 3) & 0x3ff) + 1;
NumSets = ((CCSIDR >> 13) & 0x7fff) + 1;
// LineSize is in words (4 byte chunks)
return NumSets * Associativity * LineSize * 4;
}
UINTN
EFIAPI
ArmInstructionCacheAssociativity (
VOID
)
{
UINT32 CCSIDR = ReadCCSIDR (1);
return ((CCSIDR >> 3) & 0x3ff) + 1;
// return 4;
}
UINTN
EFIAPI
ArmInstructionCacheSets (
VOID
)
{
UINT32 CCSIDR = ReadCCSIDR (1);
return ((CCSIDR >> 13) & 0x7fff) + 1;
}
UINTN
EFIAPI
ArmInstructionCacheLineLength (
VOID
)
{
UINT32 CCSIDR = ReadCCSIDR (1) & 7;
// * 4 converts to bytes
return (1 << (CCSIDR + 2)) * 4;
// return 64;
}
VOID
ArmV7DataCacheOperation (
IN ARM_V7_CACHE_OPERATION DataCacheOperation
)
{
UINTN SavedInterruptState;
SavedInterruptState = ArmGetInterruptState ();
ArmDisableInterrupts ();
ArmV7AllDataCachesOperation (DataCacheOperation);
ArmDrainWriteBuffer ();
if (SavedInterruptState) {
ArmEnableInterrupts ();
}
}
VOID
ArmV7PoUDataCacheOperation (
IN ARM_V7_CACHE_OPERATION DataCacheOperation
)
{
UINTN SavedInterruptState;
SavedInterruptState = ArmGetInterruptState ();
ArmDisableInterrupts ();
ArmV7PerformPoUDataCacheOperation (DataCacheOperation);
ArmDrainWriteBuffer ();
if (SavedInterruptState) {
ArmEnableInterrupts ();
}
}
VOID
EFIAPI
ArmInvalidateDataCache (
VOID
)
{
ArmV7DataCacheOperation (ArmInvalidateDataCacheEntryBySetWay);
}
VOID
EFIAPI
ArmCleanInvalidateDataCache (
VOID
)
{
ArmV7DataCacheOperation (ArmCleanInvalidateDataCacheEntryBySetWay);
}
VOID
EFIAPI
ArmCleanDataCache (
VOID
)
{
ArmV7DataCacheOperation (ArmCleanDataCacheEntryBySetWay);
}
VOID
EFIAPI
ArmCleanDataCacheToPoU (
VOID
)
{
ArmV7PoUDataCacheOperation (ArmCleanDataCacheEntryBySetWay);
}
/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <Uefi.h>
#include <Chipset/ArmV7.h>
#include <Library/ArmLib.h>
#include <Library/BaseLib.h>
#include <Library/IoLib.h>
#include "ArmV7Lib.h"
#include "ArmLibPrivate.h"
ARM_CACHE_TYPE
EFIAPI
ArmCacheType (
VOID
)
{
return ARM_CACHE_TYPE_WRITE_BACK;
}
ARM_CACHE_ARCHITECTURE
EFIAPI
ArmCacheArchitecture (
VOID
)
{
UINT32 CLIDR = ReadCLIDR ();
return (ARM_CACHE_ARCHITECTURE)CLIDR; // BugBug Fix Me
}
BOOLEAN
EFIAPI
ArmDataCachePresent (
VOID
)
{
UINT32 CLIDR = ReadCLIDR ();
if ((CLIDR & 0x2) == 0x2) {
// Instruction cache exists
return TRUE;
}
if ((CLIDR & 0x7) == 0x4) {
// Unified cache
return TRUE;
}
return FALSE;
}
UINTN
EFIAPI
ArmDataCacheSize (
VOID
)
{
UINT32 NumSets;
UINT32 Associativity;
UINT32 LineSize;
UINT32 CCSIDR = ReadCCSIDR (0);
LineSize = (1 << ((CCSIDR & 0x7) + 2));
Associativity = ((CCSIDR >> 3) & 0x3ff) + 1;
NumSets = ((CCSIDR >> 13) & 0x7fff) + 1;
// LineSize is in words (4 byte chunks)
return NumSets * Associativity * LineSize * 4;
}
UINTN
EFIAPI
ArmDataCacheAssociativity (
VOID
)
{
UINT32 CCSIDR = ReadCCSIDR (0);
return ((CCSIDR >> 3) & 0x3ff) + 1;
}
UINTN
ArmDataCacheSets (
VOID
)
{
UINT32 CCSIDR = ReadCCSIDR (0);
return ((CCSIDR >> 13) & 0x7fff) + 1;
}
UINTN
EFIAPI
ArmDataCacheLineLength (
VOID
)
{
UINT32 CCSIDR = ReadCCSIDR (0) & 7;
// * 4 converts to bytes
return (1 << (CCSIDR + 2)) * 4;
}
BOOLEAN
EFIAPI
ArmInstructionCachePresent (
VOID
)
{
UINT32 CLIDR = ReadCLIDR ();
if ((CLIDR & 1) == 1) {
// Instruction cache exists
return TRUE;
}
if ((CLIDR & 0x7) == 0x4) {
// Unified cache
return TRUE;
}
return FALSE;
}
UINTN
EFIAPI
ArmInstructionCacheSize (
VOID
)
{
UINT32 NumSets;
UINT32 Associativity;
UINT32 LineSize;
UINT32 CCSIDR = ReadCCSIDR (1);
LineSize = (1 << ((CCSIDR & 0x7) + 2));
Associativity = ((CCSIDR >> 3) & 0x3ff) + 1;
NumSets = ((CCSIDR >> 13) & 0x7fff) + 1;
// LineSize is in words (4 byte chunks)
return NumSets * Associativity * LineSize * 4;
}
UINTN
EFIAPI
ArmInstructionCacheAssociativity (
VOID
)
{
UINT32 CCSIDR = ReadCCSIDR (1);
return ((CCSIDR >> 3) & 0x3ff) + 1;
// return 4;
}
UINTN
EFIAPI
ArmInstructionCacheSets (
VOID
)
{
UINT32 CCSIDR = ReadCCSIDR (1);
return ((CCSIDR >> 13) & 0x7fff) + 1;
}
UINTN
EFIAPI
ArmInstructionCacheLineLength (
VOID
)
{
UINT32 CCSIDR = ReadCCSIDR (1) & 7;
// * 4 converts to bytes
return (1 << (CCSIDR + 2)) * 4;
// return 64;
}
VOID
ArmV7DataCacheOperation (
IN ARM_V7_CACHE_OPERATION DataCacheOperation
)
{
UINTN SavedInterruptState;
SavedInterruptState = ArmGetInterruptState ();
ArmDisableInterrupts ();
ArmV7AllDataCachesOperation (DataCacheOperation);
ArmDrainWriteBuffer ();
if (SavedInterruptState) {
ArmEnableInterrupts ();
}
}
VOID
ArmV7PoUDataCacheOperation (
IN ARM_V7_CACHE_OPERATION DataCacheOperation
)
{
UINTN SavedInterruptState;
SavedInterruptState = ArmGetInterruptState ();
ArmDisableInterrupts ();
ArmV7PerformPoUDataCacheOperation (DataCacheOperation);
ArmDrainWriteBuffer ();
if (SavedInterruptState) {
ArmEnableInterrupts ();
}
}
VOID
EFIAPI
ArmInvalidateDataCache (
VOID
)
{
ArmV7DataCacheOperation (ArmInvalidateDataCacheEntryBySetWay);
}
VOID
EFIAPI
ArmCleanInvalidateDataCache (
VOID
)
{
ArmV7DataCacheOperation (ArmCleanInvalidateDataCacheEntryBySetWay);
}
VOID
EFIAPI
ArmCleanDataCache (
VOID
)
{
ArmV7DataCacheOperation (ArmCleanDataCacheEntryBySetWay);
}
VOID
EFIAPI
ArmCleanDataCacheToPoU (
VOID
)
{
ArmV7PoUDataCacheOperation (ArmCleanDataCacheEntryBySetWay);
}

122
ArmPkg/Library/BaseMemoryLibStm/Arm/CopyMem.asm
View File

@ -38,16 +38,16 @@ InternalMemCopyMem (
)
**/
EXPORT InternalMemCopyMem
AREA AsmMemStuff, CODE, READONLY
AREA AsmMemStuff, CODE, READONLY
InternalMemCopyMem
stmfd sp!, {r4-r11, lr}
// Save the input parameters in extra registers (r11 = destination, r14 = source, r12 = length)
mov r11, r0
mov r10, r0
mov r12, r2
mov r14, r1
stmfd sp!, {r4-r11, lr}
// Save the input parameters in extra registers (r11 = destination, r14 = source, r12 = length)
mov r11, r0
mov r10, r0
mov r12, r2
mov r14, r1
memcopy_check_overlapped
cmp r11, r1
@ -70,42 +70,42 @@ memcopy_check_overlapped
memcopy_check_optim_default
// Check if we can use an optimized path ((length >= 32) && destination word-aligned && source word-aligned) for the memcopy (optimized path if r0 == 1)
tst r0, #0xF
movne r0, #0
bne memcopy_default
tst r1, #0xF
movne r3, #0
moveq r3, #1
cmp r2, #31
movls r0, #0
andhi r0, r3, #1
b memcopy_default
memcopy_check_optim_overlap
// r10 = dest_end, r14 = source_end
add r10, r11, r12
add r14, r12, r1
// Are we in the optimized case ((length >= 32) && dest_end word-aligned && source_end word-aligned)
cmp r2, #31
movls r0, #0
movhi r0, #1
tst r10, #0xF
movne r0, #0
tst r14, #0xF
movne r0, #0
movne r0, #0
bne memcopy_default
tst r1, #0xF
movne r3, #0
moveq r3, #1
cmp r2, #31
movls r0, #0
andhi r0, r3, #1
b memcopy_default
memcopy_check_optim_overlap
// r10 = dest_end, r14 = source_end
add r10, r11, r12
add r14, r12, r1
// Are we in the optimized case ((length >= 32) && dest_end word-aligned && source_end word-aligned)
cmp r2, #31
movls r0, #0
movhi r0, #1
tst r10, #0xF
movne r0, #0
tst r14, #0xF
movne r0, #0
b memcopy_overlapped
memcopy_overlapped_non_optim
// We read 1 byte from the end of the source buffer
sub r3, r14, #1
sub r12, r12, #1
ldrb r3, [r3, #0]
sub r2, r10, #1
cmp r12, #0
sub r3, r14, #1
sub r12, r12, #1
ldrb r3, [r3, #0]
sub r2, r10, #1
cmp r12, #0
// We write 1 byte at the end of the dest buffer
sub r10, r10, #1
sub r14, r14, #1
strb r3, [r2, #0]
sub r10, r10, #1
sub r14, r14, #1
strb r3, [r2, #0]
bne memcopy_overlapped_non_optim
b memcopy_end
@ -114,16 +114,16 @@ memcopy_overlapped
// Are we in the optimized case ?
cmp r0, #0
beq memcopy_overlapped_non_optim
// Optimized Overlapped - Read 32 bytes
sub r14, r14, #32
sub r12, r12, #32
cmp r12, #31
ldmia r14, {r2-r9}
// If length is less than 32 then disable optim
movls r0, #0
cmp r12, #0
// Optimized Overlapped - Write 32 bytes
@ -136,37 +136,37 @@ memcopy_overlapped
memcopy_default_non_optim
// Byte copy
ldrb r3, [r14], #1
sub r12, r12, #1
strb r3, [r10], #1
ldrb r3, [r14], #1
sub r12, r12, #1
strb r3, [r10], #1
memcopy_default
cmp r12, #0
beq memcopy_end
cmp r12, #0
beq memcopy_end
// r10 = dest, r14 = source
memcopy_default_loop
cmp r0, #0
cmp r0, #0
beq memcopy_default_non_optim
// Optimized memcopy - Read 32 Bytes
sub r12, r12, #32
cmp r12, #31
ldmia r14!, {r2-r9}
sub r12, r12, #32
cmp r12, #31
ldmia r14!, {r2-r9}
// If length is less than 32 then disable optim
movls r0, #0
movls r0, #0
cmp r12, #0
cmp r12, #0
// Optimized memcopy - Write 32 Bytes
stmia r10!, {r2-r9}
stmia r10!, {r2-r9}
// while (length != 0)
bne memcopy_default_loop
memcopy_end
mov r0, r11
mov r0, r11
ldmfd sp!, {r4-r11, pc}
END

140
ArmPkg/Library/BaseMemoryLibVstm/Arm/CopyMem.asm
View File

@ -38,78 +38,78 @@ InternalMemCopyMem (
)
**/
EXPORT InternalMemCopyMem
AREA AsmMemStuff, CODE, READONLY
AREA AsmMemStuff, CODE, READONLY
InternalMemCopyMem
stmfd sp!, {r4, r9, lr}
tst r0, #3
mov r4, r0
mov r9, r0
mov ip, r2
mov lr, r1
movne r0, #0
bne L4
tst r1, #3
movne r3, #0
moveq r3, #1
cmp r2, #127
movls r0, #0
andhi r0, r3, #1
L4
cmp r4, r1
bcc L26
bls L7
rsb r3, r1, r4
cmp ip, r3
bcc L26
cmp ip, #0
beq L7
add r9, r4, ip
add lr, ip, r1
b L16
L29
sub ip, ip, #8
cmp ip, #7
ldrd r2, [lr, #-8]!
movls r0, #0
cmp ip, #0
strd r2, [r9, #-8]!
beq L7
L16
cmp r0, #0
bne L29
sub r3, lr, #1
sub ip, ip, #1
ldrb r3, [r3, #0]
sub r2, r9, #1
cmp ip, #0
sub r9, r9, #1
sub lr, lr, #1
strb r3, [r2, #0]
bne L16
b L7
L11
ldrb r3, [lr], #1
sub ip, ip, #1
strb r3, [r9], #1
L26
cmp ip, #0
beq L7
L30
cmp r0, #0
beq L11
sub ip, ip, #128 // 32
cmp ip, #127 // 31
vldm lr!, {d0-d15}
movls r0, #0
cmp ip, #0
vstm r9!, {d0-d15}
bne L30
L7
dsb
mov r0, r4
ldmfd sp!, {r4, r9, pc}
stmfd sp!, {r4, r9, lr}
tst r0, #3
mov r4, r0
mov r9, r0
mov ip, r2
mov lr, r1
movne r0, #0
bne L4
tst r1, #3
movne r3, #0
moveq r3, #1
cmp r2, #127
movls r0, #0
andhi r0, r3, #1
L4
cmp r4, r1
bcc L26
bls L7
rsb r3, r1, r4
cmp ip, r3
bcc L26
cmp ip, #0
beq L7
add r9, r4, ip
add lr, ip, r1
b L16
L29
sub ip, ip, #8
cmp ip, #7
ldrd r2, [lr, #-8]!
movls r0, #0
cmp ip, #0
strd r2, [r9, #-8]!
beq L7
L16
cmp r0, #0
bne L29
sub r3, lr, #1
sub ip, ip, #1
ldrb r3, [r3, #0]
sub r2, r9, #1
cmp ip, #0
sub r9, r9, #1
sub lr, lr, #1
strb r3, [r2, #0]
bne L16
b L7
L11
ldrb r3, [lr], #1
sub ip, ip, #1
strb r3, [r9], #1
L26
cmp ip, #0
beq L7
L30
cmp r0, #0
beq L11
sub ip, ip, #128 // 32
cmp ip, #127 // 31
vldm lr!, {d0-d15}
movls r0, #0
cmp ip, #0
vstm r9!, {d0-d15}
bne L30
L7
dsb
mov r0, r4
ldmfd sp!, {r4, r9, pc}
END

2
ArmPkg/Library/BaseMemoryLibVstm/Arm/SetMem.S
View File

@ -77,4 +77,4 @@ L43:
cmp r1, #0
bne L34
ldmfd sp!, {pc}

4
ArmPkg/Library/BaseMemoryLibVstm/Arm/SetMem.asm
View File

@ -36,7 +36,7 @@ InternalMemSetMem (
EXPORT InternalMemSetMem
AREA AsmMemStuff, CODE, READONLY
AREA AsmMemStuff, CODE, READONLY
InternalMemSetMem
stmfd sp!, {lr}
@ -77,4 +77,4 @@ L43
ldmfd sp!, {pc}
END

288
ArmPkg/Library/BdsLib/BdsAppLoader.c
View File

@ -1,144 +1,144 @@
/** @file
*
* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
* which accompanies this distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#include "BdsInternal.h"
//#include <Library/DxeServicesLib.h>
STATIC
EFI_STATUS
BdsLoadFileFromFirmwareVolume (
IN EFI_HANDLE FvHandle,
IN CHAR16 *FilePath,
IN EFI_FV_FILETYPE FileTypeFilter,
OUT EFI_DEVICE_PATH **EfiAppDevicePath
)
{
EFI_FIRMWARE_VOLUME2_PROTOCOL *FvProtocol;
VOID *Key;
EFI_STATUS Status, FileStatus;
EFI_GUID NameGuid;
EFI_FV_FILETYPE FileType;
EFI_FV_FILE_ATTRIBUTES Attributes;
UINTN Size;
UINTN UiStringLen;
CHAR16 *UiSection;
UINT32 Authentication;
EFI_DEVICE_PATH *FvDevicePath;
MEDIA_FW_VOL_FILEPATH_DEVICE_PATH FileDevicePath;
Status = gBS->HandleProtocol (FvHandle,&gEfiFirmwareVolume2ProtocolGuid, (VOID **)&FvProtocol);
if (EFI_ERROR(Status)) {
return Status;
}
// Length of FilePath
UiStringLen = StrLen (FilePath);
// Allocate Key
Key = AllocatePool (FvProtocol->KeySize);
ASSERT (Key != NULL);
ZeroMem (Key, FvProtocol->KeySize);
do {
// Search in all files
FileType = FileTypeFilter;
Status = FvProtocol->GetNextFile (FvProtocol, Key, &FileType, &NameGuid, &Attributes, &Size);
if (!EFI_ERROR (Status)) {
UiSection = NULL;
FileStatus = FvProtocol->ReadSection (
FvProtocol,
&NameGuid,
EFI_SECTION_USER_INTERFACE,
0,
(VOID **)&UiSection,
&Size,
&Authentication
);
if (!EFI_ERROR (FileStatus)) {
if (StrnCmp (FilePath, UiSection, UiStringLen) == 0) {
//
// We found a UiString match.
//
Status = gBS->HandleProtocol (FvHandle, &gEfiDevicePathProtocolGuid, (VOID **)&FvDevicePath);
// Generate the Device Path for the file
//DevicePath = DuplicateDevicePath(FvDevicePath);
EfiInitializeFwVolDevicepathNode (&FileDevicePath, &NameGuid);
*EfiAppDevicePath = AppendDevicePathNode (FvDevicePath, (EFI_DEVICE_PATH_PROTOCOL *)&FileDevicePath);
FreePool (Key);
FreePool (UiSection);
return FileStatus;
}
FreePool (UiSection);
}
}
} while (!EFI_ERROR (Status));
FreePool(Key);
return Status;
}
/**
Start an EFI Application from any Firmware Volume
@param EfiApp EFI Application Name
@retval EFI_SUCCESS All drivers have been connected
@retval EFI_NOT_FOUND The Linux kernel Device Path has not been found
@retval EFI_OUT_OF_RESOURCES There is not enough resource memory to store the matching results.
**/
EFI_STATUS
BdsLoadApplication (
IN EFI_HANDLE ParentImageHandle,
IN CHAR16* EfiApp,
IN UINTN LoadOptionsSize,
IN VOID* LoadOptions
)
{
EFI_STATUS Status;
UINTN NoHandles, HandleIndex;
EFI_HANDLE *Handles;
EFI_DEVICE_PATH *EfiAppDevicePath;
// Need to connect every drivers to ensure no dependencies are missing for the application
Status = BdsConnectAllDrivers();
if (EFI_ERROR(Status)) {
DEBUG ((EFI_D_ERROR, "FAIL to connect all drivers\n"));
return Status;
}
// Search the application in any Firmware Volume
Status = gBS->LocateHandleBuffer (ByProtocol, &gEfiFirmwareVolume2ProtocolGuid, NULL, &NoHandles, &Handles);
if (EFI_ERROR (Status) || (NoHandles == 0)) {
DEBUG ((EFI_D_ERROR, "FAIL to find Firmware Volume\n"));
return Status;
}
// Search in all Firmware Volume for the EFI Application
for (HandleIndex = 0; HandleIndex < NoHandles; HandleIndex++) {
EfiAppDevicePath = NULL;
Status = BdsLoadFileFromFirmwareVolume (Handles[HandleIndex], EfiApp, EFI_FV_FILETYPE_APPLICATION, &EfiAppDevicePath);
if (!EFI_ERROR (Status)) {
// Start the application
Status = BdsStartEfiApplication (ParentImageHandle, EfiAppDevicePath, LoadOptionsSize, LoadOptions);
return Status;
}
}
return Status;
}
/** @file
*
* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
* which accompanies this distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#include "BdsInternal.h"
//#include <Library/DxeServicesLib.h>
STATIC
EFI_STATUS
BdsLoadFileFromFirmwareVolume (
IN EFI_HANDLE FvHandle,
IN CHAR16 *FilePath,
IN EFI_FV_FILETYPE FileTypeFilter,
OUT EFI_DEVICE_PATH **EfiAppDevicePath
)
{
EFI_FIRMWARE_VOLUME2_PROTOCOL *FvProtocol;
VOID *Key;
EFI_STATUS Status, FileStatus;
EFI_GUID NameGuid;
EFI_FV_FILETYPE FileType;
EFI_FV_FILE_ATTRIBUTES Attributes;
UINTN Size;
UINTN UiStringLen;
CHAR16 *UiSection;
UINT32 Authentication;
EFI_DEVICE_PATH *FvDevicePath;
MEDIA_FW_VOL_FILEPATH_DEVICE_PATH FileDevicePath;
Status = gBS->HandleProtocol (FvHandle,&gEfiFirmwareVolume2ProtocolGuid, (VOID **)&FvProtocol);
if (EFI_ERROR(Status)) {
return Status;
}
// Length of FilePath
UiStringLen = StrLen (FilePath);
// Allocate Key
Key = AllocatePool (FvProtocol->KeySize);
ASSERT (Key != NULL);
ZeroMem (Key, FvProtocol->KeySize);
do {
// Search in all files
FileType = FileTypeFilter;
Status = FvProtocol->GetNextFile (FvProtocol, Key, &FileType, &NameGuid, &Attributes, &Size);
if (!EFI_ERROR (Status)) {
UiSection = NULL;
FileStatus = FvProtocol->ReadSection (
FvProtocol,
&NameGuid,
EFI_SECTION_USER_INTERFACE,
0,
(VOID **)&UiSection,
&Size,
&Authentication
);
if (!EFI_ERROR (FileStatus)) {
if (StrnCmp (FilePath, UiSection, UiStringLen) == 0) {
//
// We found a UiString match.
//
Status = gBS->HandleProtocol (FvHandle, &gEfiDevicePathProtocolGuid, (VOID **)&FvDevicePath);
// Generate the Device Path for the file
//DevicePath = DuplicateDevicePath(FvDevicePath);
EfiInitializeFwVolDevicepathNode (&FileDevicePath, &NameGuid);
*EfiAppDevicePath = AppendDevicePathNode (FvDevicePath, (EFI_DEVICE_PATH_PROTOCOL *)&FileDevicePath);
FreePool (Key);
FreePool (UiSection);
return FileStatus;
}
FreePool (UiSection);
}
}
} while (!EFI_ERROR (Status));
FreePool(Key);
return Status;
}
/**
Start an EFI Application from any Firmware Volume
@param EfiApp EFI Application Name
@retval EFI_SUCCESS All drivers have been connected
@retval EFI_NOT_FOUND The Linux kernel Device Path has not been found
@retval EFI_OUT_OF_RESOURCES There is not enough resource memory to store the matching results.
**/
EFI_STATUS
BdsLoadApplication (
IN EFI_HANDLE ParentImageHandle,
IN CHAR16* EfiApp,
IN UINTN LoadOptionsSize,
IN VOID* LoadOptions
)
{
EFI_STATUS Status;
UINTN NoHandles, HandleIndex;
EFI_HANDLE *Handles;
EFI_DEVICE_PATH *EfiAppDevicePath;
// Need to connect every drivers to ensure no dependencies are missing for the application
Status = BdsConnectAllDrivers();
if (EFI_ERROR(Status)) {
DEBUG ((EFI_D_ERROR, "FAIL to connect all drivers\n"));
return Status;
}
// Search the application in any Firmware Volume
Status = gBS->LocateHandleBuffer (ByProtocol, &gEfiFirmwareVolume2ProtocolGuid, NULL, &NoHandles, &Handles);
if (EFI_ERROR (Status) || (NoHandles == 0)) {
DEBUG ((EFI_D_ERROR, "FAIL to find Firmware Volume\n"));
return Status;
}
// Search in all Firmware Volume for the EFI Application
for (HandleIndex = 0; HandleIndex < NoHandles; HandleIndex++) {
EfiAppDevicePath = NULL;
Status = BdsLoadFileFromFirmwareVolume (Handles[HandleIndex], EfiApp, EFI_FV_FILETYPE_APPLICATION, &EfiAppDevicePath);
if (!EFI_ERROR (Status)) {
// Start the application
Status = BdsStartEfiApplication (ParentImageHandle, EfiAppDevicePath, LoadOptionsSize, LoadOptions);
return Status;
}
}
return Status;
}

1812
ArmPkg/Library/BdsLib/BdsFilePath.c
View File

File diff suppressed because it is too large Load Diff

694
ArmPkg/Library/BdsLib/BdsHelper.c
View File

@ -1,347 +1,347 @@
/** @file
*
* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
* which accompanies this distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#include "BdsInternal.h"
#include <Library/DxeServicesTableLib.h>
#include <Library/HobLib.h>
#include <Library/TimerLib.h>
#include <Library/PrintLib.h>
#include <Library/SerialPortLib.h>
STATIC CHAR8 *mTokenList[] = {
/*"SEC",*/
"PEI",
"DXE",
"BDS",
NULL
};
EFI_STATUS
ShutdownUefiBootServices (
VOID
)
{
EFI_STATUS Status;
UINTN MemoryMapSize;
EFI_MEMORY_DESCRIPTOR *MemoryMap;
UINTN MapKey;
UINTN DescriptorSize;
UINT32 DescriptorVersion;
UINTN Pages;
MemoryMap = NULL;
MemoryMapSize = 0;
Pages = 0;
do {
Status = gBS->GetMemoryMap (
&MemoryMapSize,
MemoryMap,
&MapKey,
&DescriptorSize,
&DescriptorVersion
);
if (Status == EFI_BUFFER_TOO_SMALL) {
Pages = EFI_SIZE_TO_PAGES (MemoryMapSize) + 1;
MemoryMap = AllocatePages (Pages);
//
// Get System MemoryMap
//
Status = gBS->GetMemoryMap (
&MemoryMapSize,
MemoryMap,
&MapKey,
&DescriptorSize,
&DescriptorVersion
);
}
// Don't do anything between the GetMemoryMap() and ExitBootServices()
if (!EFI_ERROR(Status)) {
Status = gBS->ExitBootServices (gImageHandle, MapKey);
if (EFI_ERROR(Status)) {
FreePages (MemoryMap, Pages);
MemoryMap = NULL;
MemoryMapSize = 0;
}
}
} while (EFI_ERROR(Status));
return Status;
}
/**
Connect all DXE drivers
@retval EFI_SUCCESS All drivers have been connected
@retval EFI_NOT_FOUND No handles match the search.
@retval EFI_OUT_OF_RESOURCES There is not resource pool memory to store the matching results.
**/
EFI_STATUS
BdsConnectAllDrivers (
VOID
)
{
UINTN HandleCount, Index;
EFI_HANDLE *HandleBuffer;
EFI_STATUS Status;
do {
// Locate all the driver handles
Status = gBS->LocateHandleBuffer (
AllHandles,
NULL,
NULL,
&HandleCount,
&HandleBuffer
);
if (EFI_ERROR (Status)) {
break;
}
// Connect every handles
for (Index = 0; Index < HandleCount; Index++) {
gBS->ConnectController (HandleBuffer[Index], NULL, NULL, TRUE);
}
if (HandleBuffer != NULL) {
FreePool (HandleBuffer);
}
// Check if new handles have been created after the start of the previous handles
Status = gDS->Dispatch ();
} while (!EFI_ERROR(Status));
return EFI_SUCCESS;
}
STATIC
EFI_STATUS
InsertSystemMemoryResources (
LIST_ENTRY *ResourceList,
EFI_HOB_RESOURCE_DESCRIPTOR *ResHob
)
{
BDS_SYSTEM_MEMORY_RESOURCE *NewResource;
LIST_ENTRY *Link;
LIST_ENTRY *NextLink;
LIST_ENTRY AttachedResources;
BDS_SYSTEM_MEMORY_RESOURCE *Resource;
EFI_PHYSICAL_ADDRESS NewResourceEnd;
if (IsListEmpty (ResourceList)) {
NewResource = AllocateZeroPool (sizeof(BDS_SYSTEM_MEMORY_RESOURCE));
NewResource->PhysicalStart = ResHob->PhysicalStart;
NewResource->ResourceLength = ResHob->ResourceLength;
InsertTailList (ResourceList, &NewResource->Link);
return EFI_SUCCESS;
}
InitializeListHead (&AttachedResources);
Link = ResourceList->ForwardLink;
ASSERT (Link != NULL);
while (Link != ResourceList) {
Resource = (BDS_SYSTEM_MEMORY_RESOURCE*)Link;
// Sanity Check. The resources should not overlapped.
ASSERT(!((ResHob->PhysicalStart >= Resource->PhysicalStart) && (ResHob->PhysicalStart < (Resource->PhysicalStart + Resource->ResourceLength))));
ASSERT(!((ResHob->PhysicalStart + ResHob->ResourceLength - 1 >= Resource->PhysicalStart) &&
((ResHob->PhysicalStart + ResHob->ResourceLength - 1) < (Resource->PhysicalStart + Resource->ResourceLength))));
// The new resource is attached after this resource descriptor
if (ResHob->PhysicalStart == Resource->PhysicalStart + Resource->ResourceLength) {
Resource->ResourceLength = Resource->ResourceLength + ResHob->ResourceLength;
NextLink = RemoveEntryList (&Resource->Link);
InsertTailList (&AttachedResources, &Resource->Link);
Link = NextLink;
}
// The new resource is attached before this resource descriptor
else if (ResHob->PhysicalStart + ResHob->ResourceLength == Resource->PhysicalStart) {
Resource->PhysicalStart = ResHob->PhysicalStart;
Resource->ResourceLength = Resource->ResourceLength + ResHob->ResourceLength;
NextLink = RemoveEntryList (&Resource->Link);
InsertTailList (&AttachedResources, &Resource->Link);
Link = NextLink;
} else {
Link = Link->ForwardLink;
}
}
if (!IsListEmpty (&AttachedResources)) {
// See if we can merge the attached resource with other resources
NewResource = (BDS_SYSTEM_MEMORY_RESOURCE*)GetFirstNode (&AttachedResources);
Link = RemoveEntryList (&NewResource->Link);
while (!IsListEmpty (&AttachedResources)) {
// Merge resources
Resource = (BDS_SYSTEM_MEMORY_RESOURCE*)Link;
// Ensure they overlap each other
ASSERT(
((NewResource->PhysicalStart >= Resource->PhysicalStart) && (NewResource->PhysicalStart < (Resource->PhysicalStart + Resource->ResourceLength))) ||
(((NewResource->PhysicalStart + NewResource->ResourceLength) >= Resource->PhysicalStart) && ((NewResource->PhysicalStart + NewResource->ResourceLength) < (Resource->PhysicalStart + Resource->ResourceLength)))
);
NewResourceEnd = MAX (NewResource->PhysicalStart + NewResource->ResourceLength, Resource->PhysicalStart + Resource->ResourceLength);
NewResource->PhysicalStart = MIN (NewResource->PhysicalStart, Resource->PhysicalStart);
NewResource->ResourceLength = NewResourceEnd - NewResource->PhysicalStart;
Link = RemoveEntryList (Link);
}
} else {
// None of the Resource of the list is attached to this ResHob. Create a new entry for it
NewResource = AllocateZeroPool (sizeof(BDS_SYSTEM_MEMORY_RESOURCE));
NewResource->PhysicalStart = ResHob->PhysicalStart;
NewResource->ResourceLength = ResHob->ResourceLength;
}
InsertTailList (ResourceList, &NewResource->Link);
return EFI_SUCCESS;
}
EFI_STATUS
GetSystemMemoryResources (
IN LIST_ENTRY *ResourceList
)
{
EFI_HOB_RESOURCE_DESCRIPTOR *ResHob;
InitializeListHead (ResourceList);
// Find the first System Memory Resource Descriptor
ResHob = (EFI_HOB_RESOURCE_DESCRIPTOR *)GetFirstHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR);
while ((ResHob != NULL) && (ResHob->ResourceType != EFI_RESOURCE_SYSTEM_MEMORY)) {
ResHob = (EFI_HOB_RESOURCE_DESCRIPTOR *)GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR,(VOID *)((UINTN)ResHob + ResHob->Header.HobLength));
}
// Did not find any
if (ResHob == NULL) {
return EFI_NOT_FOUND;
} else {
InsertSystemMemoryResources (ResourceList, ResHob);
}
ResHob = (EFI_HOB_RESOURCE_DESCRIPTOR *)GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR,(VOID *)((UINTN)ResHob + ResHob->Header.HobLength));
while (ResHob != NULL) {
if (ResHob->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) {
InsertSystemMemoryResources (ResourceList, ResHob);
}
ResHob = (EFI_HOB_RESOURCE_DESCRIPTOR *)GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR,(VOID *)((UINTN)ResHob + ResHob->Header.HobLength));
}
return EFI_SUCCESS;
}
VOID
PrintPerformance (
VOID
)
{
UINTN Key;
CONST VOID *Handle;
CONST CHAR8 *Token, *Module;
UINT64 Start, Stop, TimeStamp;
UINT64 Delta, TicksPerSecond, Milliseconds;
UINTN Index;
CHAR8 Buffer[100];
UINTN CharCount;
BOOLEAN CountUp;
TicksPerSecond = GetPerformanceCounterProperties (&Start, &Stop);
if (Start < Stop) {
CountUp = TRUE;
} else {
CountUp = FALSE;
}
TimeStamp = 0;
Key = 0;
do {
Key = GetPerformanceMeasurement (Key, (CONST VOID **)&Handle, &Token, &Module, &Start, &Stop);
if (Key != 0) {
for (Index = 0; mTokenList[Index] != NULL; Index++) {
if (AsciiStriCmp (mTokenList[Index], Token) == 0) {
Delta = CountUp?(Stop - Start):(Start - Stop);
TimeStamp += Delta;
Milliseconds = DivU64x64Remainder (MultU64x32 (Delta, 1000), TicksPerSecond, NULL);
CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"%6a %6ld ms\n", Token, Milliseconds);
SerialPortWrite ((UINT8 *) Buffer, CharCount);
break;
}
}
}
} while (Key != 0);
CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Total Time = %ld ms\n\n", DivU64x64Remainder (MultU64x32 (TimeStamp, 1000), TicksPerSecond, NULL));
SerialPortWrite ((UINT8 *) Buffer, CharCount);
}
EFI_STATUS
GetEnvironmentVariable (
IN CONST CHAR16* VariableName,
IN VOID* DefaultValue,
IN OUT UINTN* Size,
OUT VOID** Value
)
{
EFI_STATUS Status;
UINTN VariableSize;
// Try to get the variable size.
*Value = NULL;
VariableSize = 0;
Status = gRT->GetVariable ((CHAR16 *) VariableName, &gEfiGlobalVariableGuid, NULL, &VariableSize, *Value);
if (Status == EFI_NOT_FOUND) {
if ((DefaultValue != NULL) && (Size != NULL) && (*Size != 0)) {
// If the environment variable does not exist yet then set it with the default value
Status = gRT->SetVariable (
(CHAR16*)VariableName,
&gEfiGlobalVariableGuid,
EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
*Size,
DefaultValue
);
*Value = DefaultValue;
} else {
return EFI_NOT_FOUND;
}
} else if (Status == EFI_BUFFER_TOO_SMALL) {
// Get the environment variable value
*Value = AllocatePool (VariableSize);
if (*Value == NULL) {
return EFI_OUT_OF_RESOURCES;
}
Status = gRT->GetVariable ((CHAR16 *)VariableName, &gEfiGlobalVariableGuid, NULL, &VariableSize, *Value);
if (EFI_ERROR (Status)) {
FreePool(*Value);
return EFI_INVALID_PARAMETER;
}
if (Size) {
*Size = VariableSize;
}
} else {
*Value = DefaultValue;
return Status;
}
return EFI_SUCCESS;
}
/** @file
*
* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
* which accompanies this distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#include "BdsInternal.h"
#include <Library/DxeServicesTableLib.h>
#include <Library/HobLib.h>
#include <Library/TimerLib.h>
#include <Library/PrintLib.h>
#include <Library/SerialPortLib.h>
STATIC CHAR8 *mTokenList[] = {
/*"SEC",*/
"PEI",
"DXE",
"BDS",
NULL
};
EFI_STATUS
ShutdownUefiBootServices (
VOID
)
{
EFI_STATUS Status;
UINTN MemoryMapSize;
EFI_MEMORY_DESCRIPTOR *MemoryMap;
UINTN MapKey;
UINTN DescriptorSize;
UINT32 DescriptorVersion;
UINTN Pages;
MemoryMap = NULL;
MemoryMapSize = 0;
Pages = 0;
do {
Status = gBS->GetMemoryMap (
&MemoryMapSize,
MemoryMap,
&MapKey,
&DescriptorSize,
&DescriptorVersion
);
if (Status == EFI_BUFFER_TOO_SMALL) {
Pages = EFI_SIZE_TO_PAGES (MemoryMapSize) + 1;
MemoryMap = AllocatePages (Pages);
//
// Get System MemoryMap
//
Status = gBS->GetMemoryMap (
&MemoryMapSize,
MemoryMap,
&MapKey,
&DescriptorSize,
&DescriptorVersion
);
}
// Don't do anything between the GetMemoryMap() and ExitBootServices()
if (!EFI_ERROR(Status)) {
Status = gBS->ExitBootServices (gImageHandle, MapKey);
if (EFI_ERROR(Status)) {
FreePages (MemoryMap, Pages);
MemoryMap = NULL;
MemoryMapSize = 0;
}
}
} while (EFI_ERROR(Status));
return Status;
}
/**
Connect all DXE drivers
@retval EFI_SUCCESS All drivers have been connected
@retval EFI_NOT_FOUND No handles match the search.
@retval EFI_OUT_OF_RESOURCES There is not resource pool memory to store the matching results.
**/
EFI_STATUS
BdsConnectAllDrivers (
VOID
)
{
UINTN HandleCount, Index;
EFI_HANDLE *HandleBuffer;
EFI_STATUS Status;
do {
// Locate all the driver handles
Status = gBS->LocateHandleBuffer (
AllHandles,
NULL,
NULL,
&HandleCount,
&HandleBuffer
);
if (EFI_ERROR (Status)) {
break;
}
// Connect every handles
for (Index = 0; Index < HandleCount; Index++) {
gBS->ConnectController (HandleBuffer[Index], NULL, NULL, TRUE);
}
if (HandleBuffer != NULL) {
FreePool (HandleBuffer);
}
// Check if new handles have been created after the start of the previous handles
Status = gDS->Dispatch ();
} while (!EFI_ERROR(Status));
return EFI_SUCCESS;
}
STATIC
EFI_STATUS
InsertSystemMemoryResources (
LIST_ENTRY *ResourceList,
EFI_HOB_RESOURCE_DESCRIPTOR *ResHob
)
{
BDS_SYSTEM_MEMORY_RESOURCE *NewResource;
LIST_ENTRY *Link;
LIST_ENTRY *NextLink;
LIST_ENTRY AttachedResources;
BDS_SYSTEM_MEMORY_RESOURCE *Resource;
EFI_PHYSICAL_ADDRESS NewResourceEnd;
if (IsListEmpty (ResourceList)) {
NewResource = AllocateZeroPool (sizeof(BDS_SYSTEM_MEMORY_RESOURCE));
NewResource->PhysicalStart = ResHob->PhysicalStart;
NewResource->ResourceLength = ResHob->ResourceLength;
InsertTailList (ResourceList, &NewResource->Link);
return EFI_SUCCESS;
}
InitializeListHead (&AttachedResources);
Link = ResourceList->ForwardLink;
ASSERT (Link != NULL);
while (Link != ResourceList) {
Resource = (BDS_SYSTEM_MEMORY_RESOURCE*)Link;
// Sanity Check. The resources should not overlapped.
ASSERT(!((ResHob->PhysicalStart >= Resource->PhysicalStart) && (ResHob->PhysicalStart < (Resource->PhysicalStart + Resource->ResourceLength))));
ASSERT(!((ResHob->PhysicalStart + ResHob->ResourceLength - 1 >= Resource->PhysicalStart) &&
((ResHob->PhysicalStart + ResHob->ResourceLength - 1) < (Resource->PhysicalStart + Resource->ResourceLength))));
// The new resource is attached after this resource descriptor
if (ResHob->PhysicalStart == Resource->PhysicalStart + Resource->ResourceLength) {
Resource->ResourceLength = Resource->ResourceLength + ResHob->ResourceLength;
NextLink = RemoveEntryList (&Resource->Link);
InsertTailList (&AttachedResources, &Resource->Link);
Link = NextLink;
}
// The new resource is attached before this resource descriptor
else if (ResHob->PhysicalStart + ResHob->ResourceLength == Resource->PhysicalStart) {
Resource->PhysicalStart = ResHob->PhysicalStart;
Resource->ResourceLength = Resource->ResourceLength + ResHob->ResourceLength;
NextLink = RemoveEntryList (&Resource->Link);
InsertTailList (&AttachedResources, &Resource->Link);
Link = NextLink;
} else {
Link = Link->ForwardLink;
}
}
if (!IsListEmpty (&AttachedResources)) {
// See if we can merge the attached resource with other resources
NewResource = (BDS_SYSTEM_MEMORY_RESOURCE*)GetFirstNode (&AttachedResources);
Link = RemoveEntryList (&NewResource->Link);
while (!IsListEmpty (&AttachedResources)) {
// Merge resources
Resource = (BDS_SYSTEM_MEMORY_RESOURCE*)Link;
// Ensure they overlap each other
ASSERT(
((NewResource->PhysicalStart >= Resource->PhysicalStart) && (NewResource->PhysicalStart < (Resource->PhysicalStart + Resource->ResourceLength))) ||
(((NewResource->PhysicalStart + NewResource->ResourceLength) >= Resource->PhysicalStart) && ((NewResource->PhysicalStart + NewResource->ResourceLength) < (Resource->PhysicalStart + Resource->ResourceLength)))
);
NewResourceEnd = MAX (NewResource->PhysicalStart + NewResource->ResourceLength, Resource->PhysicalStart + Resource->ResourceLength);
NewResource->PhysicalStart = MIN (NewResource->PhysicalStart, Resource->PhysicalStart);
NewResource->ResourceLength = NewResourceEnd - NewResource->PhysicalStart;
Link = RemoveEntryList (Link);
}
} else {
// None of the Resource of the list is attached to this ResHob. Create a new entry for it
NewResource = AllocateZeroPool (sizeof(BDS_SYSTEM_MEMORY_RESOURCE));
NewResource->PhysicalStart = ResHob->PhysicalStart;
NewResource->ResourceLength = ResHob->ResourceLength;
}
InsertTailList (ResourceList, &NewResource->Link);
return EFI_SUCCESS;
}
EFI_STATUS
GetSystemMemoryResources (
IN LIST_ENTRY *ResourceList
)
{
EFI_HOB_RESOURCE_DESCRIPTOR *ResHob;
InitializeListHead (ResourceList);
// Find the first System Memory Resource Descriptor
ResHob = (EFI_HOB_RESOURCE_DESCRIPTOR *)GetFirstHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR);
while ((ResHob != NULL) && (ResHob->ResourceType != EFI_RESOURCE_SYSTEM_MEMORY)) {
ResHob = (EFI_HOB_RESOURCE_DESCRIPTOR *)GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR,(VOID *)((UINTN)ResHob + ResHob->Header.HobLength));
}
// Did not find any
if (ResHob == NULL) {
return EFI_NOT_FOUND;
} else {
InsertSystemMemoryResources (ResourceList, ResHob);
}
ResHob = (EFI_HOB_RESOURCE_DESCRIPTOR *)GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR,(VOID *)((UINTN)ResHob + ResHob->Header.HobLength));
while (ResHob != NULL) {
if (ResHob->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) {
InsertSystemMemoryResources (ResourceList, ResHob);
}
ResHob = (EFI_HOB_RESOURCE_DESCRIPTOR *)GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR,(VOID *)((UINTN)ResHob + ResHob->Header.HobLength));
}
return EFI_SUCCESS;
}
VOID
PrintPerformance (
VOID
)
{
UINTN Key;
CONST VOID *Handle;
CONST CHAR8 *Token, *Module;
UINT64 Start, Stop, TimeStamp;
UINT64 Delta, TicksPerSecond, Milliseconds;
UINTN Index;
CHAR8 Buffer[100];
UINTN CharCount;
BOOLEAN CountUp;
TicksPerSecond = GetPerformanceCounterProperties (&Start, &Stop);
if (Start < Stop) {
CountUp = TRUE;
} else {
CountUp = FALSE;
}
TimeStamp = 0;
Key = 0;
do {
Key = GetPerformanceMeasurement (Key, (CONST VOID **)&Handle, &Token, &Module, &Start, &Stop);
if (Key != 0) {
for (Index = 0; mTokenList[Index] != NULL; Index++) {
if (AsciiStriCmp (mTokenList[Index], Token) == 0) {
Delta = CountUp?(Stop - Start):(Start - Stop);
TimeStamp += Delta;
Milliseconds = DivU64x64Remainder (MultU64x32 (Delta, 1000), TicksPerSecond, NULL);
CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"%6a %6ld ms\n", Token, Milliseconds);
SerialPortWrite ((UINT8 *) Buffer, CharCount);
break;
}
}
}
} while (Key != 0);
CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Total Time = %ld ms\n\n", DivU64x64Remainder (MultU64x32 (TimeStamp, 1000), TicksPerSecond, NULL));
SerialPortWrite ((UINT8 *) Buffer, CharCount);
}
EFI_STATUS
GetEnvironmentVariable (
IN CONST CHAR16* VariableName,
IN VOID* DefaultValue,
IN OUT UINTN* Size,
OUT VOID** Value
)
{
EFI_STATUS Status;
UINTN VariableSize;
// Try to get the variable size.
*Value = NULL;
VariableSize = 0;
Status = gRT->GetVariable ((CHAR16 *) VariableName, &gEfiGlobalVariableGuid, NULL, &VariableSize, *Value);
if (Status == EFI_NOT_FOUND) {
if ((DefaultValue != NULL) && (Size != NULL) && (*Size != 0)) {
// If the environment variable does not exist yet then set it with the default value
Status = gRT->SetVariable (
(CHAR16*)VariableName,
&gEfiGlobalVariableGuid,
EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
*Size,
DefaultValue
);
*Value = DefaultValue;
} else {
return EFI_NOT_FOUND;
}
} else if (Status == EFI_BUFFER_TOO_SMALL) {
// Get the environment variable value
*Value = AllocatePool (VariableSize);
if (*Value == NULL) {
return EFI_OUT_OF_RESOURCES;
}
Status = gRT->GetVariable ((CHAR16 *)VariableName, &gEfiGlobalVariableGuid, NULL, &VariableSize, *Value);
if (EFI_ERROR (Status)) {
FreePool(*Value);
return EFI_INVALID_PARAMETER;
}
if (Size) {
*Size = VariableSize;
}
} else {
*Value = DefaultValue;
return Status;
}
return EFI_SUCCESS;
}

196
ArmPkg/Library/BdsLib/BdsInternal.h
View File

@ -1,98 +1,98 @@
/** @file
*
* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
* which accompanies this distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#ifndef __BDS_INTERNAL_H__
#define __BDS_INTERNAL_H__
#include <PiDxe.h>
#include <Library/ArmLib.h>
#include <Library/BaseLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/HobLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiLib.h>
#include <Library/DevicePathLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/DebugLib.h>
#include <Library/BdsLib.h>
#include <Library/PcdLib.h>
#include <Library/PerformanceLib.h>
#include <Library/PrintLib.h>
#include <Library/UefiRuntimeServicesTableLib.h>
#include <Guid/ArmMpCoreInfo.h>
#include <Guid/GlobalVariable.h>
#include <Guid/FileInfo.h>
#include <Protocol/DevicePath.h>
#include <Protocol/DevicePathFromText.h>
#include <Protocol/SimpleFileSystem.h>
#include <Protocol/FirmwareVolume2.h>
#include <Protocol/LoadFile.h>
#include <Protocol/PxeBaseCode.h>
#include <Uefi.h>
typedef BOOLEAN (*BDS_FILE_LOADER_SUPPORT) (
IN EFI_DEVICE_PATH *DevicePath,
IN EFI_HANDLE Handle,
IN EFI_DEVICE_PATH *RemainingDevicePath
);
typedef EFI_STATUS (*BDS_FILE_LOADER_LOAD_IMAGE) (
IN EFI_DEVICE_PATH *DevicePath,
IN EFI_HANDLE Handle,
IN EFI_DEVICE_PATH *RemainingDevicePath,
IN EFI_ALLOCATE_TYPE Type,
IN OUT EFI_PHYSICAL_ADDRESS* Image,
OUT UINTN *ImageSize
);
typedef struct {
BDS_FILE_LOADER_SUPPORT Support;
BDS_FILE_LOADER_LOAD_IMAGE LoadImage;
} BDS_FILE_LOADER;
typedef struct _BDS_SYSTEM_MEMORY_RESOURCE {
LIST_ENTRY Link; // This attribute must be the first entry of this structure (to avoid pointer computation)
EFI_PHYSICAL_ADDRESS PhysicalStart;
UINT64 ResourceLength;
} BDS_SYSTEM_MEMORY_RESOURCE;
// BdsHelper.c
EFI_STATUS
ShutdownUefiBootServices (
VOID
);
EFI_STATUS
GetSystemMemoryResources (
LIST_ENTRY *ResourceList
);
VOID
PrintPerformance (
VOID
);
EFI_STATUS
BdsLoadImage (
IN EFI_DEVICE_PATH *DevicePath,
IN EFI_ALLOCATE_TYPE Type,
IN OUT EFI_PHYSICAL_ADDRESS* Image,
OUT UINTN *FileSize
);
#endif
/** @file
*
* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
* which accompanies this distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#ifndef __BDS_INTERNAL_H__
#define __BDS_INTERNAL_H__
#include <PiDxe.h>
#include <Library/ArmLib.h>
#include <Library/BaseLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/HobLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiLib.h>
#include <Library/DevicePathLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/DebugLib.h>
#include <Library/BdsLib.h>
#include <Library/PcdLib.h>
#include <Library/PerformanceLib.h>
#include <Library/PrintLib.h>
#include <Library/UefiRuntimeServicesTableLib.h>
#include <Guid/ArmMpCoreInfo.h>
#include <Guid/GlobalVariable.h>
#include <Guid/FileInfo.h>
#include <Protocol/DevicePath.h>
#include <Protocol/DevicePathFromText.h>
#include <Protocol/SimpleFileSystem.h>
#include <Protocol/FirmwareVolume2.h>
#include <Protocol/LoadFile.h>
#include <Protocol/PxeBaseCode.h>
#include <Uefi.h>
typedef BOOLEAN (*BDS_FILE_LOADER_SUPPORT) (
IN EFI_DEVICE_PATH *DevicePath,
IN EFI_HANDLE Handle,
IN EFI_DEVICE_PATH *RemainingDevicePath
);
typedef EFI_STATUS (*BDS_FILE_LOADER_LOAD_IMAGE) (
IN EFI_DEVICE_PATH *DevicePath,
IN EFI_HANDLE Handle,
IN EFI_DEVICE_PATH *RemainingDevicePath,
IN EFI_ALLOCATE_TYPE Type,
IN OUT EFI_PHYSICAL_ADDRESS* Image,
OUT UINTN *ImageSize
);
typedef struct {
BDS_FILE_LOADER_SUPPORT Support;
BDS_FILE_LOADER_LOAD_IMAGE LoadImage;
} BDS_FILE_LOADER;
typedef struct _BDS_SYSTEM_MEMORY_RESOURCE {
LIST_ENTRY Link; // This attribute must be the first entry of this structure (to avoid pointer computation)
EFI_PHYSICAL_ADDRESS PhysicalStart;
UINT64 ResourceLength;
} BDS_SYSTEM_MEMORY_RESOURCE;
// BdsHelper.c
EFI_STATUS
ShutdownUefiBootServices (
VOID
);
EFI_STATUS
GetSystemMemoryResources (
LIST_ENTRY *ResourceList
);
VOID
PrintPerformance (
VOID
);
EFI_STATUS
BdsLoadImage (
IN EFI_DEVICE_PATH *DevicePath,
IN EFI_ALLOCATE_TYPE Type,
IN OUT EFI_PHYSICAL_ADDRESS* Image,
OUT UINTN *FileSize
);
#endif

154
ArmPkg/Library/BdsLib/BdsLib.inf
View File

@ -1,77 +1,77 @@
#/* @file
#
# Copyright (c) 2011-2012, ARM Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#*/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = BdsLib
FILE_GUID = ddbf73a0-bb25-11df-8e4e-0002a5d5c51b
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
LIBRARY_CLASS = BdsLib
[Sources.common]
BdsFilePath.c
BdsAppLoader.c
BdsHelper.c
BdsLoadOption.c
BdsLinuxLoader.c
BdsLinuxAtag.c
BdsLinuxFdt.c
[Packages]
MdePkg/MdePkg.dec
EmbeddedPkg/EmbeddedPkg.dec
ArmPkg/ArmPkg.dec
[LibraryClasses]
ArmLib
BaseLib
DebugLib
DevicePathLib
HobLib
PerformanceLib
SerialPortLib
FdtLib
[Guids]
gEfiFileInfoGuid
gArmMpCoreInfoGuid
[Protocols]
gEfiBdsArchProtocolGuid
gEfiDevicePathProtocolGuid
gEfiDevicePathFromTextProtocolGuid
gEfiSimpleFileSystemProtocolGuid
gEfiFirmwareVolume2ProtocolGuid
gEfiLoadFileProtocolGuid
gEfiPxeBaseCodeProtocolGuid
gEfiDiskIoProtocolGuid
gEfiUsbIoProtocolGuid
gEfiLoadedImageProtocolGuid
[FeaturePcd]
[FixedPcd]
gArmTokenSpaceGuid.PcdSystemMemoryBase
gArmTokenSpaceGuid.PcdSystemMemorySize
gArmTokenSpaceGuid.PcdArmMachineType
gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset
gArmTokenSpaceGuid.PcdArmLinuxKernelFixedOffset
gArmTokenSpaceGuid.PcdArmLinuxKernelMaxOffset
gArmTokenSpaceGuid.PcdArmLinuxAtagMaxOffset
[Depex]
TRUE
#/* @file
#
# Copyright (c) 2011-2012, ARM Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#*/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = BdsLib
FILE_GUID = ddbf73a0-bb25-11df-8e4e-0002a5d5c51b
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
LIBRARY_CLASS = BdsLib
[Sources.common]
BdsFilePath.c
BdsAppLoader.c
BdsHelper.c
BdsLoadOption.c
BdsLinuxLoader.c
BdsLinuxAtag.c
BdsLinuxFdt.c
[Packages]
MdePkg/MdePkg.dec
EmbeddedPkg/EmbeddedPkg.dec
ArmPkg/ArmPkg.dec
[LibraryClasses]
ArmLib
BaseLib
DebugLib
DevicePathLib
HobLib
PerformanceLib
SerialPortLib
FdtLib
[Guids]
gEfiFileInfoGuid
gArmMpCoreInfoGuid
[Protocols]
gEfiBdsArchProtocolGuid
gEfiDevicePathProtocolGuid
gEfiDevicePathFromTextProtocolGuid
gEfiSimpleFileSystemProtocolGuid
gEfiFirmwareVolume2ProtocolGuid
gEfiLoadFileProtocolGuid
gEfiPxeBaseCodeProtocolGuid
gEfiDiskIoProtocolGuid
gEfiUsbIoProtocolGuid
gEfiLoadedImageProtocolGuid
[FeaturePcd]
[FixedPcd]
gArmTokenSpaceGuid.PcdSystemMemoryBase
gArmTokenSpaceGuid.PcdSystemMemorySize
gArmTokenSpaceGuid.PcdArmMachineType
gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset
gArmTokenSpaceGuid.PcdArmLinuxKernelFixedOffset
gArmTokenSpaceGuid.PcdArmLinuxKernelMaxOffset
gArmTokenSpaceGuid.PcdArmLinuxAtagMaxOffset
[Depex]
TRUE

346
ArmPkg/Library/BdsLib/BdsLinuxAtag.c
View File

@ -1,173 +1,173 @@
/** @file
*
* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
* which accompanies this distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#include "BdsInternal.h"
#include "BdsLinuxLoader.h"
// Point to the current ATAG
STATIC LINUX_ATAG *mLinuxKernelCurrentAtag;
STATIC
VOID
SetupCoreTag (
IN UINT32 PageSize
)
{
mLinuxKernelCurrentAtag->header.size = tag_size(LINUX_ATAG_CORE);
mLinuxKernelCurrentAtag->header.type = ATAG_CORE;
mLinuxKernelCurrentAtag->body.core_tag.flags = 1; /* ensure read-only */
mLinuxKernelCurrentAtag->body.core_tag.pagesize = PageSize; /* systems PageSize (4k) */
mLinuxKernelCurrentAtag->body.core_tag.rootdev = 0; /* zero root device (typically overridden from kernel command line )*/
// move pointer to next tag
mLinuxKernelCurrentAtag = next_tag_address(mLinuxKernelCurrentAtag);
}
STATIC
VOID
SetupMemTag (
IN UINTN StartAddress,
IN UINT32 Size
)
{
mLinuxKernelCurrentAtag->header.size = tag_size(LINUX_ATAG_MEM);
mLinuxKernelCurrentAtag->header.type = ATAG_MEM;
mLinuxKernelCurrentAtag->body.mem_tag.start = StartAddress; /* Start of memory chunk for AtagMem */
mLinuxKernelCurrentAtag->body.mem_tag.size = Size; /* Size of memory chunk for AtagMem */
// move pointer to next tag
mLinuxKernelCurrentAtag = next_tag_address(mLinuxKernelCurrentAtag);
}
STATIC
VOID
SetupCmdlineTag (
IN CONST CHAR8 *CmdLine
)
{
UINT32 LineLength;
// Increment the line length by 1 to account for the null string terminator character
LineLength = AsciiStrLen(CmdLine) + 1;
/* Check for NULL strings.
* Do not insert a tag for an empty CommandLine, don't even modify the tag address pointer.
* Remember, you have at least one null string terminator character.
*/
if(LineLength > 1) {
mLinuxKernelCurrentAtag->header.size = ((UINT32)sizeof(LINUX_ATAG_HEADER) + LineLength + (UINT32)3) >> 2;
mLinuxKernelCurrentAtag->header.type = ATAG_CMDLINE;
/* place CommandLine into tag */
AsciiStrCpy(mLinuxKernelCurrentAtag->body.cmdline_tag.cmdline, CmdLine);
// move pointer to next tag
mLinuxKernelCurrentAtag = next_tag_address(mLinuxKernelCurrentAtag);
}
}
STATIC
VOID
SetupInitrdTag (
IN UINT32 InitrdImage,
IN UINT32 InitrdImageSize
)
{
mLinuxKernelCurrentAtag->header.size = tag_size(LINUX_ATAG_INITRD2);
mLinuxKernelCurrentAtag->header.type = ATAG_INITRD2;
mLinuxKernelCurrentAtag->body.initrd2_tag.start = InitrdImage;
mLinuxKernelCurrentAtag->body.initrd2_tag.size = InitrdImageSize;
// Move pointer to next tag
mLinuxKernelCurrentAtag = next_tag_address(mLinuxKernelCurrentAtag);
}
STATIC
VOID
SetupEndTag (
VOID
)
{
// Empty tag ends list; this has zero length and no body
mLinuxKernelCurrentAtag->header.type = ATAG_NONE;
mLinuxKernelCurrentAtag->header.size = 0;
/* We can not calculate the next address by using the standard macro:
* Params = next_tag_address(Params);
* because it relies on the header.size, which here it is 0 (zero).
* The easiest way is to add the sizeof(mLinuxKernelCurrentAtag->header).
*/
mLinuxKernelCurrentAtag = (LINUX_ATAG*)((UINT32)mLinuxKernelCurrentAtag + sizeof(mLinuxKernelCurrentAtag->header));
}
EFI_STATUS
PrepareAtagList (
IN CONST CHAR8* CommandLineString,
IN EFI_PHYSICAL_ADDRESS InitrdImage,
IN UINTN InitrdImageSize,
OUT EFI_PHYSICAL_ADDRESS *AtagBase,
OUT UINT32 *AtagSize
)
{
EFI_STATUS Status;
LIST_ENTRY *ResourceLink;
LIST_ENTRY ResourceList;
EFI_PHYSICAL_ADDRESS AtagStartAddress;
BDS_SYSTEM_MEMORY_RESOURCE *Resource;
AtagStartAddress = LINUX_ATAG_MAX_OFFSET;
Status = gBS->AllocatePages (AllocateMaxAddress, EfiBootServicesData, EFI_SIZE_TO_PAGES(ATAG_MAX_SIZE), &AtagStartAddress);
if (EFI_ERROR(Status)) {
DEBUG ((EFI_D_WARN, "Warning: Failed to allocate Atag at 0x%lX (%r). The Atag will be allocated somewhere else in System Memory.\n", AtagStartAddress, Status));
Status = gBS->AllocatePages (AllocateAnyPages, EfiBootServicesData, EFI_SIZE_TO_PAGES(ATAG_MAX_SIZE), &AtagStartAddress);
ASSERT_EFI_ERROR(Status);
}
// Ready to setup the atag list
mLinuxKernelCurrentAtag = (LINUX_ATAG*)(UINTN)AtagStartAddress;
// Standard core tag 4k PageSize
SetupCoreTag( (UINT32)SIZE_4KB );
// Physical memory setup
GetSystemMemoryResources (&ResourceList);
ResourceLink = ResourceList.ForwardLink;
while (ResourceLink != NULL && ResourceLink != &ResourceList) {
Resource = (BDS_SYSTEM_MEMORY_RESOURCE*)ResourceLink;
DEBUG((EFI_D_INFO,"- [0x%08X,0x%08X]\n",(UINT32)Resource->PhysicalStart,(UINT32)Resource->PhysicalStart+(UINT32)Resource->ResourceLength));
SetupMemTag( (UINT32)Resource->PhysicalStart, (UINT32)Resource->ResourceLength );
ResourceLink = ResourceLink->ForwardLink;
}
// CommandLine setting root device
if (CommandLineString) {
SetupCmdlineTag (CommandLineString);
}
if (InitrdImageSize > 0 && InitrdImage != 0) {
SetupInitrdTag ((UINT32)InitrdImage, (UINT32)InitrdImageSize);
}
// End of tags
SetupEndTag();
// Calculate atag list size
*AtagBase = AtagStartAddress;
*AtagSize = (UINT32)mLinuxKernelCurrentAtag - (UINT32)AtagStartAddress + 1;
return EFI_SUCCESS;
}
/** @file
*
* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
* which accompanies this distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#include "BdsInternal.h"
#include "BdsLinuxLoader.h"
// Point to the current ATAG
STATIC LINUX_ATAG *mLinuxKernelCurrentAtag;
STATIC
VOID
SetupCoreTag (
IN UINT32 PageSize
)
{
mLinuxKernelCurrentAtag->header.size = tag_size(LINUX_ATAG_CORE);
mLinuxKernelCurrentAtag->header.type = ATAG_CORE;
mLinuxKernelCurrentAtag->body.core_tag.flags = 1; /* ensure read-only */
mLinuxKernelCurrentAtag->body.core_tag.pagesize = PageSize; /* systems PageSize (4k) */
mLinuxKernelCurrentAtag->body.core_tag.rootdev = 0; /* zero root device (typically overridden from kernel command line )*/
// move pointer to next tag
mLinuxKernelCurrentAtag = next_tag_address(mLinuxKernelCurrentAtag);
}
STATIC
VOID
SetupMemTag (
IN UINTN StartAddress,
IN UINT32 Size
)
{
mLinuxKernelCurrentAtag->header.size = tag_size(LINUX_ATAG_MEM);
mLinuxKernelCurrentAtag->header.type = ATAG_MEM;
mLinuxKernelCurrentAtag->body.mem_tag.start = StartAddress; /* Start of memory chunk for AtagMem */
mLinuxKernelCurrentAtag->body.mem_tag.size = Size; /* Size of memory chunk for AtagMem */
// move pointer to next tag
mLinuxKernelCurrentAtag = next_tag_address(mLinuxKernelCurrentAtag);
}
STATIC
VOID
SetupCmdlineTag (
IN CONST CHAR8 *CmdLine
)
{
UINT32 LineLength;
// Increment the line length by 1 to account for the null string terminator character
LineLength = AsciiStrLen(CmdLine) + 1;
/* Check for NULL strings.
* Do not insert a tag for an empty CommandLine, don't even modify the tag address pointer.
* Remember, you have at least one null string terminator character.
*/
if(LineLength > 1) {
mLinuxKernelCurrentAtag->header.size = ((UINT32)sizeof(LINUX_ATAG_HEADER) + LineLength + (UINT32)3) >> 2;
mLinuxKernelCurrentAtag->header.type = ATAG_CMDLINE;
/* place CommandLine into tag */
AsciiStrCpy(mLinuxKernelCurrentAtag->body.cmdline_tag.cmdline, CmdLine);
// move pointer to next tag
mLinuxKernelCurrentAtag = next_tag_address(mLinuxKernelCurrentAtag);
}
}
STATIC
VOID
SetupInitrdTag (
IN UINT32 InitrdImage,
IN UINT32 InitrdImageSize
)
{
mLinuxKernelCurrentAtag->header.size = tag_size(LINUX_ATAG_INITRD2);
mLinuxKernelCurrentAtag->header.type = ATAG_INITRD2;
mLinuxKernelCurrentAtag->body.initrd2_tag.start = InitrdImage;
mLinuxKernelCurrentAtag->body.initrd2_tag.size = InitrdImageSize;
// Move pointer to next tag
mLinuxKernelCurrentAtag = next_tag_address(mLinuxKernelCurrentAtag);
}
STATIC
VOID
SetupEndTag (
VOID
)
{
// Empty tag ends list; this has zero length and no body
mLinuxKernelCurrentAtag->header.type = ATAG_NONE;
mLinuxKernelCurrentAtag->header.size = 0;
/* We can not calculate the next address by using the standard macro:
* Params = next_tag_address(Params);
* because it relies on the header.size, which here it is 0 (zero).
* The easiest way is to add the sizeof(mLinuxKernelCurrentAtag->header).
*/
mLinuxKernelCurrentAtag = (LINUX_ATAG*)((UINT32)mLinuxKernelCurrentAtag + sizeof(mLinuxKernelCurrentAtag->header));
}
EFI_STATUS
PrepareAtagList (
IN CONST CHAR8* CommandLineString,
IN EFI_PHYSICAL_ADDRESS InitrdImage,
IN UINTN InitrdImageSize,
OUT EFI_PHYSICAL_ADDRESS *AtagBase,
OUT UINT32 *AtagSize
)
{
EFI_STATUS Status;
LIST_ENTRY *ResourceLink;
LIST_ENTRY ResourceList;
EFI_PHYSICAL_ADDRESS AtagStartAddress;
BDS_SYSTEM_MEMORY_RESOURCE *Resource;
AtagStartAddress = LINUX_ATAG_MAX_OFFSET;
Status = gBS->AllocatePages (AllocateMaxAddress, EfiBootServicesData, EFI_SIZE_TO_PAGES(ATAG_MAX_SIZE), &AtagStartAddress);
if (EFI_ERROR(Status)) {
DEBUG ((EFI_D_WARN, "Warning: Failed to allocate Atag at 0x%lX (%r). The Atag will be allocated somewhere else in System Memory.\n", AtagStartAddress, Status));
Status = gBS->AllocatePages (AllocateAnyPages, EfiBootServicesData, EFI_SIZE_TO_PAGES(ATAG_MAX_SIZE), &AtagStartAddress);
ASSERT_EFI_ERROR(Status);
}
// Ready to setup the atag list
mLinuxKernelCurrentAtag = (LINUX_ATAG*)(UINTN)AtagStartAddress;
// Standard core tag 4k PageSize
SetupCoreTag( (UINT32)SIZE_4KB );
// Physical memory setup
GetSystemMemoryResources (&ResourceList);
ResourceLink = ResourceList.ForwardLink;
while (ResourceLink != NULL && ResourceLink != &ResourceList) {
Resource = (BDS_SYSTEM_MEMORY_RESOURCE*)ResourceLink;
DEBUG((EFI_D_INFO,"- [0x%08X,0x%08X]\n",(UINT32)Resource->PhysicalStart,(UINT32)Resource->PhysicalStart+(UINT32)Resource->ResourceLength));
SetupMemTag( (UINT32)Resource->PhysicalStart, (UINT32)Resource->ResourceLength );
ResourceLink = ResourceLink->ForwardLink;
}
// CommandLine setting root device
if (CommandLineString) {
SetupCmdlineTag (CommandLineString);
}
if (InitrdImageSize > 0 && InitrdImage != 0) {
SetupInitrdTag ((UINT32)InitrdImage, (UINT32)InitrdImageSize);
}
// End of tags
SetupEndTag();
// Calculate atag list size
*AtagBase = AtagStartAddress;
*AtagSize = (UINT32)mLinuxKernelCurrentAtag - (UINT32)AtagStartAddress + 1;
return EFI_SUCCESS;
}

548
ArmPkg/Library/BdsLib/BdsLinuxLoader.c
View File

@ -1,274 +1,274 @@
/** @file
*
* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
* which accompanies this distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#include "BdsInternal.h"
#include "BdsLinuxLoader.h"
#define ALIGN32_BELOW(addr) ALIGN_POINTER(addr - 32,32)
STATIC
EFI_STATUS
PreparePlatformHardware (
VOID
)
{
//Note: Interrupts will be disabled by the GIC driver when ExitBootServices() will be called.
// Clean, invalidate, disable data cache
ArmDisableDataCache();
ArmCleanInvalidateDataCache();
// Invalidate and disable the Instruction cache
ArmDisableInstructionCache ();
ArmInvalidateInstructionCache ();
// Turn off MMU
ArmDisableMmu();
return EFI_SUCCESS;
}
STATIC
EFI_STATUS
StartLinux (
IN EFI_PHYSICAL_ADDRESS LinuxImage,
IN UINTN LinuxImageSize,
IN EFI_PHYSICAL_ADDRESS KernelParamsAddress,
IN UINTN KernelParamsSize,
IN UINT32 MachineType
)
{
EFI_STATUS Status;
LINUX_KERNEL LinuxKernel;
// Shut down UEFI boot services. ExitBootServices() will notify every driver that created an event on
// ExitBootServices event. Example the Interrupt DXE driver will disable the interrupts on this event.
Status = ShutdownUefiBootServices ();
if(EFI_ERROR(Status)) {
DEBUG((EFI_D_ERROR,"ERROR: Can not shutdown UEFI boot services. Status=0x%X\n", Status));
goto Exit;
}
// Move the kernel parameters to any address inside the first 1MB.
// This is necessary because the ARM Linux kernel requires
// the FTD / ATAG List to reside entirely inside the first 1MB of
// physical memory.
//Note: There is no requirement on the alignment
if (MachineType != ARM_FDT_MACHINE_TYPE) {
if (((UINTN)KernelParamsAddress > LINUX_ATAG_MAX_OFFSET) && (KernelParamsSize < PcdGet32(PcdArmLinuxAtagMaxOffset))) {
KernelParamsAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)CopyMem (ALIGN32_BELOW(LINUX_ATAG_MAX_OFFSET - KernelParamsSize), (VOID*)(UINTN)KernelParamsAddress, KernelParamsSize);
}
} else {
if (((UINTN)KernelParamsAddress > LINUX_FDT_MAX_OFFSET) && (KernelParamsSize < PcdGet32(PcdArmLinuxFdtMaxOffset))) {
KernelParamsAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)CopyMem (ALIGN32_BELOW(LINUX_FDT_MAX_OFFSET - KernelParamsSize), (VOID*)(UINTN)KernelParamsAddress, KernelParamsSize);
}
}
if ((UINTN)LinuxImage > LINUX_KERNEL_MAX_OFFSET) {
//Note: There is no requirement on the alignment
LinuxKernel = (LINUX_KERNEL)CopyMem (ALIGN32_BELOW(LINUX_KERNEL_MAX_OFFSET - LinuxImageSize), (VOID*)(UINTN)LinuxImage, LinuxImageSize);
} else {
LinuxKernel = (LINUX_KERNEL)(UINTN)LinuxImage;
}
// Check if the Linux Image is a uImage
if (*(UINT32*)LinuxKernel == LINUX_UIMAGE_SIGNATURE) {
// Assume the Image Entry Point is just after the uImage header (64-byte size)
LinuxKernel = (LINUX_KERNEL)((UINTN)LinuxKernel + 64);
LinuxImageSize -= 64;
}
//TODO: Check there is no overlapping between kernel and Atag
//
// Switch off interrupts, caches, mmu, etc
//
Status = PreparePlatformHardware ();
ASSERT_EFI_ERROR(Status);
// Register and print out performance information
PERF_END (NULL, "BDS", NULL, 0);
if (PerformanceMeasurementEnabled ()) {
PrintPerformance ();
}
//
// Start the Linux Kernel
//
// Outside BootServices, so can't use Print();
DEBUG((EFI_D_ERROR, "\nStarting the kernel:\n\n"));
// Jump to kernel with register set
LinuxKernel ((UINTN)0, MachineType, (UINTN)KernelParamsAddress);
// Kernel should never exit
// After Life services are not provided
ASSERT(FALSE);
Exit:
// Only be here if we fail to start Linux
Print (L"ERROR : Can not start the kernel. Status=0x%X\n", Status);
// Free Runtimee Memory (kernel and FDT)
return Status;
}
/**
Start a Linux kernel from a Device Path
@param LinuxKernel Device Path to the Linux Kernel
@param Parameters Linux kernel arguments
@param Fdt Device Path to the Flat Device Tree
@retval EFI_SUCCESS All drivers have been connected
@retval EFI_NOT_FOUND The Linux kernel Device Path has not been found
@retval EFI_OUT_OF_RESOURCES There is not enough resource memory to store the matching results.
**/
EFI_STATUS
BdsBootLinuxAtag (
IN EFI_DEVICE_PATH_PROTOCOL* LinuxKernelDevicePath,
IN EFI_DEVICE_PATH_PROTOCOL* InitrdDevicePath,
IN CONST CHAR8* CommandLineArguments
)
{
EFI_STATUS Status;
UINT32 LinuxImageSize;
UINT32 InitrdImageSize = 0;
UINT32 AtagSize;
EFI_PHYSICAL_ADDRESS AtagBase;
EFI_PHYSICAL_ADDRESS LinuxImage;
EFI_PHYSICAL_ADDRESS InitrdImage;
PERF_START (NULL, "BDS", NULL, 0);
// Load the Linux kernel from a device path
LinuxImage = LINUX_KERNEL_MAX_OFFSET;
Status = BdsLoadImage (LinuxKernelDevicePath, AllocateMaxAddress, &LinuxImage, &LinuxImageSize);
if (EFI_ERROR(Status)) {
Print (L"ERROR: Did not find Linux kernel.\n");
return Status;
}
if (InitrdDevicePath) {
// Load the initrd near to the Linux kernel
InitrdImage = LINUX_KERNEL_MAX_OFFSET;
Status = BdsLoadImage (InitrdDevicePath, AllocateMaxAddress, &InitrdImage, &InitrdImageSize);
if (Status == EFI_OUT_OF_RESOURCES) {
Status = BdsLoadImage (InitrdDevicePath, AllocateAnyPages, &InitrdImage, &InitrdImageSize);
}
if (EFI_ERROR(Status)) {
Print (L"ERROR: Did not find initrd image.\n");
return Status;
}
// Check if the initrd is a uInitrd
if (*(UINT32*)((UINTN)InitrdImage) == LINUX_UIMAGE_SIGNATURE) {
// Skip the 64-byte image header
InitrdImage = (EFI_PHYSICAL_ADDRESS)((UINTN)InitrdImage + 64);
InitrdImageSize -= 64;
}
}
//
// Setup the Linux Kernel Parameters
//
// By setting address=0 we leave the memory allocation to the function
Status = PrepareAtagList (CommandLineArguments, InitrdImage, InitrdImageSize, &AtagBase, &AtagSize);
if (EFI_ERROR(Status)) {
Print(L"ERROR: Can not prepare ATAG list. Status=0x%X\n", Status);
return Status;
}
return StartLinux (LinuxImage, LinuxImageSize, AtagBase, AtagSize, PcdGet32(PcdArmMachineType));
}
/**
Start a Linux kernel from a Device Path
@param LinuxKernel Device Path to the Linux Kernel
@param Parameters Linux kernel arguments
@param Fdt Device Path to the Flat Device Tree
@retval EFI_SUCCESS All drivers have been connected
@retval EFI_NOT_FOUND The Linux kernel Device Path has not been found
@retval EFI_OUT_OF_RESOURCES There is not enough resource memory to store the matching results.
**/
EFI_STATUS
BdsBootLinuxFdt (
IN EFI_DEVICE_PATH_PROTOCOL* LinuxKernelDevicePath,
IN EFI_DEVICE_PATH_PROTOCOL* InitrdDevicePath,
IN CONST CHAR8* CommandLineArguments,
IN EFI_DEVICE_PATH_PROTOCOL* FdtDevicePath
)
{
EFI_STATUS Status;
UINT32 LinuxImageSize;
UINT32 InitrdImageSize = 0;
UINT32 FdtBlobSize;
EFI_PHYSICAL_ADDRESS FdtBlobBase;
EFI_PHYSICAL_ADDRESS LinuxImage;
EFI_PHYSICAL_ADDRESS InitrdImage;
PERF_START (NULL, "BDS", NULL, 0);
// Load the Linux kernel from a device path
LinuxImage = LINUX_KERNEL_MAX_OFFSET;
Status = BdsLoadImage (LinuxKernelDevicePath, AllocateMaxAddress, &LinuxImage, &LinuxImageSize);
if (EFI_ERROR(Status)) {
Print (L"ERROR: Did not find Linux kernel.\n");
return Status;
}
if (InitrdDevicePath) {
InitrdImage = LINUX_KERNEL_MAX_OFFSET;
Status = BdsLoadImage (InitrdDevicePath, AllocateMaxAddress, &InitrdImage, &InitrdImageSize);
if (Status == EFI_OUT_OF_RESOURCES) {
Status = BdsLoadImage (InitrdDevicePath, AllocateAnyPages, &InitrdImage, &InitrdImageSize);
}
if (EFI_ERROR(Status)) {
Print (L"ERROR: Did not find initrd image.\n");
return Status;
}
// Check if the initrd is a uInitrd
if (*(UINT32*)((UINTN)InitrdImage) == LINUX_UIMAGE_SIGNATURE) {
// Skip the 64-byte image header
InitrdImage = (EFI_PHYSICAL_ADDRESS)((UINTN)InitrdImage + 64);
InitrdImageSize -= 64;
}
}
// Load the FDT binary from a device path. The FDT will be reloaded later to a more appropriate location for the Linux kernel.
FdtBlobBase = 0;
Status = BdsLoadImage (FdtDevicePath, AllocateAnyPages, &FdtBlobBase, &FdtBlobSize);
if (EFI_ERROR(Status)) {
Print (L"ERROR: Did not find Device Tree blob.\n");
return Status;
}
// Update the Fdt with the Initrd information. The FDT will increase in size.
// By setting address=0 we leave the memory allocation to the function
Status = PrepareFdt (CommandLineArguments, InitrdImage, InitrdImageSize, &FdtBlobBase, &FdtBlobSize);
if (EFI_ERROR(Status)) {
Print(L"ERROR: Can not load kernel with FDT. Status=%r\n", Status);
return Status;
}
return StartLinux (LinuxImage, LinuxImageSize, FdtBlobBase, FdtBlobSize, ARM_FDT_MACHINE_TYPE);
}
/** @file
*
* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
* which accompanies this distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#include "BdsInternal.h"
#include "BdsLinuxLoader.h"
#define ALIGN32_BELOW(addr) ALIGN_POINTER(addr - 32,32)
STATIC
EFI_STATUS
PreparePlatformHardware (
VOID
)
{
//Note: Interrupts will be disabled by the GIC driver when ExitBootServices() will be called.
// Clean, invalidate, disable data cache
ArmDisableDataCache();
ArmCleanInvalidateDataCache();
// Invalidate and disable the Instruction cache
ArmDisableInstructionCache ();
ArmInvalidateInstructionCache ();
// Turn off MMU
ArmDisableMmu();
return EFI_SUCCESS;
}
STATIC
EFI_STATUS
StartLinux (
IN EFI_PHYSICAL_ADDRESS LinuxImage,
IN UINTN LinuxImageSize,
IN EFI_PHYSICAL_ADDRESS KernelParamsAddress,
IN UINTN KernelParamsSize,
IN UINT32 MachineType
)
{
EFI_STATUS Status;
LINUX_KERNEL LinuxKernel;
// Shut down UEFI boot services. ExitBootServices() will notify every driver that created an event on
// ExitBootServices event. Example the Interrupt DXE driver will disable the interrupts on this event.
Status = ShutdownUefiBootServices ();
if(EFI_ERROR(Status)) {
DEBUG((EFI_D_ERROR,"ERROR: Can not shutdown UEFI boot services. Status=0x%X\n", Status));
goto Exit;
}
// Move the kernel parameters to any address inside the first 1MB.
// This is necessary because the ARM Linux kernel requires
// the FTD / ATAG List to reside entirely inside the first 1MB of
// physical memory.
//Note: There is no requirement on the alignment
if (MachineType != ARM_FDT_MACHINE_TYPE) {
if (((UINTN)KernelParamsAddress > LINUX_ATAG_MAX_OFFSET) && (KernelParamsSize < PcdGet32(PcdArmLinuxAtagMaxOffset))) {
KernelParamsAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)CopyMem (ALIGN32_BELOW(LINUX_ATAG_MAX_OFFSET - KernelParamsSize), (VOID*)(UINTN)KernelParamsAddress, KernelParamsSize);
}
} else {
if (((UINTN)KernelParamsAddress > LINUX_FDT_MAX_OFFSET) && (KernelParamsSize < PcdGet32(PcdArmLinuxFdtMaxOffset))) {
KernelParamsAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)CopyMem (ALIGN32_BELOW(LINUX_FDT_MAX_OFFSET - KernelParamsSize), (VOID*)(UINTN)KernelParamsAddress, KernelParamsSize);
}
}
if ((UINTN)LinuxImage > LINUX_KERNEL_MAX_OFFSET) {
//Note: There is no requirement on the alignment
LinuxKernel = (LINUX_KERNEL)CopyMem (ALIGN32_BELOW(LINUX_KERNEL_MAX_OFFSET - LinuxImageSize), (VOID*)(UINTN)LinuxImage, LinuxImageSize);
} else {
LinuxKernel = (LINUX_KERNEL)(UINTN)LinuxImage;
}
// Check if the Linux Image is a uImage
if (*(UINT32*)LinuxKernel == LINUX_UIMAGE_SIGNATURE) {
// Assume the Image Entry Point is just after the uImage header (64-byte size)
LinuxKernel = (LINUX_KERNEL)((UINTN)LinuxKernel + 64);
LinuxImageSize -= 64;
}
//TODO: Check there is no overlapping between kernel and Atag
//
// Switch off interrupts, caches, mmu, etc
//
Status = PreparePlatformHardware ();
ASSERT_EFI_ERROR(Status);
// Register and print out performance information
PERF_END (NULL, "BDS", NULL, 0);
if (PerformanceMeasurementEnabled ()) {
PrintPerformance ();
}
//
// Start the Linux Kernel
//
// Outside BootServices, so can't use Print();
DEBUG((EFI_D_ERROR, "\nStarting the kernel:\n\n"));
// Jump to kernel with register set
LinuxKernel ((UINTN)0, MachineType, (UINTN)KernelParamsAddress);
// Kernel should never exit
// After Life services are not provided
ASSERT(FALSE);
Exit:
// Only be here if we fail to start Linux
Print (L"ERROR : Can not start the kernel. Status=0x%X\n", Status);
// Free Runtimee Memory (kernel and FDT)
return Status;
}
/**
Start a Linux kernel from a Device Path
@param LinuxKernel Device Path to the Linux Kernel
@param Parameters Linux kernel arguments
@param Fdt Device Path to the Flat Device Tree
@retval EFI_SUCCESS All drivers have been connected
@retval EFI_NOT_FOUND The Linux kernel Device Path has not been found
@retval EFI_OUT_OF_RESOURCES There is not enough resource memory to store the matching results.
**/
EFI_STATUS
BdsBootLinuxAtag (
IN EFI_DEVICE_PATH_PROTOCOL* LinuxKernelDevicePath,
IN EFI_DEVICE_PATH_PROTOCOL* InitrdDevicePath,
IN CONST CHAR8* CommandLineArguments
)
{
EFI_STATUS Status;
UINT32 LinuxImageSize;
UINT32 InitrdImageSize = 0;
UINT32 AtagSize;
EFI_PHYSICAL_ADDRESS AtagBase;
EFI_PHYSICAL_ADDRESS LinuxImage;
EFI_PHYSICAL_ADDRESS InitrdImage;
PERF_START (NULL, "BDS", NULL, 0);
// Load the Linux kernel from a device path
LinuxImage = LINUX_KERNEL_MAX_OFFSET;
Status = BdsLoadImage (LinuxKernelDevicePath, AllocateMaxAddress, &LinuxImage, &LinuxImageSize);
if (EFI_ERROR(Status)) {
Print (L"ERROR: Did not find Linux kernel.\n");
return Status;
}
if (InitrdDevicePath) {
// Load the initrd near to the Linux kernel
InitrdImage = LINUX_KERNEL_MAX_OFFSET;
Status = BdsLoadImage (InitrdDevicePath, AllocateMaxAddress, &InitrdImage, &InitrdImageSize);
if (Status == EFI_OUT_OF_RESOURCES) {
Status = BdsLoadImage (InitrdDevicePath, AllocateAnyPages, &InitrdImage, &InitrdImageSize);
}
if (EFI_ERROR(Status)) {
Print (L"ERROR: Did not find initrd image.\n");
return Status;
}
// Check if the initrd is a uInitrd
if (*(UINT32*)((UINTN)InitrdImage) == LINUX_UIMAGE_SIGNATURE) {
// Skip the 64-byte image header
InitrdImage = (EFI_PHYSICAL_ADDRESS)((UINTN)InitrdImage + 64);
InitrdImageSize -= 64;
}
}
//
// Setup the Linux Kernel Parameters
//
// By setting address=0 we leave the memory allocation to the function
Status = PrepareAtagList (CommandLineArguments, InitrdImage, InitrdImageSize, &AtagBase, &AtagSize);
if (EFI_ERROR(Status)) {
Print(L"ERROR: Can not prepare ATAG list. Status=0x%X\n", Status);
return Status;
}
return StartLinux (LinuxImage, LinuxImageSize, AtagBase, AtagSize, PcdGet32(PcdArmMachineType));
}
/**
Start a Linux kernel from a Device Path
@param LinuxKernel Device Path to the Linux Kernel
@param Parameters Linux kernel arguments
@param Fdt Device Path to the Flat Device Tree
@retval EFI_SUCCESS All drivers have been connected
@retval EFI_NOT_FOUND The Linux kernel Device Path has not been found
@retval EFI_OUT_OF_RESOURCES There is not enough resource memory to store the matching results.
**/
EFI_STATUS
BdsBootLinuxFdt (
IN EFI_DEVICE_PATH_PROTOCOL* LinuxKernelDevicePath,
IN EFI_DEVICE_PATH_PROTOCOL* InitrdDevicePath,
IN CONST CHAR8* CommandLineArguments,
IN EFI_DEVICE_PATH_PROTOCOL* FdtDevicePath
)
{
EFI_STATUS Status;
UINT32 LinuxImageSize;
UINT32 InitrdImageSize = 0;
UINT32 FdtBlobSize;
EFI_PHYSICAL_ADDRESS FdtBlobBase;
EFI_PHYSICAL_ADDRESS LinuxImage;
EFI_PHYSICAL_ADDRESS InitrdImage;
PERF_START (NULL, "BDS", NULL, 0);
// Load the Linux kernel from a device path
LinuxImage = LINUX_KERNEL_MAX_OFFSET;
Status = BdsLoadImage (LinuxKernelDevicePath, AllocateMaxAddress, &LinuxImage, &LinuxImageSize);
if (EFI_ERROR(Status)) {
Print (L"ERROR: Did not find Linux kernel.\n");
return Status;
}
if (InitrdDevicePath) {
InitrdImage = LINUX_KERNEL_MAX_OFFSET;
Status = BdsLoadImage (InitrdDevicePath, AllocateMaxAddress, &InitrdImage, &InitrdImageSize);
if (Status == EFI_OUT_OF_RESOURCES) {
Status = BdsLoadImage (InitrdDevicePath, AllocateAnyPages, &InitrdImage, &InitrdImageSize);
}
if (EFI_ERROR(Status)) {
Print (L"ERROR: Did not find initrd image.\n");
return Status;
}
// Check if the initrd is a uInitrd
if (*(UINT32*)((UINTN)InitrdImage) == LINUX_UIMAGE_SIGNATURE) {
// Skip the 64-byte image header
InitrdImage = (EFI_PHYSICAL_ADDRESS)((UINTN)InitrdImage + 64);
InitrdImageSize -= 64;
}
}
// Load the FDT binary from a device path. The FDT will be reloaded later to a more appropriate location for the Linux kernel.
FdtBlobBase = 0;
Status = BdsLoadImage (FdtDevicePath, AllocateAnyPages, &FdtBlobBase, &FdtBlobSize);
if (EFI_ERROR(Status)) {
Print (L"ERROR: Did not find Device Tree blob.\n");
return Status;
}
// Update the Fdt with the Initrd information. The FDT will increase in size.
// By setting address=0 we leave the memory allocation to the function
Status = PrepareFdt (CommandLineArguments, InitrdImage, InitrdImageSize, &FdtBlobBase, &FdtBlobSize);
if (EFI_ERROR(Status)) {
Print(L"ERROR: Can not load kernel with FDT. Status=%r\n", Status);
return Status;
}
return StartLinux (LinuxImage, LinuxImageSize, FdtBlobBase, FdtBlobSize, ARM_FDT_MACHINE_TYPE);
}

312
ArmPkg/Library/BdsLib/BdsLinuxLoader.h
View File

@ -1,156 +1,156 @@
/** @file
*
* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
* which accompanies this distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#ifndef __BDSLINUXLOADER_H
#define __BDSLINUXLOADER_H
#define LINUX_UIMAGE_SIGNATURE 0x56190527
#define LINUX_KERNEL_MAX_OFFSET (PcdGet32(PcdSystemMemoryBase) + PcdGet32(PcdArmLinuxKernelMaxOffset))
#define LINUX_ATAG_MAX_OFFSET (PcdGet32(PcdSystemMemoryBase) + PcdGet32(PcdArmLinuxAtagMaxOffset))
#define LINUX_FDT_MAX_OFFSET (PcdGet32(PcdSystemMemoryBase) + PcdGet32(PcdArmLinuxFdtMaxOffset))
// Additional size that could be used for FDT entries added by the UEFI OS Loader
// Estimation based on: EDID (300bytes) + bootargs (200bytes) + initrd region (20bytes)
// + system memory region (20bytes) + mp_core entries (200 bytes)
#define FDT_ADDITIONAL_ENTRIES_SIZE 0x300
#define ARM_FDT_MACHINE_TYPE 0xFFFFFFFF
typedef VOID (*LINUX_KERNEL)(UINT32 Zero, UINT32 Arch, UINTN ParametersBase);
//
// ATAG Definitions
//
#define ATAG_MAX_SIZE 0x3000
/* ATAG : list of possible tags */
#define ATAG_NONE 0x00000000
#define ATAG_CORE 0x54410001
#define ATAG_MEM 0x54410002
#define ATAG_VIDEOTEXT 0x54410003
#define ATAG_RAMDISK 0x54410004
#define ATAG_INITRD2 0x54420005
#define ATAG_SERIAL 0x54410006
#define ATAG_REVISION 0x54410007
#define ATAG_VIDEOLFB 0x54410008
#define ATAG_CMDLINE 0x54410009
#define ATAG_ARM_MP_CORE 0x5441000A
#define next_tag_address(t) ((LINUX_ATAG*)((UINT32)(t) + (((t)->header.size) << 2) ))
#define tag_size(type) ((UINT32)((sizeof(LINUX_ATAG_HEADER) + sizeof(type)) >> 2))
typedef struct {
UINT32 size; /* length of tag in words including this header */
UINT32 type; /* tag type */
} LINUX_ATAG_HEADER;
typedef struct {
UINT32 flags;
UINT32 pagesize;
UINT32 rootdev;
} LINUX_ATAG_CORE;
typedef struct {
UINT32 size;
UINTN start;
} LINUX_ATAG_MEM;
typedef struct {
UINT8 x;
UINT8 y;
UINT16 video_page;
UINT8 video_mode;
UINT8 video_cols;
UINT16 video_ega_bx;
UINT8 video_lines;
UINT8 video_isvga;
UINT16 video_points;
} LINUX_ATAG_VIDEOTEXT;
typedef struct {
UINT32 flags;
UINT32 size;
UINTN start;
} LINUX_ATAG_RAMDISK;
typedef struct {
UINT32 start;
UINT32 size;
} LINUX_ATAG_INITRD2;
typedef struct {
UINT32 low;
UINT32 high;
} LINUX_ATAG_SERIALNR;
typedef struct {
UINT32 rev;
} LINUX_ATAG_REVISION;
typedef struct {
UINT16 lfb_width;
UINT16 lfb_height;
UINT16 lfb_depth;
UINT16 lfb_linelength;
UINT32 lfb_base;
UINT32 lfb_size;
UINT8 red_size;
UINT8 red_pos;
UINT8 green_size;
UINT8 green_pos;
UINT8 blue_size;
UINT8 blue_pos;
UINT8 rsvd_size;
UINT8 rsvd_pos;
} LINUX_ATAG_VIDEOLFB;
typedef struct {
CHAR8 cmdline[1];
} LINUX_ATAG_CMDLINE;
typedef struct {
LINUX_ATAG_HEADER header;
union {
LINUX_ATAG_CORE core_tag;
LINUX_ATAG_MEM mem_tag;
LINUX_ATAG_VIDEOTEXT videotext_tag;
LINUX_ATAG_RAMDISK ramdisk_tag;
LINUX_ATAG_INITRD2 initrd2_tag;
LINUX_ATAG_SERIALNR serialnr_tag;
LINUX_ATAG_REVISION revision_tag;
LINUX_ATAG_VIDEOLFB videolfb_tag;
LINUX_ATAG_CMDLINE cmdline_tag;
} body;
} LINUX_ATAG;
EFI_STATUS
PrepareAtagList (
IN CONST CHAR8* CommandLineString,
IN EFI_PHYSICAL_ADDRESS InitrdImage,
IN UINTN InitrdImageSize,
OUT EFI_PHYSICAL_ADDRESS *AtagBase,
OUT UINT32 *AtagSize
);
EFI_STATUS
PrepareFdt (
IN CONST CHAR8* CommandLineArguments,
IN EFI_PHYSICAL_ADDRESS InitrdImage,
IN UINTN InitrdImageSize,
IN OUT EFI_PHYSICAL_ADDRESS *FdtBlobBase,
IN OUT UINT32 *FdtBlobSize
);
#endif
/** @file
*
* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
* which accompanies this distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#ifndef __BDSLINUXLOADER_H
#define __BDSLINUXLOADER_H
#define LINUX_UIMAGE_SIGNATURE 0x56190527
#define LINUX_KERNEL_MAX_OFFSET (PcdGet32(PcdSystemMemoryBase) + PcdGet32(PcdArmLinuxKernelMaxOffset))
#define LINUX_ATAG_MAX_OFFSET (PcdGet32(PcdSystemMemoryBase) + PcdGet32(PcdArmLinuxAtagMaxOffset))
#define LINUX_FDT_MAX_OFFSET (PcdGet32(PcdSystemMemoryBase) + PcdGet32(PcdArmLinuxFdtMaxOffset))
// Additional size that could be used for FDT entries added by the UEFI OS Loader
// Estimation based on: EDID (300bytes) + bootargs (200bytes) + initrd region (20bytes)
// + system memory region (20bytes) + mp_core entries (200 bytes)
#define FDT_ADDITIONAL_ENTRIES_SIZE 0x300
#define ARM_FDT_MACHINE_TYPE 0xFFFFFFFF
typedef VOID (*LINUX_KERNEL)(UINT32 Zero, UINT32 Arch, UINTN ParametersBase);
//
// ATAG Definitions
//
#define ATAG_MAX_SIZE 0x3000
/* ATAG : list of possible tags */
#define ATAG_NONE 0x00000000
#define ATAG_CORE 0x54410001
#define ATAG_MEM 0x54410002
#define ATAG_VIDEOTEXT 0x54410003
#define ATAG_RAMDISK 0x54410004
#define ATAG_INITRD2 0x54420005
#define ATAG_SERIAL 0x54410006
#define ATAG_REVISION 0x54410007
#define ATAG_VIDEOLFB 0x54410008
#define ATAG_CMDLINE 0x54410009
#define ATAG_ARM_MP_CORE 0x5441000A
#define next_tag_address(t) ((LINUX_ATAG*)((UINT32)(t) + (((t)->header.size) << 2) ))
#define tag_size(type) ((UINT32)((sizeof(LINUX_ATAG_HEADER) + sizeof(type)) >> 2))
typedef struct {
UINT32 size; /* length of tag in words including this header */
UINT32 type; /* tag type */
} LINUX_ATAG_HEADER;
typedef struct {
UINT32 flags;
UINT32 pagesize;
UINT32 rootdev;
} LINUX_ATAG_CORE;
typedef struct {
UINT32 size;
UINTN start;
} LINUX_ATAG_MEM;
typedef struct {
UINT8 x;
UINT8 y;
UINT16 video_page;
UINT8 video_mode;
UINT8 video_cols;
UINT16 video_ega_bx;
UINT8 video_lines;
UINT8 video_isvga;
UINT16 video_points;
} LINUX_ATAG_VIDEOTEXT;
typedef struct {
UINT32 flags;
UINT32 size;
UINTN start;
} LINUX_ATAG_RAMDISK;
typedef struct {
UINT32 start;
UINT32 size;
} LINUX_ATAG_INITRD2;
typedef struct {
UINT32 low;
UINT32 high;
} LINUX_ATAG_SERIALNR;
typedef struct {
UINT32 rev;
} LINUX_ATAG_REVISION;
typedef struct {
UINT16 lfb_width;
UINT16 lfb_height;
UINT16 lfb_depth;
UINT16 lfb_linelength;
UINT32 lfb_base;
UINT32 lfb_size;
UINT8 red_size;
UINT8 red_pos;
UINT8 green_size;
UINT8 green_pos;
UINT8 blue_size;
UINT8 blue_pos;
UINT8 rsvd_size;
UINT8 rsvd_pos;
} LINUX_ATAG_VIDEOLFB;
typedef struct {
CHAR8 cmdline[1];
} LINUX_ATAG_CMDLINE;
typedef struct {
LINUX_ATAG_HEADER header;
union {
LINUX_ATAG_CORE core_tag;
LINUX_ATAG_MEM mem_tag;
LINUX_ATAG_VIDEOTEXT videotext_tag;
LINUX_ATAG_RAMDISK ramdisk_tag;
LINUX_ATAG_INITRD2 initrd2_tag;
LINUX_ATAG_SERIALNR serialnr_tag;
LINUX_ATAG_REVISION revision_tag;
LINUX_ATAG_VIDEOLFB videolfb_tag;
LINUX_ATAG_CMDLINE cmdline_tag;
} body;
} LINUX_ATAG;
EFI_STATUS
PrepareAtagList (
IN CONST CHAR8* CommandLineString,
IN EFI_PHYSICAL_ADDRESS InitrdImage,
IN UINTN InitrdImageSize,
OUT EFI_PHYSICAL_ADDRESS *AtagBase,
OUT UINT32 *AtagSize
);
EFI_STATUS
PrepareFdt (
IN CONST CHAR8* CommandLineArguments,
IN EFI_PHYSICAL_ADDRESS InitrdImage,
IN UINTN InitrdImageSize,
IN OUT EFI_PHYSICAL_ADDRESS *FdtBlobBase,
IN OUT UINT32 *FdtBlobSize
);
#endif

540
ArmPkg/Library/BdsLib/BdsLoadOption.c
View File

@ -1,270 +1,270 @@
/** @file
*
* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
* which accompanies this distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#include "BdsInternal.h"
EFI_STATUS
BootOptionParseLoadOption (
IN EFI_LOAD_OPTION EfiLoadOption,
IN UINTN EfiLoadOptionSize,
IN OUT BDS_LOAD_OPTION **BdsLoadOption
)
{
BDS_LOAD_OPTION *LoadOption;
UINTN DescriptionLength;
if (EfiLoadOption == NULL) {
return EFI_INVALID_PARAMETER;
}
if (EfiLoadOptionSize < sizeof(UINT32) + sizeof(UINT16) + sizeof(CHAR16) + sizeof(EFI_DEVICE_PATH_PROTOCOL)) {
return EFI_BAD_BUFFER_SIZE;
}
if (*BdsLoadOption == NULL) {
LoadOption = (BDS_LOAD_OPTION*)AllocateZeroPool (sizeof(BDS_LOAD_OPTION));
if (LoadOption == NULL) {
return EFI_OUT_OF_RESOURCES;
}
} else {
LoadOption = *BdsLoadOption;
}
LoadOption->LoadOption = EfiLoadOption;
LoadOption->LoadOptionSize = EfiLoadOptionSize;
LoadOption->Attributes = *(UINT32*)EfiLoadOption;
LoadOption->FilePathListLength = *(UINT16*)(EfiLoadOption + sizeof(UINT32));
LoadOption->Description = (CHAR16*)(EfiLoadOption + sizeof(UINT32) + sizeof(UINT16));
DescriptionLength = StrSize (LoadOption->Description);
LoadOption->FilePathList = (EFI_DEVICE_PATH_PROTOCOL*)(EfiLoadOption + sizeof(UINT32) + sizeof(UINT16) + DescriptionLength);
// If ((End of EfiLoadOptiony - Start of EfiLoadOption) == EfiLoadOptionSize) then No Optional Data
if ((UINTN)((UINTN)LoadOption->FilePathList + LoadOption->FilePathListLength - (UINTN)EfiLoadOption) == EfiLoadOptionSize) {
LoadOption->OptionalData = NULL;
LoadOption->OptionalDataSize = 0;
} else {
LoadOption->OptionalData = (VOID*)((UINTN)(LoadOption->FilePathList) + LoadOption->FilePathListLength);
LoadOption->OptionalDataSize = EfiLoadOptionSize - ((UINTN)LoadOption->OptionalData - (UINTN)EfiLoadOption);
}
if (*BdsLoadOption == NULL) {
*BdsLoadOption = LoadOption;
}
return EFI_SUCCESS;
}
EFI_STATUS
BootOptionFromLoadOptionVariable (
IN CHAR16* BootVariableName,
OUT BDS_LOAD_OPTION** BdsLoadOption
)
{
EFI_STATUS Status;
EFI_LOAD_OPTION EfiLoadOption;
UINTN EfiLoadOptionSize;
Status = GetEnvironmentVariable (BootVariableName, NULL, &EfiLoadOptionSize, (VOID**)&EfiLoadOption);
if (!EFI_ERROR(Status)) {
*BdsLoadOption = NULL;
Status = BootOptionParseLoadOption (EfiLoadOption, EfiLoadOptionSize, BdsLoadOption);
}
return Status;
}
EFI_STATUS
BootOptionFromLoadOptionIndex (
IN UINT16 LoadOptionIndex,
OUT BDS_LOAD_OPTION **BdsLoadOption
)
{
CHAR16 BootVariableName[9];
EFI_STATUS Status;
UnicodeSPrint (BootVariableName, 9 * sizeof(CHAR16), L"Boot%04X", LoadOptionIndex);
Status = BootOptionFromLoadOptionVariable (BootVariableName, BdsLoadOption);
if (!EFI_ERROR(Status)) {
(*BdsLoadOption)->LoadOptionIndex = LoadOptionIndex;
}
return Status;
}
EFI_STATUS
BootOptionToLoadOptionVariable (
IN BDS_LOAD_OPTION* BdsLoadOption
)
{
EFI_STATUS Status;
UINTN DescriptionSize;
//UINT16 FilePathListLength;
EFI_DEVICE_PATH_PROTOCOL* DevicePathNode;
UINTN NodeLength;
UINT8* EfiLoadOptionPtr;
VOID* OldLoadOption;
CHAR16 BootVariableName[9];
UINTN BootOrderSize;
UINT16* BootOrder;
// If we are overwriting an existent Boot Option then we have to free previously allocated memory
if (BdsLoadOption->LoadOptionSize > 0) {
OldLoadOption = BdsLoadOption->LoadOption;
} else {
OldLoadOption = NULL;
// If this function is called at the creation of the Boot Device entry (not at the update) the
// BootOption->LoadOptionSize must be zero then we get a new BootIndex for this entry
BdsLoadOption->LoadOptionIndex = BootOptionAllocateBootIndex ();
//TODO: Add to the the Boot Entry List
}
DescriptionSize = StrSize(BdsLoadOption->Description);
// Ensure the FilePathListLength information is correct
ASSERT (GetDevicePathSize (BdsLoadOption->FilePathList) == BdsLoadOption->FilePathListLength);
// Allocate the memory for the EFI Load Option
BdsLoadOption->LoadOptionSize = sizeof(UINT32) + sizeof(UINT16) + DescriptionSize + BdsLoadOption->FilePathListLength + BdsLoadOption->OptionalDataSize;
BdsLoadOption->LoadOption = (EFI_LOAD_OPTION)AllocateZeroPool (BdsLoadOption->LoadOptionSize);
if (BdsLoadOption->LoadOption == NULL) {
return EFI_OUT_OF_RESOURCES;
}
EfiLoadOptionPtr = BdsLoadOption->LoadOption;
//
// Populate the EFI Load Option and BDS Boot Option structures
//
// Attributes fields
*(UINT32*)EfiLoadOptionPtr = BdsLoadOption->Attributes;
EfiLoadOptionPtr += sizeof(UINT32);
// FilePath List fields
*(UINT16*)EfiLoadOptionPtr = BdsLoadOption->FilePathListLength;
EfiLoadOptionPtr += sizeof(UINT16);
// Boot description fields
CopyMem (EfiLoadOptionPtr, BdsLoadOption->Description, DescriptionSize);
EfiLoadOptionPtr += DescriptionSize;
// File path fields
DevicePathNode = BdsLoadOption->FilePathList;
while (!IsDevicePathEndType (DevicePathNode)) {
NodeLength = DevicePathNodeLength(DevicePathNode);
CopyMem (EfiLoadOptionPtr, DevicePathNode, NodeLength);
EfiLoadOptionPtr += NodeLength;
DevicePathNode = NextDevicePathNode (DevicePathNode);
}
// Set the End Device Path Type
SetDevicePathEndNode (EfiLoadOptionPtr);
EfiLoadOptionPtr += sizeof(EFI_DEVICE_PATH);
// Fill the Optional Data
if (BdsLoadOption->OptionalDataSize > 0) {
CopyMem (EfiLoadOptionPtr, BdsLoadOption->OptionalData, BdsLoadOption->OptionalDataSize);
}
// Case where the fields have been updated
if (OldLoadOption) {
// Now, the old data has been copied to the new allocated packed structure, we need to update the pointers of BdsLoadOption
BootOptionParseLoadOption (BdsLoadOption->LoadOption, BdsLoadOption->LoadOptionSize, &BdsLoadOption);
// Free the old packed structure
FreePool (OldLoadOption);
}
// Create/Update Boot#### environment variable
UnicodeSPrint (BootVariableName, 9 * sizeof(CHAR16), L"Boot%04X", BdsLoadOption->LoadOptionIndex);
Status = gRT->SetVariable (
BootVariableName,
&gEfiGlobalVariableGuid,
EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
BdsLoadOption->LoadOptionSize,
BdsLoadOption->LoadOption
);
// When it is a new entry we must add the entry to the BootOrder
if (OldLoadOption == NULL) {
// Add the new Boot Index to the list
Status = GetEnvironmentVariable (L"BootOrder", NULL, &BootOrderSize, (VOID**)&BootOrder);
if (!EFI_ERROR(Status)) {
BootOrder = ReallocatePool (BootOrderSize, BootOrderSize + sizeof(UINT16), BootOrder);
// Add the new index at the end
BootOrder[BootOrderSize / sizeof(UINT16)] = BdsLoadOption->LoadOptionIndex;
BootOrderSize += sizeof(UINT16);
} else {
// BootOrder does not exist. Create it
BootOrderSize = sizeof(UINT16);
BootOrder = &(BdsLoadOption->LoadOptionIndex);
}
// Update (or Create) the BootOrder environment variable
gRT->SetVariable (
L"BootOrder",
&gEfiGlobalVariableGuid,
EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
BootOrderSize,
BootOrder
);
DEBUG((EFI_D_ERROR,"Create %s\n",BootVariableName));
// Free memory allocated by GetEnvironmentVariable
if (!EFI_ERROR(Status)) {
FreePool (BootOrder);
}
} else {
DEBUG((EFI_D_ERROR,"Update %s\n",BootVariableName));
}
return EFI_SUCCESS;
}
UINT16
BootOptionAllocateBootIndex (
VOID
)
{
EFI_STATUS Status;
UINTN Index;
UINT32 BootIndex;
UINT16 *BootOrder;
UINTN BootOrderSize;
BOOLEAN Found;
// Get the Boot Option Order from the environment variable
Status = GetEnvironmentVariable (L"BootOrder", NULL, &BootOrderSize, (VOID**)&BootOrder);
if (!EFI_ERROR(Status)) {
for (BootIndex = 0; BootIndex <= 0xFFFF; BootIndex++) {
Found = FALSE;
for (Index = 0; Index < BootOrderSize / sizeof (UINT16); Index++) {
if (BootOrder[Index] == BootIndex) {
Found = TRUE;
break;
}
}
if (!Found) {
return BootIndex;
}
}
FreePool (BootOrder);
}
// Return the first index
return 0;
}
/** @file
*
* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
* which accompanies this distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#include "BdsInternal.h"
EFI_STATUS
BootOptionParseLoadOption (
IN EFI_LOAD_OPTION EfiLoadOption,
IN UINTN EfiLoadOptionSize,
IN OUT BDS_LOAD_OPTION **BdsLoadOption
)
{
BDS_LOAD_OPTION *LoadOption;
UINTN DescriptionLength;
if (EfiLoadOption == NULL) {
return EFI_INVALID_PARAMETER;
}
if (EfiLoadOptionSize < sizeof(UINT32) + sizeof(UINT16) + sizeof(CHAR16) + sizeof(EFI_DEVICE_PATH_PROTOCOL)) {
return EFI_BAD_BUFFER_SIZE;
}
if (*BdsLoadOption == NULL) {
LoadOption = (BDS_LOAD_OPTION*)AllocateZeroPool (sizeof(BDS_LOAD_OPTION));
if (LoadOption == NULL) {
return EFI_OUT_OF_RESOURCES;
}
} else {
LoadOption = *BdsLoadOption;
}
LoadOption->LoadOption = EfiLoadOption;
LoadOption->LoadOptionSize = EfiLoadOptionSize;
LoadOption->Attributes = *(UINT32*)EfiLoadOption;
LoadOption->FilePathListLength = *(UINT16*)(EfiLoadOption + sizeof(UINT32));
LoadOption->Description = (CHAR16*)(EfiLoadOption + sizeof(UINT32) + sizeof(UINT16));
DescriptionLength = StrSize (LoadOption->Description);
LoadOption->FilePathList = (EFI_DEVICE_PATH_PROTOCOL*)(EfiLoadOption + sizeof(UINT32) + sizeof(UINT16) + DescriptionLength);
// If ((End of EfiLoadOptiony - Start of EfiLoadOption) == EfiLoadOptionSize) then No Optional Data
if ((UINTN)((UINTN)LoadOption->FilePathList + LoadOption->FilePathListLength - (UINTN)EfiLoadOption) == EfiLoadOptionSize) {
LoadOption->OptionalData = NULL;
LoadOption->OptionalDataSize = 0;
} else {
LoadOption->OptionalData = (VOID*)((UINTN)(LoadOption->FilePathList) + LoadOption->FilePathListLength);
LoadOption->OptionalDataSize = EfiLoadOptionSize - ((UINTN)LoadOption->OptionalData - (UINTN)EfiLoadOption);
}
if (*BdsLoadOption == NULL) {
*BdsLoadOption = LoadOption;
}
return EFI_SUCCESS;
}
EFI_STATUS
BootOptionFromLoadOptionVariable (
IN CHAR16* BootVariableName,
OUT BDS_LOAD_OPTION** BdsLoadOption
)
{
EFI_STATUS Status;
EFI_LOAD_OPTION EfiLoadOption;
UINTN EfiLoadOptionSize;
Status = GetEnvironmentVariable (BootVariableName, NULL, &EfiLoadOptionSize, (VOID**)&EfiLoadOption);
if (!EFI_ERROR(Status)) {
*BdsLoadOption = NULL;
Status = BootOptionParseLoadOption (EfiLoadOption, EfiLoadOptionSize, BdsLoadOption);
}
return Status;
}
EFI_STATUS
BootOptionFromLoadOptionIndex (
IN UINT16 LoadOptionIndex,
OUT BDS_LOAD_OPTION **BdsLoadOption
)
{
CHAR16 BootVariableName[9];
EFI_STATUS Status;
UnicodeSPrint (BootVariableName, 9 * sizeof(CHAR16), L"Boot%04X", LoadOptionIndex);
Status = BootOptionFromLoadOptionVariable (BootVariableName, BdsLoadOption);
if (!EFI_ERROR(Status)) {
(*BdsLoadOption)->LoadOptionIndex = LoadOptionIndex;
}
return Status;
}
EFI_STATUS
BootOptionToLoadOptionVariable (
IN BDS_LOAD_OPTION* BdsLoadOption
)
{
EFI_STATUS Status;
UINTN DescriptionSize;
//UINT16 FilePathListLength;
EFI_DEVICE_PATH_PROTOCOL* DevicePathNode;
UINTN NodeLength;
UINT8* EfiLoadOptionPtr;
VOID* OldLoadOption;
CHAR16 BootVariableName[9];
UINTN BootOrderSize;
UINT16* BootOrder;
// If we are overwriting an existent Boot Option then we have to free previously allocated memory
if (BdsLoadOption->LoadOptionSize > 0) {
OldLoadOption = BdsLoadOption->LoadOption;
} else {
OldLoadOption = NULL;
// If this function is called at the creation of the Boot Device entry (not at the update) the
// BootOption->LoadOptionSize must be zero then we get a new BootIndex for this entry
BdsLoadOption->LoadOptionIndex = BootOptionAllocateBootIndex ();
//TODO: Add to the the Boot Entry List
}
DescriptionSize = StrSize(BdsLoadOption->Description);
// Ensure the FilePathListLength information is correct
ASSERT (GetDevicePathSize (BdsLoadOption->FilePathList) == BdsLoadOption->FilePathListLength);
// Allocate the memory for the EFI Load Option
BdsLoadOption->LoadOptionSize = sizeof(UINT32) + sizeof(UINT16) + DescriptionSize + BdsLoadOption->FilePathListLength + BdsLoadOption->OptionalDataSize;
BdsLoadOption->LoadOption = (EFI_LOAD_OPTION)AllocateZeroPool (BdsLoadOption->LoadOptionSize);
if (BdsLoadOption->LoadOption == NULL) {
return EFI_OUT_OF_RESOURCES;
}
EfiLoadOptionPtr = BdsLoadOption->LoadOption;
//
// Populate the EFI Load Option and BDS Boot Option structures
//
// Attributes fields
*(UINT32*)EfiLoadOptionPtr = BdsLoadOption->Attributes;
EfiLoadOptionPtr += sizeof(UINT32);
// FilePath List fields
*(UINT16*)EfiLoadOptionPtr = BdsLoadOption->FilePathListLength;
EfiLoadOptionPtr += sizeof(UINT16);
// Boot description fields
CopyMem (EfiLoadOptionPtr, BdsLoadOption->Description, DescriptionSize);
EfiLoadOptionPtr += DescriptionSize;
// File path fields
DevicePathNode = BdsLoadOption->FilePathList;
while (!IsDevicePathEndType (DevicePathNode)) {
NodeLength = DevicePathNodeLength(DevicePathNode);
CopyMem (EfiLoadOptionPtr, DevicePathNode, NodeLength);
EfiLoadOptionPtr += NodeLength;
DevicePathNode = NextDevicePathNode (DevicePathNode);
}
// Set the End Device Path Type
SetDevicePathEndNode (EfiLoadOptionPtr);
EfiLoadOptionPtr += sizeof(EFI_DEVICE_PATH);
// Fill the Optional Data
if (BdsLoadOption->OptionalDataSize > 0) {
CopyMem (EfiLoadOptionPtr, BdsLoadOption->OptionalData, BdsLoadOption->OptionalDataSize);
}
// Case where the fields have been updated
if (OldLoadOption) {
// Now, the old data has been copied to the new allocated packed structure, we need to update the pointers of BdsLoadOption
BootOptionParseLoadOption (BdsLoadOption->LoadOption, BdsLoadOption->LoadOptionSize, &BdsLoadOption);
// Free the old packed structure
FreePool (OldLoadOption);
}
// Create/Update Boot#### environment variable
UnicodeSPrint (BootVariableName, 9 * sizeof(CHAR16), L"Boot%04X", BdsLoadOption->LoadOptionIndex);
Status = gRT->SetVariable (
BootVariableName,
&gEfiGlobalVariableGuid,
EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
BdsLoadOption->LoadOptionSize,
BdsLoadOption->LoadOption
);
// When it is a new entry we must add the entry to the BootOrder
if (OldLoadOption == NULL) {
// Add the new Boot Index to the list
Status = GetEnvironmentVariable (L"BootOrder", NULL, &BootOrderSize, (VOID**)&BootOrder);
if (!EFI_ERROR(Status)) {
BootOrder = ReallocatePool (BootOrderSize, BootOrderSize + sizeof(UINT16), BootOrder);
// Add the new index at the end
BootOrder[BootOrderSize / sizeof(UINT16)] = BdsLoadOption->LoadOptionIndex;
BootOrderSize += sizeof(UINT16);
} else {
// BootOrder does not exist. Create it
BootOrderSize = sizeof(UINT16);
BootOrder = &(BdsLoadOption->LoadOptionIndex);
}
// Update (or Create) the BootOrder environment variable
gRT->SetVariable (
L"BootOrder",
&gEfiGlobalVariableGuid,
EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
BootOrderSize,
BootOrder
);
DEBUG((EFI_D_ERROR,"Create %s\n",BootVariableName));
// Free memory allocated by GetEnvironmentVariable
if (!EFI_ERROR(Status)) {
FreePool (BootOrder);
}
} else {
DEBUG((EFI_D_ERROR,"Update %s\n",BootVariableName));
}
return EFI_SUCCESS;
}
UINT16
BootOptionAllocateBootIndex (
VOID
)
{
EFI_STATUS Status;
UINTN Index;
UINT32 BootIndex;
UINT16 *BootOrder;
UINTN BootOrderSize;
BOOLEAN Found;
// Get the Boot Option Order from the environment variable
Status = GetEnvironmentVariable (L"BootOrder", NULL, &BootOrderSize, (VOID**)&BootOrder);
if (!EFI_ERROR(Status)) {
for (BootIndex = 0; BootIndex <= 0xFFFF; BootIndex++) {
Found = FALSE;
for (Index = 0; Index < BootOrderSize / sizeof (UINT16); Index++) {
if (BootOrder[Index] == BootIndex) {
Found = TRUE;
break;
}
}
if (!Found) {
return BootIndex;
}
}
FreePool (BootOrder);
}
// Return the first index
return 0;
}

198
ArmPkg/Library/CompilerIntrinsicsLib/Arm/Llvm_int_lib.h
View File

@ -1,99 +1,99 @@
/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
/**
University of Illinois/NCSA
Open Source License
Copyright (c) 2003-2008 University of Illinois at Urbana-Champaign.
All rights reserved.
Developed by:
LLVM Team
University of Illinois at Urbana-Champaign
http://llvm.org
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal with
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimers.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimers in the
documentation and/or other materials provided with the distribution.
* Neither the names of the LLVM Team, University of Illinois at
Urbana-Champaign, nor the names of its contributors may be used to
endorse or promote products derived from this Software without specific
prior written permission.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
SOFTWARE.
**/
#include <Base.h>
#include <Library/DebugLib.h>
#define CHAR_BIT 8
typedef union {
INT64 all;
struct {
UINT32 low;
INT32 high;
};
} dwords;
typedef union {
UINT64 all;
struct {
UINT32 low;
UINT32 high;
};
} udwords;
// __aeabi_ return values
typedef struct {
UINT64 Quotent;
UINT64 Remainder;
} ulldiv_t;
typedef struct {
INT64 Quotent;
INT64 Remainder;
} lldiv_t;
typedef struct {
UINT32 Quotent;
UINT32 Remainder;
} uidiv_return;
#if __GNUC__
#define COUNT_LEADING_ZEROS(_a) __builtin_clz((_a))
#define COUNT_TRAILING_ZEROS(_a) __builtin_ctz((_a))
#else
#error COUNT_LEADING_ZEROS() and COUNT_TRAILING_ZEROS() macros not ported to your compiler
#endif
/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
/**
University of Illinois/NCSA
Open Source License
Copyright (c) 2003-2008 University of Illinois at Urbana-Champaign.
All rights reserved.
Developed by:
LLVM Team
University of Illinois at Urbana-Champaign
http://llvm.org
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal with
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimers.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimers in the
documentation and/or other materials provided with the distribution.
* Neither the names of the LLVM Team, University of Illinois at
Urbana-Champaign, nor the names of its contributors may be used to
endorse or promote products derived from this Software without specific
prior written permission.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
SOFTWARE.
**/
#include <Base.h>
#include <Library/DebugLib.h>
#define CHAR_BIT 8
typedef union {
INT64 all;
struct {
UINT32 low;
INT32 high;
};
} dwords;
typedef union {
UINT64 all;
struct {
UINT32 low;
UINT32 high;
};
} udwords;
// __aeabi_ return values
typedef struct {
UINT64 Quotent;
UINT64 Remainder;
} ulldiv_t;
typedef struct {
INT64 Quotent;
INT64 Remainder;
} lldiv_t;
typedef struct {
UINT32 Quotent;
UINT32 Remainder;
} uidiv_return;
#if __GNUC__
#define COUNT_LEADING_ZEROS(_a) __builtin_clz((_a))
#define COUNT_TRAILING_ZEROS(_a) __builtin_ctz((_a))
#else
#error COUNT_LEADING_ZEROS() and COUNT_TRAILING_ZEROS() macros not ported to your compiler
#endif

70
ArmPkg/Library/CompilerIntrinsicsLib/Arm/ashldi3.S
View File

@ -1,35 +1,35 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
.text
.align 2
GCC_ASM_EXPORT(__ashldi3)
ASM_PFX(__ashldi3):
cmp r2, #31
bls L2
cmp r2, #63
subls r2, r2, #32
movls r2, r0, asl r2
movhi r2, #0
mov r1, r2
mov r0, #0
bx lr
L2:
cmp r2, #0
rsbne r3, r2, #32
movne r3, r0, lsr r3
movne r0, r0, asl r2
orrne r1, r3, r1, asl r2
bx lr
#------------------------------------------------------------------------------
#
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
.text
.align 2
GCC_ASM_EXPORT(__ashldi3)
ASM_PFX(__ashldi3):
cmp r2, #31
bls L2
cmp r2, #63
subls r2, r2, #32
movls r2, r0, asl r2
movhi r2, #0
mov r1, r2
mov r0, #0
bx lr
L2:
cmp r2, #0
rsbne r3, r2, #32
movne r3, r0, lsr r3
movne r0, r0, asl r2
orrne r1, r3, r1, asl r2
bx lr

166
ArmPkg/Library/CompilerIntrinsicsLib/Arm/ashldi3.c
View File

@ -1,83 +1,83 @@
/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
/**
University of Illinois/NCSA
Open Source License
Copyright (c) 2003-2008 University of Illinois at Urbana-Champaign.
All rights reserved.
Developed by:
LLVM Team
University of Illinois at Urbana-Champaign
http://llvm.org
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal with
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimers.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimers in the
documentation and/or other materials provided with the distribution.
* Neither the names of the LLVM Team, University of Illinois at
Urbana-Champaign, nor the names of its contributors may be used to
endorse or promote products derived from this Software without specific
prior written permission.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
SOFTWARE.
**/
#include "Llvm_int_lib.h"
// Returns: a << b
// Precondition: 0 <= b < bits_in_dword
INT64
__ashldi3(INT64 a, INT32 b)
{
const int bits_in_word = (int)(sizeof(INT32) * CHAR_BIT);
dwords input;
dwords result;
input.all = a;
if (b & bits_in_word) // bits_in_word <= b < bits_in_dword
{
result.low = 0;
result.high = input.low << (b - bits_in_word);
}
else // 0 <= b < bits_in_word
{
if (b == 0)
return a;
result.low = input.low << b;
result.high = (input.high << b) | (input.low >> (bits_in_word - b));
}
return result.all;
}
/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
/**
University of Illinois/NCSA
Open Source License
Copyright (c) 2003-2008 University of Illinois at Urbana-Champaign.
All rights reserved.
Developed by:
LLVM Team
University of Illinois at Urbana-Champaign
http://llvm.org
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal with
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimers.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimers in the
documentation and/or other materials provided with the distribution.
* Neither the names of the LLVM Team, University of Illinois at
Urbana-Champaign, nor the names of its contributors may be used to
endorse or promote products derived from this Software without specific
prior written permission.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
SOFTWARE.
**/
#include "Llvm_int_lib.h"
// Returns: a << b
// Precondition: 0 <= b < bits_in_dword
INT64
__ashldi3(INT64 a, INT32 b)
{
const int bits_in_word = (int)(sizeof(INT32) * CHAR_BIT);
dwords input;
dwords result;
input.all = a;
if (b & bits_in_word) // bits_in_word <= b < bits_in_dword
{
result.low = 0;
result.high = input.low << (b - bits_in_word);
}
else // 0 <= b < bits_in_word
{
if (b == 0)
return a;
result.low = input.low << b;
result.high = (input.high << b) | (input.low >> (bits_in_word - b));
}
return result.all;
}

72
ArmPkg/Library/CompilerIntrinsicsLib/Arm/ashrdi3.S
View File

@ -1,36 +1,36 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
.text
.align 2
GCC_ASM_EXPORT(__ashrdi3)
ASM_PFX(__ashrdi3):
cmp r2, #31
bls L2
cmp r2, #63
subls r2, r2, #32
mov ip, r1, asr #31
movls r2, r1, asr r2
movhi r2, ip
mov r0, r2
mov r1, ip
bx lr
L2:
cmp r2, #0
rsbne r3, r2, #32
movne r3, r1, asl r3
movne r1, r1, asr r2
orrne r0, r3, r0, lsr r2
bx lr
#------------------------------------------------------------------------------
#
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
.text
.align 2
GCC_ASM_EXPORT(__ashrdi3)
ASM_PFX(__ashrdi3):
cmp r2, #31
bls L2
cmp r2, #63
subls r2, r2, #32
mov ip, r1, asr #31
movls r2, r1, asr r2
movhi r2, ip
mov r0, r2
mov r1, ip
bx lr
L2:
cmp r2, #0
rsbne r3, r2, #32
movne r3, r1, asl r3
movne r1, r1, asr r2
orrne r0, r3, r0, lsr r2
bx lr

168
ArmPkg/Library/CompilerIntrinsicsLib/Arm/ashrdi3.c
View File

@ -1,84 +1,84 @@
/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
/**
University of Illinois/NCSA
Open Source License
Copyright (c) 2003-2008 University of Illinois at Urbana-Champaign.
All rights reserved.
Developed by:
LLVM Team
University of Illinois at Urbana-Champaign
http://llvm.org
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal with
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimers.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimers in the
documentation and/or other materials provided with the distribution.
* Neither the names of the LLVM Team, University of Illinois at
Urbana-Champaign, nor the names of its contributors may be used to
endorse or promote products derived from this Software without specific
prior written permission.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
SOFTWARE.
**/
#include "Llvm_int_lib.h"
// Returns: arithmetic a >> b
// Precondition: 0 <= b < bits_in_dword
INT64
__ashrdi3(INT64 a, INT32 b)
{
const int bits_in_word = (int)(sizeof(INT32) * CHAR_BIT);
dwords input;
dwords result;
input.all = a;
if (b & bits_in_word) // bits_in_word <= b < bits_in_dword
{
// result.high = input.high < 0 ? -1 : 0
result.high = input.high >> (bits_in_word - 1);
result.low = input.high >> (b - bits_in_word);
}
else // 0 <= b < bits_in_word
{
if (b == 0)
return a;
result.high = input.high >> b;
result.low = (input.high << (bits_in_word - b)) | (input.low >> b);
}
return result.all;
}
/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
/**
University of Illinois/NCSA
Open Source License
Copyright (c) 2003-2008 University of Illinois at Urbana-Champaign.
All rights reserved.
Developed by:
LLVM Team
University of Illinois at Urbana-Champaign
http://llvm.org
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal with
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimers.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimers in the
documentation and/or other materials provided with the distribution.
* Neither the names of the LLVM Team, University of Illinois at
Urbana-Champaign, nor the names of its contributors may be used to
endorse or promote products derived from this Software without specific
prior written permission.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
SOFTWARE.
**/
#include "Llvm_int_lib.h"
// Returns: arithmetic a >> b
// Precondition: 0 <= b < bits_in_dword
INT64
__ashrdi3(INT64 a, INT32 b)
{
const int bits_in_word = (int)(sizeof(INT32) * CHAR_BIT);
dwords input;
dwords result;
input.all = a;
if (b & bits_in_word) // bits_in_word <= b < bits_in_dword
{
// result.high = input.high < 0 ? -1 : 0
result.high = input.high >> (bits_in_word - 1);
result.low = input.high >> (b - bits_in_word);
}
else // 0 <= b < bits_in_word
{
if (b == 0)
return a;
result.high = input.high >> b;
result.low = (input.high << (bits_in_word - b)) | (input.low >> b);
}
return result.all;
}

114
ArmPkg/Library/CompilerIntrinsicsLib/Arm/clzsi2.S
View File

@ -1,57 +1,57 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
.text
.align 2
GCC_ASM_EXPORT(__clzsi2)
ASM_PFX(__clzsi2):
@ frame_needed = 1, uses_anonymous_args = 0
stmfd sp!, {r7, lr}
add r7, sp, #0
movs r3, r0, lsr #16
movne r3, #16
moveq r3, #0
movne r9, #0
moveq r9, #16
mov r3, r0, lsr r3
tst r3, #65280
movne r0, #8
moveq r0, #0
movne lr, #0
moveq lr, #8
mov r3, r3, lsr r0
tst r3, #240
movne r0, #4
moveq r0, #0
movne ip, #0
moveq ip, #4
mov r3, r3, lsr r0
tst r3, #12
movne r0, #2
moveq r0, #0
movne r1, #0
moveq r1, #2
mov r2, r3, lsr r0
add r3, lr, r9
add r0, r3, ip
add r1, r0, r1
mov r0, r2, lsr #1
eor r0, r0, #1
ands r0, r0, #1
mvnne r0, #0
rsb r3, r2, #2
and r0, r0, r3
add r0, r1, r0
ldmfd sp!, {r7, pc}
#------------------------------------------------------------------------------
#
# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
.text
.align 2
GCC_ASM_EXPORT(__clzsi2)
ASM_PFX(__clzsi2):
@ frame_needed = 1, uses_anonymous_args = 0
stmfd sp!, {r7, lr}
add r7, sp, #0
movs r3, r0, lsr #16
movne r3, #16
moveq r3, #0
movne r9, #0
moveq r9, #16
mov r3, r0, lsr r3
tst r3, #65280
movne r0, #8
moveq r0, #0
movne lr, #0
moveq lr, #8
mov r3, r3, lsr r0
tst r3, #240
movne r0, #4
moveq r0, #0
movne ip, #0
moveq ip, #4
mov r3, r3, lsr r0
tst r3, #12
movne r0, #2
moveq r0, #0
movne r1, #0
moveq r1, #2
mov r2, r3, lsr r0
add r3, lr, r9
add r0, r3, ip
add r1, r0, r1
mov r0, r2, lsr #1
eor r0, r0, #1
ands r0, r0, #1
mvnne r0, #0
rsb r3, r2, #2
and r0, r0, r3
add r0, r1, r0
ldmfd sp!, {r7, pc}

192
ArmPkg/Library/CompilerIntrinsicsLib/Arm/clzsi2.c
View File

@ -1,96 +1,96 @@
/** @file
Compiler intrinsic to return the number of leading zeros, ported from LLVM code.
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
/**
University of Illinois/NCSA
Open Source License
Copyright (c) 2003-2008 University of Illinois at Urbana-Champaign.
All rights reserved.
Developed by:
LLVM Team
University of Illinois at Urbana-Champaign
http://llvm.org
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal with
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimers.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimers in the
documentation and/or other materials provided with the distribution.
* Neither the names of the LLVM Team, University of Illinois at
Urbana-Champaign, nor the names of its contributors may be used to
endorse or promote products derived from this Software without specific
prior written permission.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
SOFTWARE.
**/
#include "Llvm_int_lib.h"
// Returns: the number of leading 0-bits
// Precondition: a != 0
INT32
__clzsi2(INT32 a)
{
UINT32 x = (UINT32)a;
INT32 t = ((x & 0xFFFF0000) == 0) << 4; // if (x is small) t = 16 else 0
x >>= 16 - t; // x = [0 - 0xFFFF]
UINT32 r = t; // r = [0, 16]
// return r + clz(x)
t = ((x & 0xFF00) == 0) << 3;
x >>= 8 - t; // x = [0 - 0xFF]
r += t; // r = [0, 8, 16, 24]
// return r + clz(x)
t = ((x & 0xF0) == 0) << 2;
x >>= 4 - t; // x = [0 - 0xF]
r += t; // r = [0, 4, 8, 12, 16, 20, 24, 28]
// return r + clz(x)
t = ((x & 0xC) == 0) << 1;
x >>= 2 - t; // x = [0 - 3]
r += t; // r = [0 - 30] and is even
// return r + clz(x)
// switch (x)
// {
// case 0:
// return r + 2;
// case 1:
// return r + 1;
// case 2:
// case 3:
// return r;
// }
return r + ((2 - x) & -((x & 2) == 0));
}
/** @file
Compiler intrinsic to return the number of leading zeros, ported from LLVM code.
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
/**
University of Illinois/NCSA
Open Source License
Copyright (c) 2003-2008 University of Illinois at Urbana-Champaign.
All rights reserved.
Developed by:
LLVM Team
University of Illinois at Urbana-Champaign
http://llvm.org
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal with
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimers.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimers in the
documentation and/or other materials provided with the distribution.
* Neither the names of the LLVM Team, University of Illinois at
Urbana-Champaign, nor the names of its contributors may be used to
endorse or promote products derived from this Software without specific
prior written permission.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
SOFTWARE.
**/
#include "Llvm_int_lib.h"
// Returns: the number of leading 0-bits
// Precondition: a != 0
INT32
__clzsi2(INT32 a)
{
UINT32 x = (UINT32)a;
INT32 t = ((x & 0xFFFF0000) == 0) << 4; // if (x is small) t = 16 else 0
x >>= 16 - t; // x = [0 - 0xFFFF]
UINT32 r = t; // r = [0, 16]
// return r + clz(x)
t = ((x & 0xFF00) == 0) << 3;
x >>= 8 - t; // x = [0 - 0xFF]
r += t; // r = [0, 8, 16, 24]
// return r + clz(x)
t = ((x & 0xF0) == 0) << 2;
x >>= 4 - t; // x = [0 - 0xF]
r += t; // r = [0, 4, 8, 12, 16, 20, 24, 28]
// return r + clz(x)
t = ((x & 0xC) == 0) << 1;
x >>= 2 - t; // x = [0 - 3]
r += t; // r = [0 - 30] and is even
// return r + clz(x)
// switch (x)
// {
// case 0:
// return r + 2;
// case 1:
// return r + 1;
// case 2:
// case 3:
// return r;
// }
return r + ((2 - x) & -((x & 2) == 0));
}

98
ArmPkg/Library/CompilerIntrinsicsLib/Arm/ctzsi2.S
View File

@ -1,49 +1,49 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
.text
.align 2
GCC_ASM_EXPORT(__ctzsi2)
ASM_PFX(__ctzsi2):
uxth r3, r0
cmp r3, #0
moveq ip, #16
movne ip, #0
@ lr needed for prologue
mov r0, r0, lsr ip
tst r0, #255
movne r3, #0
moveq r3, #8
mov r0, r0, lsr r3
tst r0, #15
movne r1, #0
moveq r1, #4
add r3, r3, ip
mov r0, r0, lsr r1
tst r0, #3
movne r2, #0
moveq r2, #2
add r3, r3, r1
mov r0, r0, lsr r2
and r0, r0, #3
add r2, r3, r2
eor r3, r0, #1
mov r0, r0, lsr #1
ands r3, r3, #1
mvnne r3, #0
rsb r0, r0, #2
and r0, r3, r0
add r0, r2, r0
bx lr
#------------------------------------------------------------------------------
#
# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
.text
.align 2
GCC_ASM_EXPORT(__ctzsi2)
ASM_PFX(__ctzsi2):
uxth r3, r0
cmp r3, #0
moveq ip, #16
movne ip, #0
@ lr needed for prologue
mov r0, r0, lsr ip
tst r0, #255
movne r3, #0
moveq r3, #8
mov r0, r0, lsr r3
tst r0, #15
movne r1, #0
moveq r1, #4
add r3, r3, ip
mov r0, r0, lsr r1
tst r0, #3
movne r2, #0
moveq r2, #2
add r3, r3, r1
mov r0, r0, lsr r2
and r0, r0, #3
add r2, r3, r2
eor r3, r0, #1
mov r0, r0, lsr #1
ands r3, r3, #1
mvnne r3, #0
rsb r0, r0, #2
and r0, r3, r0
add r0, r2, r0
bx lr

196
ArmPkg/Library/CompilerIntrinsicsLib/Arm/ctzsi2.c
View File

@ -1,98 +1,98 @@
/** @file
Compiler intrinsic to return the number of trailing zeros, ported from LLVM code.
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
/**
University of Illinois/NCSA
Open Source License
Copyright (c) 2003-2008 University of Illinois at Urbana-Champaign.
All rights reserved.
Developed by:
LLVM Team
University of Illinois at Urbana-Champaign
http://llvm.org
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal with
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimers.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimers in the
documentation and/or other materials provided with the distribution.
* Neither the names of the LLVM Team, University of Illinois at
Urbana-Champaign, nor the names of its contributors may be used to
endorse or promote products derived from this Software without specific
prior written permission.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
SOFTWARE.
**/
#include "Llvm_int_lib.h"
// Returns: the number of trailing 0-bits
// Precondition: a != 0
INT32
__ctzsi2(INT32 a)
{
UINT32 x = (UINT32)a;
INT32 t = ((x & 0x0000FFFF) == 0) << 4; // if (x has no small bits) t = 16 else 0
x >>= t; // x = [0 - 0xFFFF] + higher garbage bits
UINT32 r = t; // r = [0, 16]
// return r + ctz(x)
t = ((x & 0x00FF) == 0) << 3;
x >>= t; // x = [0 - 0xFF] + higher garbage bits
r += t; // r = [0, 8, 16, 24]
// return r + ctz(x)
t = ((x & 0x0F) == 0) << 2;
x >>= t; // x = [0 - 0xF] + higher garbage bits
r += t; // r = [0, 4, 8, 12, 16, 20, 24, 28]
// return r + ctz(x)
t = ((x & 0x3) == 0) << 1;
x >>= t;
x &= 3; // x = [0 - 3]
r += t; // r = [0 - 30] and is even
// return r + ctz(x)
// The branch-less return statement below is equivalent
// to the following switch statement:
// switch (x)
// {
// case 0:
// return r + 2;
// case 2:
// return r + 1;
// case 1:
// case 3:
// return r;
// }
return r + ((2 - (x >> 1)) & -((x & 1) == 0));
}
/** @file
Compiler intrinsic to return the number of trailing zeros, ported from LLVM code.
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
/**
University of Illinois/NCSA
Open Source License
Copyright (c) 2003-2008 University of Illinois at Urbana-Champaign.
All rights reserved.
Developed by:
LLVM Team
University of Illinois at Urbana-Champaign
http://llvm.org
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal with
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimers.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimers in the
documentation and/or other materials provided with the distribution.
* Neither the names of the LLVM Team, University of Illinois at
Urbana-Champaign, nor the names of its contributors may be used to
endorse or promote products derived from this Software without specific
prior written permission.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
SOFTWARE.
**/
#include "Llvm_int_lib.h"
// Returns: the number of trailing 0-bits
// Precondition: a != 0
INT32
__ctzsi2(INT32 a)
{
UINT32 x = (UINT32)a;
INT32 t = ((x & 0x0000FFFF) == 0) << 4; // if (x has no small bits) t = 16 else 0
x >>= t; // x = [0 - 0xFFFF] + higher garbage bits
UINT32 r = t; // r = [0, 16]
// return r + ctz(x)
t = ((x & 0x00FF) == 0) << 3;
x >>= t; // x = [0 - 0xFF] + higher garbage bits
r += t; // r = [0, 8, 16, 24]
// return r + ctz(x)
t = ((x & 0x0F) == 0) << 2;
x >>= t; // x = [0 - 0xF] + higher garbage bits
r += t; // r = [0, 4, 8, 12, 16, 20, 24, 28]
// return r + ctz(x)
t = ((x & 0x3) == 0) << 1;
x >>= t;
x &= 3; // x = [0 - 3]
r += t; // r = [0 - 30] and is even
// return r + ctz(x)
// The branch-less return statement below is equivalent
// to the following switch statement:
// switch (x)
// {
// case 0:
// return r + 2;
// case 2:
// return r + 1;
// case 1:
// case 3:
// return r;
// }
return r + ((2 - (x >> 1)) & -((x & 1) == 0));
}

306
ArmPkg/Library/CompilerIntrinsicsLib/Arm/div.S
View File

@ -1,153 +1,153 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2011, ARM. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
.text
.align 2
GCC_ASM_EXPORT(__aeabi_uidiv)
GCC_ASM_EXPORT(__aeabi_uidivmod)
GCC_ASM_EXPORT(__aeabi_idiv)
GCC_ASM_EXPORT(__aeabi_idivmod)
# AREA Math, CODE, READONLY
#
#UINT32
#EFIAPI
#__aeabi_uidivmode (
# IN UINT32 Dividen
# IN UINT32 Divisor
# );
#
ASM_PFX(__aeabi_uidiv):
ASM_PFX(__aeabi_uidivmod):
rsbs r12, r1, r0, LSR #4
mov r2, #0
bcc ASM_PFX(__arm_div4)
rsbs r12, r1, r0, LSR #8
bcc ASM_PFX(__arm_div8)
mov r3, #0
b ASM_PFX(__arm_div_large)
#
#INT32
#EFIAPI
#__aeabi_idivmode (
# IN INT32 Dividen
# IN INT32 Divisor
# );
#
ASM_PFX(__aeabi_idiv):
ASM_PFX(__aeabi_idivmod):
orrs r12, r0, r1
bmi ASM_PFX(__arm_div_negative)
rsbs r12, r1, r0, LSR #1
mov r2, #0
bcc ASM_PFX(__arm_div1)
rsbs r12, r1, r0, LSR #4
bcc ASM_PFX(__arm_div4)
rsbs r12, r1, r0, LSR #8
bcc ASM_PFX(__arm_div8)
mov r3, #0
b ASM_PFX(__arm_div_large)
ASM_PFX(__arm_div8):
rsbs r12, r1, r0, LSR #7
subcs r0, r0, r1, LSL #7
adc r2, r2, r2
rsbs r12, r1, r0,LSR #6
subcs r0, r0, r1, LSL #6
adc r2, r2, r2
rsbs r12, r1, r0, LSR #5
subcs r0, r0, r1, LSL #5
adc r2, r2, r2
rsbs r12, r1, r0, LSR #4
subcs r0, r0, r1, LSL #4
adc r2, r2, r2
ASM_PFX(__arm_div4):
rsbs r12, r1, r0, LSR #3
subcs r0, r0, r1, LSL #3
adc r2, r2, r2
rsbs r12, r1, r0, LSR #2
subcs r0, r0, r1, LSL #2
adcs r2, r2, r2
rsbs r12, r1, r0, LSR #1
subcs r0, r0, r1, LSL #1
adc r2, r2, r2
ASM_PFX(__arm_div1):
subs r1, r0, r1
movcc r1, r0
adc r0, r2, r2
bx r14
ASM_PFX(__arm_div_negative):
ands r2, r1, #0x80000000
rsbmi r1, r1, #0
eors r3, r2, r0, ASR #32
rsbcs r0, r0, #0
rsbs r12, r1, r0, LSR #4
bcc label1
rsbs r12, r1, r0, LSR #8
bcc label2
ASM_PFX(__arm_div_large):
lsl r1, r1, #6
rsbs r12, r1, r0, LSR #8
orr r2, r2, #0xfc000000
bcc label2
lsl r1, r1, #6
rsbs r12, r1, r0, LSR #8
orr r2, r2, #0x3f00000
bcc label2
lsl r1, r1, #6
rsbs r12, r1, r0, LSR #8
orr r2, r2, #0xfc000
orrcs r2, r2, #0x3f00
lslcs r1, r1, #6
rsbs r12, r1, #0
bcs ASM_PFX(__aeabi_idiv0)
label3:
lsrcs r1, r1, #6
label2:
rsbs r12, r1, r0, LSR #7
subcs r0, r0, r1, LSL #7
adc r2, r2, r2
rsbs r12, r1, r0, LSR #6
subcs r0, r0, r1, LSL #6
adc r2, r2, r2
rsbs r12, r1, r0, LSR #5
subcs r0, r0, r1, LSL #5
adc r2, r2, r2
rsbs r12, r1, r0, LSR #4
subcs r0, r0, r1, LSL #4
adc r2, r2, r2
label1:
rsbs r12, r1, r0, LSR #3
subcs r0, r0, r1, LSL #3
adc r2, r2, r2
rsbs r12, r1, r0, LSR #2
subcs r0, r0, r1, LSL #2
adcs r2, r2, r2
bcs label3
rsbs r12, r1, r0, LSR #1
subcs r0, r0, r1, LSL #1
adc r2, r2, r2
subs r1, r0, r1
movcc r1, r0
adc r0, r2, r2
asrs r3, r3, #31
rsbmi r0, r0, #0
rsbcs r1, r1, #0
bx r14
@ What to do about division by zero? For now, just return.
ASM_PFX(__aeabi_idiv0):
bx r14
#------------------------------------------------------------------------------
#
# Copyright (c) 2011, ARM. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
.text
.align 2
GCC_ASM_EXPORT(__aeabi_uidiv)
GCC_ASM_EXPORT(__aeabi_uidivmod)
GCC_ASM_EXPORT(__aeabi_idiv)
GCC_ASM_EXPORT(__aeabi_idivmod)
# AREA Math, CODE, READONLY
#
#UINT32
#EFIAPI
#__aeabi_uidivmode (
# IN UINT32 Dividen
# IN UINT32 Divisor
# );
#
ASM_PFX(__aeabi_uidiv):
ASM_PFX(__aeabi_uidivmod):
rsbs r12, r1, r0, LSR #4
mov r2, #0
bcc ASM_PFX(__arm_div4)
rsbs r12, r1, r0, LSR #8
bcc ASM_PFX(__arm_div8)
mov r3, #0
b ASM_PFX(__arm_div_large)
#
#INT32
#EFIAPI
#__aeabi_idivmode (
# IN INT32 Dividen
# IN INT32 Divisor
# );
#
ASM_PFX(__aeabi_idiv):
ASM_PFX(__aeabi_idivmod):
orrs r12, r0, r1
bmi ASM_PFX(__arm_div_negative)
rsbs r12, r1, r0, LSR #1
mov r2, #0
bcc ASM_PFX(__arm_div1)
rsbs r12, r1, r0, LSR #4
bcc ASM_PFX(__arm_div4)
rsbs r12, r1, r0, LSR #8
bcc ASM_PFX(__arm_div8)
mov r3, #0
b ASM_PFX(__arm_div_large)
ASM_PFX(__arm_div8):
rsbs r12, r1, r0, LSR #7
subcs r0, r0, r1, LSL #7
adc r2, r2, r2
rsbs r12, r1, r0,LSR #6
subcs r0, r0, r1, LSL #6
adc r2, r2, r2
rsbs r12, r1, r0, LSR #5
subcs r0, r0, r1, LSL #5
adc r2, r2, r2
rsbs r12, r1, r0, LSR #4
subcs r0, r0, r1, LSL #4
adc r2, r2, r2
ASM_PFX(__arm_div4):
rsbs r12, r1, r0, LSR #3
subcs r0, r0, r1, LSL #3
adc r2, r2, r2
rsbs r12, r1, r0, LSR #2
subcs r0, r0, r1, LSL #2
adcs r2, r2, r2
rsbs r12, r1, r0, LSR #1
subcs r0, r0, r1, LSL #1
adc r2, r2, r2
ASM_PFX(__arm_div1):
subs r1, r0, r1
movcc r1, r0
adc r0, r2, r2
bx r14
ASM_PFX(__arm_div_negative):
ands r2, r1, #0x80000000
rsbmi r1, r1, #0
eors r3, r2, r0, ASR #32
rsbcs r0, r0, #0
rsbs r12, r1, r0, LSR #4
bcc label1
rsbs r12, r1, r0, LSR #8
bcc label2
ASM_PFX(__arm_div_large):
lsl r1, r1, #6
rsbs r12, r1, r0, LSR #8
orr r2, r2, #0xfc000000
bcc label2
lsl r1, r1, #6
rsbs r12, r1, r0, LSR #8
orr r2, r2, #0x3f00000
bcc label2
lsl r1, r1, #6
rsbs r12, r1, r0, LSR #8
orr r2, r2, #0xfc000
orrcs r2, r2, #0x3f00
lslcs r1, r1, #6
rsbs r12, r1, #0
bcs ASM_PFX(__aeabi_idiv0)
label3:
lsrcs r1, r1, #6
label2:
rsbs r12, r1, r0, LSR #7
subcs r0, r0, r1, LSL #7
adc r2, r2, r2
rsbs r12, r1, r0, LSR #6
subcs r0, r0, r1, LSL #6
adc r2, r2, r2
rsbs r12, r1, r0, LSR #5
subcs r0, r0, r1, LSL #5
adc r2, r2, r2
rsbs r12, r1, r0, LSR #4
subcs r0, r0, r1, LSL #4
adc r2, r2, r2
label1:
rsbs r12, r1, r0, LSR #3
subcs r0, r0, r1, LSL #3
adc r2, r2, r2
rsbs r12, r1, r0, LSR #2
subcs r0, r0, r1, LSL #2
adcs r2, r2, r2
bcs label3
rsbs r12, r1, r0, LSR #1
subcs r0, r0, r1, LSL #1
adc r2, r2, r2
subs r1, r0, r1
movcc r1, r0
adc r0, r2, r2
asrs r3, r3, #31
rsbmi r0, r0, #0
rsbcs r1, r1, #0
bx r14
@ What to do about division by zero? For now, just return.
ASM_PFX(__aeabi_idiv0):
bx r14

310
ArmPkg/Library/CompilerIntrinsicsLib/Arm/div.asm
View File

@ -1,155 +1,155 @@
//------------------------------------------------------------------------------
//
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
//------------------------------------------------------------------------------
EXPORT __aeabi_uidiv
EXPORT __aeabi_uidivmod
EXPORT __aeabi_idiv
EXPORT __aeabi_idivmod
AREA Math, CODE, READONLY
;
;UINT32
;EFIAPI
;__aeabi_uidivmode (
; IN UINT32 Dividen
; IN UINT32 Divisor
; );
;
__aeabi_uidiv
__aeabi_uidivmod
RSBS r12, r1, r0, LSR #4
MOV r2, #0
BCC __arm_div4
RSBS r12, r1, r0, LSR #8
BCC __arm_div8
MOV r3, #0
B __arm_div_large
;
;INT32
;EFIAPI
;__aeabi_idivmode (
; IN INT32 Dividen
; IN INT32 Divisor
; );
;
__aeabi_idiv
__aeabi_idivmod
ORRS r12, r0, r1
BMI __arm_div_negative
RSBS r12, r1, r0, LSR #1
MOV r2, #0
BCC __arm_div1
RSBS r12, r1, r0, LSR #4
BCC __arm_div4
RSBS r12, r1, r0, LSR #8
BCC __arm_div8
MOV r3, #0
B __arm_div_large
__arm_div8
RSBS r12, r1, r0, LSR #7
SUBCS r0, r0, r1, LSL #7
ADC r2, r2, r2
RSBS r12, r1, r0,LSR #6
SUBCS r0, r0, r1, LSL #6
ADC r2, r2, r2
RSBS r12, r1, r0, LSR #5
SUBCS r0, r0, r1, LSL #5
ADC r2, r2, r2
RSBS r12, r1, r0, LSR #4
SUBCS r0, r0, r1, LSL #4
ADC r2, r2, r2
__arm_div4
RSBS r12, r1, r0, LSR #3
SUBCS r0, r0, r1, LSL #3
ADC r2, r2, r2
RSBS r12, r1, r0, LSR #2
SUBCS r0, r0, r1, LSL #2
ADCS r2, r2, r2
RSBS r12, r1, r0, LSR #1
SUBCS r0, r0, r1, LSL #1
ADC r2, r2, r2
__arm_div1
SUBS r1, r0, r1
MOVCC r1, r0
ADC r0, r2, r2
BX r14
__arm_div_negative
ANDS r2, r1, #0x80000000
RSBMI r1, r1, #0
EORS r3, r2, r0, ASR #32
RSBCS r0, r0, #0
RSBS r12, r1, r0, LSR #4
BCC label1
RSBS r12, r1, r0, LSR #8
BCC label2
__arm_div_large
LSL r1, r1, #6
RSBS r12, r1, r0, LSR #8
ORR r2, r2, #0xfc000000
BCC label2
LSL r1, r1, #6
RSBS r12, r1, r0, LSR #8
ORR r2, r2, #0x3f00000
BCC label2
LSL r1, r1, #6
RSBS r12, r1, r0, LSR #8
ORR r2, r2, #0xfc000
ORRCS r2, r2, #0x3f00
LSLCS r1, r1, #6
RSBS r12, r1, #0
BCS __aeabi_idiv0
label3
LSRCS r1, r1, #6
label2
RSBS r12, r1, r0, LSR #7
SUBCS r0, r0, r1, LSL #7
ADC r2, r2, r2
RSBS r12, r1, r0, LSR #6
SUBCS r0, r0, r1, LSL #6
ADC r2, r2, r2
RSBS r12, r1, r0, LSR #5
SUBCS r0, r0, r1, LSL #5
ADC r2, r2, r2
RSBS r12, r1, r0, LSR #4
SUBCS r0, r0, r1, LSL #4
ADC r2, r2, r2
label1
RSBS r12, r1, r0, LSR #3
SUBCS r0, r0, r1, LSL #3
ADC r2, r2, r2
RSBS r12, r1, r0, LSR #2
SUBCS r0, r0, r1, LSL #2
ADCS r2, r2, r2
BCS label3
RSBS r12, r1, r0, LSR #1
SUBCS r0, r0, r1, LSL #1
ADC r2, r2, r2
SUBS r1, r0, r1
MOVCC r1, r0
ADC r0, r2, r2
ASRS r3, r3, #31
RSBMI r0, r0, #0
RSBCS r1, r1, #0
BX r14
; What to do about division by zero? For now, just return.
__aeabi_idiv0
BX r14
END
//------------------------------------------------------------------------------
//
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
//------------------------------------------------------------------------------
EXPORT __aeabi_uidiv
EXPORT __aeabi_uidivmod
EXPORT __aeabi_idiv
EXPORT __aeabi_idivmod
AREA Math, CODE, READONLY
;
;UINT32
;EFIAPI
;__aeabi_uidivmode (
; IN UINT32 Dividen
; IN UINT32 Divisor
; );
;
__aeabi_uidiv
__aeabi_uidivmod
RSBS r12, r1, r0, LSR #4
MOV r2, #0
BCC __arm_div4
RSBS r12, r1, r0, LSR #8
BCC __arm_div8
MOV r3, #0
B __arm_div_large
;
;INT32
;EFIAPI
;__aeabi_idivmode (
; IN INT32 Dividen
; IN INT32 Divisor
; );
;
__aeabi_idiv
__aeabi_idivmod
ORRS r12, r0, r1
BMI __arm_div_negative
RSBS r12, r1, r0, LSR #1
MOV r2, #0
BCC __arm_div1
RSBS r12, r1, r0, LSR #4
BCC __arm_div4
RSBS r12, r1, r0, LSR #8
BCC __arm_div8
MOV r3, #0
B __arm_div_large
__arm_div8
RSBS r12, r1, r0, LSR #7
SUBCS r0, r0, r1, LSL #7
ADC r2, r2, r2
RSBS r12, r1, r0,LSR #6
SUBCS r0, r0, r1, LSL #6
ADC r2, r2, r2
RSBS r12, r1, r0, LSR #5
SUBCS r0, r0, r1, LSL #5
ADC r2, r2, r2
RSBS r12, r1, r0, LSR #4
SUBCS r0, r0, r1, LSL #4
ADC r2, r2, r2
__arm_div4
RSBS r12, r1, r0, LSR #3
SUBCS r0, r0, r1, LSL #3
ADC r2, r2, r2
RSBS r12, r1, r0, LSR #2
SUBCS r0, r0, r1, LSL #2
ADCS r2, r2, r2
RSBS r12, r1, r0, LSR #1
SUBCS r0, r0, r1, LSL #1
ADC r2, r2, r2
__arm_div1
SUBS r1, r0, r1
MOVCC r1, r0
ADC r0, r2, r2
BX r14
__arm_div_negative
ANDS r2, r1, #0x80000000
RSBMI r1, r1, #0
EORS r3, r2, r0, ASR #32
RSBCS r0, r0, #0
RSBS r12, r1, r0, LSR #4
BCC label1
RSBS r12, r1, r0, LSR #8
BCC label2
__arm_div_large
LSL r1, r1, #6
RSBS r12, r1, r0, LSR #8
ORR r2, r2, #0xfc000000
BCC label2
LSL r1, r1, #6
RSBS r12, r1, r0, LSR #8
ORR r2, r2, #0x3f00000
BCC label2
LSL r1, r1, #6
RSBS r12, r1, r0, LSR #8
ORR r2, r2, #0xfc000
ORRCS r2, r2, #0x3f00
LSLCS r1, r1, #6
RSBS r12, r1, #0
BCS __aeabi_idiv0
label3
LSRCS r1, r1, #6
label2
RSBS r12, r1, r0, LSR #7
SUBCS r0, r0, r1, LSL #7
ADC r2, r2, r2
RSBS r12, r1, r0, LSR #6
SUBCS r0, r0, r1, LSL #6
ADC r2, r2, r2
RSBS r12, r1, r0, LSR #5
SUBCS r0, r0, r1, LSL #5
ADC r2, r2, r2
RSBS r12, r1, r0, LSR #4
SUBCS r0, r0, r1, LSL #4
ADC r2, r2, r2
label1
RSBS r12, r1, r0, LSR #3
SUBCS r0, r0, r1, LSL #3
ADC r2, r2, r2
RSBS r12, r1, r0, LSR #2
SUBCS r0, r0, r1, LSL #2
ADCS r2, r2, r2
BCS label3
RSBS r12, r1, r0, LSR #1
SUBCS r0, r0, r1, LSL #1
ADC r2, r2, r2
SUBS r1, r0, r1
MOVCC r1, r0
ADC r0, r2, r2
ASRS r3, r3, #31
RSBMI r0, r0, #0
RSBCS r1, r1, #0
BX r14
; What to do about division by zero? For now, just return.
__aeabi_idiv0
BX r14
END

98
ArmPkg/Library/CompilerIntrinsicsLib/Arm/divdi3.S
View File

@ -1,49 +1,49 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
.text
.align 2
GCC_ASM_EXPORT(__divdi3)
ASM_PFX(__divdi3):
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 1, uses_anonymous_args = 0
stmfd sp!, {r4, r5, r7, lr}
mov r4, r3, asr #31
add r7, sp, #8
stmfd sp!, {r10, r11}
mov r10, r1, asr #31
sub sp, sp, #8
mov r11, r10
mov r5, r4
eor r0, r0, r10
eor r1, r1, r10
eor r2, r2, r4
eor r3, r3, r4
subs r2, r2, r4
sbc r3, r3, r5
mov ip, #0
subs r0, r0, r10
sbc r1, r1, r11
str ip, [sp, #0]
bl ASM_PFX(__udivmoddi4)
eor r2, r10, r4
eor r3, r10, r4
eor r0, r0, r2
eor r1, r1, r3
subs r0, r0, r2
sbc r1, r1, r3
sub sp, r7, #16
ldmfd sp!, {r10, r11}
ldmfd sp!, {r4, r5, r7, pc}
#------------------------------------------------------------------------------
#
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
.text
.align 2
GCC_ASM_EXPORT(__divdi3)
ASM_PFX(__divdi3):
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 1, uses_anonymous_args = 0
stmfd sp!, {r4, r5, r7, lr}
mov r4, r3, asr #31
add r7, sp, #8
stmfd sp!, {r10, r11}
mov r10, r1, asr #31
sub sp, sp, #8
mov r11, r10
mov r5, r4
eor r0, r0, r10
eor r1, r1, r10
eor r2, r2, r4
eor r3, r3, r4
subs r2, r2, r4
sbc r3, r3, r5
mov ip, #0
subs r0, r0, r10
sbc r1, r1, r11
str ip, [sp, #0]
bl ASM_PFX(__udivmoddi4)
eor r2, r10, r4
eor r3, r10, r4
eor r0, r0, r2
eor r1, r1, r3
subs r0, r0, r2
sbc r1, r1, r3
sub sp, r7, #16
ldmfd sp!, {r10, r11}
ldmfd sp!, {r4, r5, r7, pc}

154
ArmPkg/Library/CompilerIntrinsicsLib/Arm/divdi3.c
View File

@ -1,77 +1,77 @@
/** @file
Compiler intrinsic for 64-bit compare, ported from LLVM code.
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
/**
University of Illinois/NCSA
Open Source License
Copyright (c) 2003-2008 University of Illinois at Urbana-Champaign.
All rights reserved.
Developed by:
LLVM Team
University of Illinois at Urbana-Champaign
http://llvm.org
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal with
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimers.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimers in the
documentation and/or other materials provided with the distribution.
* Neither the names of the LLVM Team, University of Illinois at
Urbana-Champaign, nor the names of its contributors may be used to
endorse or promote products derived from this Software without specific
prior written permission.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
SOFTWARE.
**/
#include "Llvm_int_lib.h"
UINT64 __udivmoddi4(UINT64 a, UINT64 b, UINT64* rem);
// Returns: a / b
INT64
__divdi3(INT64 a, INT64 b)
{
const int bits_in_dword_m1 = (int)(sizeof(INT64) * CHAR_BIT) - 1;
INT64 s_a = a >> bits_in_dword_m1; // s_a = a < 0 ? -1 : 0
INT64 s_b = b >> bits_in_dword_m1; // s_b = b < 0 ? -1 : 0
a = (a ^ s_a) - s_a; // negate if s_a == -1
b = (b ^ s_b) - s_b; // negate if s_b == -1
s_a ^= s_b; // sign of quotient
return (__udivmoddi4(a, b, (UINT64*)0) ^ s_a) - s_a; // negate if s_a == -1
}
/** @file
Compiler intrinsic for 64-bit compare, ported from LLVM code.
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
/**
University of Illinois/NCSA
Open Source License
Copyright (c) 2003-2008 University of Illinois at Urbana-Champaign.
All rights reserved.
Developed by:
LLVM Team
University of Illinois at Urbana-Champaign
http://llvm.org
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal with
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimers.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimers in the
documentation and/or other materials provided with the distribution.
* Neither the names of the LLVM Team, University of Illinois at
Urbana-Champaign, nor the names of its contributors may be used to
endorse or promote products derived from this Software without specific
prior written permission.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
SOFTWARE.
**/
#include "Llvm_int_lib.h"
UINT64 __udivmoddi4(UINT64 a, UINT64 b, UINT64* rem);
// Returns: a / b
INT64
__divdi3(INT64 a, INT64 b)
{
const int bits_in_dword_m1 = (int)(sizeof(INT64) * CHAR_BIT) - 1;
INT64 s_a = a >> bits_in_dword_m1; // s_a = a < 0 ? -1 : 0
INT64 s_b = b >> bits_in_dword_m1; // s_b = b < 0 ? -1 : 0
a = (a ^ s_a) - s_a; // negate if s_a == -1
b = (b ^ s_b) - s_b; // negate if s_b == -1
s_a ^= s_b; // sign of quotient
return (__udivmoddi4(a, b, (UINT64*)0) ^ s_a) - s_a; // negate if s_a == -1
}

64
ArmPkg/Library/CompilerIntrinsicsLib/Arm/divsi3.S
View File

@ -1,32 +1,32 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
.text
.align 2
GCC_ASM_EXPORT(__divsi3)
ASM_PFX(__divsi3):
eor r3, r0, r0, asr #31
eor r2, r1, r1, asr #31
stmfd sp!, {r4, r5, r7, lr}
mov r5, r0, asr #31
add r7, sp, #8
mov r4, r1, asr #31
sub r0, r3, r0, asr #31
sub r1, r2, r1, asr #31
bl ASM_PFX(__udivsi3)
eor r1, r5, r4
eor r0, r0, r1
rsb r0, r1, r0
ldmfd sp!, {r4, r5, r7, pc}
#------------------------------------------------------------------------------
#
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
.text
.align 2
GCC_ASM_EXPORT(__divsi3)
ASM_PFX(__divsi3):
eor r3, r0, r0, asr #31
eor r2, r1, r1, asr #31
stmfd sp!, {r4, r5, r7, lr}
mov r5, r0, asr #31
add r7, sp, #8
mov r4, r1, asr #31
sub r0, r3, r0, asr #31
sub r1, r2, r1, asr #31
bl ASM_PFX(__udivsi3)
eor r1, r5, r4
eor r0, r0, r1
rsb r0, r1, r0
ldmfd sp!, {r4, r5, r7, pc}

156
ArmPkg/Library/CompilerIntrinsicsLib/Arm/divsi3.c
View File

@ -1,78 +1,78 @@
/** @file
Compiler intrinsic for 32--bit unsigned division, ported from LLVM code.
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
/**
University of Illinois/NCSA
Open Source License
Copyright (c) 2003-2008 University of Illinois at Urbana-Champaign.
All rights reserved.
Developed by:
LLVM Team
University of Illinois at Urbana-Champaign
http://llvm.org
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal with
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimers.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimers in the
documentation and/or other materials provided with the distribution.
* Neither the names of the LLVM Team, University of Illinois at
Urbana-Champaign, nor the names of its contributors may be used to
endorse or promote products derived from this Software without specific
prior written permission.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
SOFTWARE.
**/
#include "Llvm_int_lib.h"
UINT32 __udivsi3(UINT32 n, UINT32 d);
// Returns: a / b
INT32
__divsi3(INT32 a, INT32 b)
{
const int bits_in_word_m1 = (int)(sizeof(INT32) * CHAR_BIT) - 1;
INT32 s_a = a >> bits_in_word_m1; // s_a = a < 0 ? -1 : 0
INT32 s_b = b >> bits_in_word_m1; // s_b = b < 0 ? -1 : 0
a = (a ^ s_a) - s_a; // negate if s_a == -1
b = (b ^ s_b) - s_b; // negate if s_b == -1
s_a ^= s_b; // sign of quotient
return (__udivsi3(a, b) ^ s_a) - s_a; // negate if s_a == -1
}
/** @file
Compiler intrinsic for 32--bit unsigned division, ported from LLVM code.
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
/**
University of Illinois/NCSA
Open Source License
Copyright (c) 2003-2008 University of Illinois at Urbana-Champaign.
All rights reserved.
Developed by:
LLVM Team
University of Illinois at Urbana-Champaign
http://llvm.org
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal with
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimers.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimers in the
documentation and/or other materials provided with the distribution.
* Neither the names of the LLVM Team, University of Illinois at
Urbana-Champaign, nor the names of its contributors may be used to
endorse or promote products derived from this Software without specific
prior written permission.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
SOFTWARE.
**/
#include "Llvm_int_lib.h"
UINT32 __udivsi3(UINT32 n, UINT32 d);
// Returns: a / b
INT32
__divsi3(INT32 a, INT32 b)
{
const int bits_in_word_m1 = (int)(sizeof(INT32) * CHAR_BIT) - 1;
INT32 s_a = a >> bits_in_word_m1; // s_a = a < 0 ? -1 : 0
INT32 s_b = b >> bits_in_word_m1; // s_b = b < 0 ? -1 : 0
a = (a ^ s_a) - s_a; // negate if s_a == -1
b = (b ^ s_b) - s_b; // negate if s_b == -1
s_a ^= s_b; // sign of quotient
return (__udivsi3(a, b) ^ s_a) - s_a; // negate if s_a == -1
}

82
ArmPkg/Library/CompilerIntrinsicsLib/Arm/lasr.asm
View File

@ -1,41 +1,41 @@
//------------------------------------------------------------------------------
//
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
//------------------------------------------------------------------------------
EXPORT __aeabi_lasr
AREA Math, CODE, READONLY
;
;UINT32
;EFIAPI
;__aeabi_lasr (
; IN UINT32 Dividen
; IN UINT32 Divisor
; );
;
__aeabi_lasr
SUBS r3,r2,#0x20
BPL {pc} + 0x18 ; 0x1c
RSB r3,r2,#0x20
LSR r0,r0,r2
ORR r0,r0,r1,LSL r3
ASR r1,r1,r2
BX lr
ASR r0,r1,r3
ASR r1,r1,#31
BX lr
END
//------------------------------------------------------------------------------
//
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
//------------------------------------------------------------------------------
EXPORT __aeabi_lasr
AREA Math, CODE, READONLY
;
;UINT32
;EFIAPI
;__aeabi_lasr (
; IN UINT32 Dividen
; IN UINT32 Divisor
; );
;
__aeabi_lasr
SUBS r3,r2,#0x20
BPL {pc} + 0x18 ; 0x1c
RSB r3,r2,#0x20
LSR r0,r0,r2
ORR r0,r0,r1,LSL r3
ASR r1,r1,r2
BX lr
ASR r0,r1,r3
ASR r1,r1,#31
BX lr
END

118
ArmPkg/Library/CompilerIntrinsicsLib/Arm/ldivmod.S
View File

@ -1,59 +1,59 @@
//------------------------------------------------------------------------------
//
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
//------------------------------------------------------------------------------
.text
.align 2
GCC_ASM_EXPORT(__aeabi_ldivmod)
//
// A pair of (unsigned) long longs is returned in {{r0, r1}, {r2, r3}},
// the quotient in {r0, r1}, and the remainder in {r2, r3}.
//
//__value_in_regs lldiv_t
//EFIAPI
//__aeabi_ldivmod (
// IN UINT64 Dividen
// IN UINT64 Divisor
// )//
//
ASM_PFX(__aeabi_ldivmod):
push {r4,lr}
asrs r4,r1,#1
eor r4,r4,r3,LSR #1
bpl L_Test1
rsbs r0,r0,#0
rsc r1,r1,#0
L_Test1:
tst r3,r3
bpl L_Test2
rsbs r2,r2,#0
rsc r3,r3,#0
L_Test2:
bl ASM_PFX(__aeabi_uldivmod)
tst r4,#0x40000000
beq L_Test3
rsbs r0,r0,#0
rsc r1,r1,#0
L_Test3:
tst r4,#0x80000000
beq L_Exit
rsbs r2,r2,#0
rsc r3,r3,#0
L_Exit:
pop {r4,pc}
//------------------------------------------------------------------------------
//
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
//------------------------------------------------------------------------------
.text
.align 2
GCC_ASM_EXPORT(__aeabi_ldivmod)
//
// A pair of (unsigned) long longs is returned in {{r0, r1}, {r2, r3}},
// the quotient in {r0, r1}, and the remainder in {r2, r3}.
//
//__value_in_regs lldiv_t
//EFIAPI
//__aeabi_ldivmod (
// IN UINT64 Dividen
// IN UINT64 Divisor
// )//
//
ASM_PFX(__aeabi_ldivmod):
push {r4,lr}
asrs r4,r1,#1
eor r4,r4,r3,LSR #1
bpl L_Test1
rsbs r0,r0,#0
rsc r1,r1,#0
L_Test1:
tst r3,r3
bpl L_Test2
rsbs r2,r2,#0
rsc r3,r3,#0
L_Test2:
bl ASM_PFX(__aeabi_uldivmod)
tst r4,#0x40000000
beq L_Test3
rsbs r0,r0,#0
rsc r1,r1,#0
L_Test3:
tst r4,#0x80000000
beq L_Exit
rsbs r2,r2,#0
rsc r3,r3,#0
L_Exit:
pop {r4,pc}

116
ArmPkg/Library/CompilerIntrinsicsLib/Arm/ldivmod.asm
View File

@ -1,58 +1,58 @@
//------------------------------------------------------------------------------
//
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
//------------------------------------------------------------------------------
EXPORT __aeabi_ldivmod
EXTERN __aeabi_uldivmod
AREA Math, CODE, READONLY
;
;UINT32
;EFIAPI
;__aeabi_uidivmode (
; IN UINT32 Dividen
; IN UINT32 Divisor
; );
;
__aeabi_ldivmod
PUSH {r4,lr}
ASRS r4,r1,#1
EOR r4,r4,r3,LSR #1
BPL L_Test1
RSBS r0,r0,#0
RSC r1,r1,#0
L_Test1
TST r3,r3
BPL L_Test2
RSBS r2,r2,#0
RSC r3,r3,#0
L_Test2
BL __aeabi_uldivmod ;
TST r4,#0x40000000
BEQ L_Test3
RSBS r0,r0,#0
RSC r1,r1,#0
L_Test3
TST r4,#0x80000000
BEQ L_Exit
RSBS r2,r2,#0
RSC r3,r3,#0
L_Exit
POP {r4,pc}
END
//------------------------------------------------------------------------------
//
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
//------------------------------------------------------------------------------
EXPORT __aeabi_ldivmod
EXTERN __aeabi_uldivmod
AREA Math, CODE, READONLY
;
;UINT32
;EFIAPI
;__aeabi_uidivmode (
; IN UINT32 Dividen
; IN UINT32 Divisor
; );
;
__aeabi_ldivmod
PUSH {r4,lr}
ASRS r4,r1,#1
EOR r4,r4,r3,LSR #1
BPL L_Test1
RSBS r0,r0,#0
RSC r1,r1,#0
L_Test1
TST r3,r3
BPL L_Test2
RSBS r2,r2,#0
RSC r3,r3,#0
L_Test2
BL __aeabi_uldivmod ;
TST r4,#0x40000000
BEQ L_Test3
RSBS r0,r0,#0
RSC r1,r1,#0
L_Test3
TST r4,#0x80000000
BEQ L_Exit
RSBS r2,r2,#0
RSC r3,r3,#0
L_Exit
POP {r4,pc}
END

86
ArmPkg/Library/CompilerIntrinsicsLib/Arm/llsl.asm
View File

@ -1,43 +1,43 @@
//------------------------------------------------------------------------------
//
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
//------------------------------------------------------------------------------
EXPORT __aeabi_llsl
AREA Math, CODE, READONLY
;
;VOID
;EFIAPI
;__aeabi_llsl (
; IN VOID *Destination,
; IN VOID *Source,
; IN UINT32 Size
; );
;
__aeabi_llsl
SUBS r3,r2,#0x20
BPL {pc} + 0x18 ; 0x1c
RSB r3,r2,#0x20
LSL r1,r1,r2
ORR r1,r1,r0,LSR r3
LSL r0,r0,r2
BX lr
LSL r1,r0,r3
MOV r0,#0
BX lr
END
//------------------------------------------------------------------------------
//
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
//------------------------------------------------------------------------------
EXPORT __aeabi_llsl
AREA Math, CODE, READONLY
;
;VOID
;EFIAPI
;__aeabi_llsl (
; IN VOID *Destination,
; IN VOID *Source,
; IN UINT32 Size
; );
;
__aeabi_llsl
SUBS r3,r2,#0x20
BPL {pc} + 0x18 ; 0x1c
RSB r3,r2,#0x20
LSL r1,r1,r2
ORR r1,r1,r0,LSR r3
LSL r0,r0,r2
BX lr
LSL r1,r0,r3
MOV r0,#0
BX lr
END

88
ArmPkg/Library/CompilerIntrinsicsLib/Arm/llsr.asm
View File

@ -1,44 +1,44 @@
//------------------------------------------------------------------------------
//
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
//------------------------------------------------------------------------------
EXPORT __aeabi_llsr
AREA Math, CODE, READONLY
;
;VOID
;EFIAPI
;__aeabi_llsr (
; IN VOID *Destination,
; IN VOID *Source,
; IN UINT32 Size
; );
;
__aeabi_llsr
SUBS r3,r2,#0x20
BPL {pc} + 0x18 ; 0x1c
RSB r3,r2,#0x20
LSR r0,r0,r2
ORR r0,r0,r1,LSL r3
LSR r1,r1,r2
BX lr
LSR r0,r1,r3
MOV r1,#0
BX lr
END
//------------------------------------------------------------------------------
//
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
//------------------------------------------------------------------------------
EXPORT __aeabi_llsr
AREA Math, CODE, READONLY
;
;VOID
;EFIAPI
;__aeabi_llsr (
; IN VOID *Destination,
; IN VOID *Source,
; IN UINT32 Size
; );
;
__aeabi_llsr
SUBS r3,r2,#0x20
BPL {pc} + 0x18 ; 0x1c
RSB r3,r2,#0x20
LSR r0,r0,r2
ORR r0,r0,r1,LSL r3
LSR r1,r1,r2
BX lr
LSR r0,r1,r3
MOV r1,#0
BX lr
END

70
ArmPkg/Library/CompilerIntrinsicsLib/Arm/lshrdi3.S
View File

@ -1,35 +1,35 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
.text
.align 2
GCC_ASM_EXPORT(__lshrdi3)
ASM_PFX(__lshrdi3):
cmp r2, #31
bls L2
cmp r2, #63
subls r2, r2, #32
movls r2, r1, lsr r2
movhi r2, #0
mov r0, r2
mov r1, #0
bx lr
L2:
cmp r2, #0
rsbne r3, r2, #32
movne r3, r1, asl r3
movne r1, r1, lsr r2
orrne r0, r3, r0, lsr r2
bx lr
#------------------------------------------------------------------------------
#
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
.text
.align 2
GCC_ASM_EXPORT(__lshrdi3)
ASM_PFX(__lshrdi3):
cmp r2, #31
bls L2
cmp r2, #63
subls r2, r2, #32
movls r2, r1, lsr r2
movhi r2, #0
mov r0, r2
mov r1, #0
bx lr
L2:
cmp r2, #0
rsbne r3, r2, #32
movne r3, r1, asl r3
movne r1, r1, lsr r2
orrne r0, r3, r0, lsr r2
bx lr

166
ArmPkg/Library/CompilerIntrinsicsLib/Arm/lshrdi3.c
View File

@ -1,83 +1,83 @@
/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
/**
University of Illinois/NCSA
Open Source License
Copyright (c) 2003-2008 University of Illinois at Urbana-Champaign.
All rights reserved.
Developed by:
LLVM Team
University of Illinois at Urbana-Champaign
http://llvm.org
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal with
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimers.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimers in the
documentation and/or other materials provided with the distribution.
* Neither the names of the LLVM Team, University of Illinois at
Urbana-Champaign, nor the names of its contributors may be used to
endorse or promote products derived from this Software without specific
prior written permission.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
SOFTWARE.
**/
#include "Llvm_int_lib.h"
// Returns: logical a >> b
// Precondition: 0 <= b < bits_in_dword
INT64
__lshrdi3(INT64 a, INT32 b)
{
const int bits_in_word = (int)(sizeof(INT32) * CHAR_BIT);
udwords input;
udwords result;
input.all = a;
if (b & bits_in_word) // bits_in_word <= b < bits_in_dword
{
result.high = 0;
result.low = input.high >> (b - bits_in_word);
}
else // 0 <= b < bits_in_word
{
if (b == 0)
return a;
result.high = input.high >> b;
result.low = (input.high << (bits_in_word - b)) | (input.low >> b);
}
return result.all;
}
/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
/**
University of Illinois/NCSA
Open Source License
Copyright (c) 2003-2008 University of Illinois at Urbana-Champaign.
All rights reserved.
Developed by:
LLVM Team
University of Illinois at Urbana-Champaign
http://llvm.org
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal with
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimers.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimers in the
documentation and/or other materials provided with the distribution.
* Neither the names of the LLVM Team, University of Illinois at
Urbana-Champaign, nor the names of its contributors may be used to
endorse or promote products derived from this Software without specific
prior written permission.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
SOFTWARE.
**/
#include "Llvm_int_lib.h"
// Returns: logical a >> b
// Precondition: 0 <= b < bits_in_dword
INT64
__lshrdi3(INT64 a, INT32 b)
{
const int bits_in_word = (int)(sizeof(INT32) * CHAR_BIT);
udwords input;
udwords result;
input.all = a;
if (b & bits_in_word) // bits_in_word <= b < bits_in_dword
{
result.high = 0;
result.low = input.high >> (b - bits_in_word);
}
else // 0 <= b < bits_in_word
{
if (b == 0)
return a;
result.high = input.high >> b;
result.low = (input.high << (bits_in_word - b)) | (input.low >> b);
}
return result.all;
}

68
ArmPkg/Library/CompilerIntrinsicsLib/Arm/memcpy.S
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@ -1,34 +1,34 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
.text
.align 2
GCC_ASM_EXPORT(memcpy)
ASM_PFX(memcpy):
stmfd sp!, {r7, lr}
mov ip, #0
add r7, sp, #0
mov lr, r0
b L4
L5:
ldrb r3, [r1], #1 @ zero_extendqisi2
add ip, ip, #1
and r3, r3, #255
strb r3, [lr], #1
L4:
cmp ip, r2
bne L5
ldmfd sp!, {r7, pc}
#------------------------------------------------------------------------------
#
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
.text
.align 2
GCC_ASM_EXPORT(memcpy)
ASM_PFX(memcpy):
stmfd sp!, {r7, lr}
mov ip, #0
add r7, sp, #0
mov lr, r0
b L4
L5:
ldrb r3, [r1], #1 @ zero_extendqisi2
add ip, ip, #1
and r3, r3, #255
strb r3, [lr], #1
L4:
cmp ip, r2
bne L5
ldmfd sp!, {r7, pc}

80
ArmPkg/Library/CompilerIntrinsicsLib/Arm/memcpy.asm
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@ -1,40 +1,40 @@
//------------------------------------------------------------------------------
//
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
//------------------------------------------------------------------------------
EXPORT __aeabi_memcpy
AREA Memcpy, CODE, READONLY
;
;VOID
;EFIAPI
;__aeabi_memcpy (
; IN VOID *Destination,
; IN VOID *Source,
; IN UINT32 Size
; );
;
__aeabi_memcpy
CMP r2, #0
BXEQ r14
loop
LDRB r3, [r1], #1
STRB r3, [r0], #1
SUBS r2, r2, #1
BXEQ r14
B loop
END
//------------------------------------------------------------------------------
//
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
//------------------------------------------------------------------------------
EXPORT __aeabi_memcpy
AREA Memcpy, CODE, READONLY
;
;VOID
;EFIAPI
;__aeabi_memcpy (
; IN VOID *Destination,
; IN VOID *Source,
; IN UINT32 Size
; );
;
__aeabi_memcpy
CMP r2, #0
BXEQ r14
loop
LDRB r3, [r1], #1
STRB r3, [r0], #1
SUBS r2, r2, #1
BXEQ r14
B loop
END

122
ArmPkg/Library/CompilerIntrinsicsLib/Arm/memcpy4.asm
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@ -1,61 +1,61 @@
//------------------------------------------------------------------------------
//
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
//------------------------------------------------------------------------------
EXPORT __aeabi_memcpy4
AREA Memcpy4, CODE, READONLY
;
;VOID
;EFIAPI
;__aeabi_memcpy (
; IN VOID *Destination,
; IN VOID *Source,
; IN UINT32 Size
; );
;
__aeabi_memcpy4
stmdb sp!, {r4, lr}
subs r2, r2, #32 ; 0x20
bcc memcpy4_label2
memcpy4_label1
ldmcsia r1!, {r3, r4, ip, lr}
stmcsia r0!, {r3, r4, ip, lr}
ldmcsia r1!, {r3, r4, ip, lr}
stmcsia r0!, {r3, r4, ip, lr}
subcss r2, r2, #32 ; 0x20
bcs memcpy4_label1
memcpy4_label2
movs ip, r2, lsl #28
ldmcsia r1!, {r3, r4, ip, lr}
stmcsia r0!, {r3, r4, ip, lr}
ldmmiia r1!, {r3, r4}
stmmiia r0!, {r3, r4}
ldmia sp!, {r4, lr}
movs ip, r2, lsl #30
ldrcs r3, [r1], #4
strcs r3, [r0], #4
bxeq lr
_memcpy4_lastbytes_aligned
movs r2, r2, lsl #31
ldrcsh r3, [r1], #2
ldrmib r2, [r1], #1
strcsh r3, [r0], #2
strmib r2, [r0], #1
bx lr
END
//------------------------------------------------------------------------------
//
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
//------------------------------------------------------------------------------
EXPORT __aeabi_memcpy4
AREA Memcpy4, CODE, READONLY
;
;VOID
;EFIAPI
;__aeabi_memcpy (
; IN VOID *Destination,
; IN VOID *Source,
; IN UINT32 Size
; );
;
__aeabi_memcpy4
stmdb sp!, {r4, lr}
subs r2, r2, #32 ; 0x20
bcc memcpy4_label2
memcpy4_label1
ldmcsia r1!, {r3, r4, ip, lr}
stmcsia r0!, {r3, r4, ip, lr}
ldmcsia r1!, {r3, r4, ip, lr}
stmcsia r0!, {r3, r4, ip, lr}
subcss r2, r2, #32 ; 0x20
bcs memcpy4_label1
memcpy4_label2
movs ip, r2, lsl #28
ldmcsia r1!, {r3, r4, ip, lr}
stmcsia r0!, {r3, r4, ip, lr}
ldmmiia r1!, {r3, r4}
stmmiia r0!, {r3, r4}
ldmia sp!, {r4, lr}
movs ip, r2, lsl #30
ldrcs r3, [r1], #4
strcs r3, [r0], #4
bxeq lr
_memcpy4_lastbytes_aligned
movs r2, r2, lsl #31
ldrcsh r3, [r1], #2
ldrmib r2, [r1], #1
strcsh r3, [r0], #2
strmib r2, [r0], #1
bx lr
END

108
ArmPkg/Library/CompilerIntrinsicsLib/Arm/memmove.asm
View File

@ -1,54 +1,54 @@
//------------------------------------------------------------------------------
//
// Copyright (c) 2011, ARM Limited. All rights reserved.
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
//------------------------------------------------------------------------------
EXPORT __aeabi_memmove
AREA Memmove, CODE, READONLY
;
;VOID
;EFIAPI
;__aeabi_memmove (
; IN VOID *Destination,
; IN CONST VOID *Source,
; IN UINT32 Size
; );
;
__aeabi_memmove
CMP r2, #0
BXEQ r14
CMP r0, r1
BXEQ r14
BHI memmove_backward
BLS memmove_forward
memmove_forward
LDRB r3, [r1], #1
STRB r3, [r0], #1
SUBS r2, r2, #1
BXEQ r14
B memmove_forward
memmove_backward
add r0, r2
add r1, r2
memmove_backward_loop
LDRB r3, [r1], #-1
STRB r3, [r0], #-1
SUBS r2, r2, #-1
BXEQ r14
B memmove_backward_loop
END
//------------------------------------------------------------------------------
//
// Copyright (c) 2011, ARM Limited. All rights reserved.
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
//------------------------------------------------------------------------------
EXPORT __aeabi_memmove
AREA Memmove, CODE, READONLY
;
;VOID
;EFIAPI
;__aeabi_memmove (
; IN VOID *Destination,
; IN CONST VOID *Source,
; IN UINT32 Size
; );
;
__aeabi_memmove
CMP r2, #0
BXEQ r14
CMP r0, r1
BXEQ r14
BHI memmove_backward
BLS memmove_forward
memmove_forward
LDRB r3, [r1], #1
STRB r3, [r0], #1
SUBS r2, r2, #1
BXEQ r14
B memmove_forward
memmove_backward
add r0, r2
add r1, r2
memmove_backward_loop
LDRB r3, [r1], #-1
STRB r3, [r0], #-1
SUBS r2, r2, #-1
BXEQ r14
B memmove_backward_loop
END

76
ArmPkg/Library/CompilerIntrinsicsLib/Arm/memset.S
View File

@ -1,38 +1,38 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
.text
.align 2
GCC_ASM_EXPORT (memset)
ASM_PFX(memset):
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 1, uses_anonymous_args = 0
stmfd sp!, {r7, lr}
mov ip, #0
add r7, sp, #0
mov lr, r0
b L9
L10:
and r3, r1, #255
add ip, ip, #1
strb r3, [lr], #1
L9:
cmp ip, r2
bne L10
ldmfd sp!, {r7, pc}
#------------------------------------------------------------------------------
#
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
.text
.align 2
GCC_ASM_EXPORT (memset)
ASM_PFX(memset):
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 1, uses_anonymous_args = 0
stmfd sp!, {r7, lr}
mov ip, #0
add r7, sp, #0
mov lr, r0
b L9
L10:
and r3, r1, #255
add ip, ip, #1
strb r3, [lr], #1
L9:
cmp ip, r2
bne L10
ldmfd sp!, {r7, pc}

118
ArmPkg/Library/CompilerIntrinsicsLib/Arm/memset.asm
View File

@ -1,59 +1,59 @@
//------------------------------------------------------------------------------
//
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
//------------------------------------------------------------------------------
EXPORT __aeabi_memset
EXPORT __aeabi_memclr
EXPORT __aeabi_memclr4
AREA Memset, CODE, READONLY
;
;VOID
;EFIAPI
;__aeabi_memset (
; IN VOID *Destination,
; IN UINT32 Character,
; IN UINT32 Size
; );
;
__aeabi_memset
; args = 0, pretend = 0, frame = 0
; frame_needed = 1, uses_anonymous_args = 0
stmfd sp!, {r7, lr}
mov ip, #0
add r7, sp, #0
mov lr, r0
b L9
L10
and r3, r1, #255
add ip, ip, #1
strb r3, [lr], #1
L9
cmp ip, r2
bne L10
ldmfd sp!, {r7, pc}
__aeabi_memclr
mov r2, r1
mov r1, #0
b __aeabi_memset
__aeabi_memclr4
mov r2, r1
mov r1, #0
b __aeabi_memset
END
//------------------------------------------------------------------------------
//
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
//------------------------------------------------------------------------------
EXPORT __aeabi_memset
EXPORT __aeabi_memclr
EXPORT __aeabi_memclr4
AREA Memset, CODE, READONLY
;
;VOID
;EFIAPI
;__aeabi_memset (
; IN VOID *Destination,
; IN UINT32 Character,
; IN UINT32 Size
; );
;
__aeabi_memset
; args = 0, pretend = 0, frame = 0
; frame_needed = 1, uses_anonymous_args = 0
stmfd sp!, {r7, lr}
mov ip, #0
add r7, sp, #0
mov lr, r0
b L9
L10
and r3, r1, #255
add ip, ip, #1
strb r3, [lr], #1
L9
cmp ip, r2
bne L10
ldmfd sp!, {r7, pc}
__aeabi_memclr
mov r2, r1
mov r1, #0
b __aeabi_memset
__aeabi_memclr4
mov r2, r1
mov r1, #0
b __aeabi_memset
END

92
ArmPkg/Library/CompilerIntrinsicsLib/Arm/moddi3.S
View File

@ -1,46 +1,46 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
.text
.align 2
GCC_ASM_EXPORT(__moddi3)
ASM_PFX(__moddi3):
stmfd sp!, {r4, r5, r7, lr}
mov r4, r1, asr #31
add r7, sp, #8
stmfd sp!, {r10, r11}
mov r10, r3, asr #31
sub sp, sp, #16
mov r5, r4
mov r11, r10
eor r0, r0, r4
eor r1, r1, r4
eor r2, r2, r10
eor r3, r3, r10
add ip, sp, #8
subs r0, r0, r4
sbc r1, r1, r5
subs r2, r2, r10
sbc r3, r3, r11
str ip, [sp, #0]
bl ASM_PFX(__udivmoddi4)
ldrd r0, [sp, #8]
eor r0, r0, r4
eor r1, r1, r4
subs r0, r0, r4
sbc r1, r1, r5
sub sp, r7, #16
ldmfd sp!, {r10, r11}
ldmfd sp!, {r4, r5, r7, pc}
#------------------------------------------------------------------------------
#
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
.text
.align 2
GCC_ASM_EXPORT(__moddi3)
ASM_PFX(__moddi3):
stmfd sp!, {r4, r5, r7, lr}
mov r4, r1, asr #31
add r7, sp, #8
stmfd sp!, {r10, r11}
mov r10, r3, asr #31
sub sp, sp, #16
mov r5, r4
mov r11, r10
eor r0, r0, r4
eor r1, r1, r4
eor r2, r2, r10
eor r3, r3, r10
add ip, sp, #8
subs r0, r0, r4
sbc r1, r1, r5
subs r2, r2, r10
sbc r3, r3, r11
str ip, [sp, #0]
bl ASM_PFX(__udivmoddi4)
ldrd r0, [sp, #8]
eor r0, r0, r4
eor r1, r1, r4
subs r0, r0, r4
sbc r1, r1, r5
sub sp, r7, #16
ldmfd sp!, {r10, r11}
ldmfd sp!, {r4, r5, r7, pc}

154
ArmPkg/Library/CompilerIntrinsicsLib/Arm/moddi3.c
View File

@ -1,77 +1,77 @@
/** @file
Compiler intrinsic for 64-bit mod, ported from LLVM code.
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
/**
University of Illinois/NCSA
Open Source License
Copyright (c) 2003-2008 University of Illinois at Urbana-Champaign.
All rights reserved.
Developed by:
LLVM Team
University of Illinois at Urbana-Champaign
http://llvm.org
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal with
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimers.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimers in the
documentation and/or other materials provided with the distribution.
* Neither the names of the LLVM Team, University of Illinois at
Urbana-Champaign, nor the names of its contributors may be used to
endorse or promote products derived from this Software without specific
prior written permission.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
SOFTWARE.
**/
#include "Llvm_int_lib.h"
UINT64 __udivmoddi4(UINT64 a, UINT64 b, UINT64* rem);
// Returns: a % b
INT64
__moddi3(INT64 a, INT64 b)
{
const int bits_in_dword_m1 = (int)(sizeof(INT64) * CHAR_BIT) - 1;
INT64 s = b >> bits_in_dword_m1; // s = b < 0 ? -1 : 0
b = (b ^ s) - s; // negate if s == -1
s = a >> bits_in_dword_m1; // s = a < 0 ? -1 : 0
a = (a ^ s) - s; // negate if s == -1
INT64 r;
__udivmoddi4(a, b, (UINT64*)&r);
return (r ^ s) - s; // negate if s == -1
}
/** @file
Compiler intrinsic for 64-bit mod, ported from LLVM code.
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
/**
University of Illinois/NCSA
Open Source License
Copyright (c) 2003-2008 University of Illinois at Urbana-Champaign.
All rights reserved.
Developed by:
LLVM Team
University of Illinois at Urbana-Champaign
http://llvm.org
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal with
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimers.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimers in the
documentation and/or other materials provided with the distribution.
* Neither the names of the LLVM Team, University of Illinois at
Urbana-Champaign, nor the names of its contributors may be used to
endorse or promote products derived from this Software without specific
prior written permission.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
SOFTWARE.
**/
#include "Llvm_int_lib.h"
UINT64 __udivmoddi4(UINT64 a, UINT64 b, UINT64* rem);
// Returns: a % b
INT64
__moddi3(INT64 a, INT64 b)
{
const int bits_in_dword_m1 = (int)(sizeof(INT64) * CHAR_BIT) - 1;
INT64 s = b >> bits_in_dword_m1; // s = b < 0 ? -1 : 0
b = (b ^ s) - s; // negate if s == -1
s = a >> bits_in_dword_m1; // s = a < 0 ? -1 : 0
a = (a ^ s) - s; // negate if s == -1
INT64 r;
__udivmoddi4(a, b, (UINT64*)&r);
return (r ^ s) - s; // negate if s == -1
}

54
ArmPkg/Library/CompilerIntrinsicsLib/Arm/modsi3.S
View File

@ -1,27 +1,27 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
.text
.align 2
GCC_ASM_EXPORT(__modsi3)
ASM_PFX(__modsi3):
stmfd sp!, {r4, r5, r7, lr}
add r7, sp, #8
mov r5, r0
mov r4, r1
bl ___divsi3
mul r0, r4, r0
rsb r0, r0, r5
ldmfd sp!, {r4, r5, r7, pc}
#------------------------------------------------------------------------------
#
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
.text
.align 2
GCC_ASM_EXPORT(__modsi3)
ASM_PFX(__modsi3):
stmfd sp!, {r4, r5, r7, lr}
add r7, sp, #8
mov r5, r0
mov r4, r1
bl ___divsi3
mul r0, r4, r0
rsb r0, r0, r5
ldmfd sp!, {r4, r5, r7, pc}

140
ArmPkg/Library/CompilerIntrinsicsLib/Arm/modsi3.c
View File

@ -1,70 +1,70 @@
/** @file
Compiler intrinsic for 32-bit mod, ported from LLVM code.
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
/**
University of Illinois/NCSA
Open Source License
Copyright (c) 2003-2008 University of Illinois at Urbana-Champaign.
All rights reserved.
Developed by:
LLVM Team
University of Illinois at Urbana-Champaign
http://llvm.org
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal with
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimers.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimers in the
documentation and/or other materials provided with the distribution.
* Neither the names of the LLVM Team, University of Illinois at
Urbana-Champaign, nor the names of its contributors may be used to
endorse or promote products derived from this Software without specific
prior written permission.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
SOFTWARE.
**/
#include "Llvm_int_lib.h"
// Returns: a % b
INT32
__modsi3(INT32 a, INT32 b)
{
return a - (a / b) * b;
}
/** @file
Compiler intrinsic for 32-bit mod, ported from LLVM code.
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
/**
University of Illinois/NCSA
Open Source License
Copyright (c) 2003-2008 University of Illinois at Urbana-Champaign.
All rights reserved.
Developed by:
LLVM Team
University of Illinois at Urbana-Champaign
http://llvm.org
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal with
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimers.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimers in the
documentation and/or other materials provided with the distribution.
* Neither the names of the LLVM Team, University of Illinois at
Urbana-Champaign, nor the names of its contributors may be used to
endorse or promote products derived from this Software without specific
prior written permission.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
SOFTWARE.
**/
#include "Llvm_int_lib.h"
// Returns: a % b
INT32
__modsi3(INT32 a, INT32 b)
{
return a - (a / b) * b;
}

116
ArmPkg/Library/CompilerIntrinsicsLib/Arm/muldi3.S
View File

@ -1,58 +1,58 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
.text
.align 2
GCC_ASM_EXPORT(__muldi3)
ASM_PFX(__muldi3):
stmfd sp!, {r4, r5, r6, r7, lr}
add r7, sp, #12
stmfd sp!, {r8, r10, r11}
ldr r11, L4
mov r4, r0, lsr #16
and r8, r0, r11
and ip, r2, r11
mul lr, ip, r8
mul ip, r4, ip
sub sp, sp, #8
add r10, ip, lr, lsr #16
and ip, r10, r11
and lr, lr, r11
mov r6, r2, lsr #16
str r4, [sp, #4]
add r4, lr, ip, asl #16
mul ip, r8, r6
mov r5, r10, lsr #16
add r10, ip, r4, lsr #16
and ip, r10, r11
and lr, r4, r11
add r4, lr, ip, asl #16
mul r0, r3, r0
add ip, r5, r10, lsr #16
ldr r5, [sp, #4]
mla r0, r2, r1, r0
mla r5, r6, r5, ip
mov r10, r4
add r11, r0, r5
mov r1, r11
mov r0, r4
sub sp, r7, #24
ldmfd sp!, {r8, r10, r11}
ldmfd sp!, {r4, r5, r6, r7, pc}
.p2align 2
L5:
.align 2
L4:
.long 65535
#------------------------------------------------------------------------------
#
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
.text
.align 2
GCC_ASM_EXPORT(__muldi3)
ASM_PFX(__muldi3):
stmfd sp!, {r4, r5, r6, r7, lr}
add r7, sp, #12
stmfd sp!, {r8, r10, r11}
ldr r11, L4
mov r4, r0, lsr #16
and r8, r0, r11
and ip, r2, r11
mul lr, ip, r8
mul ip, r4, ip
sub sp, sp, #8
add r10, ip, lr, lsr #16
and ip, r10, r11
and lr, lr, r11
mov r6, r2, lsr #16
str r4, [sp, #4]
add r4, lr, ip, asl #16
mul ip, r8, r6
mov r5, r10, lsr #16
add r10, ip, r4, lsr #16
and ip, r10, r11
and lr, r4, r11
add r4, lr, ip, asl #16
mul r0, r3, r0
add ip, r5, r10, lsr #16
ldr r5, [sp, #4]
mla r0, r2, r1, r0
mla r5, r6, r5, ip
mov r10, r4
add r11, r0, r5
mov r1, r11
mov r0, r4
sub sp, r7, #24
ldmfd sp!, {r8, r10, r11}
ldmfd sp!, {r4, r5, r6, r7, pc}
.p2align 2
L5:
.align 2
L4:
.long 65535

196
ArmPkg/Library/CompilerIntrinsicsLib/Arm/muldi3.c
View File

@ -1,98 +1,98 @@
/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
/**
University of Illinois/NCSA
Open Source License
Copyright (c) 2003-2008 University of Illinois at Urbana-Champaign.
All rights reserved.
Developed by:
LLVM Team
University of Illinois at Urbana-Champaign
http://llvm.org
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal with
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimers.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimers in the
documentation and/or other materials provided with the distribution.
* Neither the names of the LLVM Team, University of Illinois at
Urbana-Champaign, nor the names of its contributors may be used to
endorse or promote products derived from this Software without specific
prior written permission.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
SOFTWARE.
**/
#include <Base.h>
#include "Llvm_int_lib.h"
// Returns: a * b
static
INT64
__muldsi3(UINT32 a, UINT32 b)
{
dwords r;
const int bits_in_word_2 = (int)(sizeof(INT32) * CHAR_BIT) / 2;
const UINT32 lower_mask = (UINT32)~0 >> bits_in_word_2;
r.low = (a & lower_mask) * (b & lower_mask);
UINT32 t = r.low >> bits_in_word_2;
r.low &= lower_mask;
t += (a >> bits_in_word_2) * (b & lower_mask);
r.low += (t & lower_mask) << bits_in_word_2;
r.high = t >> bits_in_word_2;
t = r.low >> bits_in_word_2;
r.low &= lower_mask;
t += (b >> bits_in_word_2) * (a & lower_mask);
r.low += (t & lower_mask) << bits_in_word_2;
r.high += t >> bits_in_word_2;
r.high += (a >> bits_in_word_2) * (b >> bits_in_word_2);
return r.all;
}
// Returns: a * b
INT64
__muldi3(INT64 a, INT64 b)
{
dwords x;
x.all = a;
dwords y;
y.all = b;
dwords r;
r.all = __muldsi3(x.low, y.low);
r.high += x.high * y.low + x.low * y.high;
return r.all;
}
/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
/**
University of Illinois/NCSA
Open Source License
Copyright (c) 2003-2008 University of Illinois at Urbana-Champaign.
All rights reserved.
Developed by:
LLVM Team
University of Illinois at Urbana-Champaign
http://llvm.org
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal with
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimers.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimers in the
documentation and/or other materials provided with the distribution.
* Neither the names of the LLVM Team, University of Illinois at
Urbana-Champaign, nor the names of its contributors may be used to
endorse or promote products derived from this Software without specific
prior written permission.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
SOFTWARE.
**/
#include <Base.h>
#include "Llvm_int_lib.h"
// Returns: a * b
static
INT64
__muldsi3(UINT32 a, UINT32 b)
{
dwords r;
const int bits_in_word_2 = (int)(sizeof(INT32) * CHAR_BIT) / 2;
const UINT32 lower_mask = (UINT32)~0 >> bits_in_word_2;
r.low = (a & lower_mask) * (b & lower_mask);
UINT32 t = r.low >> bits_in_word_2;
r.low &= lower_mask;
t += (a >> bits_in_word_2) * (b & lower_mask);
r.low += (t & lower_mask) << bits_in_word_2;
r.high = t >> bits_in_word_2;
t = r.low >> bits_in_word_2;
r.low &= lower_mask;
t += (b >> bits_in_word_2) * (a & lower_mask);
r.low += (t & lower_mask) << bits_in_word_2;
r.high += t >> bits_in_word_2;
r.high += (a >> bits_in_word_2) * (b >> bits_in_word_2);
return r.all;
}
// Returns: a * b
INT64
__muldi3(INT64 a, INT64 b)
{
dwords x;
x.all = a;
dwords y;
y.all = b;
dwords r;
r.all = __muldsi3(x.low, y.low);
r.high += x.high * y.low + x.low * y.high;
return r.all;
}

98
ArmPkg/Library/CompilerIntrinsicsLib/Arm/mullu.asm
View File

@ -1,49 +1,49 @@
//------------------------------------------------------------------------------
//
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
//------------------------------------------------------------------------------
EXPORT __ARM_ll_mullu
EXPORT __aeabi_lmul
AREA Math, CODE, READONLY
;
;INT64
;EFIAPI
;__aeabi_lmul (
; IN INT64 Multiplicand
; IN INT32 Multiplier
; );
;
__ARM_ll_mullu
mov r3, #0
// Make upper part of INT64 Multiplier 0 and use __aeabi_lmul
;
;INT64
;EFIAPI
;__aeabi_lmul (
; IN INT64 Multiplicand
; IN INT64 Multiplier
; );
;
__aeabi_lmul
stmdb sp!, {lr}
mov lr, r0
umull r0, ip, r2, lr
mla r1, r2, r1, ip
mla r1, r3, lr, r1
ldmia sp!, {pc}
END
//------------------------------------------------------------------------------
//
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
//------------------------------------------------------------------------------
EXPORT __ARM_ll_mullu
EXPORT __aeabi_lmul
AREA Math, CODE, READONLY
;
;INT64
;EFIAPI
;__aeabi_lmul (
; IN INT64 Multiplicand
; IN INT32 Multiplier
; );
;
__ARM_ll_mullu
mov r3, #0
// Make upper part of INT64 Multiplier 0 and use __aeabi_lmul
;
;INT64
;EFIAPI
;__aeabi_lmul (
; IN INT64 Multiplicand
; IN INT64 Multiplier
; );
;
__aeabi_lmul
stmdb sp!, {lr}
mov lr, r0
umull r0, ip, r2, lr
mla r1, r2, r1, ip
mla r1, r3, lr, r1
ldmia sp!, {pc}
END

58
ArmPkg/Library/CompilerIntrinsicsLib/Arm/switch.asm
View File

@ -1,29 +1,29 @@
///------------------------------------------------------------------------------
//
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
//------------------------------------------------------------------------------
EXPORT __ARM_switch8
AREA ArmSwitch, CODE, READONLY
__ARM_switch8
LDRB r12,[lr,#-1]
CMP r3,r12
LDRBCC r3,[lr,r3]
LDRBCS r3,[lr,r12]
ADD r12,lr,r3,LSL #1
BX r12
END
///------------------------------------------------------------------------------
//
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
//------------------------------------------------------------------------------
EXPORT __ARM_switch8
AREA ArmSwitch, CODE, READONLY
__ARM_switch8
LDRB r12,[lr,#-1]
CMP r3,r12
LDRBCC r3,[lr,r3]
LDRBCS r3,[lr,r12]
ADD r12,lr,r3,LSL #1
BX r12
END

62
ArmPkg/Library/CompilerIntrinsicsLib/Arm/switch16.S
View File

@ -1,31 +1,31 @@
#/** @file
# Compiler intrinsic for ARM compiler
#
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.;
#
#**/
#
.text
.p2align 2
GCC_ASM_EXPORT(__switch16)
ASM_PFX(__switch16):
ldrh ip, [lr, #-1]
cmp r0, ip
add r0, lr, r0, lsl #1
ldrccsh r0, [r0, #1]
add ip, lr, ip, lsl #1
ldrcssh r0, [ip, #1]
add ip, lr, r0, lsl #1
bx ip
#/** @file
# Compiler intrinsic for ARM compiler
#
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.;
#
#**/
#
.text
.p2align 2
GCC_ASM_EXPORT(__switch16)
ASM_PFX(__switch16):
ldrh ip, [lr, #-1]
cmp r0, ip
add r0, lr, r0, lsl #1
ldrccsh r0, [r0, #1]
add ip, lr, ip, lsl #1
ldrcssh r0, [ip, #1]
add ip, lr, r0, lsl #1
bx ip

60
ArmPkg/Library/CompilerIntrinsicsLib/Arm/switch32.S
View File

@ -1,30 +1,30 @@
#/** @file
# Compiler intrinsic for ARM compiler
#
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.;
#
#**/
#
.text
.p2align 2
GCC_ASM_EXPORT(__switch32)
ASM_PFX(__switch32):
ldr ip, [lr, #-1]
cmp r0, ip
add r0, lr, r0, lsl #2
ldrcc r0, [r0, #3]
add ip, lr, ip, lsl #2
ldrcs r0, [ip, #3]
add ip, lr, r0
bx ip
#/** @file
# Compiler intrinsic for ARM compiler
#
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.;
#
#**/
#
.text
.p2align 2
GCC_ASM_EXPORT(__switch32)
ASM_PFX(__switch32):
ldr ip, [lr, #-1]
cmp r0, ip
add r0, lr, r0, lsl #2
ldrcc r0, [r0, #3]
add ip, lr, ip, lsl #2
ldrcs r0, [ip, #3]
add ip, lr, r0
bx ip

56
ArmPkg/Library/CompilerIntrinsicsLib/Arm/switch8.S
View File

@ -1,28 +1,28 @@
#/** @file
# Compiler intrinsic for ARM compiler
#
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http)://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.;
#
#**/
#
.text
.p2align 2
GCC_ASM_EXPORT(__switch8)
ASM_PFX(__switch8):
ldrb ip, [lr, #-1]
cmp r0, ip
ldrccsb r0, [lr, r0]
ldrcssb r0, [lr, ip]
add ip, lr, r0, lsl #1
bx ip
#/** @file
# Compiler intrinsic for ARM compiler
#
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http)://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.;
#
#**/
#
.text
.p2align 2
GCC_ASM_EXPORT(__switch8)
ASM_PFX(__switch8):
ldrb ip, [lr, #-1]
cmp r0, ip
ldrccsb r0, [lr, r0]
ldrcssb r0, [lr, ip]
add ip, lr, r0, lsl #1
bx ip

58
ArmPkg/Library/CompilerIntrinsicsLib/Arm/switchu8.S
View File

@ -1,29 +1,29 @@
#/** @file
# Compiler intrinsic for ARM compiler
#
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http)://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.;
#
#**/
#
.text
.p2align 2
GCC_ASM_EXPORT(__switchu8)
ASM_PFX(__switchu8):
ldrb ip,[lr,#-1]
cmp r0,ip
ldrccb r0,[lr,r0]
ldrcsb r0,[lr,ip]
add ip,lr,r0,LSL #1
bx ip
#/** @file
# Compiler intrinsic for ARM compiler
#
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http)://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.;
#
#**/
#
.text
.p2align 2
GCC_ASM_EXPORT(__switchu8)
ASM_PFX(__switchu8):
ldrb ip,[lr,#-1]
cmp r0,ip
ldrccb r0,[lr,r0]
ldrcsb r0,[lr,ip]
add ip,lr,r0,LSL #1
bx ip

76
ArmPkg/Library/CompilerIntrinsicsLib/Arm/ucmpdi2.S
View File

@ -1,38 +1,38 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
.text
.align 2
GCC_ASM_EXPORT(__ucmpdi2)
ASM_PFX(__ucmpdi2):
stmfd sp!, {r4, r5, r8, lr}
cmp r1, r3
mov r8, r0
mov r4, r2
mov r5, r3
bcc L2
bhi L4
cmp r0, r2
bcc L2
movls r0, #1
bls L8
b L4
L2:
mov r0, #0
b L8
L4:
mov r0, #2
L8:
ldmfd sp!, {r4, r5, r8, pc}
#------------------------------------------------------------------------------
#
# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
.text
.align 2
GCC_ASM_EXPORT(__ucmpdi2)
ASM_PFX(__ucmpdi2):
stmfd sp!, {r4, r5, r8, lr}
cmp r1, r3
mov r8, r0
mov r4, r2
mov r5, r3
bcc L2
bhi L4
cmp r0, r2
bcc L2
movls r0, #1
bls L8
b L4
L2:
mov r0, #0
b L8
L4:
mov r0, #2
L8:
ldmfd sp!, {r4, r5, r8, pc}

164
ArmPkg/Library/CompilerIntrinsicsLib/Arm/ucmpdi2.c
View File

@ -1,82 +1,82 @@
/** @file
Compiler intrinsic for 64-bit compare, ported from LLVM code.
Copyright (c) 2008-2009, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
/**
University of Illinois/NCSA
Open Source License
Copyright (c) 2003-2008 University of Illinois at Urbana-Champaign.
All rights reserved.
Developed by:
LLVM Team
University of Illinois at Urbana-Champaign
http://llvm.org
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal with
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimers.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimers in the
documentation and/or other materials provided with the distribution.
* Neither the names of the LLVM Team, University of Illinois at
Urbana-Champaign, nor the names of its contributors may be used to
endorse or promote products derived from this Software without specific
prior written permission.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
SOFTWARE.
**/
#include "Llvm_int_lib.h"
// Returns: if (a < b) returns 0
// if (a == b) returns 1
// if (a > b) returns 2
UINT32
__ucmpdi2(UINT64 a, UINT64 b)
{
udwords x;
x.all = a;
udwords y;
y.all = b;
if (x.high < y.high)
return 0;
if (x.high > y.high)
return 2;
if (x.low < y.low)
return 0;
if (x.low > y.low)
return 2;
return 1;
}
/** @file
Compiler intrinsic for 64-bit compare, ported from LLVM code.
Copyright (c) 2008-2009, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
/**
University of Illinois/NCSA
Open Source License
Copyright (c) 2003-2008 University of Illinois at Urbana-Champaign.
All rights reserved.
Developed by:
LLVM Team
University of Illinois at Urbana-Champaign
http://llvm.org
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal with
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimers.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimers in the
documentation and/or other materials provided with the distribution.
* Neither the names of the LLVM Team, University of Illinois at
Urbana-Champaign, nor the names of its contributors may be used to
endorse or promote products derived from this Software without specific
prior written permission.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
SOFTWARE.
**/
#include "Llvm_int_lib.h"
// Returns: if (a < b) returns 0
// if (a == b) returns 1
// if (a > b) returns 2
UINT32
__ucmpdi2(UINT64 a, UINT64 b)
{
udwords x;
x.all = a;
udwords y;
y.all = b;
if (x.high < y.high)
return 0;
if (x.high > y.high)
return 2;
if (x.low < y.low)
return 0;
if (x.low > y.low)
return 2;
return 1;
}

54
ArmPkg/Library/CompilerIntrinsicsLib/Arm/udivdi3.S
View File

@ -1,27 +1,27 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
.text
.align 2
GCC_ASM_EXPORT(__udivdi3)
ASM_PFX(__udivdi3):
stmfd sp!, {r7, lr}
add r7, sp, #0
sub sp, sp, #8
mov ip, #0
str ip, [sp, #0]
bl ASM_PFX(__udivmoddi4)
sub sp, r7, #0
ldmfd sp!, {r7, pc}
#------------------------------------------------------------------------------
#
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
.text
.align 2
GCC_ASM_EXPORT(__udivdi3)
ASM_PFX(__udivdi3):
stmfd sp!, {r7, lr}
add r7, sp, #0
sub sp, sp, #8
mov ip, #0
str ip, [sp, #0]
bl ASM_PFX(__udivmoddi4)
sub sp, r7, #0
ldmfd sp!, {r7, pc}

142
ArmPkg/Library/CompilerIntrinsicsLib/Arm/udivdi3.c
View File

@ -1,71 +1,71 @@
/** @file
Compiler intrinsic for 64-bit unisigned div, ported from LLVM code.
Copyright (c) 2008-2009, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
/**
University of Illinois/NCSA
Open Source License
Copyright (c) 2003-2008 University of Illinois at Urbana-Champaign.
All rights reserved.
Developed by:
LLVM Team
University of Illinois at Urbana-Champaign
http://llvm.org
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal with
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimers.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimers in the
documentation and/or other materials provided with the distribution.
* Neither the names of the LLVM Team, University of Illinois at
Urbana-Champaign, nor the names of its contributors may be used to
endorse or promote products derived from this Software without specific
prior written permission.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
SOFTWARE.
**/
#include "Llvm_int_lib.h"
UINT64 __udivmoddi4 (UINT64 a, UINT64 b, UINT64 *rem);
// Returns: a / b
UINT64
__udivdi3(UINT64 a, UINT64 b)
{
return __udivmoddi4(a, b, 0);
}
/** @file
Compiler intrinsic for 64-bit unisigned div, ported from LLVM code.
Copyright (c) 2008-2009, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
/**
University of Illinois/NCSA
Open Source License
Copyright (c) 2003-2008 University of Illinois at Urbana-Champaign.
All rights reserved.
Developed by:
LLVM Team
University of Illinois at Urbana-Champaign
http://llvm.org
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal with
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimers.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimers in the
documentation and/or other materials provided with the distribution.
* Neither the names of the LLVM Team, University of Illinois at
Urbana-Champaign, nor the names of its contributors may be used to
endorse or promote products derived from this Software without specific
prior written permission.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
SOFTWARE.
**/
#include "Llvm_int_lib.h"
UINT64 __udivmoddi4 (UINT64 a, UINT64 b, UINT64 *rem);
// Returns: a / b
UINT64
__udivdi3(UINT64 a, UINT64 b)
{
return __udivmoddi4(a, b, 0);
}

484
ArmPkg/Library/CompilerIntrinsicsLib/Arm/udivmoddi4.S
View File

@ -1,242 +1,242 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
.text
.align 2
GCC_ASM_EXPORT(__udivmoddi4)
ASM_PFX(__udivmoddi4):
stmfd sp!, {r4, r5, r6, r7, lr}
add r7, sp, #12
stmfd sp!, {r10, r11}
sub sp, sp, #20
stmia sp, {r2-r3}
ldr r6, [sp, #48]
orrs r2, r2, r3
mov r10, r0
mov r11, r1
beq L2
subs ip, r1, #0
bne L4
cmp r3, #0
bne L6
cmp r6, #0
beq L8
mov r1, r2
bl ASM_PFX(__umodsi3)
mov r1, #0
stmia r6, {r0-r1}
L8:
ldr r1, [sp, #0]
mov r0, r10
b L45
L6:
cmp r6, #0
movne r1, #0
stmneia r6, {r0-r1}
b L2
L4:
ldr r1, [sp, #0]
cmp r1, #0
bne L12
ldr r2, [sp, #4]
cmp r2, #0
bne L14
cmp r6, #0
beq L16
mov r1, r2
mov r0, r11
bl ASM_PFX(__umodsi3)
mov r1, #0
stmia r6, {r0-r1}
L16:
ldr r1, [sp, #4]
mov r0, r11
L45:
bl ASM_PFX(__udivsi3)
L46:
mov r10, r0
mov r11, #0
b L10
L14:
subs r1, r0, #0
bne L18
cmp r6, #0
beq L16
ldr r1, [sp, #4]
mov r0, r11
bl ASM_PFX(__umodsi3)
mov r4, r10
mov r5, r0
stmia r6, {r4-r5}
b L16
L18:
sub r3, r2, #1
tst r2, r3
bne L22
cmp r6, #0
movne r4, r0
andne r5, ip, r3
stmneia r6, {r4-r5}
L24:
rsb r3, r2, #0
and r3, r2, r3
clz r3, r3
rsb r3, r3, #31
mov r0, ip, lsr r3
b L46
L22:
clz r2, r2
clz r3, ip
rsb r3, r3, r2
cmp r3, #30
bhi L48
rsb r2, r3, #31
add lr, r3, #1
mov r3, r1, asl r2
str r3, [sp, #12]
mov r3, r1, lsr lr
ldr r0, [sp, #0]
mov r5, ip, lsr lr
orr r4, r3, ip, asl r2
str r0, [sp, #8]
b L29
L12:
ldr r3, [sp, #4]
cmp r3, #0
bne L30
sub r3, r1, #1
tst r1, r3
bne L32
cmp r6, #0
andne r3, r3, r0
movne r2, r3
movne r3, #0
stmneia r6, {r2-r3}
L34:
cmp r1, #1
beq L10
rsb r3, r1, #0
and r3, r1, r3
clz r3, r3
rsb r0, r3, #31
mov r1, ip, lsr r0
rsb r3, r0, #32
mov r0, r10, lsr r0
orr ip, r0, ip, asl r3
str r1, [sp, #12]
str ip, [sp, #8]
ldrd r10, [sp, #8]
b L10
L32:
clz r2, r1
clz r3, ip
rsb r3, r3, r2
rsb r4, r3, #31
mov r2, r0, asl r4
mvn r1, r3
and r2, r2, r1, asr #31
add lr, r3, #33
str r2, [sp, #8]
add r2, r3, #1
mov r3, r3, asr #31
and r0, r3, r0, asl r1
mov r3, r10, lsr r2
orr r3, r3, ip, asl r4
and r3, r3, r1, asr #31
orr r0, r0, r3
mov r3, ip, lsr lr
str r0, [sp, #12]
mov r0, r10, lsr lr
and r5, r3, r2, asr #31
rsb r3, lr, #31
mov r3, r3, asr #31
orr r0, r0, ip, asl r1
and r3, r3, ip, lsr r2
and r0, r0, r2, asr #31
orr r4, r3, r0
b L29
L30:
clz r2, r3
clz r3, ip
rsb r3, r3, r2
cmp r3, #31
bls L37
L48:
cmp r6, #0
stmneia r6, {r10-r11}
b L2
L37:
rsb r1, r3, #31
mov r0, r0, asl r1
add lr, r3, #1
mov r2, #0
str r0, [sp, #12]
mov r0, r10, lsr lr
str r2, [sp, #8]
sub r2, r3, #31
and r0, r0, r2, asr #31
mov r3, ip, lsr lr
orr r4, r0, ip, asl r1
and r5, r3, r2, asr #31
L29:
mov ip, #0
mov r10, ip
b L40
L41:
ldr r1, [sp, #12]
ldr r2, [sp, #8]
mov r3, r4, lsr #31
orr r5, r3, r5, asl #1
mov r3, r1, lsr #31
orr r4, r3, r4, asl #1
mov r3, r2, lsr #31
orr r0, r3, r1, asl #1
orr r1, ip, r2, asl #1
ldmia sp, {r2-r3}
str r0, [sp, #12]
subs r2, r2, r4
sbc r3, r3, r5
str r1, [sp, #8]
subs r0, r2, #1
sbc r1, r3, #0
mov r2, r1, asr #31
ldmia sp, {r0-r1}
mov r3, r2
and ip, r2, #1
and r3, r3, r1
and r2, r2, r0
subs r4, r4, r2
sbc r5, r5, r3
add r10, r10, #1
L40:
cmp r10, lr
bne L41
ldrd r0, [sp, #8]
adds r0, r0, r0
adc r1, r1, r1
cmp r6, #0
orr r10, r0, ip
mov r11, r1
stmneia r6, {r4-r5}
b L10
L2:
mov r10, #0
mov r11, #0
L10:
mov r0, r10
mov r1, r11
sub sp, r7, #20
ldmfd sp!, {r10, r11}
ldmfd sp!, {r4, r5, r6, r7, pc}
#------------------------------------------------------------------------------
#
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
.text
.align 2
GCC_ASM_EXPORT(__udivmoddi4)
ASM_PFX(__udivmoddi4):
stmfd sp!, {r4, r5, r6, r7, lr}
add r7, sp, #12
stmfd sp!, {r10, r11}
sub sp, sp, #20
stmia sp, {r2-r3}
ldr r6, [sp, #48]
orrs r2, r2, r3
mov r10, r0
mov r11, r1
beq L2
subs ip, r1, #0
bne L4
cmp r3, #0
bne L6
cmp r6, #0
beq L8
mov r1, r2
bl ASM_PFX(__umodsi3)
mov r1, #0
stmia r6, {r0-r1}
L8:
ldr r1, [sp, #0]
mov r0, r10
b L45
L6:
cmp r6, #0
movne r1, #0
stmneia r6, {r0-r1}
b L2
L4:
ldr r1, [sp, #0]
cmp r1, #0
bne L12
ldr r2, [sp, #4]
cmp r2, #0
bne L14
cmp r6, #0
beq L16
mov r1, r2
mov r0, r11
bl ASM_PFX(__umodsi3)
mov r1, #0
stmia r6, {r0-r1}
L16:
ldr r1, [sp, #4]
mov r0, r11
L45:
bl ASM_PFX(__udivsi3)
L46:
mov r10, r0
mov r11, #0
b L10
L14:
subs r1, r0, #0
bne L18
cmp r6, #0
beq L16
ldr r1, [sp, #4]
mov r0, r11
bl ASM_PFX(__umodsi3)
mov r4, r10
mov r5, r0
stmia r6, {r4-r5}
b L16
L18:
sub r3, r2, #1
tst r2, r3
bne L22
cmp r6, #0
movne r4, r0
andne r5, ip, r3
stmneia r6, {r4-r5}
L24:
rsb r3, r2, #0
and r3, r2, r3
clz r3, r3
rsb r3, r3, #31
mov r0, ip, lsr r3
b L46
L22:
clz r2, r2
clz r3, ip
rsb r3, r3, r2
cmp r3, #30
bhi L48
rsb r2, r3, #31
add lr, r3, #1
mov r3, r1, asl r2
str r3, [sp, #12]
mov r3, r1, lsr lr
ldr r0, [sp, #0]
mov r5, ip, lsr lr
orr r4, r3, ip, asl r2
str r0, [sp, #8]
b L29
L12:
ldr r3, [sp, #4]
cmp r3, #0
bne L30
sub r3, r1, #1
tst r1, r3
bne L32
cmp r6, #0
andne r3, r3, r0
movne r2, r3
movne r3, #0
stmneia r6, {r2-r3}
L34:
cmp r1, #1
beq L10
rsb r3, r1, #0
and r3, r1, r3
clz r3, r3
rsb r0, r3, #31
mov r1, ip, lsr r0
rsb r3, r0, #32
mov r0, r10, lsr r0
orr ip, r0, ip, asl r3
str r1, [sp, #12]
str ip, [sp, #8]
ldrd r10, [sp, #8]
b L10
L32:
clz r2, r1
clz r3, ip
rsb r3, r3, r2
rsb r4, r3, #31
mov r2, r0, asl r4
mvn r1, r3
and r2, r2, r1, asr #31
add lr, r3, #33
str r2, [sp, #8]
add r2, r3, #1
mov r3, r3, asr #31
and r0, r3, r0, asl r1
mov r3, r10, lsr r2
orr r3, r3, ip, asl r4
and r3, r3, r1, asr #31
orr r0, r0, r3
mov r3, ip, lsr lr
str r0, [sp, #12]
mov r0, r10, lsr lr
and r5, r3, r2, asr #31
rsb r3, lr, #31
mov r3, r3, asr #31
orr r0, r0, ip, asl r1
and r3, r3, ip, lsr r2
and r0, r0, r2, asr #31
orr r4, r3, r0
b L29
L30:
clz r2, r3
clz r3, ip
rsb r3, r3, r2
cmp r3, #31
bls L37
L48:
cmp r6, #0
stmneia r6, {r10-r11}
b L2
L37:
rsb r1, r3, #31
mov r0, r0, asl r1
add lr, r3, #1
mov r2, #0
str r0, [sp, #12]
mov r0, r10, lsr lr
str r2, [sp, #8]
sub r2, r3, #31
and r0, r0, r2, asr #31
mov r3, ip, lsr lr
orr r4, r0, ip, asl r1
and r5, r3, r2, asr #31
L29:
mov ip, #0
mov r10, ip
b L40
L41:
ldr r1, [sp, #12]
ldr r2, [sp, #8]
mov r3, r4, lsr #31
orr r5, r3, r5, asl #1
mov r3, r1, lsr #31
orr r4, r3, r4, asl #1
mov r3, r2, lsr #31
orr r0, r3, r1, asl #1
orr r1, ip, r2, asl #1
ldmia sp, {r2-r3}
str r0, [sp, #12]
subs r2, r2, r4
sbc r3, r3, r5
str r1, [sp, #8]
subs r0, r2, #1
sbc r1, r3, #0
mov r2, r1, asr #31
ldmia sp, {r0-r1}
mov r3, r2
and ip, r2, #1
and r3, r3, r1
and r2, r2, r0
subs r4, r4, r2
sbc r5, r5, r3
add r10, r10, #1
L40:
cmp r10, lr
bne L41
ldrd r0, [sp, #8]
adds r0, r0, r0
adc r1, r1, r1
cmp r6, #0
orr r10, r0, ip
mov r11, r1
stmneia r6, {r4-r5}
b L10
L2:
mov r10, #0
mov r11, #0
L10:
mov r0, r10
mov r1, r11
sub sp, r7, #20
ldmfd sp!, {r10, r11}
ldmfd sp!, {r4, r5, r6, r7, pc}

574
ArmPkg/Library/CompilerIntrinsicsLib/Arm/udivmoddi4.c
View File

@ -1,287 +1,287 @@
/** @file
Compiler intrinsic for 64-bit compare, ported from LLVM code.
Copyright (c) 2008-2009, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
/**
University of Illinois/NCSA
Open Source License
Copyright (c) 2003-2008 University of Illinois at Urbana-Champaign.
All rights reserved.
Developed by:
LLVM Team
University of Illinois at Urbana-Champaign
http://llvm.org
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal with
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimers.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimers in the
documentation and/or other materials provided with the distribution.
* Neither the names of the LLVM Team, University of Illinois at
Urbana-Champaign, nor the names of its contributors may be used to
endorse or promote products derived from this Software without specific
prior written permission.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
SOFTWARE.
**/
#include "Llvm_int_lib.h"
// Effects: if rem != 0, *rem = a % b
// Returns: a / b
// Translated from Figure 3-40 of The PowerPC Compiler Writer's Guide
UINT64
__udivmoddi4 (UINT64 a, UINT64 b, UINT64* rem)
{
const unsigned n_uword_bits = sizeof(UINT32) * CHAR_BIT;
const unsigned n_udword_bits = sizeof(UINT64) * CHAR_BIT;
udwords n;
n.all = a;
udwords d;
d.all = b;
udwords q;
udwords r;
unsigned sr;
if (b == 0) {
// ASSERT (FALSE);
return 0;
}
// special cases, X is unknown, K != 0
if (n.high == 0)
{
if (d.high == 0)
{
// 0 X
// ---
// 0 X
if (rem)
*rem = n.low % d.low;
return n.low / d.low;
}
// 0 X
// ---
// K X
if (rem)
*rem = n.low;
return 0;
}
// n.high != 0
if (d.low == 0)
{
if (d.high == 0)
{
// K X
// ---
// 0 0
if (rem)
*rem = n.high % d.low;
return n.high / d.low;
}
// d.high != 0
if (n.low == 0)
{
// K 0
// ---
// K 0
if (rem)
{
r.high = n.high % d.high;
r.low = 0;
*rem = r.all;
}
return n.high / d.high;
}
// K K
// ---
// K 0
if ((d.high & (d.high - 1)) == 0) // if d is a power of 2
{
if (rem)
{
r.low = n.low;
r.high = n.high & (d.high - 1);
*rem = r.all;
}
return n.high >> COUNT_TRAILING_ZEROS(d.high);
}
// K K
// ---
// K 0
sr = COUNT_LEADING_ZEROS(d.high) - COUNT_LEADING_ZEROS(n.high);
// 0 <= sr <= n_uword_bits - 2 or sr large
if (sr > n_uword_bits - 2)
{
if (rem)
*rem = n.all;
return 0;
}
++sr;
// 1 <= sr <= n_uword_bits - 1
// q.all = n.all << (n_udword_bits - sr);
q.low = 0;
q.high = n.low << (n_uword_bits - sr);
// r.all = n.all >> sr;
r.high = n.high >> sr;
r.low = (n.high << (n_uword_bits - sr)) | (n.low >> sr);
}
else // d.low != 0
{
if (d.high == 0)
{
// K X
// ---
// 0 K
if ((d.low & (d.low - 1)) == 0) // if d is a power of 2
{
if (rem)
*rem = n.low & (d.low - 1);
if (d.low == 1)
return n.all;
unsigned sr = COUNT_TRAILING_ZEROS(d.low);
q.high = n.high >> sr;
q.low = (n.high << (n_uword_bits - sr)) | (n.low >> sr);
return q.all;
}
// K X
// ---
// 0 K
sr = 1 + n_uword_bits + COUNT_LEADING_ZEROS(d.low) - COUNT_LEADING_ZEROS(n.high);
// 2 <= sr <= n_udword_bits - 1
// q.all = n.all << (n_udword_bits - sr);
// r.all = n.all >> sr;
// if (sr == n_uword_bits)
// {
// q.low = 0;
// q.high = n.low;
// r.high = 0;
// r.low = n.high;
// }
// else if (sr < n_uword_bits) // 2 <= sr <= n_uword_bits - 1
// {
// q.low = 0;
// q.high = n.low << (n_uword_bits - sr);
// r.high = n.high >> sr;
// r.low = (n.high << (n_uword_bits - sr)) | (n.low >> sr);
// }
// else // n_uword_bits + 1 <= sr <= n_udword_bits - 1
// {
// q.low = n.low << (n_udword_bits - sr);
// q.high = (n.high << (n_udword_bits - sr)) |
// (n.low >> (sr - n_uword_bits));
// r.high = 0;
// r.low = n.high >> (sr - n_uword_bits);
// }
q.low = (n.low << (n_udword_bits - sr)) &
((INT32)(n_uword_bits - sr) >> (n_uword_bits-1));
q.high = ((n.low << ( n_uword_bits - sr)) &
((INT32)(sr - n_uword_bits - 1) >> (n_uword_bits-1))) |
(((n.high << (n_udword_bits - sr)) |
(n.low >> (sr - n_uword_bits))) &
((INT32)(n_uword_bits - sr) >> (n_uword_bits-1)));
r.high = (n.high >> sr) &
((INT32)(sr - n_uword_bits) >> (n_uword_bits-1));
r.low = ((n.high >> (sr - n_uword_bits)) &
((INT32)(n_uword_bits - sr - 1) >> (n_uword_bits-1))) |
(((n.high << (n_uword_bits - sr)) |
(n.low >> sr)) &
((INT32)(sr - n_uword_bits) >> (n_uword_bits-1)));
}
else
{
// K X
// ---
// K K
sr = COUNT_LEADING_ZEROS(d.high) - COUNT_LEADING_ZEROS(n.high);
// 0 <= sr <= n_uword_bits - 1 or sr large
if (sr > n_uword_bits - 1)
{
if (rem)
*rem = n.all;
return 0;
}
++sr;
// 1 <= sr <= n_uword_bits
// q.all = n.all << (n_udword_bits - sr);
q.low = 0;
q.high = n.low << (n_uword_bits - sr);
// r.all = n.all >> sr;
// if (sr < n_uword_bits)
// {
// r.high = n.high >> sr;
// r.low = (n.high << (n_uword_bits - sr)) | (n.low >> sr);
// }
// else
// {
// r.high = 0;
// r.low = n.high;
// }
r.high = (n.high >> sr) &
((INT32)(sr - n_uword_bits) >> (n_uword_bits-1));
r.low = (n.high << (n_uword_bits - sr)) |
((n.low >> sr) &
((INT32)(sr - n_uword_bits) >> (n_uword_bits-1)));
}
}
// Not a special case
// q and r are initialized with:
// q.all = n.all << (n_udword_bits - sr);
// r.all = n.all >> sr;
// 1 <= sr <= n_udword_bits - 1
UINT32 carry = 0;
for (; sr > 0; --sr)
{
// r:q = ((r:q) << 1) | carry
r.high = (r.high << 1) | (r.low >> (n_uword_bits - 1));
r.low = (r.low << 1) | (q.high >> (n_uword_bits - 1));
q.high = (q.high << 1) | (q.low >> (n_uword_bits - 1));
q.low = (q.low << 1) | carry;
// carry = 0;
// if (r.all >= d.all)
// {
// r.all -= d.all;
// carry = 1;
// }
const INT64 s = (INT64)(d.all - r.all - 1) >> (n_udword_bits - 1);
carry = s & 1;
r.all -= d.all & s;
}
q.all = (q.all << 1) | carry;
if (rem)
*rem = r.all;
return q.all;
}
/** @file
Compiler intrinsic for 64-bit compare, ported from LLVM code.
Copyright (c) 2008-2009, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
/**
University of Illinois/NCSA
Open Source License
Copyright (c) 2003-2008 University of Illinois at Urbana-Champaign.
All rights reserved.
Developed by:
LLVM Team
University of Illinois at Urbana-Champaign
http://llvm.org
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal with
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimers.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimers in the
documentation and/or other materials provided with the distribution.
* Neither the names of the LLVM Team, University of Illinois at
Urbana-Champaign, nor the names of its contributors may be used to
endorse or promote products derived from this Software without specific
prior written permission.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
SOFTWARE.
**/
#include "Llvm_int_lib.h"
// Effects: if rem != 0, *rem = a % b
// Returns: a / b
// Translated from Figure 3-40 of The PowerPC Compiler Writer's Guide
UINT64
__udivmoddi4 (UINT64 a, UINT64 b, UINT64* rem)
{
const unsigned n_uword_bits = sizeof(UINT32) * CHAR_BIT;
const unsigned n_udword_bits = sizeof(UINT64) * CHAR_BIT;
udwords n;
n.all = a;
udwords d;
d.all = b;
udwords q;
udwords r;
unsigned sr;
if (b == 0) {
// ASSERT (FALSE);
return 0;
}
// special cases, X is unknown, K != 0
if (n.high == 0)
{
if (d.high == 0)
{
// 0 X
// ---
// 0 X
if (rem)
*rem = n.low % d.low;
return n.low / d.low;
}
// 0 X
// ---
// K X
if (rem)
*rem = n.low;
return 0;
}
// n.high != 0
if (d.low == 0)
{
if (d.high == 0)
{
// K X
// ---
// 0 0
if (rem)
*rem = n.high % d.low;
return n.high / d.low;
}
// d.high != 0
if (n.low == 0)
{
// K 0
// ---
// K 0
if (rem)
{
r.high = n.high % d.high;
r.low = 0;
*rem = r.all;
}
return n.high / d.high;
}
// K K
// ---
// K 0
if ((d.high & (d.high - 1)) == 0) // if d is a power of 2
{
if (rem)
{
r.low = n.low;
r.high = n.high & (d.high - 1);
*rem = r.all;
}
return n.high >> COUNT_TRAILING_ZEROS(d.high);
}
// K K
// ---
// K 0
sr = COUNT_LEADING_ZEROS(d.high) - COUNT_LEADING_ZEROS(n.high);
// 0 <= sr <= n_uword_bits - 2 or sr large
if (sr > n_uword_bits - 2)
{
if (rem)
*rem = n.all;
return 0;
}
++sr;
// 1 <= sr <= n_uword_bits - 1
// q.all = n.all << (n_udword_bits - sr);
q.low = 0;
q.high = n.low << (n_uword_bits - sr);
// r.all = n.all >> sr;
r.high = n.high >> sr;
r.low = (n.high << (n_uword_bits - sr)) | (n.low >> sr);
}
else // d.low != 0
{
if (d.high == 0)
{
// K X
// ---
// 0 K
if ((d.low & (d.low - 1)) == 0) // if d is a power of 2
{
if (rem)
*rem = n.low & (d.low - 1);
if (d.low == 1)
return n.all;
unsigned sr = COUNT_TRAILING_ZEROS(d.low);
q.high = n.high >> sr;
q.low = (n.high << (n_uword_bits - sr)) | (n.low >> sr);
return q.all;
}
// K X
// ---
// 0 K
sr = 1 + n_uword_bits + COUNT_LEADING_ZEROS(d.low) - COUNT_LEADING_ZEROS(n.high);
// 2 <= sr <= n_udword_bits - 1
// q.all = n.all << (n_udword_bits - sr);
// r.all = n.all >> sr;
// if (sr == n_uword_bits)
// {
// q.low = 0;
// q.high = n.low;
// r.high = 0;
// r.low = n.high;
// }
// else if (sr < n_uword_bits) // 2 <= sr <= n_uword_bits - 1
// {
// q.low = 0;
// q.high = n.low << (n_uword_bits - sr);
// r.high = n.high >> sr;
// r.low = (n.high << (n_uword_bits - sr)) | (n.low >> sr);
// }
// else // n_uword_bits + 1 <= sr <= n_udword_bits - 1
// {
// q.low = n.low << (n_udword_bits - sr);
// q.high = (n.high << (n_udword_bits - sr)) |
// (n.low >> (sr - n_uword_bits));
// r.high = 0;
// r.low = n.high >> (sr - n_uword_bits);
// }
q.low = (n.low << (n_udword_bits - sr)) &
((INT32)(n_uword_bits - sr) >> (n_uword_bits-1));
q.high = ((n.low << ( n_uword_bits - sr)) &
((INT32)(sr - n_uword_bits - 1) >> (n_uword_bits-1))) |
(((n.high << (n_udword_bits - sr)) |
(n.low >> (sr - n_uword_bits))) &
((INT32)(n_uword_bits - sr) >> (n_uword_bits-1)));
r.high = (n.high >> sr) &
((INT32)(sr - n_uword_bits) >> (n_uword_bits-1));
r.low = ((n.high >> (sr - n_uword_bits)) &
((INT32)(n_uword_bits - sr - 1) >> (n_uword_bits-1))) |
(((n.high << (n_uword_bits - sr)) |
(n.low >> sr)) &
((INT32)(sr - n_uword_bits) >> (n_uword_bits-1)));
}
else
{
// K X
// ---
// K K
sr = COUNT_LEADING_ZEROS(d.high) - COUNT_LEADING_ZEROS(n.high);
// 0 <= sr <= n_uword_bits - 1 or sr large
if (sr > n_uword_bits - 1)
{
if (rem)
*rem = n.all;
return 0;
}
++sr;
// 1 <= sr <= n_uword_bits
// q.all = n.all << (n_udword_bits - sr);
q.low = 0;
q.high = n.low << (n_uword_bits - sr);
// r.all = n.all >> sr;
// if (sr < n_uword_bits)
// {
// r.high = n.high >> sr;
// r.low = (n.high << (n_uword_bits - sr)) | (n.low >> sr);
// }
// else
// {
// r.high = 0;
// r.low = n.high;
// }
r.high = (n.high >> sr) &
((INT32)(sr - n_uword_bits) >> (n_uword_bits-1));
r.low = (n.high << (n_uword_bits - sr)) |
((n.low >> sr) &
((INT32)(sr - n_uword_bits) >> (n_uword_bits-1)));
}
}
// Not a special case
// q and r are initialized with:
// q.all = n.all << (n_udword_bits - sr);
// r.all = n.all >> sr;
// 1 <= sr <= n_udword_bits - 1
UINT32 carry = 0;
for (; sr > 0; --sr)
{
// r:q = ((r:q) << 1) | carry
r.high = (r.high << 1) | (r.low >> (n_uword_bits - 1));
r.low = (r.low << 1) | (q.high >> (n_uword_bits - 1));
q.high = (q.high << 1) | (q.low >> (n_uword_bits - 1));
q.low = (q.low << 1) | carry;
// carry = 0;
// if (r.all >= d.all)
// {
// r.all -= d.all;
// carry = 1;
// }
const INT64 s = (INT64)(d.all - r.all - 1) >> (n_udword_bits - 1);
carry = s & 1;
r.all -= d.all & s;
}
q.all = (q.all << 1) | carry;
if (rem)
*rem = r.all;
return q.all;
}

114
ArmPkg/Library/CompilerIntrinsicsLib/Arm/udivsi3.S
View File

@ -1,57 +1,57 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
.text
.align 2
GCC_ASM_EXPORT(__udivsi3)
ASM_PFX(__udivsi3):
cmp r1, #0
cmpne r0, #0
stmfd sp!, {r4, r5, r7, lr}
add r7, sp, #8
beq L2
clz r2, r1
clz r3, r0
rsb r3, r3, r2
cmp r3, #31
bhi L2
ldmeqfd sp!, {r4, r5, r7, pc}
add r5, r3, #1
rsb r3, r3, #31
mov lr, #0
mov r2, r0, asl r3
mov ip, r0, lsr r5
mov r4, lr
b L8
L9:
mov r0, r2, lsr #31
orr ip, r0, ip, asl #1
orr r2, r3, lr
rsb r3, ip, r1
sub r3, r3, #1
and r0, r1, r3, asr #31
mov lr, r3, lsr #31
rsb ip, r0, ip
add r4, r4, #1
L8:
cmp r4, r5
mov r3, r2, asl #1
bne L9
orr r0, r3, lr
ldmfd sp!, {r4, r5, r7, pc}
L2:
mov r0, #0
ldmfd sp!, {r4, r5, r7, pc}
#------------------------------------------------------------------------------
#
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
.text
.align 2
GCC_ASM_EXPORT(__udivsi3)
ASM_PFX(__udivsi3):
cmp r1, #0
cmpne r0, #0
stmfd sp!, {r4, r5, r7, lr}
add r7, sp, #8
beq L2
clz r2, r1
clz r3, r0
rsb r3, r3, r2
cmp r3, #31
bhi L2
ldmeqfd sp!, {r4, r5, r7, pc}
add r5, r3, #1
rsb r3, r3, #31
mov lr, #0
mov r2, r0, asl r3
mov ip, r0, lsr r5
mov r4, lr
b L8
L9:
mov r0, r2, lsr #31
orr ip, r0, ip, asl #1
orr r2, r3, lr
rsb r3, ip, r1
sub r3, r3, #1
and r0, r1, r3, asr #31
mov lr, r3, lsr #31
rsb ip, r0, ip
add r4, r4, #1
L8:
cmp r4, r5
mov r3, r2, asl #1
bne L9
orr r0, r3, lr
ldmfd sp!, {r4, r5, r7, pc}
L2:
mov r0, #0
ldmfd sp!, {r4, r5, r7, pc}

222
ArmPkg/Library/CompilerIntrinsicsLib/Arm/udivsi3.c
View File

@ -1,111 +1,111 @@
/** @file
Compiler intrinsic for 32-bit unsigned div, ported from LLVM code.
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
/**
University of Illinois/NCSA
Open Source License
Copyright (c) 2003-2008 University of Illinois at Urbana-Champaign.
All rights reserved.
Developed by:
LLVM Team
University of Illinois at Urbana-Champaign
http://llvm.org
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal with
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimers.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimers in the
documentation and/or other materials provided with the distribution.
* Neither the names of the LLVM Team, University of Illinois at
Urbana-Champaign, nor the names of its contributors may be used to
endorse or promote products derived from this Software without specific
prior written permission.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
SOFTWARE.
**/
#include "Llvm_int_lib.h"
// Returns: n / d
// Translated from Figure 3-40 of The PowerPC Compiler Writer's Guide
UINT32
__udivsi3(UINT32 n, UINT32 d)
{
const unsigned n_uword_bits = sizeof(UINT32) * CHAR_BIT;
UINT32 q;
UINT32 r;
unsigned sr;
// special cases
if (d == 0) {
// ASSERT (FALSE);
return 0; // ?!
}
if (n == 0)
return 0;
sr = COUNT_LEADING_ZEROS(d) - COUNT_LEADING_ZEROS(n);
// 0 <= sr <= n_uword_bits - 1 or sr large
if (sr > n_uword_bits - 1) // d > r
return 0;
if (sr == n_uword_bits - 1) // d == 1
return n;
++sr;
// 1 <= sr <= n_uword_bits - 1
// Not a special case
q = n << (n_uword_bits - sr);
r = n >> sr;
UINT32 carry = 0;
for (; sr > 0; --sr)
{
// r:q = ((r:q) << 1) | carry
r = (r << 1) | (q >> (n_uword_bits - 1));
q = (q << 1) | carry;
// carry = 0;
// if (r.all >= d.all)
// {
// r.all -= d.all;
// carry = 1;
// }
const INT32 s = (INT32)(d - r - 1) >> (n_uword_bits - 1);
carry = s & 1;
r -= d & s;
}
q = (q << 1) | carry;
return q;
}
/** @file
Compiler intrinsic for 32-bit unsigned div, ported from LLVM code.
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
/**
University of Illinois/NCSA
Open Source License
Copyright (c) 2003-2008 University of Illinois at Urbana-Champaign.
All rights reserved.
Developed by:
LLVM Team
University of Illinois at Urbana-Champaign
http://llvm.org
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal with
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimers.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimers in the
documentation and/or other materials provided with the distribution.
* Neither the names of the LLVM Team, University of Illinois at
Urbana-Champaign, nor the names of its contributors may be used to
endorse or promote products derived from this Software without specific
prior written permission.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
SOFTWARE.
**/
#include "Llvm_int_lib.h"
// Returns: n / d
// Translated from Figure 3-40 of The PowerPC Compiler Writer's Guide
UINT32
__udivsi3(UINT32 n, UINT32 d)
{
const unsigned n_uword_bits = sizeof(UINT32) * CHAR_BIT;
UINT32 q;
UINT32 r;
unsigned sr;
// special cases
if (d == 0) {
// ASSERT (FALSE);
return 0; // ?!
}
if (n == 0)
return 0;
sr = COUNT_LEADING_ZEROS(d) - COUNT_LEADING_ZEROS(n);
// 0 <= sr <= n_uword_bits - 1 or sr large
if (sr > n_uword_bits - 1) // d > r
return 0;
if (sr == n_uword_bits - 1) // d == 1
return n;
++sr;
// 1 <= sr <= n_uword_bits - 1
// Not a special case
q = n << (n_uword_bits - sr);
r = n >> sr;
UINT32 carry = 0;
for (; sr > 0; --sr)
{
// r:q = ((r:q) << 1) | carry
r = (r << 1) | (q >> (n_uword_bits - 1));
q = (q << 1) | carry;
// carry = 0;
// if (r.all >= d.all)
// {
// r.all -= d.all;
// carry = 1;
// }
const INT32 s = (INT32)(d - r - 1) >> (n_uword_bits - 1);
carry = s & 1;
r -= d & s;
}
q = (q << 1) | carry;
return q;
}

534
ArmPkg/Library/CompilerIntrinsicsLib/Arm/uldiv.S
View File

@ -1,267 +1,267 @@
//------------------------------------------------------------------------------
//
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
//------------------------------------------------------------------------------
.text
.align 2
GCC_ASM_EXPORT(__aeabi_uldivmod)
//
//UINT64
//EFIAPI
//__aeabi_uldivmod (
// IN UINT64 Dividend
// IN UINT64 Divisor
// )
//
ASM_PFX(__aeabi_uldivmod):
stmdb sp!, {r4, r5, r6, lr}
mov r4, r1
mov r5, r0
mov r6, #0 // 0x0
orrs ip, r3, r2, lsr #31
bne ASM_PFX(__aeabi_uldivmod_label1)
tst r2, r2
beq ASM_PFX(_ll_div0)
movs ip, r2, lsr #15
addeq r6, r6, #16 // 0x10
mov ip, r2, lsl r6
movs lr, ip, lsr #23
moveq ip, ip, lsl #8
addeq r6, r6, #8 // 0x8
movs lr, ip, lsr #27
moveq ip, ip, lsl #4
addeq r6, r6, #4 // 0x4
movs lr, ip, lsr #29
moveq ip, ip, lsl #2
addeq r6, r6, #2 // 0x2
movs lr, ip, lsr #30
moveq ip, ip, lsl #1
addeq r6, r6, #1 // 0x1
b ASM_PFX(_ll_udiv_small)
ASM_PFX(__aeabi_uldivmod_label1):
tst r3, #-2147483648 // 0x80000000
bne ASM_PFX(__aeabi_uldivmod_label2)
movs ip, r3, lsr #15
addeq r6, r6, #16 // 0x10
mov ip, r3, lsl r6
movs lr, ip, lsr #23
moveq ip, ip, lsl #8
addeq r6, r6, #8 // 0x8
movs lr, ip, lsr #27
moveq ip, ip, lsl #4
addeq r6, r6, #4 // 0x4
movs lr, ip, lsr #29
moveq ip, ip, lsl #2
addeq r6, r6, #2 // 0x2
movs lr, ip, lsr #30
addeq r6, r6, #1 // 0x1
rsb r3, r6, #32 // 0x20
moveq ip, ip, lsl #1
orr ip, ip, r2, lsr r3
mov lr, r2, lsl r6
b ASM_PFX(_ll_udiv_big)
ASM_PFX(__aeabi_uldivmod_label2):
mov ip, r3
mov lr, r2
b ASM_PFX(_ll_udiv_ginormous)
ASM_PFX(_ll_udiv_small):
cmp r4, ip, lsl #1
mov r3, #0 // 0x0
subcs r4, r4, ip, lsl #1
addcs r3, r3, #2 // 0x2
cmp r4, ip
subcs r4, r4, ip
adcs r3, r3, #0 // 0x0
add r2, r6, #32 // 0x20
cmp r2, #32 // 0x20
rsb ip, ip, #0 // 0x0
bcc ASM_PFX(_ll_udiv_small_label1)
orrs r0, r4, r5, lsr #30
moveq r4, r5
moveq r5, #0 // 0x0
subeq r2, r2, #32 // 0x20
ASM_PFX(_ll_udiv_small_label1):
mov r1, #0 // 0x0
cmp r2, #16 // 0x10
bcc ASM_PFX(_ll_udiv_small_label2)
movs r0, r4, lsr #14
moveq r4, r4, lsl #16
addeq r1, r1, #16 // 0x10
ASM_PFX(_ll_udiv_small_label2):
sub lr, r2, r1
cmp lr, #8 // 0x8
bcc ASM_PFX(_ll_udiv_small_label3)
movs r0, r4, lsr #22
moveq r4, r4, lsl #8
addeq r1, r1, #8 // 0x8
ASM_PFX(_ll_udiv_small_label3):
rsb r0, r1, #32 // 0x20
sub r2, r2, r1
orr r4, r4, r5, lsr r0
mov r5, r5, lsl r1
cmp r2, #1 // 0x1
bcc ASM_PFX(_ll_udiv_small_label5)
sub r2, r2, #1 // 0x1
and r0, r2, #7 // 0x7
eor r0, r0, #7 // 0x7
adds r0, r0, r0, lsl #1
add pc, pc, r0, lsl #2
nop // (mov r0,r0)
ASM_PFX(_ll_udiv_small_label4):
adcs r5, r5, r5
adcs r4, ip, r4, lsl #1
rsbcc r4, ip, r4
adcs r5, r5, r5
adcs r4, ip, r4, lsl #1
rsbcc r4, ip, r4
adcs r5, r5, r5
adcs r4, ip, r4, lsl #1
rsbcc r4, ip, r4
adcs r5, r5, r5
adcs r4, ip, r4, lsl #1
rsbcc r4, ip, r4
adcs r5, r5, r5
adcs r4, ip, r4, lsl #1
rsbcc r4, ip, r4
adcs r5, r5, r5
adcs r4, ip, r4, lsl #1
rsbcc r4, ip, r4
adcs r5, r5, r5
adcs r4, ip, r4, lsl #1
rsbcc r4, ip, r4
adcs r5, r5, r5
adcs r4, ip, r4, lsl #1
sub r2, r2, #8 // 0x8
tst r2, r2
rsbcc r4, ip, r4
bpl ASM_PFX(_ll_udiv_small_label4)
ASM_PFX(_ll_udiv_small_label5):
mov r2, r4, lsr r6
bic r4, r4, r2, lsl r6
adcs r0, r5, r5
adc r1, r4, r4
add r1, r1, r3, lsl r6
mov r3, #0 // 0x0
ldmia sp!, {r4, r5, r6, pc}
ASM_PFX(_ll_udiv_big):
subs r0, r5, lr
mov r3, #0 // 0x0
sbcs r1, r4, ip
movcs r5, r0
movcs r4, r1
adcs r3, r3, #0 // 0x0
subs r0, r5, lr
sbcs r1, r4, ip
movcs r5, r0
movcs r4, r1
adcs r3, r3, #0 // 0x0
subs r0, r5, lr
sbcs r1, r4, ip
movcs r5, r0
movcs r4, r1
adcs r3, r3, #0 // 0x0
mov r1, #0 // 0x0
rsbs lr, lr, #0 // 0x0
rsc ip, ip, #0 // 0x0
cmp r6, #16 // 0x10
bcc ASM_PFX(_ll_udiv_big_label1)
movs r0, r4, lsr #14
moveq r4, r4, lsl #16
addeq r1, r1, #16 // 0x10
ASM_PFX(_ll_udiv_big_label1):
sub r2, r6, r1
cmp r2, #8 // 0x8
bcc ASM_PFX(_ll_udiv_big_label2)
movs r0, r4, lsr #22
moveq r4, r4, lsl #8
addeq r1, r1, #8 // 0x8
ASM_PFX(_ll_udiv_big_label2):
rsb r0, r1, #32 // 0x20
sub r2, r6, r1
orr r4, r4, r5, lsr r0
mov r5, r5, lsl r1
cmp r2, #1 // 0x1
bcc ASM_PFX(_ll_udiv_big_label4)
sub r2, r2, #1 // 0x1
and r0, r2, #3 // 0x3
rsb r0, r0, #3 // 0x3
adds r0, r0, r0, lsl #1
add pc, pc, r0, lsl #3
nop // (mov r0,r0)
ASM_PFX(_ll_udiv_big_label3):
adcs r5, r5, r5
adcs r4, r4, r4
adcs r0, lr, r5
adcs r1, ip, r4
movcs r5, r0
movcs r4, r1
adcs r5, r5, r5
adcs r4, r4, r4
adcs r0, lr, r5
adcs r1, ip, r4
movcs r5, r0
movcs r4, r1
adcs r5, r5, r5
adcs r4, r4, r4
adcs r0, lr, r5
adcs r1, ip, r4
movcs r5, r0
movcs r4, r1
sub r2, r2, #4 // 0x4
adcs r5, r5, r5
adcs r4, r4, r4
adcs r0, lr, r5
adcs r1, ip, r4
tst r2, r2
movcs r5, r0
movcs r4, r1
bpl ASM_PFX(_ll_udiv_big_label3)
ASM_PFX(_ll_udiv_big_label4):
mov r1, #0 // 0x0
mov r2, r5, lsr r6
bic r5, r5, r2, lsl r6
adcs r0, r5, r5
adc r1, r1, #0 // 0x0
movs lr, r3, lsl r6
mov r3, r4, lsr r6
bic r4, r4, r3, lsl r6
adc r1, r1, #0 // 0x0
adds r0, r0, lr
orr r2, r2, r4, ror r6
adc r1, r1, #0 // 0x0
ldmia sp!, {r4, r5, r6, pc}
ASM_PFX(_ll_udiv_ginormous):
subs r2, r5, lr
mov r1, #0 // 0x0
sbcs r3, r4, ip
adc r0, r1, r1
movcc r2, r5
movcc r3, r4
ldmia sp!, {r4, r5, r6, pc}
ASM_PFX(_ll_div0):
ldmia sp!, {r4, r5, r6, lr}
mov r0, #0 // 0x0
mov r1, #0 // 0x0
b ASM_PFX(__aeabi_ldiv0)
ASM_PFX(__aeabi_ldiv0):
bx r14
//------------------------------------------------------------------------------
//
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
//------------------------------------------------------------------------------
.text
.align 2
GCC_ASM_EXPORT(__aeabi_uldivmod)
//
//UINT64
//EFIAPI
//__aeabi_uldivmod (
// IN UINT64 Dividend
// IN UINT64 Divisor
// )
//
ASM_PFX(__aeabi_uldivmod):
stmdb sp!, {r4, r5, r6, lr}
mov r4, r1
mov r5, r0
mov r6, #0 // 0x0
orrs ip, r3, r2, lsr #31
bne ASM_PFX(__aeabi_uldivmod_label1)
tst r2, r2
beq ASM_PFX(_ll_div0)
movs ip, r2, lsr #15
addeq r6, r6, #16 // 0x10
mov ip, r2, lsl r6
movs lr, ip, lsr #23
moveq ip, ip, lsl #8
addeq r6, r6, #8 // 0x8
movs lr, ip, lsr #27
moveq ip, ip, lsl #4
addeq r6, r6, #4 // 0x4
movs lr, ip, lsr #29
moveq ip, ip, lsl #2
addeq r6, r6, #2 // 0x2
movs lr, ip, lsr #30
moveq ip, ip, lsl #1
addeq r6, r6, #1 // 0x1
b ASM_PFX(_ll_udiv_small)
ASM_PFX(__aeabi_uldivmod_label1):
tst r3, #-2147483648 // 0x80000000
bne ASM_PFX(__aeabi_uldivmod_label2)
movs ip, r3, lsr #15
addeq r6, r6, #16 // 0x10
mov ip, r3, lsl r6
movs lr, ip, lsr #23
moveq ip, ip, lsl #8
addeq r6, r6, #8 // 0x8
movs lr, ip, lsr #27
moveq ip, ip, lsl #4
addeq r6, r6, #4 // 0x4
movs lr, ip, lsr #29
moveq ip, ip, lsl #2
addeq r6, r6, #2 // 0x2
movs lr, ip, lsr #30
addeq r6, r6, #1 // 0x1
rsb r3, r6, #32 // 0x20
moveq ip, ip, lsl #1
orr ip, ip, r2, lsr r3
mov lr, r2, lsl r6
b ASM_PFX(_ll_udiv_big)
ASM_PFX(__aeabi_uldivmod_label2):
mov ip, r3
mov lr, r2
b ASM_PFX(_ll_udiv_ginormous)
ASM_PFX(_ll_udiv_small):
cmp r4, ip, lsl #1
mov r3, #0 // 0x0
subcs r4, r4, ip, lsl #1
addcs r3, r3, #2 // 0x2
cmp r4, ip
subcs r4, r4, ip
adcs r3, r3, #0 // 0x0
add r2, r6, #32 // 0x20
cmp r2, #32 // 0x20
rsb ip, ip, #0 // 0x0
bcc ASM_PFX(_ll_udiv_small_label1)
orrs r0, r4, r5, lsr #30
moveq r4, r5
moveq r5, #0 // 0x0
subeq r2, r2, #32 // 0x20
ASM_PFX(_ll_udiv_small_label1):
mov r1, #0 // 0x0
cmp r2, #16 // 0x10
bcc ASM_PFX(_ll_udiv_small_label2)
movs r0, r4, lsr #14
moveq r4, r4, lsl #16
addeq r1, r1, #16 // 0x10
ASM_PFX(_ll_udiv_small_label2):
sub lr, r2, r1
cmp lr, #8 // 0x8
bcc ASM_PFX(_ll_udiv_small_label3)
movs r0, r4, lsr #22
moveq r4, r4, lsl #8
addeq r1, r1, #8 // 0x8
ASM_PFX(_ll_udiv_small_label3):
rsb r0, r1, #32 // 0x20
sub r2, r2, r1
orr r4, r4, r5, lsr r0
mov r5, r5, lsl r1
cmp r2, #1 // 0x1
bcc ASM_PFX(_ll_udiv_small_label5)
sub r2, r2, #1 // 0x1
and r0, r2, #7 // 0x7
eor r0, r0, #7 // 0x7
adds r0, r0, r0, lsl #1
add pc, pc, r0, lsl #2
nop // (mov r0,r0)
ASM_PFX(_ll_udiv_small_label4):
adcs r5, r5, r5
adcs r4, ip, r4, lsl #1
rsbcc r4, ip, r4
adcs r5, r5, r5
adcs r4, ip, r4, lsl #1
rsbcc r4, ip, r4
adcs r5, r5, r5
adcs r4, ip, r4, lsl #1
rsbcc r4, ip, r4
adcs r5, r5, r5
adcs r4, ip, r4, lsl #1
rsbcc r4, ip, r4
adcs r5, r5, r5
adcs r4, ip, r4, lsl #1
rsbcc r4, ip, r4
adcs r5, r5, r5
adcs r4, ip, r4, lsl #1
rsbcc r4, ip, r4
adcs r5, r5, r5
adcs r4, ip, r4, lsl #1
rsbcc r4, ip, r4
adcs r5, r5, r5
adcs r4, ip, r4, lsl #1
sub r2, r2, #8 // 0x8
tst r2, r2
rsbcc r4, ip, r4
bpl ASM_PFX(_ll_udiv_small_label4)
ASM_PFX(_ll_udiv_small_label5):
mov r2, r4, lsr r6
bic r4, r4, r2, lsl r6
adcs r0, r5, r5
adc r1, r4, r4
add r1, r1, r3, lsl r6
mov r3, #0 // 0x0
ldmia sp!, {r4, r5, r6, pc}
ASM_PFX(_ll_udiv_big):
subs r0, r5, lr
mov r3, #0 // 0x0
sbcs r1, r4, ip
movcs r5, r0
movcs r4, r1
adcs r3, r3, #0 // 0x0
subs r0, r5, lr
sbcs r1, r4, ip
movcs r5, r0
movcs r4, r1
adcs r3, r3, #0 // 0x0
subs r0, r5, lr
sbcs r1, r4, ip
movcs r5, r0
movcs r4, r1
adcs r3, r3, #0 // 0x0
mov r1, #0 // 0x0
rsbs lr, lr, #0 // 0x0
rsc ip, ip, #0 // 0x0
cmp r6, #16 // 0x10
bcc ASM_PFX(_ll_udiv_big_label1)
movs r0, r4, lsr #14
moveq r4, r4, lsl #16
addeq r1, r1, #16 // 0x10
ASM_PFX(_ll_udiv_big_label1):
sub r2, r6, r1
cmp r2, #8 // 0x8
bcc ASM_PFX(_ll_udiv_big_label2)
movs r0, r4, lsr #22
moveq r4, r4, lsl #8
addeq r1, r1, #8 // 0x8
ASM_PFX(_ll_udiv_big_label2):
rsb r0, r1, #32 // 0x20
sub r2, r6, r1
orr r4, r4, r5, lsr r0
mov r5, r5, lsl r1
cmp r2, #1 // 0x1
bcc ASM_PFX(_ll_udiv_big_label4)
sub r2, r2, #1 // 0x1
and r0, r2, #3 // 0x3
rsb r0, r0, #3 // 0x3
adds r0, r0, r0, lsl #1
add pc, pc, r0, lsl #3
nop // (mov r0,r0)
ASM_PFX(_ll_udiv_big_label3):
adcs r5, r5, r5
adcs r4, r4, r4
adcs r0, lr, r5
adcs r1, ip, r4
movcs r5, r0
movcs r4, r1
adcs r5, r5, r5
adcs r4, r4, r4
adcs r0, lr, r5
adcs r1, ip, r4
movcs r5, r0
movcs r4, r1
adcs r5, r5, r5
adcs r4, r4, r4
adcs r0, lr, r5
adcs r1, ip, r4
movcs r5, r0
movcs r4, r1
sub r2, r2, #4 // 0x4
adcs r5, r5, r5
adcs r4, r4, r4
adcs r0, lr, r5
adcs r1, ip, r4
tst r2, r2
movcs r5, r0
movcs r4, r1
bpl ASM_PFX(_ll_udiv_big_label3)
ASM_PFX(_ll_udiv_big_label4):
mov r1, #0 // 0x0
mov r2, r5, lsr r6
bic r5, r5, r2, lsl r6
adcs r0, r5, r5
adc r1, r1, #0 // 0x0
movs lr, r3, lsl r6
mov r3, r4, lsr r6
bic r4, r4, r3, lsl r6
adc r1, r1, #0 // 0x0
adds r0, r0, lr
orr r2, r2, r4, ror r6
adc r1, r1, #0 // 0x0
ldmia sp!, {r4, r5, r6, pc}
ASM_PFX(_ll_udiv_ginormous):
subs r2, r5, lr
mov r1, #0 // 0x0
sbcs r3, r4, ip
adc r0, r1, r1
movcc r2, r5
movcc r3, r4
ldmia sp!, {r4, r5, r6, pc}
ASM_PFX(_ll_div0):
ldmia sp!, {r4, r5, r6, lr}
mov r0, #0 // 0x0
mov r1, #0 // 0x0
b ASM_PFX(__aeabi_ldiv0)
ASM_PFX(__aeabi_ldiv0):
bx r14

536
ArmPkg/Library/CompilerIntrinsicsLib/Arm/uldiv.asm
View File

@ -1,268 +1,268 @@
//------------------------------------------------------------------------------
//
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
//------------------------------------------------------------------------------
EXPORT __aeabi_uldivmod
AREA Uldivmod, CODE, READONLY
;
;UINT64
;EFIAPI
;__aeabi_uldivmod (
; IN UINT64 Dividend
; IN UINT64 Divisor
; )
;
__aeabi_uldivmod
stmdb sp!, {r4, r5, r6, lr}
mov r4, r1
mov r5, r0
mov r6, #0 ; 0x0
orrs ip, r3, r2, lsr #31
bne __aeabi_uldivmod_label1
tst r2, r2
beq _ll_div0
movs ip, r2, lsr #15
addeq r6, r6, #16 ; 0x10
mov ip, r2, lsl r6
movs lr, ip, lsr #23
moveq ip, ip, lsl #8
addeq r6, r6, #8 ; 0x8
movs lr, ip, lsr #27
moveq ip, ip, lsl #4
addeq r6, r6, #4 ; 0x4
movs lr, ip, lsr #29
moveq ip, ip, lsl #2
addeq r6, r6, #2 ; 0x2
movs lr, ip, lsr #30
moveq ip, ip, lsl #1
addeq r6, r6, #1 ; 0x1
b _ll_udiv_small
__aeabi_uldivmod_label1
tst r3, #-2147483648 ; 0x80000000
bne __aeabi_uldivmod_label2
movs ip, r3, lsr #15
addeq r6, r6, #16 ; 0x10
mov ip, r3, lsl r6
movs lr, ip, lsr #23
moveq ip, ip, lsl #8
addeq r6, r6, #8 ; 0x8
movs lr, ip, lsr #27
moveq ip, ip, lsl #4
addeq r6, r6, #4 ; 0x4
movs lr, ip, lsr #29
moveq ip, ip, lsl #2
addeq r6, r6, #2 ; 0x2
movs lr, ip, lsr #30
addeq r6, r6, #1 ; 0x1
rsb r3, r6, #32 ; 0x20
moveq ip, ip, lsl #1
orr ip, ip, r2, lsr r3
mov lr, r2, lsl r6
b _ll_udiv_big
__aeabi_uldivmod_label2
mov ip, r3
mov lr, r2
b _ll_udiv_ginormous
_ll_udiv_small
cmp r4, ip, lsl #1
mov r3, #0 ; 0x0
subcs r4, r4, ip, lsl #1
addcs r3, r3, #2 ; 0x2
cmp r4, ip
subcs r4, r4, ip
adcs r3, r3, #0 ; 0x0
add r2, r6, #32 ; 0x20
cmp r2, #32 ; 0x20
rsb ip, ip, #0 ; 0x0
bcc _ll_udiv_small_label1
orrs r0, r4, r5, lsr #30
moveq r4, r5
moveq r5, #0 ; 0x0
subeq r2, r2, #32 ; 0x20
_ll_udiv_small_label1
mov r1, #0 ; 0x0
cmp r2, #16 ; 0x10
bcc _ll_udiv_small_label2
movs r0, r4, lsr #14
moveq r4, r4, lsl #16
addeq r1, r1, #16 ; 0x10
_ll_udiv_small_label2
sub lr, r2, r1
cmp lr, #8 ; 0x8
bcc _ll_udiv_small_label3
movs r0, r4, lsr #22
moveq r4, r4, lsl #8
addeq r1, r1, #8 ; 0x8
_ll_udiv_small_label3
rsb r0, r1, #32 ; 0x20
sub r2, r2, r1
orr r4, r4, r5, lsr r0
mov r5, r5, lsl r1
cmp r2, #1 ; 0x1
bcc _ll_udiv_small_label5
sub r2, r2, #1 ; 0x1
and r0, r2, #7 ; 0x7
eor r0, r0, #7 ; 0x7
adds r0, r0, r0, lsl #1
add pc, pc, r0, lsl #2
nop ; (mov r0,r0)
_ll_udiv_small_label4
adcs r5, r5, r5
adcs r4, ip, r4, lsl #1
rsbcc r4, ip, r4
adcs r5, r5, r5
adcs r4, ip, r4, lsl #1
rsbcc r4, ip, r4
adcs r5, r5, r5
adcs r4, ip, r4, lsl #1
rsbcc r4, ip, r4
adcs r5, r5, r5
adcs r4, ip, r4, lsl #1
rsbcc r4, ip, r4
adcs r5, r5, r5
adcs r4, ip, r4, lsl #1
rsbcc r4, ip, r4
adcs r5, r5, r5
adcs r4, ip, r4, lsl #1
rsbcc r4, ip, r4
adcs r5, r5, r5
adcs r4, ip, r4, lsl #1
rsbcc r4, ip, r4
adcs r5, r5, r5
adcs r4, ip, r4, lsl #1
sub r2, r2, #8 ; 0x8
tst r2, r2
rsbcc r4, ip, r4
bpl _ll_udiv_small_label4
_ll_udiv_small_label5
mov r2, r4, lsr r6
bic r4, r4, r2, lsl r6
adcs r0, r5, r5
adc r1, r4, r4
add r1, r1, r3, lsl r6
mov r3, #0 ; 0x0
ldmia sp!, {r4, r5, r6, pc}
_ll_udiv_big
subs r0, r5, lr
mov r3, #0 ; 0x0
sbcs r1, r4, ip
movcs r5, r0
movcs r4, r1
adcs r3, r3, #0 ; 0x0
subs r0, r5, lr
sbcs r1, r4, ip
movcs r5, r0
movcs r4, r1
adcs r3, r3, #0 ; 0x0
subs r0, r5, lr
sbcs r1, r4, ip
movcs r5, r0
movcs r4, r1
adcs r3, r3, #0 ; 0x0
mov r1, #0 ; 0x0
rsbs lr, lr, #0 ; 0x0
rsc ip, ip, #0 ; 0x0
cmp r6, #16 ; 0x10
bcc _ll_udiv_big_label1
movs r0, r4, lsr #14
moveq r4, r4, lsl #16
addeq r1, r1, #16 ; 0x10
_ll_udiv_big_label1
sub r2, r6, r1
cmp r2, #8 ; 0x8
bcc _ll_udiv_big_label2
movs r0, r4, lsr #22
moveq r4, r4, lsl #8
addeq r1, r1, #8 ; 0x8
_ll_udiv_big_label2
rsb r0, r1, #32 ; 0x20
sub r2, r6, r1
orr r4, r4, r5, lsr r0
mov r5, r5, lsl r1
cmp r2, #1 ; 0x1
bcc _ll_udiv_big_label4
sub r2, r2, #1 ; 0x1
and r0, r2, #3 ; 0x3
rsb r0, r0, #3 ; 0x3
adds r0, r0, r0, lsl #1
add pc, pc, r0, lsl #3
nop ; (mov r0,r0)
_ll_udiv_big_label3
adcs r5, r5, r5
adcs r4, r4, r4
adcs r0, lr, r5
adcs r1, ip, r4
movcs r5, r0
movcs r4, r1
adcs r5, r5, r5
adcs r4, r4, r4
adcs r0, lr, r5
adcs r1, ip, r4
movcs r5, r0
movcs r4, r1
adcs r5, r5, r5
adcs r4, r4, r4
adcs r0, lr, r5
adcs r1, ip, r4
movcs r5, r0
movcs r4, r1
sub r2, r2, #4 ; 0x4
adcs r5, r5, r5
adcs r4, r4, r4
adcs r0, lr, r5
adcs r1, ip, r4
tst r2, r2
movcs r5, r0
movcs r4, r1
bpl _ll_udiv_big_label3
_ll_udiv_big_label4
mov r1, #0 ; 0x0
mov r2, r5, lsr r6
bic r5, r5, r2, lsl r6
adcs r0, r5, r5
adc r1, r1, #0 ; 0x0
movs lr, r3, lsl r6
mov r3, r4, lsr r6
bic r4, r4, r3, lsl r6
adc r1, r1, #0 ; 0x0
adds r0, r0, lr
orr r2, r2, r4, ror r6
adc r1, r1, #0 ; 0x0
ldmia sp!, {r4, r5, r6, pc}
_ll_udiv_ginormous
subs r2, r5, lr
mov r1, #0 ; 0x0
sbcs r3, r4, ip
adc r0, r1, r1
movcc r2, r5
movcc r3, r4
ldmia sp!, {r4, r5, r6, pc}
_ll_div0
ldmia sp!, {r4, r5, r6, lr}
mov r0, #0 ; 0x0
mov r1, #0 ; 0x0
b __aeabi_ldiv0
__aeabi_ldiv0
BX r14
END
//------------------------------------------------------------------------------
//
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
//------------------------------------------------------------------------------
EXPORT __aeabi_uldivmod
AREA Uldivmod, CODE, READONLY
;
;UINT64
;EFIAPI
;__aeabi_uldivmod (
; IN UINT64 Dividend
; IN UINT64 Divisor
; )
;
__aeabi_uldivmod
stmdb sp!, {r4, r5, r6, lr}
mov r4, r1
mov r5, r0
mov r6, #0 ; 0x0
orrs ip, r3, r2, lsr #31
bne __aeabi_uldivmod_label1
tst r2, r2
beq _ll_div0
movs ip, r2, lsr #15
addeq r6, r6, #16 ; 0x10
mov ip, r2, lsl r6
movs lr, ip, lsr #23
moveq ip, ip, lsl #8
addeq r6, r6, #8 ; 0x8
movs lr, ip, lsr #27
moveq ip, ip, lsl #4
addeq r6, r6, #4 ; 0x4
movs lr, ip, lsr #29
moveq ip, ip, lsl #2
addeq r6, r6, #2 ; 0x2
movs lr, ip, lsr #30
moveq ip, ip, lsl #1
addeq r6, r6, #1 ; 0x1
b _ll_udiv_small
__aeabi_uldivmod_label1
tst r3, #-2147483648 ; 0x80000000
bne __aeabi_uldivmod_label2
movs ip, r3, lsr #15
addeq r6, r6, #16 ; 0x10
mov ip, r3, lsl r6
movs lr, ip, lsr #23
moveq ip, ip, lsl #8
addeq r6, r6, #8 ; 0x8
movs lr, ip, lsr #27
moveq ip, ip, lsl #4
addeq r6, r6, #4 ; 0x4
movs lr, ip, lsr #29
moveq ip, ip, lsl #2
addeq r6, r6, #2 ; 0x2
movs lr, ip, lsr #30
addeq r6, r6, #1 ; 0x1
rsb r3, r6, #32 ; 0x20
moveq ip, ip, lsl #1
orr ip, ip, r2, lsr r3
mov lr, r2, lsl r6
b _ll_udiv_big
__aeabi_uldivmod_label2
mov ip, r3
mov lr, r2
b _ll_udiv_ginormous
_ll_udiv_small
cmp r4, ip, lsl #1
mov r3, #0 ; 0x0
subcs r4, r4, ip, lsl #1
addcs r3, r3, #2 ; 0x2
cmp r4, ip
subcs r4, r4, ip
adcs r3, r3, #0 ; 0x0
add r2, r6, #32 ; 0x20
cmp r2, #32 ; 0x20
rsb ip, ip, #0 ; 0x0
bcc _ll_udiv_small_label1
orrs r0, r4, r5, lsr #30
moveq r4, r5
moveq r5, #0 ; 0x0
subeq r2, r2, #32 ; 0x20
_ll_udiv_small_label1
mov r1, #0 ; 0x0
cmp r2, #16 ; 0x10
bcc _ll_udiv_small_label2
movs r0, r4, lsr #14
moveq r4, r4, lsl #16
addeq r1, r1, #16 ; 0x10
_ll_udiv_small_label2
sub lr, r2, r1
cmp lr, #8 ; 0x8
bcc _ll_udiv_small_label3
movs r0, r4, lsr #22
moveq r4, r4, lsl #8
addeq r1, r1, #8 ; 0x8
_ll_udiv_small_label3
rsb r0, r1, #32 ; 0x20
sub r2, r2, r1
orr r4, r4, r5, lsr r0
mov r5, r5, lsl r1
cmp r2, #1 ; 0x1
bcc _ll_udiv_small_label5
sub r2, r2, #1 ; 0x1
and r0, r2, #7 ; 0x7
eor r0, r0, #7 ; 0x7
adds r0, r0, r0, lsl #1
add pc, pc, r0, lsl #2
nop ; (mov r0,r0)
_ll_udiv_small_label4
adcs r5, r5, r5
adcs r4, ip, r4, lsl #1
rsbcc r4, ip, r4
adcs r5, r5, r5
adcs r4, ip, r4, lsl #1
rsbcc r4, ip, r4
adcs r5, r5, r5
adcs r4, ip, r4, lsl #1
rsbcc r4, ip, r4
adcs r5, r5, r5
adcs r4, ip, r4, lsl #1
rsbcc r4, ip, r4
adcs r5, r5, r5
adcs r4, ip, r4, lsl #1
rsbcc r4, ip, r4
adcs r5, r5, r5
adcs r4, ip, r4, lsl #1
rsbcc r4, ip, r4
adcs r5, r5, r5
adcs r4, ip, r4, lsl #1
rsbcc r4, ip, r4
adcs r5, r5, r5
adcs r4, ip, r4, lsl #1
sub r2, r2, #8 ; 0x8
tst r2, r2
rsbcc r4, ip, r4
bpl _ll_udiv_small_label4
_ll_udiv_small_label5
mov r2, r4, lsr r6
bic r4, r4, r2, lsl r6
adcs r0, r5, r5
adc r1, r4, r4
add r1, r1, r3, lsl r6
mov r3, #0 ; 0x0
ldmia sp!, {r4, r5, r6, pc}
_ll_udiv_big
subs r0, r5, lr
mov r3, #0 ; 0x0
sbcs r1, r4, ip
movcs r5, r0
movcs r4, r1
adcs r3, r3, #0 ; 0x0
subs r0, r5, lr
sbcs r1, r4, ip
movcs r5, r0
movcs r4, r1
adcs r3, r3, #0 ; 0x0
subs r0, r5, lr
sbcs r1, r4, ip
movcs r5, r0
movcs r4, r1
adcs r3, r3, #0 ; 0x0
mov r1, #0 ; 0x0
rsbs lr, lr, #0 ; 0x0
rsc ip, ip, #0 ; 0x0
cmp r6, #16 ; 0x10
bcc _ll_udiv_big_label1
movs r0, r4, lsr #14
moveq r4, r4, lsl #16
addeq r1, r1, #16 ; 0x10
_ll_udiv_big_label1
sub r2, r6, r1
cmp r2, #8 ; 0x8
bcc _ll_udiv_big_label2
movs r0, r4, lsr #22
moveq r4, r4, lsl #8
addeq r1, r1, #8 ; 0x8
_ll_udiv_big_label2
rsb r0, r1, #32 ; 0x20
sub r2, r6, r1
orr r4, r4, r5, lsr r0
mov r5, r5, lsl r1
cmp r2, #1 ; 0x1
bcc _ll_udiv_big_label4
sub r2, r2, #1 ; 0x1
and r0, r2, #3 ; 0x3
rsb r0, r0, #3 ; 0x3
adds r0, r0, r0, lsl #1
add pc, pc, r0, lsl #3
nop ; (mov r0,r0)
_ll_udiv_big_label3
adcs r5, r5, r5
adcs r4, r4, r4
adcs r0, lr, r5
adcs r1, ip, r4
movcs r5, r0
movcs r4, r1
adcs r5, r5, r5
adcs r4, r4, r4
adcs r0, lr, r5
adcs r1, ip, r4
movcs r5, r0
movcs r4, r1
adcs r5, r5, r5
adcs r4, r4, r4
adcs r0, lr, r5
adcs r1, ip, r4
movcs r5, r0
movcs r4, r1
sub r2, r2, #4 ; 0x4
adcs r5, r5, r5
adcs r4, r4, r4
adcs r0, lr, r5
adcs r1, ip, r4
tst r2, r2
movcs r5, r0
movcs r4, r1
bpl _ll_udiv_big_label3
_ll_udiv_big_label4
mov r1, #0 ; 0x0
mov r2, r5, lsr r6
bic r5, r5, r2, lsl r6
adcs r0, r5, r5
adc r1, r1, #0 ; 0x0
movs lr, r3, lsl r6
mov r3, r4, lsr r6
bic r4, r4, r3, lsl r6
adc r1, r1, #0 ; 0x0
adds r0, r0, lr
orr r2, r2, r4, ror r6
adc r1, r1, #0 ; 0x0
ldmia sp!, {r4, r5, r6, pc}
_ll_udiv_ginormous
subs r2, r5, lr
mov r1, #0 ; 0x0
sbcs r3, r4, ip
adc r0, r1, r1
movcc r2, r5
movcc r3, r4
ldmia sp!, {r4, r5, r6, pc}
_ll_div0
ldmia sp!, {r4, r5, r6, lr}
mov r0, #0 ; 0x0
mov r1, #0 ; 0x0
b __aeabi_ldiv0
__aeabi_ldiv0
BX r14
END

86
ArmPkg/Library/CompilerIntrinsicsLib/Arm/uldivmod.c
View File

@ -1,43 +1,43 @@
/** @file
Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "Llvm_int_lib.h"
#include <Library/BaseLib.h>
UINT32 __udivsi3(UINT32 n, UINT32 d);
UINT32 __umodsi3(UINT32 a, UINT32 b);
UINT64
__aeabi_uidivmod(unsigned numerator, unsigned denominator)
{
UINT64 Return;
Return = __udivsi3 (numerator, denominator);
Return |= LShiftU64 (__umodsi3 (numerator, denominator), 32);
return Return;
}
unsigned
__aeabi_uidiv (unsigned n, unsigned d)
{
return __udivsi3 (n, d);
}
/** @file
Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "Llvm_int_lib.h"
#include <Library/BaseLib.h>
UINT32 __udivsi3(UINT32 n, UINT32 d);
UINT32 __umodsi3(UINT32 a, UINT32 b);
UINT64
__aeabi_uidivmod(unsigned numerator, unsigned denominator)
{
UINT64 Return;
Return = __udivsi3 (numerator, denominator);
Return |= LShiftU64 (__umodsi3 (numerator, denominator), 32);
return Return;
}
unsigned
__aeabi_uidiv (unsigned n, unsigned d)
{
return __udivsi3 (n, d);
}

58
ArmPkg/Library/CompilerIntrinsicsLib/Arm/umoddi3.S
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@ -1,29 +1,29 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
.text
.align 2
GCC_ASM_EXPORT(__umoddi3)
ASM_PFX(__umoddi3):
stmfd sp!, {r7, lr}
add r7, sp, #0
sub sp, sp, #16
add ip, sp, #8
str ip, [sp, #0]
bl ASM_PFX(__udivmoddi4)
ldrd r0, [sp, #8]
sub sp, r7, #0
ldmfd sp!, {r7, pc}
#------------------------------------------------------------------------------
#
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
.text
.align 2
GCC_ASM_EXPORT(__umoddi3)
ASM_PFX(__umoddi3):
stmfd sp!, {r7, lr}
add r7, sp, #0
sub sp, sp, #16
add ip, sp, #8
str ip, [sp, #0]
bl ASM_PFX(__udivmoddi4)
ldrd r0, [sp, #8]
sub sp, r7, #0
ldmfd sp!, {r7, pc}

144
ArmPkg/Library/CompilerIntrinsicsLib/Arm/umoddi3.c
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@ -1,72 +1,72 @@
/** @file
Compiler intrinsic for 64-bit unsigned mod, ported from LLVM code.
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
/**
University of Illinois/NCSA
Open Source License
Copyright (c) 2003-2008 University of Illinois at Urbana-Champaign.
All rights reserved.
Developed by:
LLVM Team
University of Illinois at Urbana-Champaign
http://llvm.org
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal with
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimers.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimers in the
documentation and/or other materials provided with the distribution.
* Neither the names of the LLVM Team, University of Illinois at
Urbana-Champaign, nor the names of its contributors may be used to
endorse or promote products derived from this Software without specific
prior written permission.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
SOFTWARE.
**/
#include "Llvm_int_lib.h"
UINT64 __udivmoddi4(UINT64 a, UINT64 b, UINT64* rem);
// Returns: a % b
UINT64
__umoddi3(UINT64 a, UINT64 b)
{
UINT64 r;
__udivmoddi4(a, b, &r);
return r;
}
/** @file
Compiler intrinsic for 64-bit unsigned mod, ported from LLVM code.
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
/**
University of Illinois/NCSA
Open Source License
Copyright (c) 2003-2008 University of Illinois at Urbana-Champaign.
All rights reserved.
Developed by:
LLVM Team
University of Illinois at Urbana-Champaign
http://llvm.org
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal with
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimers.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimers in the
documentation and/or other materials provided with the distribution.
* Neither the names of the LLVM Team, University of Illinois at
Urbana-Champaign, nor the names of its contributors may be used to
endorse or promote products derived from this Software without specific
prior written permission.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
SOFTWARE.
**/
#include "Llvm_int_lib.h"
UINT64 __udivmoddi4(UINT64 a, UINT64 b, UINT64* rem);
// Returns: a % b
UINT64
__umoddi3(UINT64 a, UINT64 b)
{
UINT64 r;
__udivmoddi4(a, b, &r);
return r;
}

56
ArmPkg/Library/CompilerIntrinsicsLib/Arm/umodsi3.S
View File

@ -1,28 +1,28 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
.text
.align 2
GCC_ASM_EXPORT(__umodsi3)
ASM_PFX(__umodsi3):
stmfd sp!, {r4, r5, r7, lr}
add r7, sp, #8
mov r5, r0
mov r4, r1
bl ASM_PFX(__udivsi3)
mul r0, r4, r0
rsb r0, r0, r5
ldmfd sp!, {r4, r5, r7, pc}
#------------------------------------------------------------------------------
#
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
.text
.align 2
GCC_ASM_EXPORT(__umodsi3)
ASM_PFX(__umodsi3):
stmfd sp!, {r4, r5, r7, lr}
add r7, sp, #8
mov r5, r0
mov r4, r1
bl ASM_PFX(__udivsi3)
mul r0, r4, r0
rsb r0, r0, r5
ldmfd sp!, {r4, r5, r7, pc}

136
ArmPkg/Library/CompilerIntrinsicsLib/Arm/umodsi3.c
View File

@ -1,68 +1,68 @@
/** @file
Compiler intrinsic for 32-bit unsigned mod, ported from LLVM code.
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
/**
University of Illinois/NCSA
Open Source License
Copyright (c) 2003-2008 University of Illinois at Urbana-Champaign.
All rights reserved.
Developed by:
LLVM Team
University of Illinois at Urbana-Champaign
http://llvm.org
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal with
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimers.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimers in the
documentation and/or other materials provided with the distribution.
* Neither the names of the LLVM Team, University of Illinois at
Urbana-Champaign, nor the names of its contributors may be used to
endorse or promote products derived from this Software without specific
prior written permission.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
SOFTWARE.
**/
#include "Llvm_int_lib.h"
// Returns: a % b
UINT32
__umodsi3(UINT32 a, UINT32 b)
{
return a - (a / b) * b;
}
/** @file
Compiler intrinsic for 32-bit unsigned mod, ported from LLVM code.
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
/**
University of Illinois/NCSA
Open Source License
Copyright (c) 2003-2008 University of Illinois at Urbana-Champaign.
All rights reserved.
Developed by:
LLVM Team
University of Illinois at Urbana-Champaign
http://llvm.org
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal with
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimers.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimers in the
documentation and/or other materials provided with the distribution.
* Neither the names of the LLVM Team, University of Illinois at
Urbana-Champaign, nor the names of its contributors may be used to
endorse or promote products derived from this Software without specific
prior written permission.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
SOFTWARE.
**/
#include "Llvm_int_lib.h"
// Returns: a % b
UINT32
__umodsi3(UINT32 a, UINT32 b)
{
return a - (a / b) * b;
}

136
ArmPkg/Library/CompilerIntrinsicsLib/Arm/uwrite.asm
View File

@ -1,68 +1,68 @@
//------------------------------------------------------------------------------
//
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
//------------------------------------------------------------------------------
EXPORT __aeabi_uwrite4
EXPORT __aeabi_uwrite8
AREA Uwrite4, CODE, READONLY
;
;UINT32
;EFIAPI
;__aeabi_uwrite4 (
; IN UINT32 Data,
; IN VOID *Pointer
; );
;
;
__aeabi_uwrite4
mov r2, r0, lsr #8
strb r0, [r1]
strb r2, [r1, #1]
mov r2, r0, lsr #16
strb r2, [r1, #2]
mov r2, r0, lsr #24
strb r2, [r1, #3]
bx lr
;
;UINT64
;EFIAPI
;__aeabi_uwrite8 (
; IN UINT64 Data, //r0-r1
; IN VOID *Pointer //r2
; );
;
;
__aeabi_uwrite8
mov r3, r0, lsr #8
strb r0, [r2]
strb r3, [r2, #1]
mov r3, r0, lsr #16
strb r3, [r2, #2]
mov r3, r0, lsr #24
strb r3, [r2, #3]
mov r3, r1, lsr #8
strb r1, [r2, #4]
strb r3, [r2, #5]
mov r3, r1, lsr #16
strb r3, [r2, #6]
mov r3, r1, lsr #24
strb r3, [r2, #7]
bx lr
END
//------------------------------------------------------------------------------
//
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
//------------------------------------------------------------------------------
EXPORT __aeabi_uwrite4
EXPORT __aeabi_uwrite8
AREA Uwrite4, CODE, READONLY
;
;UINT32
;EFIAPI
;__aeabi_uwrite4 (
; IN UINT32 Data,
; IN VOID *Pointer
; );
;
;
__aeabi_uwrite4
mov r2, r0, lsr #8
strb r0, [r1]
strb r2, [r1, #1]
mov r2, r0, lsr #16
strb r2, [r1, #2]
mov r2, r0, lsr #24
strb r2, [r1, #3]
bx lr
;
;UINT64
;EFIAPI
;__aeabi_uwrite8 (
; IN UINT64 Data, //r0-r1
; IN VOID *Pointer //r2
; );
;
;
__aeabi_uwrite8
mov r3, r0, lsr #8
strb r0, [r2]
strb r3, [r2, #1]
mov r3, r0, lsr #16
strb r3, [r2, #2]
mov r3, r0, lsr #24
strb r3, [r2, #3]
mov r3, r1, lsr #8
strb r1, [r2, #4]
strb r3, [r2, #5]
mov r3, r1, lsr #16
strb r3, [r2, #6]
mov r3, r1, lsr #24
strb r3, [r2, #7]
bx lr
END

204
ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
View File

@ -1,102 +1,102 @@
#/** @file
# Base Library implementation.
#
# Copyright (c) 2009, Apple Inc. All rights reserved.<BR>
# Copyright (c) 2011, ARM Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = CompilerIntrinsicsLib
FILE_GUID = 855274FA-3575-4C20-9709-C031DC5589FA
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = CompilerIntrinsicsLib
[Sources.common]
[Sources.ARM]
Arm/mullu.asm | RVCT
Arm/switch.asm | RVCT
Arm/llsr.asm | RVCT
Arm/memcpy.asm | RVCT
Arm/memcpy4.asm | RVCT
Arm/memset.asm | RVCT
Arm/memmove.asm | RVCT
Arm/uread.asm | RVCT
Arm/uwrite.asm | RVCT
Arm/lasr.asm | RVCT
Arm/llsl.asm | RVCT
Arm/div.asm | RVCT
Arm/uldiv.asm | RVCT
Arm/ldivmod.asm | RVCT
#
# Move .c to .s to work around LLVM issues
#
# Arm/ashrdi3.c | GCC
# Arm/ashldi3.c | GCC
# Arm/divdi3.c | GCC
# Arm/divsi3.c | GCC
# Arm/lshrdi3.c | GCC
Arm/ashrdi3.S | GCC
Arm/ashldi3.S | GCC
Arm/div.S | GCC
Arm/divdi3.S | GCC
Arm/divsi3.S | GCC
Arm/lshrdi3.S | GCC
Arm/memcpy.S | GCC
Arm/memset.S | GCC
# Arm/modsi3.c | GCC
# Arm/moddi3.c | GCC
# Arm/muldi3.c | GCC
Arm/modsi3.S | GCC
Arm/moddi3.S | GCC
Arm/muldi3.S | GCC
Arm/mullu.S | GCC
# Arm/udivsi3.c | GCC
# Arm/umodsi3.c | GCC
# Arm/udivdi3.c | GCC
# Arm/umoddi3.c | GCC
# Arm/udivmoddi4.c | GCC
Arm/udivsi3.S | GCC
Arm/umodsi3.S | GCC
Arm/udivdi3.S | GCC
Arm/umoddi3.S | GCC
Arm/udivmoddi4.S | GCC
# Arm/clzsi2.c | GCC
# Arm/ctzsi2.c | GCC
# Arm/ucmpdi2.c | GCC
Arm/clzsi2.S | GCC
Arm/ctzsi2.S | GCC
Arm/ucmpdi2.S | GCC
Arm/switch8.S | GCC
Arm/switchu8.S | GCC
Arm/switch16.S | GCC
Arm/switch32.S | GCC
Arm/sourcery.S | GCC
Arm/uldiv.S | GCC
Arm/ldivmod.S | GCC
[Packages]
MdePkg/MdePkg.dec
[LibraryClasses]
#/** @file
# Base Library implementation.
#
# Copyright (c) 2009, Apple Inc. All rights reserved.<BR>
# Copyright (c) 2011, ARM Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = CompilerIntrinsicsLib
FILE_GUID = 855274FA-3575-4C20-9709-C031DC5589FA
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = CompilerIntrinsicsLib
[Sources.common]
[Sources.ARM]
Arm/mullu.asm | RVCT
Arm/switch.asm | RVCT
Arm/llsr.asm | RVCT
Arm/memcpy.asm | RVCT
Arm/memcpy4.asm | RVCT
Arm/memset.asm | RVCT
Arm/memmove.asm | RVCT
Arm/uread.asm | RVCT
Arm/uwrite.asm | RVCT
Arm/lasr.asm | RVCT
Arm/llsl.asm | RVCT
Arm/div.asm | RVCT
Arm/uldiv.asm | RVCT
Arm/ldivmod.asm | RVCT
#
# Move .c to .s to work around LLVM issues
#
# Arm/ashrdi3.c | GCC
# Arm/ashldi3.c | GCC
# Arm/divdi3.c | GCC
# Arm/divsi3.c | GCC
# Arm/lshrdi3.c | GCC
Arm/ashrdi3.S | GCC
Arm/ashldi3.S | GCC
Arm/div.S | GCC
Arm/divdi3.S | GCC
Arm/divsi3.S | GCC
Arm/lshrdi3.S | GCC
Arm/memcpy.S | GCC
Arm/memset.S | GCC
# Arm/modsi3.c | GCC
# Arm/moddi3.c | GCC
# Arm/muldi3.c | GCC
Arm/modsi3.S | GCC
Arm/moddi3.S | GCC
Arm/muldi3.S | GCC
Arm/mullu.S | GCC
# Arm/udivsi3.c | GCC
# Arm/umodsi3.c | GCC
# Arm/udivdi3.c | GCC
# Arm/umoddi3.c | GCC
# Arm/udivmoddi4.c | GCC
Arm/udivsi3.S | GCC
Arm/umodsi3.S | GCC
Arm/udivdi3.S | GCC
Arm/umoddi3.S | GCC
Arm/udivmoddi4.S | GCC
# Arm/clzsi2.c | GCC
# Arm/ctzsi2.c | GCC
# Arm/ucmpdi2.c | GCC
Arm/clzsi2.S | GCC
Arm/ctzsi2.S | GCC
Arm/ucmpdi2.S | GCC
Arm/switch8.S | GCC
Arm/switchu8.S | GCC
Arm/switch16.S | GCC
Arm/switch32.S | GCC
Arm/sourcery.S | GCC
Arm/uldiv.S | GCC
Arm/ldivmod.S | GCC
[Packages]
MdePkg/MdePkg.dec
[LibraryClasses]

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