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MdePkg/BaseLib: Remove .S files for IA32 and X64 arch

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.nasm file has been added for X86 arch. .S assembly code
is not required any more.
https://bugzilla.tianocore.org/show_bug.cgi?id=1594

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
This commit is contained in:
Shenglei Zhang
2019-03-07 09:01:03 +08:00
committed by Liming Gao
parent 4eea7627ef
commit 1ee58b7103
39 changed files with 0 additions and 2412 deletions
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60
MdePkg/Library/BaseLib/X64/CpuId.S
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@@ -1,60 +0,0 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php.
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
# Module Name:
#
# CpuId.S
#
# Abstract:
#
# AsmCpuid function
#
# Notes:
#
#------------------------------------------------------------------------------
#------------------------------------------------------------------------------
# VOID
# EFIAPI
# AsmCpuid (
# IN UINT32 RegisterInEax,
# OUT UINT32 *RegisterOutEax OPTIONAL,
# OUT UINT32 *RegisterOutEbx OPTIONAL,
# OUT UINT32 *RegisterOutEcx OPTIONAL,
# OUT UINT32 *RegisterOutEdx OPTIONAL
# )
#------------------------------------------------------------------------------
ASM_GLOBAL ASM_PFX(AsmCpuid)
ASM_PFX(AsmCpuid):
push %rbx
mov %ecx, %eax
push %rax # save Index on stack
push %rdx
cpuid
test %r9, %r9
jz L1
mov %ecx, (%r9)
L1:
pop %rcx
jrcxz L2
mov %eax, (%rcx)
L2:
mov %r8, %rcx
jrcxz L3
mov %ebx, (%rcx)
L3:
mov 0x38(%rsp), %rcx
jrcxz L4
mov %edx, (%rcx)
L4:
pop %rax # restore Index to rax as return value
pop %rbx
ret

62
MdePkg/Library/BaseLib/X64/CpuIdEx.S
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@@ -1,62 +0,0 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php.
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
# Module Name:
#
# CpuIdEx.S
#
# Abstract:
#
# AsmCpuidEx function
#
# Notes:
#
#------------------------------------------------------------------------------
#------------------------------------------------------------------------------
# UINT32
# EFIAPI
# AsmCpuidEx (
# IN UINT32 RegisterInEax,
# IN UINT32 RegisterInEcx,
# OUT UINT32 *RegisterOutEax OPTIONAL,
# OUT UINT32 *RegisterOutEbx OPTIONAL,
# OUT UINT32 *RegisterOutEcx OPTIONAL,
# OUT UINT32 *RegisterOutEdx OPTIONAL
# )
#------------------------------------------------------------------------------
ASM_GLOBAL ASM_PFX(AsmCpuidEx)
ASM_PFX(AsmCpuidEx):
push %rbx
movl %ecx,%eax
movl %edx,%ecx
push %rax # save Index on stack
cpuid
mov 0x38(%rsp), %r10
test %r10, %r10
jz L1
mov %ecx,(%r10)
L1:
mov %r8, %rcx
jrcxz L2
movl %eax,(%rcx)
L2:
mov %r9, %rcx
jrcxz L3
mov %ebx, (%rcx)
L3:
mov 0x40(%rsp), %rcx
jrcxz L4
mov %edx, (%rcx)
L4:
pop %rax # restore Index to rax as return value
pop %rbx
ret

39
MdePkg/Library/BaseLib/X64/DisableCache.S
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@@ -1,39 +0,0 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php.
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
# Module Name:
#
# DisableCache.S
#
# Abstract:
#
# Set the CD bit of CR0 to 1, clear the NW bit of CR0 to 0, and flush all caches with a
# WBINVD instruction.
#
# Notes:
#
#------------------------------------------------------------------------------
#------------------------------------------------------------------------------
# VOID
# EFIAPI
# AsmDisableCache (
# VOID
# );
#------------------------------------------------------------------------------
ASM_GLOBAL ASM_PFX(AsmDisableCache)
ASM_PFX(AsmDisableCache):
movq %cr0, %rax
btsq $30, %rax
btrq $29, %rax
movq %rax, %cr0
wbinvd
ret

82
MdePkg/Library/BaseLib/X64/DisablePaging64.S
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@@ -1,82 +0,0 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php.
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
# Module Name:
#
# DisablePaging64.S
#
# Abstract:
#
# AsmDisablePaging64 function
#
# Notes:
#
#------------------------------------------------------------------------------
#------------------------------------------------------------------------------
# VOID
# EFIAPI
# InternalX86DisablePaging64 (
# IN UINT16 Cs,
# IN UINT32 EntryPoint,
# IN UINT32 Context1, OPTIONAL
# IN UINT32 Context2, OPTIONAL
# IN UINT32 NewStack
# );
#------------------------------------------------------------------------------
ASM_GLOBAL ASM_PFX(InternalX86DisablePaging64)
ASM_PFX(InternalX86DisablePaging64):
cli
lea L1(%rip), %rsi # rsi <- The start address of transition code
mov 0x28(%rsp), %edi # rdi <- New stack
lea _mTransitionEnd(%rip), %rax # rax <- end of transition code
sub %rsi, %rax # rax <- The size of transition piece code
add $4, %rax # round rax up to the next 4 byte boundary
and $0xfc, %al
sub %rax, %rdi # rdi <- use stack to hold transition code
mov %edi, %r10d # r10 <- The start address of transicition code below 4G
push %rcx # save rcx to stack
mov %rax, %rcx # rcx <- The size of transition piece code
rep
movsb # copy transition code to (new stack - 64byte) below 4G
pop %rcx # restore rcx
mov %r8d, %esi
mov %r9d, %edi
mov %r10d, %eax
sub $4, %eax
push %rcx # push Cs to stack
push %r10 # push address of transition code on stack
.byte 0x48, 0xcb # retq: Use far return to load CS register from stack
# (Use raw byte code since some GNU assemblers generates incorrect code for "retq")
L1:
mov %eax,%esp # set up new stack
mov %cr0,%rax
btr $0x1f,%eax # clear CR0.PG
mov %rax,%cr0 # disable paging
mov %edx,%ebx # save EntryPoint to ebx, for rdmsr will overwrite edx
mov $0xc0000080,%ecx
rdmsr
and $0xfe,%ah # clear LME
wrmsr
mov %cr4,%rax
and $0xdf,%al # clear PAE
mov %rax,%cr4
push %rdi # push Context2
push %rsi # push Context1
callq *%rbx # transfer control to EntryPoint
jmp . # no one should get here
_mTransitionEnd :

39
MdePkg/Library/BaseLib/X64/EnableCache.S
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@@ -1,39 +0,0 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php.
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
# Module Name:
#
# EnableCache.S
#
# Abstract:
#
# Flush all caches with a WBINVD instruction, clear the CD bit of CR0 to 0, and clear
# the NW bit of CR0 to 0
#
# Notes:
#
#------------------------------------------------------------------------------
#------------------------------------------------------------------------------
# VOID
# EFIAPI
# AsmEnableCache (
# VOID
# );
#------------------------------------------------------------------------------
ASM_GLOBAL ASM_PFX(AsmEnableCache)
ASM_PFX(AsmEnableCache):
wbinvd
movq %cr0, %rax
btrq $30, %rax
btrq $29, %rax
movq %rax, %cr0
ret

36
MdePkg/Library/BaseLib/X64/EnableDisableInterrupts.S
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@@ -1,36 +0,0 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php.
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
# Module Name:
#
# EnableDisableInterrupts.S
#
# Abstract:
#
# EnableDisableInterrupts function
#
# Notes:
#
#------------------------------------------------------------------------------
#------------------------------------------------------------------------------
# VOID
# EFIAPI
# EnableDisableInterrupts (
# VOID
# );
#------------------------------------------------------------------------------
ASM_GLOBAL ASM_PFX(EnableDisableInterrupts)
ASM_PFX(EnableDisableInterrupts):
sti
cli
ret

54
MdePkg/Library/BaseLib/X64/LongJump.S
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@@ -1,54 +0,0 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php.
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
# Module Name:
#
# LongJump.S
#
# Abstract:
#
# Implementation of _LongJump() on x64.
#
#------------------------------------------------------------------------------
#------------------------------------------------------------------------------
# VOID
# EFIAPI
# InternalLongJump (
# IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer,
# IN UINTN Value
# );
#------------------------------------------------------------------------------
ASM_GLOBAL ASM_PFX(InternalLongJump)
ASM_PFX(InternalLongJump):
mov (%rcx), %rbx
mov 0x8(%rcx), %rsp
mov 0x10(%rcx), %rbp
mov 0x18(%rcx), %rdi
mov 0x20(%rcx), %rsi
mov 0x28(%rcx), %r12
mov 0x30(%rcx), %r13
mov 0x38(%rcx), %r14
mov 0x40(%rcx), %r15
# load non-volatile fp registers
ldmxcsr 0x50(%rcx)
movdqu 0x58(%rcx), %xmm6
movdqu 0x68(%rcx), %xmm7
movdqu 0x78(%rcx), %xmm8
movdqu 0x88(%rcx), %xmm9
movdqu 0x98(%rcx), %xmm10
movdqu 0xA8(%rcx), %xmm11
movdqu 0xB8(%rcx), %xmm12
movdqu 0xC8(%rcx), %xmm13
movdqu 0xD8(%rcx), %xmm14
movdqu 0xE8(%rcx), %xmm15
mov %rdx, %rax # set return value
jmp *0x48(%rcx)

72
MdePkg/Library/BaseLib/X64/RdRand.S
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@@ -1,72 +0,0 @@
#------------------------------------------------------------------------------ ;
# Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php.
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
# Module Name:
#
# RdRand.S
#
# Abstract:
#
# Generates random number through CPU RdRand instruction under 64-bit platform.
#
# Notes:
#
#------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Generates a 16 bit random number through RDRAND instruction.
// Return TRUE if Rand generated successfully, or FALSE if not.
//
// BOOLEAN EFIAPI InternalX86RdRand16 (UINT16 *Rand);
//------------------------------------------------------------------------------
ASM_GLOBAL ASM_PFX(InternalX86RdRand16)
ASM_PFX(InternalX86RdRand16):
.byte 0x0f, 0xc7, 0xf0 // rdrand r16: "0f c7 /6 ModRM:r/m(w)"
jc rn16_ok // jmp if CF=1
xor %rax, %rax // reg=0 if CF=0
ret // return with failure status
rn16_ok:
mov %ax, (%rcx)
mov $0x1, %rax
ret
//------------------------------------------------------------------------------
// Generates a 32 bit random number through RDRAND instruction.
// Return TRUE if Rand generated successfully, or FALSE if not.
//
// BOOLEAN EFIAPI InternalX86RdRand32 (UINT32 *Rand);
//------------------------------------------------------------------------------
ASM_GLOBAL ASM_PFX(InternalX86RdRand32)
ASM_PFX(InternalX86RdRand32):
.byte 0x0f, 0xc7, 0xf0 // rdrand r32: "0f c7 /6 ModRM:r/m(w)"
jc rn32_ok // jmp if CF=1
xor %rax, %rax // reg=0 if CF=0
ret // return with failure status
rn32_ok:
mov %eax, (%rcx)
mov $0x1, %rax
ret
//------------------------------------------------------------------------------
// Generates a 64 bit random number through RDRAND instruction.
// Return TRUE if Rand generated successfully, or FALSE if not.
//
// BOOLEAN EFIAPI InternalX86RdRand64 (UINT64 *Rand);
//------------------------------------------------------------------------------
ASM_GLOBAL ASM_PFX(InternalX86RdRand64)
ASM_PFX(InternalX86RdRand64):
.byte 0x48, 0x0f, 0xc7, 0xf0 // rdrand r64: "REX.W + 0f c7 /6 ModRM:r/m(w)"
jc rn64_ok // jmp if CF=1
xor %rax, %rax // reg=0 if CF=0
ret // return with failure status
rn64_ok:
mov %rax, (%rcx)
mov $0x1, %rax
ret

53
MdePkg/Library/BaseLib/X64/SetJump.S
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@@ -1,53 +0,0 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php.
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
# Module Name:
#
# SetJump.S
#
# Abstract:
#
# Implementation of SetJump() on x86_64
#
#------------------------------------------------------------------------------
ASM_GLOBAL ASM_PFX(SetJump)
ASM_PFX(SetJump):
push %rcx
add $0xffffffffffffffe0,%rsp
call ASM_PFX(InternalAssertJumpBuffer)
add $0x20,%rsp
pop %rcx
pop %rdx
mov %rbx,(%rcx)
mov %rsp,0x8(%rcx)
mov %rbp,0x10(%rcx)
mov %rdi,0x18(%rcx)
mov %rsi,0x20(%rcx)
mov %r12,0x28(%rcx)
mov %r13,0x30(%rcx)
mov %r14,0x38(%rcx)
mov %r15,0x40(%rcx)
mov %rdx,0x48(%rcx)
# save non-volatile fp registers
stmxcsr 0x50(%rcx)
movdqu %xmm6, 0x58(%rcx)
movdqu %xmm7, 0x68(%rcx)
movdqu %xmm8, 0x78(%rcx)
movdqu %xmm9, 0x88(%rcx)
movdqu %xmm10, 0x98(%rcx)
movdqu %xmm11, 0xA8(%rcx)
movdqu %xmm12, 0xB8(%rcx)
movdqu %xmm13, 0xC8(%rcx)
movdqu %xmm14, 0xD8(%rcx)
movdqu %xmm15, 0xE8(%rcx)
xor %rax,%rax
jmpq *%rdx

52
MdePkg/Library/BaseLib/X64/SwitchStack.S
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@@ -1,52 +0,0 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php.
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
# Module Name:
#
# SwitchStack.S
#
# Abstract:
#
#------------------------------------------------------------------------------
#------------------------------------------------------------------------------
# Routine Description:
#
# Routine for switching stacks with 2 parameters
#
# Arguments:
#
# (rcx) EntryPoint - Entry point with new stack.
# (rdx) Context1 - Parameter1 for entry point.
# (r8) Context2 - Parameter2 for entry point.
# (r9) NewStack - The pointer to new stack.
#
# Returns:
#
# None
#
#------------------------------------------------------------------------------
ASM_GLOBAL ASM_PFX(InternalSwitchStack)
ASM_PFX(InternalSwitchStack):
pushq %rbp
movq %rsp, %rbp
mov %rcx, %rax // Shift registers for new call
mov %rdx, %rcx
mov %r8, %rdx
#
# Reserve space for register parameters (rcx, rdx, r8 & r9) on the stack,
# in case the callee wishes to spill them.
#
lea -0x20(%r9), %rsp
pushq $0 // stop gdb stack unwind
jmp *%rax // call EntryPoint ()

334
MdePkg/Library/BaseLib/X64/Thunk16.S
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@@ -1,334 +0,0 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php.
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
# Module Name:
#
# Thunk16.S
#
# Abstract:
#
# Real mode thunk
#
#------------------------------------------------------------------------------
#include <Library/BaseLib.h>
ASM_GLOBAL ASM_PFX(m16Start)
ASM_GLOBAL ASM_PFX(m16Size)
ASM_GLOBAL ASM_PFX(mThunk16Attr)
ASM_GLOBAL ASM_PFX(m16Gdt)
ASM_GLOBAL ASM_PFX(m16GdtrBase)
ASM_GLOBAL ASM_PFX(mTransition)
ASM_GLOBAL ASM_PFX(InternalAsmThunk16)
# define the structure of IA32_REGS
.set _EDI, 0 #size 4
.set _ESI, 4 #size 4
.set _EBP, 8 #size 4
.set _ESP, 12 #size 4
.set _EBX, 16 #size 4
.set _EDX, 20 #size 4
.set _ECX, 24 #size 4
.set _EAX, 28 #size 4
.set _DS, 32 #size 2
.set _ES, 34 #size 2
.set _FS, 36 #size 2
.set _GS, 38 #size 2
.set _EFLAGS, 40 #size 8
.set _EIP, 48 #size 4
.set _CS, 52 #size 2
.set _SS, 54 #size 2
.set IA32_REGS_SIZE, 56
.data
.set Lm16Size, ASM_PFX(InternalAsmThunk16) - ASM_PFX(m16Start)
ASM_PFX(m16Size): .word Lm16Size
.set LmThunk16Attr, L_ThunkAttr - ASM_PFX(m16Start)
ASM_PFX(mThunk16Attr): .word LmThunk16Attr
.set Lm16Gdt, ASM_PFX(NullSeg) - ASM_PFX(m16Start)
ASM_PFX(m16Gdt): .word Lm16Gdt
.set Lm16GdtrBase, _16GdtrBase - ASM_PFX(m16Start)
ASM_PFX(m16GdtrBase): .word Lm16GdtrBase
.set LmTransition, _EntryPoint - ASM_PFX(m16Start)
ASM_PFX(mTransition): .word LmTransition
.text
ASM_PFX(m16Start):
SavedGdt: .space 10
#------------------------------------------------------------------------------
# _BackFromUserCode() takes control in real mode after 'retf' has been executed
# by user code. It will be shadowed to somewhere in memory below 1MB.
#------------------------------------------------------------------------------
ASM_GLOBAL ASM_PFX(BackFromUserCode)
ASM_PFX(BackFromUserCode):
#
# The order of saved registers on the stack matches the order they appears
# in IA32_REGS structure. This facilitates wrapper function to extract them
# into that structure.
#
# Some instructions for manipulation of segment registers have to be written
# in opcode since 64-bit MASM prevents accesses to those registers.
#
.byte 0x16 # push ss
.byte 0xe # push cs
.byte 0x66
call L_Base # push eip
L_Base:
.byte 0x66
pushq $0 # reserved high order 32 bits of EFlags
.byte 0x66, 0x9c # pushfd actually
cli # disable interrupts
push %gs
push %fs
.byte 6 # push es
.byte 0x1e # push ds
.byte 0x66,0x60 # pushad
.byte 0x66,0xba # mov edx, imm32
L_ThunkAttr: .space 4
testb $THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15, %dl
jz L_1
movl $0x15cd2401,%eax # mov ax, 2401h & int 15h
cli # disable interrupts
jnc L_2
L_1:
testb $THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL, %dl
jz L_2
inb $0x92,%al
orb $2,%al
outb %al, $0x92 # deactivate A20M#
L_2:
xorw %ax, %ax # xor eax, eax
movl %ss, %eax # mov ax, ss
lea IA32_REGS_SIZE(%esp), %bp
#
# rsi in the following 2 instructions is indeed bp in 16-bit code
#
movw %bp, (_ESP - IA32_REGS_SIZE)(%rsi)
.byte 0x66
movl (_EIP - IA32_REGS_SIZE)(%rsi), %ebx
shlw $4,%ax # shl eax, 4
addw %ax,%bp # add ebp, eax
movw %cs,%ax
shlw $4,%ax
lea (L_64BitCode - L_Base)(%ebx, %eax), %ax
.byte 0x66,0x2e,0x89,0x87 # mov cs:[bx + (L_64Eip - L_Base)], eax
.word L_64Eip - L_Base
.byte 0x66,0xb8 # mov eax, imm32
L_SavedCr4: .space 4
movq %rax, %cr4
#
# rdi in the instruction below is indeed bx in 16-bit code
#
.byte 0x66,0x2e # 2eh is "cs:" segment override
lgdt (SavedGdt - L_Base)(%rdi)
.byte 0x66
movl $0xc0000080,%ecx
rdmsr
orb $1,%ah
wrmsr
.byte 0x66,0xb8 # mov eax, imm32
L_SavedCr0: .space 4
movq %rax, %cr0
.byte 0x66,0xea # jmp far cs:L_64Bit
L_64Eip: .space 4
L_SavedCs: .space 2
L_64BitCode:
.byte 0x90
.byte 0x48,0xbc # mov rsp, imm64
L_SavedSp: .space 8 # restore stack
nop
ret
_EntryPoint: .long ASM_PFX(ToUserCode) - ASM_PFX(m16Start)
.word CODE16
_16Gdtr: .word GDT_SIZE - 1
_16GdtrBase: .quad 0
_16Idtr: .word 0x3ff
.long 0
#------------------------------------------------------------------------------
# _ToUserCode() takes control in real mode before passing control to user code.
# It will be shadowed to somewhere in memory below 1MB.
#------------------------------------------------------------------------------
ASM_GLOBAL ASM_PFX(ToUserCode)
ASM_PFX(ToUserCode):
movl %edx,%ss # set new segment selectors
movl %edx,%ds
movl %edx,%es
movl %edx,%fs
movl %edx,%gs
.byte 0x66
movl $0xc0000080,%ecx
movq %rax, %cr0
rdmsr
andb $0xfe, %ah # $0b11111110
wrmsr
movq %rbp, %cr4
movl %esi,%ss # set up 16-bit stack segment
movw %bx,%sp # set up 16-bit stack pointer
.byte 0x66 # make the following call 32-bit
call L_Base1 # push eip
L_Base1:
popw %bp # ebp <- address of L_Base1
pushq (IA32_REGS_SIZE + 2)(%esp)
lea 0x0c(%rsi), %eax
pushq %rax
lret # execution begins at next instruction
L_RealMode:
.byte 0x66,0x2e # CS and operand size override
lidt (_16Idtr - L_Base1)(%rsi)
.byte 0x66,0x61 # popad
.byte 0x1f # pop ds
.byte 0x7 # pop es
.byte 0x0f, 0xa1 # pop fs
.byte 0x0f, 0xa9 # pop gs
.byte 0x66, 0x9d # popfd
leaw 4(%esp),%sp # skip high order 32 bits of EFlags
.byte 0x66 # make the following retf 32-bit
lret # transfer control to user code
.set CODE16, ASM_PFX(_16Code) - .
.set DATA16, ASM_PFX(_16Data) - .
.set DATA32, ASM_PFX(_32Data) - .
ASM_PFX(NullSeg): .quad 0
ASM_PFX(_16Code):
.word -1
.word 0
.byte 0
.byte 0x9b
.byte 0x8f # 16-bit segment, 4GB limit
.byte 0
ASM_PFX(_16Data):
.word -1
.word 0
.byte 0
.byte 0x93
.byte 0x8f # 16-bit segment, 4GB limit
.byte 0
ASM_PFX(_32Data):
.word -1
.word 0
.byte 0
.byte 0x93
.byte 0xcf # 16-bit segment, 4GB limit
.byte 0
.set GDT_SIZE, . - ASM_PFX(NullSeg)
#------------------------------------------------------------------------------
# IA32_REGISTER_SET *
# EFIAPI
# InternalAsmThunk16 (
# IN IA32_REGISTER_SET *RegisterSet,
# IN OUT VOID *Transition
# );
#------------------------------------------------------------------------------
ASM_GLOBAL ASM_PFX(InternalAsmThunk16)
ASM_PFX(InternalAsmThunk16):
pushq %rbp
pushq %rbx
pushq %rsi
pushq %rdi
movl %ds, %ebx
pushq %rbx # Save ds segment register on the stack
movl %es, %ebx
pushq %rbx # Save es segment register on the stack
movl %ss, %ebx
pushq %rbx # Save ss segment register on the stack
.byte 0x0f, 0xa0 #push fs
.byte 0x0f, 0xa8 #push gs
movq %rcx, %rsi
movzwl _SS(%rsi), %r8d
movl _ESP(%rsi), %edi
lea -(IA32_REGS_SIZE + 4)(%edi), %rdi
imul $16, %r8d, %eax
movl %edi,%ebx # ebx <- stack for 16-bit code
pushq $(IA32_REGS_SIZE / 4)
addl %eax,%edi # edi <- linear address of 16-bit stack
popq %rcx
rep
movsl # copy RegSet
lea (L_SavedCr4 - ASM_PFX(m16Start))(%rdx), %ecx
movl %edx,%eax # eax <- transition code address
andl $0xf,%edx
shll $12,%eax # segment address in high order 16 bits
.set LBackFromUserCodeDelta, ASM_PFX(BackFromUserCode) - ASM_PFX(m16Start)
lea (LBackFromUserCodeDelta)(%rdx), %ax
stosl # [edi] <- return address of user code
sgdt 0x60(%rsp) # save GDT stack in argument space
movzwq 0x60(%rsp), %r10 # r10 <- GDT limit
lea ((ASM_PFX(InternalAsmThunk16) - L_SavedCr4) + 0xf)(%rcx), %r11
andq $0xfffffffffffffff0, %r11 # r11 <- 16-byte aligned shadowed GDT table in real mode buffer
movw %r10w, (SavedGdt - L_SavedCr4)(%rcx) # save the limit of shadowed GDT table
movq %r11, (SavedGdt - L_SavedCr4 + 0x2)(%rcx) # save the base address of shadowed GDT table
movq 0x62(%rsp) ,%rsi # rsi <- the original GDT base address
xchg %r10, %rcx # save rcx to r10 and initialize rcx to be the limit of GDT table
incq %rcx # rcx <- the size of memory to copy
xchg %r11, %rdi # save rdi to r11 and initialize rdi to the base address of shadowed GDT table
rep
movsb # perform memory copy to shadow GDT table
movq %r10, %rcx # restore the orignal rcx before memory copy
movq %r11, %rdi # restore the original rdi before memory copy
sidt 0x50(%rsp)
movq %cr0, %rax
.set LSavedCrDelta, L_SavedCr0 - L_SavedCr4
movl %eax, (LSavedCrDelta)(%rcx)
andl $0x7ffffffe,%eax # clear PE, PG bits
movq %cr4, %rbp
movl %ebp, (%rcx) # save CR4 in SavedCr4
andl $0xffffffcf,%ebp # clear PAE, PSE bits
movl %r8d, %esi # esi <- 16-bit stack segment
.byte 0x6a, DATA32
popq %rdx
lgdt (_16Gdtr - L_SavedCr4)(%rcx)
movl %edx,%ss
pushfq
lea -8(%rdx), %edx
lea L_RetFromRealMode(%rip), %r8
pushq %r8
movl %cs, %r8d
movw %r8w, (L_SavedCs - L_SavedCr4)(%rcx)
movq %rsp, (L_SavedSp - L_SavedCr4)(%rcx)
.byte 0xff, 0x69 # jmp (_EntryPoint - L_SavedCr4)(%rcx)
.set Ltemp1, _EntryPoint - L_SavedCr4
.byte Ltemp1
L_RetFromRealMode:
popfq
lgdt 0x60(%rsp) # restore protected mode GDTR
lidt 0x50(%rsp) # restore protected mode IDTR
lea -IA32_REGS_SIZE(%rbp), %eax
.byte 0x0f, 0xa9 # pop gs
.byte 0x0f, 0xa1 # pop fs
popq %rbx
movl %ebx, %ss
popq %rbx
movl %ebx, %es
popq %rbx
movl %ebx, %ds
popq %rdi
popq %rsi
popq %rbx
popq %rbp
ret